diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/long | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/long')
72 files changed, 62162 insertions, 61954 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index f1835fc87..e646f5b40 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,110 +1,110 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.909061 # Number of seconds simulated -sim_ticks 1909061460000 # Number of ticks simulated -final_tick 1909061460000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.889223 # Number of seconds simulated +sim_ticks 1889223246000 # Number of ticks simulated +final_tick 1889223246000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24403 # Simulator instruction rate (inst/s) -host_op_rate 24403 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 829686396 # Simulator tick rate (ticks/s) -host_mem_usage 385840 # Number of bytes of host memory used -host_seconds 2300.94 # Real time elapsed on the host -sim_insts 56149847 # Number of instructions simulated -sim_ops 56149847 # Number of ops (including micro ops) simulated +host_inst_rate 22780 # Simulator instruction rate (inst/s) +host_op_rate 22780 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 766551699 # Simulator tick rate (ticks/s) +host_mem_usage 396616 # Number of bytes of host memory used +host_seconds 2464.57 # Real time elapsed on the host +sim_insts 56141873 # Number of instructions simulated +sim_ops 56141873 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1046656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24857664 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1047552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24859008 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25905280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1046656 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1046656 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7563328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7563328 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16354 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388401 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25907520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1047552 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1047552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7566528 # Number of bytes written to this memory +system.physmem.bytes_written::total 7566528 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16368 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388422 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404770 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118177 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118177 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 548257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13020882 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13569642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 548257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 548257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3961804 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3961804 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3961804 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 548257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13020882 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17531446 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404770 # Number of read requests accepted -system.physmem.writeReqs 118177 # Number of write requests accepted -system.physmem.readBursts 404770 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118177 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25897600 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue -system.physmem.bytesWritten 7561728 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25905280 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7563328 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 404805 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118227 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118227 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 554488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13158322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13713318 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 554488 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 554488 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4005100 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4005100 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4005100 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 554488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13158322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17718418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404805 # Number of read requests accepted +system.physmem.writeReqs 118227 # Number of write requests accepted +system.physmem.readBursts 404805 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 118227 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25900800 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue +system.physmem.bytesWritten 7565120 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25907520 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7566528 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25467 # Per bank write bursts -system.physmem.perBankRdBursts::1 25712 # Per bank write bursts -system.physmem.perBankRdBursts::2 25810 # Per bank write bursts -system.physmem.perBankRdBursts::3 25757 # Per bank write bursts -system.physmem.perBankRdBursts::4 25010 # Per bank write bursts -system.physmem.perBankRdBursts::5 25117 # Per bank write bursts -system.physmem.perBankRdBursts::6 24705 # Per bank write bursts -system.physmem.perBankRdBursts::7 24573 # Per bank write bursts -system.physmem.perBankRdBursts::8 25203 # Per bank write bursts -system.physmem.perBankRdBursts::9 25292 # Per bank write bursts -system.physmem.perBankRdBursts::10 25386 # Per bank write bursts -system.physmem.perBankRdBursts::11 25018 # Per bank write bursts -system.physmem.perBankRdBursts::12 24535 # Per bank write bursts -system.physmem.perBankRdBursts::13 25541 # Per bank write bursts -system.physmem.perBankRdBursts::14 25794 # Per bank write bursts -system.physmem.perBankRdBursts::15 25730 # Per bank write bursts -system.physmem.perBankWrBursts::0 7820 # Per bank write bursts +system.physmem.perBankRdBursts::0 25470 # Per bank write bursts +system.physmem.perBankRdBursts::1 25713 # Per bank write bursts +system.physmem.perBankRdBursts::2 25812 # Per bank write bursts +system.physmem.perBankRdBursts::3 25774 # Per bank write bursts +system.physmem.perBankRdBursts::4 25230 # Per bank write bursts +system.physmem.perBankRdBursts::5 24950 # Per bank write bursts +system.physmem.perBankRdBursts::6 24793 # Per bank write bursts +system.physmem.perBankRdBursts::7 24569 # Per bank write bursts +system.physmem.perBankRdBursts::8 25113 # Per bank write bursts +system.physmem.perBankRdBursts::9 25266 # Per bank write bursts +system.physmem.perBankRdBursts::10 25525 # Per bank write bursts +system.physmem.perBankRdBursts::11 24857 # Per bank write bursts +system.physmem.perBankRdBursts::12 24533 # Per bank write bursts +system.physmem.perBankRdBursts::13 25560 # Per bank write bursts +system.physmem.perBankRdBursts::14 25804 # Per bank write bursts +system.physmem.perBankRdBursts::15 25731 # Per bank write bursts +system.physmem.perBankWrBursts::0 7815 # Per bank write bursts system.physmem.perBankWrBursts::1 7678 # Per bank write bursts -system.physmem.perBankWrBursts::2 8070 # Per bank write bursts -system.physmem.perBankWrBursts::3 7721 # Per bank write bursts -system.physmem.perBankWrBursts::4 7116 # Per bank write bursts -system.physmem.perBankWrBursts::5 7111 # Per bank write bursts -system.physmem.perBankWrBursts::6 6703 # Per bank write bursts +system.physmem.perBankWrBursts::2 8068 # Per bank write bursts +system.physmem.perBankWrBursts::3 7736 # Per bank write bursts +system.physmem.perBankWrBursts::4 7326 # Per bank write bursts +system.physmem.perBankWrBursts::5 6953 # Per bank write bursts +system.physmem.perBankWrBursts::6 6780 # Per bank write bursts system.physmem.perBankWrBursts::7 6420 # Per bank write bursts -system.physmem.perBankWrBursts::8 7317 # Per bank write bursts -system.physmem.perBankWrBursts::9 6903 # Per bank write bursts -system.physmem.perBankWrBursts::10 7274 # Per bank write bursts -system.physmem.perBankWrBursts::11 7007 # Per bank write bursts -system.physmem.perBankWrBursts::12 7092 # Per bank write bursts -system.physmem.perBankWrBursts::13 7990 # Per bank write bursts -system.physmem.perBankWrBursts::14 7984 # Per bank write bursts -system.physmem.perBankWrBursts::15 7946 # Per bank write bursts +system.physmem.perBankWrBursts::8 7238 # Per bank write bursts +system.physmem.perBankWrBursts::9 6883 # Per bank write bursts +system.physmem.perBankWrBursts::10 7397 # Per bank write bursts +system.physmem.perBankWrBursts::11 6875 # Per bank write bursts +system.physmem.perBankWrBursts::12 7088 # Per bank write bursts +system.physmem.perBankWrBursts::13 8006 # Per bank write bursts +system.physmem.perBankWrBursts::14 7993 # Per bank write bursts +system.physmem.perBankWrBursts::15 7949 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 1909052547000 # Total gap between requests +system.physmem.numWrRetry 20 # Number of times write queue was full causing retry +system.physmem.totGap 1889214280000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404770 # Read request sizes (log2) +system.physmem.readPktSize::6 404805 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118177 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118227 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402482 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2156 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -149,191 +149,193 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6024 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7078 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64573 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 518.162823 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 316.799935 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 407.231768 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14977 23.19% 23.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11234 17.40% 40.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4851 7.51% 48.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3268 5.06% 53.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2473 3.83% 56.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2033 3.15% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4174 6.46% 66.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1362 2.11% 68.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20201 31.28% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64573 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5294 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 76.433321 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2890.025475 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5291 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 48 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63746 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 524.988548 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 319.641335 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 414.335221 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14725 23.10% 23.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10901 17.10% 40.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5357 8.40% 48.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3110 4.88% 53.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2601 4.08% 57.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1701 2.67% 60.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1560 2.45% 62.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1439 2.26% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22352 35.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63746 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5298 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 76.386372 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2900.765356 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5295 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5294 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5294 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.318096 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.102648 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 19.930772 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4682 88.44% 88.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 33 0.62% 89.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 23 0.43% 89.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 33 0.62% 90.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 222 4.19% 94.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 11 0.21% 94.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 11 0.21% 94.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 35 0.66% 95.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 195 3.68% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.09% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 6 0.11% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 4 0.08% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 5 0.09% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 2 0.04% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 2 0.04% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 9 0.17% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.08% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 2 0.04% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 5 0.09% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5294 # Writes before turning the bus around for reads -system.physmem.totQLat 2639973000 # Total ticks spent queuing -system.physmem.totMemAccLat 10227160500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2023250000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6524.09 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5298 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5298 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.311250 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.880356 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.145944 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4698 88.67% 88.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 33 0.62% 89.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 235 4.44% 93.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 22 0.42% 94.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 12 0.23% 94.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 14 0.26% 94.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 10 0.19% 94.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 4 0.08% 94.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 30 0.57% 95.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 15 0.28% 95.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 179 3.38% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 1 0.02% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 1 0.02% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 1 0.02% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 6 0.11% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 2 0.04% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 4 0.08% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 12 0.23% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 2 0.04% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 4 0.08% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.04% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 8 0.15% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5298 # Writes before turning the bus around for reads +system.physmem.totQLat 2164522000 # Total ticks spent queuing +system.physmem.totMemAccLat 9752647000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2023500000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5348.46 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25274.09 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.57 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.96 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.57 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.96 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 24098.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.71 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.71 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.18 # Average write queue length when enqueuing -system.physmem.readRowHits 362738 # Number of row buffer hits during reads -system.physmem.writeRowHits 95491 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.64 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes -system.physmem.avgGap 3650566.02 # Average gap between requests -system.physmem.pageHitRate 87.64 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 238623840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 130201500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1576777800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 379980720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 124690266480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 68013230490 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1085773099500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1280802180330 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.908515 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1806022540250 # Time in different power states -system.physmem_0.memoryStateTime::REF 63747580000 # Time in different power states +system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing +system.physmem.readRowHits 363251 # Number of row buffer hits during reads +system.physmem.writeRowHits 95908 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.76 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.12 # Row buffer hit rate for writes +system.physmem.avgGap 3612043.39 # Average gap between requests +system.physmem.pageHitRate 87.81 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 234556560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 127982250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1578025800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 380868480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 123394455600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 60772181625 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1080221277750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1266709348065 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.494357 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1796832063750 # Time in different power states +system.physmem_0.memoryStateTime::REF 63085100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 39286273500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 29299865000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 249548040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 136162125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1579492200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 385644240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 124690266480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 68685352830 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1085183526750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1280909992665 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.964984 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1805042162250 # Time in different power states -system.physmem_1.memoryStateTime::REF 63747580000 # Time in different power states +system.physmem_1.actEnergy 247363200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 134970000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1578634200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 385099920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 123394455600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 61856765370 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1079269896750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1266867185040 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.577899 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1795248089750 # Time in different power states +system.physmem_1.memoryStateTime::REF 63085100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 40266665250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30883852750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 15258422 # Number of BP lookups -system.cpu.branchPred.condPredicted 13121569 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 520615 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12105776 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4568162 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 15253451 # Number of BP lookups +system.cpu.branchPred.condPredicted 13119801 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 515637 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12113296 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4570787 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 37.735392 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 863536 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33630 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6539212 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 544524 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5994688 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 219095 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 37.733636 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 859438 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 30658 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6570706 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 545483 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 6025223 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 218035 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9320175 # DTB read hits -system.cpu.dtb.read_misses 17427 # DTB read misses +system.cpu.dtb.read_hits 9316925 # DTB read hits +system.cpu.dtb.read_misses 17695 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 764388 # DTB read accesses -system.cpu.dtb.write_hits 6394455 # DTB write hits -system.cpu.dtb.write_misses 2545 # DTB write misses -system.cpu.dtb.write_acv 159 # DTB write access violations -system.cpu.dtb.write_accesses 298887 # DTB write accesses -system.cpu.dtb.data_hits 15714630 # DTB hits -system.cpu.dtb.data_misses 19972 # DTB misses -system.cpu.dtb.data_acv 370 # DTB access violations -system.cpu.dtb.data_accesses 1063275 # DTB accesses -system.cpu.itb.fetch_hits 4019631 # ITB hits -system.cpu.itb.fetch_misses 6355 # ITB misses -system.cpu.itb.fetch_acv 661 # ITB acv -system.cpu.itb.fetch_accesses 4025986 # ITB accesses +system.cpu.dtb.read_accesses 764827 # DTB read accesses +system.cpu.dtb.write_hits 6393212 # DTB write hits +system.cpu.dtb.write_misses 2442 # DTB write misses +system.cpu.dtb.write_acv 158 # DTB write access violations +system.cpu.dtb.write_accesses 298820 # DTB write accesses +system.cpu.dtb.data_hits 15710137 # DTB hits +system.cpu.dtb.data_misses 20137 # DTB misses +system.cpu.dtb.data_acv 369 # DTB access violations +system.cpu.dtb.data_accesses 1063647 # DTB accesses +system.cpu.itb.fetch_hits 4018824 # ITB hits +system.cpu.itb.fetch_misses 6310 # ITB misses +system.cpu.itb.fetch_acv 701 # ITB acv +system.cpu.itb.fetch_accesses 4025134 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -346,85 +348,84 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numPwrStateTransitions 12756 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 6378 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 281603673.878959 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 439873554.784215 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 6377 99.98% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state +system.cpu.numPwrStateTransitions 12752 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 6376 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 281746974.905897 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 439847984.325030 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 6376 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 19000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 6378 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 112993228000 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1796068232000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 226008061 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::total 6376 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 92804534000 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1796418712000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 185630526 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56149847 # Number of instructions committed -system.cpu.committedOps 56149847 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2969857 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 6378 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3592114868 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 4.025088 # CPI: cycles per instruction -system.cpu.ipc 0.248442 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 3199355 5.70% 5.70% # Class of committed instruction -system.cpu.op_class_0::IntAlu 36201883 64.47% 70.17% # Class of committed instruction -system.cpu.op_class_0::IntMult 60840 0.11% 70.28% # Class of committed instruction +system.cpu.committedInsts 56141873 # Number of instructions committed +system.cpu.committedOps 56141873 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2958149 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 6376 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3592815966 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.306454 # CPI: cycles per instruction +system.cpu.ipc 0.302439 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 3199005 5.70% 5.70% # Class of committed instruction +system.cpu.op_class_0::IntAlu 36197195 64.47% 70.17% # Class of committed instruction +system.cpu.op_class_0::IntMult 60822 0.11% 70.28% # Class of committed instruction system.cpu.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.op_class_0::FloatAdd 38079 0.07% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::MemRead 9320961 16.60% 86.95% # Class of committed instruction -system.cpu.op_class_0::MemWrite 6373595 11.35% 98.31% # Class of committed instruction -system.cpu.op_class_0::IprAccess 951498 1.69% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction +system.cpu.op_class_0::MemRead 9319321 16.60% 86.95% # Class of committed instruction +system.cpu.op_class_0::MemWrite 6372729 11.35% 98.31% # Class of committed instruction +system.cpu.op_class_0::IprAccess 951086 1.69% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 56149847 # Class of committed instruction +system.cpu.op_class_0::total 56141873 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211594 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74821 40.93% 40.93% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 41.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1907 1.04% 42.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105943 57.96% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182802 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73454 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211498 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74792 40.94% 40.94% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1903 1.04% 42.05% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105883 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182709 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73425 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1907 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73454 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148946 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1839859866500 96.38% 96.38% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 85941500 0.00% 96.38% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 711439500 0.04% 96.42% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 68403193000 3.58% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1909060440500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981730 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1903 1.28% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73425 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148884 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1835945903000 97.18% 97.18% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 85568000 0.00% 97.18% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 710063500 0.04% 97.22% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 52480708000 2.78% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1889222242500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693335 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814794 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693454 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814870 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -463,513 +464,514 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4173 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175631 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6810 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175546 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6807 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5132 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5128 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192526 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5877 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1906 -system.cpu.kern.mode_good::user 1738 +system.cpu.kern.callpal::total 192434 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5876 # number of protection mode switches +system.cpu.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2091 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1905 +system.cpu.kern.mode_good::user 1737 system.cpu.kern.mode_good::idle 168 -system.cpu.kern.mode_switch_good::kernel 0.324315 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.324200 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080229 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392625 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 38921683000 2.04% 2.04% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4598347000 0.24% 2.28% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1865540400500 97.72% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080344 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392622 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 36856948000 1.95% 1.95% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4192339500 0.22% 2.17% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1848172945000 97.83% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4174 # number of times the context was actually changed -system.cpu.tickCycles 85327235 # Number of cycles that the object actually ticked -system.cpu.idleCycles 140680826 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1394976 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.976740 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13944378 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1395488 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.992474 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 124106500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.976740 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999955 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy +system.cpu.tickCycles 85233988 # Number of cycles that the object actually ticked +system.cpu.idleCycles 100396538 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1394263 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.980931 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 13942036 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1394775 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.995903 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 94238500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.980931 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999963 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999963 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 227 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63924438 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63924438 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 7983946 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7983946 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5577839 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5577839 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183518 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183518 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199043 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199043 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13561785 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13561785 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13561785 # number of overall hits -system.cpu.dcache.overall_hits::total 13561785 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1096703 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1096703 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 574639 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 574639 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 16549 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 16549 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1671342 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1671342 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1671342 # number of overall misses -system.cpu.dcache.overall_misses::total 1671342 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 45383174000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 45383174000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33964439500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33964439500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 226601500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 226601500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 79347613500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 79347613500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 79347613500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 79347613500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9080649 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9080649 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152478 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152478 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200067 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200067 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199043 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199043 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15233127 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15233127 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15233127 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15233127 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120774 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120774 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093400 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093400 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082717 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082717 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.109718 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.109718 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.109718 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.109718 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41381.462438 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41381.462438 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59105.698534 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59105.698534 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13692.760892 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13692.760892 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47475.390136 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47475.390136 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47475.390136 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47475.390136 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63909041 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63909041 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 7981560 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7981560 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5577988 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5577988 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183448 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183448 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199007 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199007 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13559548 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13559548 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13559548 # number of overall hits +system.cpu.dcache.overall_hits::total 13559548 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1096304 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1096304 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 573678 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 573678 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 16581 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 16581 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1669982 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1669982 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1669982 # number of overall misses +system.cpu.dcache.overall_misses::total 1669982 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31558344500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31558344500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22538815500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22538815500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222577500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 222577500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 54097160000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 54097160000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 54097160000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 54097160000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9077864 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9077864 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6151666 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6151666 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200029 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200029 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199007 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199007 # 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miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.109654 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.109654 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.109654 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28786.125472 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28786.125472 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39288.268855 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39288.268855 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13423.647548 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13423.647548 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32393.858137 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32393.858137 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32393.858137 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32393.858137 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 838068 # number of writebacks -system.cpu.dcache.writebacks::total 838068 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21939 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 21939 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270415 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 270415 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 837697 # number of writebacks +system.cpu.dcache.writebacks::total 837697 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21981 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 21981 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269759 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 269759 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 292354 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 292354 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 292354 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 292354 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074764 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074764 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304224 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304224 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16546 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 16546 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1378988 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378988 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1378988 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378988 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 291740 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 291740 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 291740 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 291740 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074323 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1074323 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 303919 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 303919 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16578 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 16578 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1378242 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1378242 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1378242 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1378242 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9625 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 9625 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16555 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 16555 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43721360500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43721360500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17277660500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17277660500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 209790000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 209790000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 60999021000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 60999021000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 60999021000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 60999021000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1527294000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1527294000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1527294000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 1527294000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118358 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118358 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049447 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049447 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082702 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082702 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090526 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090526 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090526 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090526 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40679.963694 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40679.963694 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56792.562388 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56792.562388 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12679.197389 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12679.197389 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44234.627858 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44234.627858 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44234.627858 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44234.627858 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220388.744589 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220388.744589 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92255.753549 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92255.753549 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1477492 # number of replacements -system.cpu.icache.tags.tagsinuse 508.111413 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 19219698 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1478003 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 13.003829 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 50147606500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.111413 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.992405 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.992405 # Average percentage of cache occupancy +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9621 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 9621 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16551 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 16551 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30011433500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30011433500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11481403000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11481403000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205832000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205832000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41492836500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 41492836500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41492836500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 41492836500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534160500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534160500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534160500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534160500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118345 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118345 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049404 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049404 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082878 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082878 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090498 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090498 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090498 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090498 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27935.205241 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27935.205241 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37777.838832 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37777.838832 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12415.972976 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12415.972976 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30105.624774 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30105.624774 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30105.624774 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30105.624774 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221379.581530 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221379.581530 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92692.918857 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92692.918857 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1476241 # number of replacements +system.cpu.icache.tags.tagsinuse 509.437018 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 19208652 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1476752 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 13.007365 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 33938325500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.437018 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994994 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994994 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 407 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 401 # 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number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1170547500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17243377000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17243377000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1170547500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25130391500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26300939000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1170547500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25130391500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26300939000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447515000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447515000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447515000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447515000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383740 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383740 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011084 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011084 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249543 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249543 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011084 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278785 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141109 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011084 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278785 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141109 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 39900 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 39900 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67624.234759 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67624.234759 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71510.018938 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71510.018938 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63343.767334 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63343.767334 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71510.018938 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64627.635663 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64905.653253 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71510.018938 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64627.635663 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64905.653253 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208876.623377 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208876.623377 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87457.857531 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87457.857531 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5742250 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2870700 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1972 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 998 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 998 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2576516 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9625 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9625 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 956247 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1477492 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 820003 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2574859 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9621 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9621 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 914412 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1476241 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 819473 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 20 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 20 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304237 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304237 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1478177 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091450 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4433791 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219310 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8653101 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189159296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143002060 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 332161356 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 423210 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7576960 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3313265 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001022 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.031947 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 303930 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 303930 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1476926 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091030 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 23 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 241 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4430038 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217161 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8647199 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 188999168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142932652 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 331931820 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 340234 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4923264 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 3228320 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000974 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.031197 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3309880 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3385 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3225175 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3145 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3313265 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5201739500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3228320 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5198149000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2217424681 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2215530716 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2105003991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2103938977 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -983,12 +985,12 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51177 # Transaction distribution -system.iobus.trans_dist::WriteResp 51177 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5106 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51173 # Transaction distribution +system.iobus.trans_dist::WriteResp 51173 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5098 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -997,11 +999,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1812 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33110 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116560 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20424 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116552 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20392 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1010,50 +1012,50 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44364 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44332 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2705972 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5417500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2705940 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 5405000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 799000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 800000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 182000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15625500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14495500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2305500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6004000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5973000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215719668 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216181312 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23485000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23481000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.297488 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.301361 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1750571994000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.297488 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.081093 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.081093 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1731952426000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.301361 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.081335 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.081335 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1062,14 +1064,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21917383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21917383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5244162285 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5244162285 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5266079668 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5266079668 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5266079668 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5266079668 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21934383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21934383 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4859195929 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4859195929 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4881130312 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4881130312 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4881130312 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4881130312 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1086,19 +1088,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126690.075145 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126690.075145 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126207.217101 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126207.217101 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126209.219125 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126209.219125 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126209.219125 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126209.219125 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126788.341040 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126788.341040 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116942.528133 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 116942.528133 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 116983.350797 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 116983.350797 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 116983.350797 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 116983.350797 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 18 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 4.500000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks @@ -1110,14 +1112,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13267383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13267383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3164763984 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3164763984 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3178031367 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3178031367 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3178031367 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3178031367 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13284383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13284383 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2779181979 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2779181979 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2792466362 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2792466362 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2792466362 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2792466362 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1126,69 +1128,75 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76690.075145 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76163.938776 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76163.938776 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76166.120240 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76166.120240 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76166.120240 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76166.120240 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76788.341040 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76788.341040 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66884.433457 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66884.433457 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66925.496992 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 66925.496992 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66925.496992 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 66925.496992 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 827436 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 381422 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 409 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 295632 # Transaction distribution -system.membus.trans_dist::WriteReq 9625 # Transaction distribution -system.membus.trans_dist::WriteResp 9625 # Transaction distribution -system.membus.trans_dist::WritebackDirty 118177 # Transaction distribution -system.membus.trans_dist::CleanEvict 262256 # Transaction distribution -system.membus.trans_dist::UpgradeReq 167 # Transaction distribution +system.membus.trans_dist::ReadResp 295668 # Transaction distribution +system.membus.trans_dist::WriteReq 9621 # Transaction distribution +system.membus.trans_dist::WriteResp 9621 # Transaction distribution +system.membus.trans_dist::WritebackDirty 118227 # Transaction distribution +system.membus.trans_dist::CleanEvict 262241 # Transaction distribution +system.membus.trans_dist::UpgradeReq 137 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 116499 # Transaction distribution -system.membus.trans_dist::ReadExResp 116499 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288726 # Transaction distribution -system.membus.trans_dist::BadAddressError 24 # Transaction distribution +system.membus.trans_dist::ReadExReq 116498 # Transaction distribution +system.membus.trans_dist::ReadExResp 116498 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 288761 # Transaction distribution +system.membus.trans_dist::BadAddressError 23 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33110 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148698 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 48 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181856 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33102 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148773 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 46 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181921 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1265281 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44364 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30810880 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30855244 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1265346 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44332 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30816320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30860652 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33512972 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33518380 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 433 # Total snoops (count) system.membus.snoopTraffic 27584 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 843934 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::samples 463499 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001458 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.038162 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 843934 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 462823 99.85% 99.85% # Request fanout histogram +system.membus.snoop_fanout::1 676 0.15% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 843934 # Request fanout histogram -system.membus.reqLayer0.occupancy 30445500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 463499 # Request fanout histogram +system.membus.reqLayer0.occupancy 29272500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1319244966 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1319341290 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 29500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 31000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2159924750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2160301000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 943117 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1220,28 +1228,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1909061460000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1889223246000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 1d7e55213..dfe837c06 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,125 +1,125 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.907672 # Number of seconds simulated -sim_ticks 1907672102500 # Number of ticks simulated -final_tick 1907672102500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.906534 # Number of seconds simulated +sim_ticks 1906533530000 # Number of ticks simulated +final_tick 1906533530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 159928 # Simulator instruction rate (inst/s) -host_op_rate 159928 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5430263290 # Simulator tick rate (ticks/s) -host_mem_usage 337712 # Number of bytes of host memory used -host_seconds 351.30 # Real time elapsed on the host -sim_insts 56183395 # Number of instructions simulated -sim_ops 56183395 # Number of ops (including micro ops) simulated +host_inst_rate 134861 # Simulator instruction rate (inst/s) +host_op_rate 134861 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4533949866 # Simulator tick rate (ticks/s) +host_mem_usage 343876 # Number of bytes of host memory used +host_seconds 420.50 # Real time elapsed on the host +sim_insts 56709432 # Number of instructions simulated +sim_ops 56709432 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 861632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24651584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 117952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 582656 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.inst 896192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24492096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 81664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 812544 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26214784 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 861632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 117952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 979584 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7845056 # Number of bytes written to this memory -system.physmem.bytes_written::total 7845056 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13463 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 385181 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1843 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9104 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26283456 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 896192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 81664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977856 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7904832 # Number of bytes written to this memory +system.physmem.bytes_written::total 7904832 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 14003 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 382689 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1276 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 12696 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 409606 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122579 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122579 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 451667 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12922338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 61830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 305428 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13741766 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 451667 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 61830 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 513497 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4112371 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4112371 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4112371 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 451667 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12922338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 61830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 305428 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17854137 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 409606 # Number of read requests accepted -system.physmem.writeReqs 122579 # Number of write requests accepted -system.physmem.readBursts 409606 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 122579 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26206336 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8448 # Total number of bytes read from write queue -system.physmem.bytesWritten 7843200 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26214784 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7845056 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 132 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 410679 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123513 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123513 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 470064 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12846402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 42834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 426189 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13785992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 470064 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 42834 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 512897 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4146180 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4146180 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4146180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 470064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12846402 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 42834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 426189 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17932172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 410679 # Number of read requests accepted +system.physmem.writeReqs 123513 # Number of write requests accepted +system.physmem.readBursts 410679 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123513 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26276352 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue +system.physmem.bytesWritten 7903488 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26283456 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7904832 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26087 # Per bank write bursts -system.physmem.perBankRdBursts::1 25986 # Per bank write bursts -system.physmem.perBankRdBursts::2 25681 # Per bank write bursts -system.physmem.perBankRdBursts::3 25351 # Per bank write bursts -system.physmem.perBankRdBursts::4 24681 # Per bank write bursts -system.physmem.perBankRdBursts::5 24934 # Per bank write bursts -system.physmem.perBankRdBursts::6 25045 # Per bank write bursts -system.physmem.perBankRdBursts::7 25140 # Per bank write bursts -system.physmem.perBankRdBursts::8 25540 # Per bank write bursts -system.physmem.perBankRdBursts::9 26037 # Per bank write bursts -system.physmem.perBankRdBursts::10 25956 # Per bank write bursts -system.physmem.perBankRdBursts::11 25606 # Per bank write bursts -system.physmem.perBankRdBursts::12 26142 # Per bank write bursts -system.physmem.perBankRdBursts::13 25795 # Per bank write bursts -system.physmem.perBankRdBursts::14 25668 # Per bank write bursts -system.physmem.perBankRdBursts::15 25825 # Per bank write bursts -system.physmem.perBankWrBursts::0 8182 # Per bank write bursts -system.physmem.perBankWrBursts::1 8217 # Per bank write bursts -system.physmem.perBankWrBursts::2 8055 # Per bank write bursts -system.physmem.perBankWrBursts::3 7694 # Per bank write bursts -system.physmem.perBankWrBursts::4 7332 # Per bank write bursts -system.physmem.perBankWrBursts::5 7389 # Per bank write bursts -system.physmem.perBankWrBursts::6 7497 # Per bank write bursts -system.physmem.perBankWrBursts::7 6907 # Per bank write bursts -system.physmem.perBankWrBursts::8 7336 # Per bank write bursts -system.physmem.perBankWrBursts::9 7821 # Per bank write bursts -system.physmem.perBankWrBursts::10 7658 # Per bank write bursts -system.physmem.perBankWrBursts::11 7295 # Per bank write bursts -system.physmem.perBankWrBursts::12 7753 # Per bank write bursts -system.physmem.perBankWrBursts::13 7589 # Per bank write bursts -system.physmem.perBankWrBursts::14 7825 # Per bank write bursts -system.physmem.perBankWrBursts::15 8000 # Per bank write bursts +system.physmem.perBankRdBursts::0 26110 # Per bank write bursts +system.physmem.perBankRdBursts::1 26073 # Per bank write bursts +system.physmem.perBankRdBursts::2 25765 # Per bank write bursts +system.physmem.perBankRdBursts::3 25777 # Per bank write bursts +system.physmem.perBankRdBursts::4 25805 # Per bank write bursts +system.physmem.perBankRdBursts::5 25558 # Per bank write bursts +system.physmem.perBankRdBursts::6 25453 # Per bank write bursts +system.physmem.perBankRdBursts::7 25268 # Per bank write bursts +system.physmem.perBankRdBursts::8 25514 # Per bank write bursts +system.physmem.perBankRdBursts::9 25670 # Per bank write bursts +system.physmem.perBankRdBursts::10 25901 # Per bank write bursts +system.physmem.perBankRdBursts::11 25385 # Per bank write bursts +system.physmem.perBankRdBursts::12 25810 # Per bank write bursts +system.physmem.perBankRdBursts::13 25833 # Per bank write bursts +system.physmem.perBankRdBursts::14 25046 # Per bank write bursts +system.physmem.perBankRdBursts::15 25600 # Per bank write bursts +system.physmem.perBankWrBursts::0 8438 # Per bank write bursts +system.physmem.perBankWrBursts::1 8395 # Per bank write bursts +system.physmem.perBankWrBursts::2 7934 # Per bank write bursts +system.physmem.perBankWrBursts::3 7573 # Per bank write bursts +system.physmem.perBankWrBursts::4 7567 # Per bank write bursts +system.physmem.perBankWrBursts::5 7501 # Per bank write bursts +system.physmem.perBankWrBursts::6 7444 # Per bank write bursts +system.physmem.perBankWrBursts::7 7061 # Per bank write bursts +system.physmem.perBankWrBursts::8 7349 # Per bank write bursts +system.physmem.perBankWrBursts::9 7703 # Per bank write bursts +system.physmem.perBankWrBursts::10 7693 # Per bank write bursts +system.physmem.perBankWrBursts::11 7415 # Per bank write bursts +system.physmem.perBankWrBursts::12 7960 # Per bank write bursts +system.physmem.perBankWrBursts::13 8226 # Per bank write bursts +system.physmem.perBankWrBursts::14 7426 # Per bank write bursts +system.physmem.perBankWrBursts::15 7807 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 17 # Number of times write queue was full causing retry -system.physmem.totGap 1907667754500 # Total gap between requests +system.physmem.numWrRetry 24 # Number of times write queue was full causing retry +system.physmem.totGap 1906529083500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 409606 # Read request sizes (log2) +system.physmem.readPktSize::6 410679 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 122579 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 37968 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24690 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 78 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 123513 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 38167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see @@ -159,193 +159,209 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6901 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 9224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64695 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 526.308617 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 319.463735 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.737705 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14846 22.95% 22.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11278 17.43% 40.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5774 8.92% 49.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2666 4.12% 53.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2483 3.84% 57.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1468 2.27% 59.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1658 2.56% 62.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1459 2.26% 64.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23063 35.65% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64695 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5527 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 74.082685 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2821.240872 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5524 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1595 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 8000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 57 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64501 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 529.911784 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 323.379229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.310744 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14472 22.44% 22.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11319 17.55% 39.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5673 8.80% 48.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2735 4.24% 53.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2521 3.91% 56.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1561 2.42% 59.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1592 2.47% 61.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1422 2.20% 64.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23206 35.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64501 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5582 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 73.544966 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2807.309852 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5579 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5527 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5527 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.172969 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.909622 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.446069 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4919 89.00% 89.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 36 0.65% 89.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 243 4.40% 94.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 19 0.34% 94.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 5 0.09% 94.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 15 0.27% 94.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 14 0.25% 95.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 2 0.04% 95.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 36 0.65% 95.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 13 0.24% 95.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 182 3.29% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 3 0.05% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 2 0.04% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.04% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 4 0.07% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 3 0.05% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 5 0.09% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 4 0.07% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 1 0.02% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 2 0.04% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.04% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 12 0.22% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5527 # Writes before turning the bus around for reads -system.physmem.totQLat 3957301251 # Total ticks spent queuing -system.physmem.totMemAccLat 11634938751 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2047370000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9664.35 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5582 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5582 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.123253 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.862531 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.587113 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4829 86.51% 86.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 142 2.54% 89.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 15 0.27% 89.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 29 0.52% 89.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 220 3.94% 93.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 21 0.38% 94.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 13 0.23% 94.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.11% 94.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 3 0.05% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.14% 94.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.14% 94.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.13% 94.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 7 0.13% 95.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.05% 95.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 1 0.02% 95.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.02% 95.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 21 0.38% 95.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.04% 95.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 16 0.29% 95.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 95.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 179 3.21% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.04% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.05% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.04% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 5 0.09% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.04% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 6 0.11% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 3 0.05% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.02% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 2 0.04% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 2 0.04% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 13 0.23% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5582 # Writes before turning the bus around for reads +system.physmem.totQLat 4047296750 # Total ticks spent queuing +system.physmem.totMemAccLat 11745446750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2052840000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9857.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28414.35 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.74 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.11 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.74 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.11 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28607.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.78 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.15 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.79 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.15 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.78 # Average write queue length when enqueuing -system.physmem.readRowHits 368811 # Number of row buffer hits during reads -system.physmem.writeRowHits 98518 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.07 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.37 # Row buffer hit rate for writes -system.physmem.avgGap 3584595.12 # Average gap between requests -system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 244392120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 133348875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1582659000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 397049040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 124599742800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 57755737350 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1093939329000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1278652258185 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.268952 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1819699135250 # Time in different power states -system.physmem_0.memoryStateTime::REF 63701300000 # Time in different power states +system.physmem.avgRdQLen 2.26 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.95 # Average write queue length when enqueuing +system.physmem.readRowHits 369870 # Number of row buffer hits during reads +system.physmem.writeRowHits 99689 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.09 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.71 # Row buffer hit rate for writes +system.physmem.avgGap 3568995.95 # Average gap between requests +system.physmem.pageHitRate 87.92 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 245828520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 134132625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1605310200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 401196240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 124525493040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 58054066515 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1092995561250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1277961588390 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.306343 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1818124535500 # Time in different power states +system.physmem_0.memoryStateTime::REF 63663080000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 24270006000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 24745773250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 244702080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 133518000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1611238200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 397074960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 124599742800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 57480963435 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1094180367000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1278647606475 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.266509 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1820097449251 # Time in different power states -system.physmem_1.memoryStateTime::REF 63701300000 # Time in different power states +system.physmem_1.actEnergy 241799040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 131934000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1597120200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 399031920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 124525493040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 57215830500 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1093730864250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1277842072950 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.243651 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1819353589250 # Time in different power states +system.physmem_1.memoryStateTime::REF 63663080000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23871705749 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23516733250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.cpu0.branchPred.lookups 18486901 # Number of BP lookups -system.cpu0.branchPred.condPredicted 15748793 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 541835 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 11639433 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5170762 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.cpu0.branchPred.lookups 16961800 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14485891 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 473040 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 10754552 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4802971 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 44.424518 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 1045004 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 41208 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 5538250 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 525213 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 5013037 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 248456 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 44.659889 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 946597 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 35405 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 5065158 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 501808 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 4563350 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 210940 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 10388247 # DTB read hits -system.cpu0.dtb.read_misses 39745 # DTB read misses +system.cpu0.dtb.read_hits 9542415 # DTB read hits +system.cpu0.dtb.read_misses 34570 # DTB read misses system.cpu0.dtb.read_acv 614 # DTB read access violations -system.cpu0.dtb.read_accesses 666259 # DTB read accesses -system.cpu0.dtb.write_hits 6304219 # DTB write hits -system.cpu0.dtb.write_misses 9494 # DTB write misses -system.cpu0.dtb.write_acv 419 # DTB write access violations -system.cpu0.dtb.write_accesses 221498 # DTB write accesses -system.cpu0.dtb.data_hits 16692466 # DTB hits -system.cpu0.dtb.data_misses 49239 # DTB misses -system.cpu0.dtb.data_acv 1033 # DTB access violations -system.cpu0.dtb.data_accesses 887757 # DTB accesses -system.cpu0.itb.fetch_hits 1498511 # ITB hits -system.cpu0.itb.fetch_misses 7842 # ITB misses -system.cpu0.itb.fetch_acv 715 # ITB acv -system.cpu0.itb.fetch_accesses 1506353 # ITB accesses +system.cpu0.dtb.read_accesses 570502 # DTB read accesses +system.cpu0.dtb.write_hits 5776455 # DTB write hits +system.cpu0.dtb.write_misses 8473 # DTB write misses +system.cpu0.dtb.write_acv 390 # DTB write access violations +system.cpu0.dtb.write_accesses 186760 # DTB write accesses +system.cpu0.dtb.data_hits 15318870 # DTB hits +system.cpu0.dtb.data_misses 43043 # DTB misses +system.cpu0.dtb.data_acv 1004 # DTB access violations +system.cpu0.dtb.data_accesses 757262 # DTB accesses +system.cpu0.itb.fetch_hits 1323023 # ITB hits +system.cpu0.itb.fetch_misses 7096 # ITB misses +system.cpu0.itb.fetch_acv 610 # ITB acv +system.cpu0.itb.fetch_accesses 1330119 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -358,606 +374,606 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 12731 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 6366 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 290215354.618913 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 443182270.048279 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 4 0.06% 0.06% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 6362 99.94% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.numPwrStateTransitions 13007 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 6504 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 284289977.091175 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 440390387.503353 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 6503 99.98% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 6366 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 60161154996 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1847510947504 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 120328672 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::total 6504 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 57511518999 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849022011001 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 115029541 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 28758768 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 80605672 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 18486901 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6740979 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 84470777 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1538724 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 99 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 28344 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 156668 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 425628 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 282 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 9251036 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 365043 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.icacheStallCycles 26105514 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 74391279 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 16961800 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6251376 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 82220028 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1360432 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 20 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 28534 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 140847 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 424678 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 286 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8564382 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 320281 # Number of outstanding Icache misses that were squashed system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 114609928 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.703304 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.035053 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::samples 109600123 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.678752 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.000671 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 99708886 87.00% 87.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 974143 0.85% 87.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1998972 1.74% 89.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 868407 0.76% 90.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2758687 2.41% 92.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 641235 0.56% 93.32% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 755467 0.66% 93.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 978409 0.85% 94.83% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5925722 5.17% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 95795479 87.40% 87.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 897061 0.82% 88.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1880834 1.72% 89.94% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 785387 0.72% 90.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2637004 2.41% 93.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 588358 0.54% 93.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 697546 0.64% 94.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 846325 0.77% 95.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5472129 4.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 114609928 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.153637 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.669879 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 23115734 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 79187494 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9649471 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1920435 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 736793 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 689182 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 33223 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 69733339 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 101960 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 736793 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 24053074 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 52045501 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18448869 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10567955 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 8757734 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 66954427 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 200777 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2040075 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 234878 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 4698433 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 45085797 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 80572701 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 80419250 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 143477 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 36303569 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8782228 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1592248 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 261178 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 13101083 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10872978 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6724173 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1603556 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1060240 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 59089633 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 2074933 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 57153011 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 84826 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10861661 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 4738821 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1447538 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 114609928 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.498674 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.243633 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 109600123 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.147456 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.646715 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 20981522 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 77286866 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8861450 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1818601 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 651683 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 621495 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 29133 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 64563390 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 88112 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 651683 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 21851256 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 51776932 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17156942 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9742291 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 8421017 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 62086646 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 197170 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2004328 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 218757 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 4545100 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 41879351 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 74952395 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 74819888 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 123702 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34134806 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 7744545 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1440211 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 234687 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12404512 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9945616 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6151141 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1474462 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 959878 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 54892526 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1879962 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 53219239 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 73531 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9606336 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 4159079 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1308684 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 109600123 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.485576 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.229164 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 91405720 79.75% 79.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9883367 8.62% 88.38% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4163005 3.63% 92.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2977529 2.60% 94.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 3083312 2.69% 97.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1549770 1.35% 98.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 1029487 0.90% 99.55% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 389877 0.34% 99.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 127861 0.11% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 87964311 80.26% 80.26% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9240201 8.43% 88.69% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3866881 3.53% 92.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2775272 2.53% 94.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2892547 2.64% 97.39% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1421694 1.30% 98.69% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 953270 0.87% 99.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 366394 0.33% 99.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 119553 0.11% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 114609928 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 109600123 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 177461 15.95% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 15.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 577417 51.89% 67.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 357940 32.17% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 170160 16.71% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.71% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 520319 51.11% 67.82% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 327644 32.18% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3316 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 38903396 68.07% 68.07% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 60002 0.10% 68.18% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.18% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 28431 0.05% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1656 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 10881663 19.04% 87.27% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6404122 11.21% 98.48% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 870425 1.52% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2537 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 36500931 68.59% 68.59% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56437 0.11% 68.70% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.70% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 25510 0.05% 68.74% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.74% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.74% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.74% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.75% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9976302 18.75% 87.49% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5867670 11.03% 98.52% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 788585 1.48% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 57153011 # Type of FU issued -system.cpu0.iq.rate 0.474974 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1112818 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019471 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 229452003 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 71724793 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 55161872 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 661591 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 320309 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 299753 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 57905331 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 357182 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 649944 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 53219239 # Type of FU issued +system.cpu0.iq.rate 0.462657 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1018124 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019131 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 216556534 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 66119650 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 51474452 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 573722 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 277081 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 260310 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 53925009 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 309817 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 608784 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2311061 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3974 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 19354 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 772397 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1996070 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4265 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 18313 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 688901 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18463 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 400325 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18448 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 363376 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 736793 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 48901711 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 778245 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 65010536 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 175759 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10872978 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6724173 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1839088 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 42617 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 533932 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 19354 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 209386 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 582195 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 791581 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 56370431 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 10457447 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 782580 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 651683 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 48679015 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 759858 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 60350483 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 162315 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9945616 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6151141 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1664805 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40490 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 518912 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 18313 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 186521 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 513145 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 699666 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 52530190 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9602772 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 689049 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3845970 # number of nop insts executed -system.cpu0.iew.exec_refs 16790279 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8937296 # Number of branches executed -system.cpu0.iew.exec_stores 6332832 # Number of stores executed -system.cpu0.iew.exec_rate 0.468470 # Inst execution rate -system.cpu0.iew.wb_sent 55678100 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 55461625 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 28192926 # num instructions producing a value -system.cpu0.iew.wb_consumers 39039520 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.460918 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.722164 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 11448425 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 627395 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 706831 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 112623597 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.474128 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.409611 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 3577995 # number of nop insts executed +system.cpu0.iew.exec_refs 15404618 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8349417 # Number of branches executed +system.cpu0.iew.exec_stores 5801846 # Number of stores executed +system.cpu0.iew.exec_rate 0.456667 # Inst execution rate +system.cpu0.iew.wb_sent 51922146 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51734762 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26504573 # num instructions producing a value +system.cpu0.iew.wb_consumers 36648490 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.449752 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.723211 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 10116425 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 571278 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 623596 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 107842796 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.464314 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.394503 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 93749029 83.24% 83.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7554104 6.71% 89.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4011836 3.56% 93.51% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2145505 1.91% 95.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1663134 1.48% 96.89% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 616876 0.55% 97.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 455080 0.40% 97.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 507934 0.45% 98.30% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1920099 1.70% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 90117032 83.56% 83.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7061240 6.55% 90.11% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3809100 3.53% 93.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2021336 1.87% 95.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1578999 1.46% 96.98% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 575276 0.53% 97.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 421394 0.39% 97.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 458654 0.43% 98.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1799765 1.67% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 112623597 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 53398017 # Number of instructions committed -system.cpu0.commit.committedOps 53398017 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 107842796 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 50072886 # Number of instructions committed +system.cpu0.commit.committedOps 50072886 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14513693 # Number of memory references committed -system.cpu0.commit.loads 8561917 # Number of loads committed -system.cpu0.commit.membars 214579 # Number of memory barriers committed -system.cpu0.commit.branches 8068022 # Number of branches committed -system.cpu0.commit.fp_insts 288973 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 49410509 # Number of committed integer instructions. -system.cpu0.commit.function_calls 696168 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 3098426 5.80% 5.80% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 34606705 64.81% 70.61% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 58588 0.11% 70.72% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.72% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 27960 0.05% 70.77% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.77% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.77% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.77% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1656 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.78% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8776496 16.44% 87.21% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5957761 11.16% 98.37% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 870425 1.63% 100.00% # Class of committed instruction +system.cpu0.commit.refs 13411786 # Number of memory references committed +system.cpu0.commit.loads 7949546 # Number of loads committed +system.cpu0.commit.membars 194670 # Number of memory barriers committed +system.cpu0.commit.branches 7579863 # Number of branches committed +system.cpu0.commit.fp_insts 251347 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 46348996 # Number of committed integer instructions. +system.cpu0.commit.function_calls 640938 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2909270 5.81% 5.81% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 32681197 65.27% 71.08% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55117 0.11% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.19% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 25038 0.05% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1267 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8144216 16.26% 87.50% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5468196 10.92% 98.43% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 788585 1.57% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 53398017 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1920099 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 175358628 # The number of ROB reads -system.cpu0.rob.rob_writes 131681344 # The number of ROB writes -system.cpu0.timesIdled 541437 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 5718744 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3694399415 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 50302904 # Number of Instructions Simulated -system.cpu0.committedOps 50302904 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.392082 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.392082 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.418046 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.418046 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 73576817 # number of integer regfile reads -system.cpu0.int_regfile_writes 40321383 # number of integer regfile writes -system.cpu0.fp_regfile_reads 142542 # number of floating regfile reads -system.cpu0.fp_regfile_writes 152983 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1859375 # number of misc regfile reads -system.cpu0.misc_regfile_writes 873240 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1336574 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.845930 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11809421 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1336976 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.832934 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 50072886 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1799765 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 166055766 # The number of ROB reads +system.cpu0.rob.rob_writes 122136916 # The number of ROB writes +system.cpu0.timesIdled 488999 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 5429418 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3697477415 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 47166151 # Number of Instructions Simulated +system.cpu0.committedOps 47166151 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.438816 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.438816 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.410035 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.410035 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 68768616 # number of integer regfile reads +system.cpu0.int_regfile_writes 37693548 # number of integer regfile writes +system.cpu0.fp_regfile_reads 122704 # number of floating regfile reads +system.cpu0.fp_regfile_writes 131478 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1676808 # number of misc regfile reads +system.cpu0.misc_regfile_writes 792469 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 1260860 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.428743 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10814422 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1261290 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.574096 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 26822500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.845930 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.987980 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.987980 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 399 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 62763513 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 62763513 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 7501117 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7501117 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3904271 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3904271 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 200075 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 200075 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 202804 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 202804 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11405388 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11405388 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11405388 # number of overall hits -system.cpu0.dcache.overall_hits::total 11405388 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1695209 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1695209 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1829361 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1829361 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22067 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22067 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 927 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 927 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3524570 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3524570 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3524570 # number of overall misses -system.cpu0.dcache.overall_misses::total 3524570 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40549578500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 40549578500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77276130293 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 77276130293 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 333041000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 333041000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 6753500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 6753500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 117825708793 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 117825708793 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 117825708793 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 117825708793 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 9196326 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 9196326 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5733632 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5733632 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 222142 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 222142 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 203731 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 203731 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14929958 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14929958 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14929958 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14929958 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.184335 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.184335 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.319058 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.319058 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.099337 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.099337 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004550 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004550 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.236074 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.236074 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.236074 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.236074 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23920.105721 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 23920.105721 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42242.143728 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 42242.143728 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15092.264467 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15092.264467 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7285.329018 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7285.329018 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33429.810954 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33429.810954 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33429.810954 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33429.810954 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 4313991 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 8795 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 119168 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 132 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 36.200918 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 66.628788 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 791920 # number of writebacks -system.cpu0.dcache.writebacks::total 791920 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 639925 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 639925 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1556053 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1556053 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 6507 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 6507 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2195978 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2195978 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2195978 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2195978 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1055284 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1055284 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 273308 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 273308 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15560 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15560 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 926 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 926 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1328592 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1328592 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1328592 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1328592 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7032 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7032 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9755 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9755 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16787 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16787 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30284931500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30284931500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12180596213 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12180596213 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 192236000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 192236000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5827500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5827500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 42465527713 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 42465527713 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 42465527713 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 42465527713 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1566422000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1566422000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1566422000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1566422000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.114751 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.114751 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.047668 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.047668 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.070045 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.070045 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004545 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004545 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.088988 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.088988 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.088988 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.088988 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28698.370770 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28698.370770 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44567.287503 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44567.287503 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12354.498715 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12354.498715 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6293.196544 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6293.196544 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31962.805521 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31962.805521 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31962.805521 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31962.805521 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222756.257110 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222756.257110 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93311.610175 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93311.610175 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1014611 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.545427 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 8173897 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1015123 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.052125 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 28452447500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.545427 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995206 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.995206 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 10266395 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 10266395 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 8173897 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 8173897 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 8173897 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 8173897 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 8173897 # number of overall hits -system.cpu0.icache.overall_hits::total 8173897 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1077136 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1077136 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1077136 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1077136 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1077136 # number of overall misses -system.cpu0.icache.overall_misses::total 1077136 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 15255278493 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 15255278493 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 15255278493 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 15255278493 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 15255278493 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 15255278493 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 9251033 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 9251033 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 9251033 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 9251033 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 9251033 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 9251033 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116434 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.116434 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116434 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.116434 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116434 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.116434 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14162.815553 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14162.815553 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14162.815553 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14162.815553 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14162.815553 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14162.815553 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5826 # number of cycles access was blocked +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.428743 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.989119 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.989119 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 412 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.839844 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 57625075 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 57625075 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 6881291 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6881291 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3568585 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3568585 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 177059 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 177059 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 182551 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 182551 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10449876 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10449876 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10449876 # number of overall hits +system.cpu0.dcache.overall_hits::total 10449876 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1562512 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1562512 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1693924 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1693924 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20209 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20209 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2828 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2828 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3256436 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3256436 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3256436 # number of overall misses +system.cpu0.dcache.overall_misses::total 3256436 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 38980676000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 38980676000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 74553561151 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 74553561151 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 291267500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 291267500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 15945500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 15945500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 113534237151 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 113534237151 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 113534237151 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 113534237151 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8443803 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8443803 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5262509 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5262509 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 197268 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 197268 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 185379 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 185379 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13706312 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13706312 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13706312 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13706312 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.185048 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.185048 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.321885 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.321885 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.102444 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.102444 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015255 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015255 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.237587 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.237587 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.237587 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.237587 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24947.441044 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 24947.441044 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44012.341257 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44012.341257 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14412.761641 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14412.761641 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5638.437058 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5638.437058 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34864.568857 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 34864.568857 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34864.568857 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34864.568857 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 4192146 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2471 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 109181 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 83 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 38.396296 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 29.771084 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 743371 # number of writebacks +system.cpu0.dcache.writebacks::total 743371 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 555767 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 555767 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1440437 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1440437 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5460 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5460 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1996204 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1996204 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1996204 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1996204 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1006745 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1006745 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 253487 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 253487 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14749 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14749 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2828 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2828 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1260232 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1260232 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1260232 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1260232 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7013 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7013 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10003 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10003 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17016 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17016 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 29619600000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 29619600000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11703772725 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11703772725 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 170858500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 170858500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 13117500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 13117500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 41323372725 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 41323372725 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 41323372725 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 41323372725 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1563340000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1563340000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1563340000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1563340000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.119229 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.119229 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048168 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048168 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.074766 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.074766 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015255 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015255 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091945 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.091945 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091945 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.091945 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29421.154314 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29421.154314 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46171.096447 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46171.096447 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11584.412503 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11584.412503 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4638.437058 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4638.437058 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32790.289982 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32790.289982 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32790.289982 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32790.289982 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222920.290888 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222920.290888 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 91874.706159 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 91874.706159 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 908505 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.512047 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7601055 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 909016 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.361850 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 28452405500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.512047 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995141 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995141 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 498 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 9473645 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 9473645 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 7601055 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7601055 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7601055 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7601055 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7601055 # number of overall hits +system.cpu0.icache.overall_hits::total 7601055 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 963326 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 963326 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 963326 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 963326 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 963326 # number of overall misses +system.cpu0.icache.overall_misses::total 963326 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13819823495 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13819823495 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13819823495 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13819823495 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13819823495 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13819823495 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8564381 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8564381 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8564381 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8564381 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8564381 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8564381 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.112481 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.112481 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.112481 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.112481 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.112481 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.112481 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14345.946746 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14345.946746 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14345.946746 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14345.946746 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14345.946746 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14345.946746 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 6257 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 231 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 203 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.220779 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 30.822660 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1014611 # number of writebacks -system.cpu0.icache.writebacks::total 1014611 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 61774 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 61774 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 61774 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 61774 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 61774 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 61774 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1015362 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1015362 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1015362 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1015362 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1015362 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1015362 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13566878495 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 13566878495 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13566878495 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 13566878495 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13566878495 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 13566878495 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.109757 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.109757 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.109757 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.109757 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.109757 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.109757 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13361.617330 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13361.617330 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13361.617330 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13361.617330 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13361.617330 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13361.617330 # average overall mshr miss latency -system.cpu1.branchPred.lookups 2716012 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2349135 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 64284 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1339574 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 486642 # Number of BTB hits +system.cpu0.icache.writebacks::writebacks 908505 # number of writebacks +system.cpu0.icache.writebacks::total 908505 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54062 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 54062 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 54062 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 54062 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 54062 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 54062 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 909264 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 909264 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 909264 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 909264 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 909264 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 909264 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12278033496 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12278033496 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12278033496 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12278033496 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12278033496 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12278033496 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.106168 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.106168 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.106168 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.106168 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.106168 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.106168 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13503.265824 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13503.265824 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13503.265824 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13503.265824 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13503.265824 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13503.265824 # average overall mshr miss latency +system.cpu1.branchPred.lookups 4250134 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3659200 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 108723 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2354380 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 849662 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 36.328116 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 131116 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 4300 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 740387 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 107863 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 632524 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 18463 # Number of mispredicted indirect branches. +system.cpu1.branchPred.BTBHitPct 36.088567 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 217108 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 8204 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 1308734 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 157441 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1151293 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 37897 # Number of mispredicted indirect branches. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1491854 # DTB read hits -system.cpu1.dtb.read_misses 11707 # DTB read misses -system.cpu1.dtb.read_acv 49 # DTB read access violations -system.cpu1.dtb.read_accesses 336889 # DTB read accesses -system.cpu1.dtb.write_hits 824931 # DTB write hits -system.cpu1.dtb.write_misses 2806 # DTB write misses -system.cpu1.dtb.write_acv 46 # DTB write access violations -system.cpu1.dtb.write_accesses 126281 # DTB write accesses -system.cpu1.dtb.data_hits 2316785 # DTB hits -system.cpu1.dtb.data_misses 14513 # DTB misses -system.cpu1.dtb.data_acv 95 # DTB access violations -system.cpu1.dtb.data_accesses 463170 # DTB accesses -system.cpu1.itb.fetch_hits 477856 # ITB hits -system.cpu1.itb.fetch_misses 2662 # ITB misses -system.cpu1.itb.fetch_acv 96 # ITB acv -system.cpu1.itb.fetch_accesses 480518 # ITB accesses +system.cpu1.dtb.read_hits 2331871 # DTB read hits +system.cpu1.dtb.read_misses 15400 # DTB read misses +system.cpu1.dtb.read_acv 73 # DTB read access violations +system.cpu1.dtb.read_accesses 429786 # DTB read accesses +system.cpu1.dtb.write_hits 1381774 # DTB write hits +system.cpu1.dtb.write_misses 3743 # DTB write misses +system.cpu1.dtb.write_acv 71 # DTB write access violations +system.cpu1.dtb.write_accesses 161427 # DTB write accesses +system.cpu1.dtb.data_hits 3713645 # DTB hits +system.cpu1.dtb.data_misses 19143 # DTB misses +system.cpu1.dtb.data_acv 144 # DTB access violations +system.cpu1.dtb.data_accesses 591213 # DTB accesses +system.cpu1.itb.fetch_hits 662529 # ITB hits +system.cpu1.itb.fetch_misses 3380 # ITB misses +system.cpu1.itb.fetch_acv 133 # ITB acv +system.cpu1.itb.fetch_accesses 665909 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -970,580 +986,572 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numPwrStateTransitions 4646 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2323 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 818936669.177787 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 339506423.560652 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 2323 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.numPwrStateTransitions 4980 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2490 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 762354971.285141 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 386526411.344669 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 2490 100.00% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 975573000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2323 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 5282220000 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1902389882500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 10566764 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 975501000 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2490 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 8269651500 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1898263878500 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 16541794 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 3825216 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 10675597 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2716012 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 725621 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 5983543 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 229964 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 23815 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 51735 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 41039 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1221851 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 48225 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 10040370 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.063267 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.470833 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 6749073 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 16895090 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4250134 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1224211 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 8698208 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 363130 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 26231 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 65753 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 47571 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1900929 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 80768 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 15768440 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.071450 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.476995 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 8168289 81.35% 81.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 102687 1.02% 82.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 210133 2.09% 84.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 146343 1.46% 85.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 249317 2.48% 88.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 97935 0.98% 89.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 113554 1.13% 90.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 71548 0.71% 91.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 880564 8.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 12797159 81.16% 81.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 186632 1.18% 82.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 321640 2.04% 84.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 225512 1.43% 85.81% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 384419 2.44% 88.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 144313 0.92% 89.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 169042 1.07% 90.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 202635 1.29% 91.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1337088 8.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 10040370 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.257033 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.010300 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 3212898 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 5233388 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1306839 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 176592 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 110652 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 87490 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 4477 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 8611500 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 14236 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 110652 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 3332108 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 534859 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 3861101 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1363516 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 838132 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 8128723 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 840 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 81504 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 20811 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 431912 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 5442265 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 9792683 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 9760108 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 27875 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 4220598 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1221659 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 323796 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 24055 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1462372 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1548375 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 895151 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 190303 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 111620 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 7151730 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 356002 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 6823456 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 19520 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1627236 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 806919 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 274884 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 10040370 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.679602 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.404814 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 15768440 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.256933 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.021358 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5523877 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 7693314 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2103455 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 273251 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 174542 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 146034 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 7171 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 13792543 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 22640 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 174542 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5705734 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 782365 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5725411 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2195690 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1184696 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 13060888 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 4153 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 107025 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 30497 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 586772 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 8670673 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 15585724 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 15521516 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 57730 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 6788049 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1882616 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 491915 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 50500 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2201368 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2434805 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1482534 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 303562 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 164759 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 11452007 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 560044 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 10991859 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 27120 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2468765 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1174488 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 414117 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 15768440 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.697080 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.421678 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 7219551 71.91% 71.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1226248 12.21% 84.12% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 523144 5.21% 89.33% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 383300 3.82% 93.15% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 329501 3.28% 96.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 173963 1.73% 98.16% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 102712 1.02% 99.18% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 58679 0.58% 99.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 23272 0.23% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 11265469 71.44% 71.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1937394 12.29% 83.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 827410 5.25% 88.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 596936 3.79% 92.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 547934 3.47% 96.24% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 289502 1.84% 98.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 188780 1.20% 99.27% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 83209 0.53% 99.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 31806 0.20% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 10040370 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 15768440 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 25321 11.84% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 11.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 118979 55.64% 67.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 69548 32.52% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 32091 10.27% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 173932 55.66% 65.93% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 106485 34.07% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3973 0.06% 0.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 4192346 61.44% 61.50% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 10770 0.16% 61.66% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.66% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10332 0.15% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.81% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1986 0.03% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1560504 22.87% 84.71% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 845461 12.39% 97.10% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 198084 2.90% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 4751 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 6803980 61.90% 61.94% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 16523 0.15% 62.09% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.09% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 13867 0.13% 62.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.24% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2450394 22.29% 84.53% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1410696 12.83% 97.37% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 289273 2.63% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 6823456 # Type of FU issued -system.cpu1.iq.rate 0.645747 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 213848 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.031340 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 23830038 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 9093503 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 6518367 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 90611 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 45521 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 43008 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 6985974 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 47357 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 77493 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 10991859 # Type of FU issued +system.cpu1.iq.rate 0.664490 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 312508 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.028431 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 37874505 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 14381418 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 10489971 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 217280 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 104295 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 101356 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 11183979 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 115637 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 113432 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 335188 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 932 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4197 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 122462 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 527848 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1066 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 5067 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 174171 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 439 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 72925 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 475 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 99025 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 110652 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 347034 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 152695 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 7850434 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 37055 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1548375 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 895151 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 329794 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4928 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 146829 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4197 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 25483 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 92224 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 117707 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 6707770 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1507715 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 115685 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 174542 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 497039 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 226226 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 12632900 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 57966 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2434805 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1482534 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 508876 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 6584 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 218362 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 5067 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 44763 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 141821 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 186584 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 10809707 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2356029 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 182151 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 342702 # number of nop insts executed -system.cpu1.iew.exec_refs 2339108 # number of memory reference insts executed -system.cpu1.iew.exec_branches 982956 # Number of branches executed -system.cpu1.iew.exec_stores 831393 # Number of stores executed -system.cpu1.iew.exec_rate 0.634799 # Inst execution rate -system.cpu1.iew.wb_sent 6597173 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 6561375 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 3197425 # num instructions producing a value -system.cpu1.iew.wb_consumers 4464974 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.620945 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.716113 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 1594434 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 81118 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 100274 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 9755465 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.627758 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.585985 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 620849 # number of nop insts executed +system.cpu1.iew.exec_refs 3747857 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1612675 # Number of branches executed +system.cpu1.iew.exec_stores 1391828 # Number of stores executed +system.cpu1.iew.exec_rate 0.653479 # Inst execution rate +system.cpu1.iew.wb_sent 10644010 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 10591327 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 5073681 # num instructions producing a value +system.cpu1.iew.wb_consumers 7144079 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.640277 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.710194 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 2479122 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 145927 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 162123 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 15327061 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.652859 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.628724 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 7484983 76.73% 76.73% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1079374 11.06% 87.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 367183 3.76% 91.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 234920 2.41% 93.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 168491 1.73% 95.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 74517 0.76% 96.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 76064 0.78% 97.23% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 56824 0.58% 97.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 213109 2.18% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 11704556 76.37% 76.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1675096 10.93% 87.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 596024 3.89% 91.18% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 370132 2.41% 93.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 281840 1.84% 95.44% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 119415 0.78% 96.22% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 109784 0.72% 96.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 115974 0.76% 97.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 354240 2.31% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 9755465 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 6124073 # Number of instructions committed -system.cpu1.commit.committedOps 6124073 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 15327061 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 10006417 # Number of instructions committed +system.cpu1.commit.committedOps 10006417 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 1985876 # Number of memory references committed -system.cpu1.commit.loads 1213187 # Number of loads committed -system.cpu1.commit.membars 22586 # Number of memory barriers committed -system.cpu1.commit.branches 866488 # Number of branches committed -system.cpu1.commit.fp_insts 41227 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 5722327 # Number of committed integer instructions. -system.cpu1.commit.function_calls 95129 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 247554 4.04% 4.04% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 3646853 59.55% 63.59% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 10597 0.17% 63.76% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 63.76% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 10326 0.17% 63.93% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 63.93% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 63.93% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 63.93% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1986 0.03% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.97% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1235773 20.18% 84.14% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 772900 12.62% 96.77% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 198084 3.23% 100.00% # Class of committed instruction +system.cpu1.commit.refs 3215320 # Number of memory references committed +system.cpu1.commit.loads 1906957 # Number of loads committed +system.cpu1.commit.membars 46297 # Number of memory barriers committed +system.cpu1.commit.branches 1432968 # Number of branches committed +system.cpu1.commit.fp_insts 99355 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 9296453 # Number of committed integer instructions. +system.cpu1.commit.function_calls 155642 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 467886 4.68% 4.68% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 5954632 59.51% 64.18% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 16225 0.16% 64.35% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 13860 0.14% 64.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1953254 19.52% 84.03% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1308912 13.08% 97.11% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 289273 2.89% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 6124073 # Class of committed instruction -system.cpu1.commit.bw_lim_events 213109 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 17170417 # The number of ROB reads -system.cpu1.rob.rob_writes 15719262 # The number of ROB writes -system.cpu1.timesIdled 71397 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 526394 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3804777442 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 5880491 # Number of Instructions Simulated -system.cpu1.committedOps 5880491 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.796919 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.796919 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.556508 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.556508 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 8685381 # number of integer regfile reads -system.cpu1.int_regfile_writes 4740732 # number of integer regfile writes -system.cpu1.fp_regfile_reads 27201 # number of floating regfile reads -system.cpu1.fp_regfile_writes 25643 # number of floating regfile writes -system.cpu1.misc_regfile_reads 310247 # number of misc regfile reads -system.cpu1.misc_regfile_writes 141917 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 65099 # number of replacements -system.cpu1.dcache.tags.tagsinuse 463.722972 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 1848833 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 65611 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.178705 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1879972526500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 463.722972 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.905709 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.905709 # Average percentage of cache occupancy +system.cpu1.commit.op_class_0::total 10006417 # Class of committed instruction +system.cpu1.commit.bw_lim_events 354240 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 27350454 # The number of ROB reads +system.cpu1.rob.rob_writes 25410376 # The number of ROB writes +system.cpu1.timesIdled 127916 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 773354 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3796525267 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 9543281 # Number of Instructions Simulated +system.cpu1.committedOps 9543281 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.733345 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.733345 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.576919 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.576919 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 13915898 # number of integer regfile reads +system.cpu1.int_regfile_writes 7574327 # number of integer regfile writes +system.cpu1.fp_regfile_reads 57027 # number of floating regfile reads +system.cpu1.fp_regfile_writes 56084 # number of floating regfile writes +system.cpu1.misc_regfile_reads 548336 # number of misc regfile reads +system.cpu1.misc_regfile_writes 233992 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 125899 # number of replacements +system.cpu1.dcache.tags.tagsinuse 488.643443 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 2930828 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 126411 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.184913 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 47496090500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 488.643443 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.954382 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.954382 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 8556411 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 8556411 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 1222356 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1222356 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 588321 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 588321 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 17437 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 17437 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 16296 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 16296 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1810677 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1810677 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1810677 # number of overall hits -system.cpu1.dcache.overall_hits::total 1810677 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 112363 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 112363 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 161965 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 161965 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1793 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1793 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 891 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 891 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 274328 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 274328 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 274328 # number of overall misses -system.cpu1.dcache.overall_misses::total 274328 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1482127500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1482127500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7331574147 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 7331574147 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 19537500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 19537500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 6718500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 6718500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 34500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 34500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8813701647 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8813701647 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8813701647 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8813701647 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1334719 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1334719 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 750286 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 750286 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 19230 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 19230 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 17187 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 17187 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2085005 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2085005 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2085005 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2085005 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.084185 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.084185 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.215871 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.215871 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.093240 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.093240 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.051842 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.051842 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.131572 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.131572 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.131572 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.131572 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13190.529801 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13190.529801 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 45266.410317 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 45266.410317 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10896.542108 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10896.542108 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7540.404040 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7540.404040 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32128.334137 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 32128.334137 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32128.334137 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 32128.334137 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 454264 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 482 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 15527 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 29.256392 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 48.200000 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 38456 # number of writebacks -system.cpu1.dcache.writebacks::total 38456 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 66033 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 66033 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 137281 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 137281 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 379 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 379 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 203314 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 203314 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 203314 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 203314 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 46330 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 46330 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 24684 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 24684 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1414 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1414 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 891 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 891 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 71014 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 71014 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 71014 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 71014 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 162 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 162 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2639 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2639 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 2801 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 2801 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 590183000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 590183000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1153615997 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1153615997 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 13566500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 13566500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5828500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5828500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 33500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 33500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1743798997 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1743798997 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1743798997 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1743798997 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 32350500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 32350500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 32350500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 32350500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.034711 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.034711 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032899 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032899 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.073531 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.073531 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.051842 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.051842 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034059 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.034059 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034059 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.034059 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12738.679042 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12738.679042 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46735.375020 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 46735.375020 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9594.413013 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9594.413013 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 6541.526375 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 6541.526375 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24555.707283 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24555.707283 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24555.707283 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24555.707283 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 199694.444444 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 199694.444444 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 11549.625134 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 11549.625134 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 129926 # number of replacements -system.cpu1.icache.tags.tagsinuse 466.448190 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1084325 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 130435 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 8.313144 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1880575078500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 466.448190 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.911032 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.911032 # Average percentage of cache occupancy +system.cpu1.dcache.tags.tag_accesses 13906652 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 13906652 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 1865609 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1865609 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 981966 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 981966 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 38120 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 38120 # 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number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2912 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 514242 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 514242 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 514242 # number of overall misses +system.cpu1.dcache.overall_misses::total 514242 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3027811000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3027811000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10676531998 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 10676531998 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 51207500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 51207500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 16199500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 16199500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 13704342998 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 13704342998 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 13704342998 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 13704342998 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2097428 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2097428 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1264389 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1264389 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 43198 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 43198 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 37769 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 37769 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3361817 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3361817 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3361817 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3361817 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110525 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.110525 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.223367 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.223367 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117552 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117552 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.077100 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.077100 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.152965 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.152965 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.152965 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.152965 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13061.099392 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13061.099392 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37803.337540 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 37803.337540 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10084.186688 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10084.186688 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5563.015110 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5563.015110 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26649.598823 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 26649.598823 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26649.598823 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 26649.598823 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 625764 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 300 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 24254 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 19 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 25.800445 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 15.789474 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 81179 # number of writebacks +system.cpu1.dcache.writebacks::total 81179 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 142547 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 142547 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 235954 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 235954 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 779 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 779 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 378501 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 378501 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 378501 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 378501 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 89272 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 89272 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 46469 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 46469 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4299 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4299 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2912 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 2912 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 135741 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 135741 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 135741 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 135741 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 182 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 182 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3016 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3016 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3198 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3198 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1142608000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1142608000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1700967690 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1700967690 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 38610000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 38610000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 13287500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 13287500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2843575690 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2843575690 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2843575690 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2843575690 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 35749500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 35749500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 35749500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 35749500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042563 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042563 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036752 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036752 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.099518 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.099518 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.077100 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.077100 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040377 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.040377 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040377 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.040377 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12799.175553 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12799.175553 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36604.353225 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36604.353225 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8981.158409 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8981.158409 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4563.015110 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4563.015110 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20948.539424 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20948.539424 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20948.539424 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20948.539424 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 196425.824176 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 196425.824176 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 11178.705441 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 11178.705441 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 243897 # number of replacements +system.cpu1.icache.tags.tagsinuse 471.203096 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1645008 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 244406 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 6.730637 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1879506005500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 471.203096 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.920319 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.920319 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 419 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 420 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 1352346 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 1352346 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 1084325 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1084325 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1084325 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1084325 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1084325 # number of overall hits -system.cpu1.icache.overall_hits::total 1084325 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 137526 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 137526 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 137526 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 137526 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 137526 # number of overall misses -system.cpu1.icache.overall_misses::total 137526 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1969078999 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1969078999 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1969078999 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1969078999 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1969078999 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1969078999 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1221851 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1221851 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1221851 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1221851 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1221851 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1221851 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.112555 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.112555 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.112555 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.112555 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14317.867160 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14317.867160 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14317.867160 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14317.867160 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14317.867160 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14317.867160 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 342 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 2145410 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 2145410 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 1645008 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1645008 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1645008 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1645008 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1645008 # number of overall hits +system.cpu1.icache.overall_hits::total 1645008 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 255921 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 255921 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 255921 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 255921 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 255921 # number of overall misses +system.cpu1.icache.overall_misses::total 255921 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3476894499 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3476894499 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3476894499 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3476894499 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3476894499 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3476894499 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1900929 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1900929 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1900929 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1900929 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1900929 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1900929 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.134629 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.134629 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.134629 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.134629 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.134629 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.134629 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13585.811633 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13585.811633 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13585.811633 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13585.811633 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13585.811633 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13585.811633 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 470 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 30 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 38 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.400000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.368421 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 129926 # number of writebacks -system.cpu1.icache.writebacks::total 129926 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7031 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 7031 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 7031 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 7031 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 7031 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 7031 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 130495 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 130495 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 130495 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 130495 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 130495 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 130495 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1753458499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 1753458499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1753458499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 1753458499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1753458499 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 1753458499 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.106801 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.106801 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.106801 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.106801 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.106801 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.106801 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13436.978421 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13436.978421 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13436.978421 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13436.978421 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13436.978421 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13436.978421 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 243897 # number of writebacks +system.cpu1.icache.writebacks::total 243897 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 11440 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 11440 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 11440 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 11440 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 11440 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 11440 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 244481 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 244481 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 244481 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 244481 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 244481 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 244481 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3131245499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3131245499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3131245499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3131245499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3131245499 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3131245499 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.128611 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.128611 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.128611 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.128611 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.128611 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.128611 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12807.725341 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12807.725341 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12807.725341 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12807.725341 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12807.725341 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12807.725341 # average overall mshr miss latency system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1556,13 +1564,13 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 7367 # Transaction distribution -system.iobus.trans_dist::ReadResp 7367 # Transaction distribution -system.iobus.trans_dist::WriteReq 53946 # Transaction distribution -system.iobus.trans_dist::WriteResp 53946 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10580 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 7374 # Transaction distribution +system.iobus.trans_dist::ReadResp 7374 # Transaction distribution +system.iobus.trans_dist::WriteReq 54571 # Transaction distribution +system.iobus.trans_dist::WriteResp 54571 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11828 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1570,12 +1578,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1814 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 39176 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 122626 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 42320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40428 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 123890 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1583,74 +1591,74 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 68530 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2730138 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 10859000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 73538 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2735194 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 12271500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 821000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 818000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 178000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 178500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14076000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14105000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2828000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6060001 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6057000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216164058 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216200796 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 26782000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27409000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41958000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 41693 # number of replacements -system.iocache.tags.tagsinuse 0.508375 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 41699 # number of replacements +system.iocache.tags.tagsinuse 0.499134 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41709 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1712300354000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.508375 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.031773 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.031773 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1712299837000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.499134 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.031196 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.031196 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375525 # Number of tag accesses -system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses -system.iocache.ReadReq_misses::total 173 # number of ReadReq misses +system.iocache.tags.tag_accesses 375579 # Number of tag accesses +system.iocache.tags.data_accesses 375579 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses +system.iocache.ReadReq_misses::total 179 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses -system.iocache.demand_misses::total 41725 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses -system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21862383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21862383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858655675 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4858655675 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4880518058 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4880518058 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4880518058 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4880518058 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41731 # number of demand (read+write) misses +system.iocache.demand_misses::total 41731 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses +system.iocache.overall_misses::total 41731 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22562883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22562883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858746913 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4858746913 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4881309796 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4881309796 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4881309796 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4881309796 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41731 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1659,38 +1667,38 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126372.156069 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126372.156069 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116929.526256 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 116929.526256 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 116968.677244 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 116968.677244 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 116968.677244 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 116968.677244 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126049.625698 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126049.625698 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116931.722011 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 116931.722011 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 116970.832139 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 116970.832139 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 116970.832139 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 116970.832139 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # 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number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13212383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13212383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778666661 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2778666661 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2791879044 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2791879044 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2791879044 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2791879044 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41731 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41731 # 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number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1699,463 +1707,452 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76372.156069 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76372.156069 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66872.031695 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66872.031695 # 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Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5305.017555 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6468.149046 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 210.708528 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 37.097733 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.812327 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.080948 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.098696 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003215 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000566 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995752 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65027 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 238 # 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mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.260010 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.019567 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.250706 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013264 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.289464 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014127 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.142329 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.161307 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013264 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.289464 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014127 # 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mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.002247 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.001093 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.427024 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.271164 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.405440 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.015404 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005220 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013246 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.272862 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.019084 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.253523 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015404 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.304432 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005220 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.103313 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.162131 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015404 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.304432 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005220 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.103313 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.162131 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 45750 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19166.666667 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 36888.888889 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 18500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79104.848165 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 104314.292075 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 81439.691219 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 74206.976578 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 75930.642633 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74350.916230 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63857.855060 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 84805.714286 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63978.016615 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74206.976578 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68237.528621 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75930.642633 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 101914.759859 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 69513.731385 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74206.976578 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68237.528621 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75930.642633 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 101914.759859 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 69513.731385 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210417.938115 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 183925.824176 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209747.810980 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 86721.967560 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 10467.323327 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 74657.935094 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 850516 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 398567 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 435 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 7194 # Transaction distribution -system.membus.trans_dist::ReadResp 297120 # Transaction distribution -system.membus.trans_dist::WriteReq 12394 # Transaction distribution -system.membus.trans_dist::WriteResp 12394 # Transaction distribution -system.membus.trans_dist::WritebackDirty 122579 # Transaction distribution -system.membus.trans_dist::CleanEvict 262673 # Transaction distribution -system.membus.trans_dist::UpgradeReq 5556 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1697 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 7195 # Transaction distribution +system.membus.trans_dist::ReadResp 297176 # Transaction distribution +system.membus.trans_dist::WriteReq 13019 # Transaction distribution +system.membus.trans_dist::WriteResp 13019 # Transaction distribution +system.membus.trans_dist::WritebackDirty 123513 # Transaction distribution +system.membus.trans_dist::CleanEvict 262911 # Transaction distribution +system.membus.trans_dist::UpgradeReq 6111 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 4826 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 120271 # Transaction distribution -system.membus.trans_dist::ReadExResp 120125 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289973 # Transaction distribution -system.membus.trans_dist::BadAddressError 47 # Transaction distribution +system.membus.trans_dist::ReadExReq 121549 # Transaction distribution +system.membus.trans_dist::ReadExResp 121146 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 290030 # Transaction distribution +system.membus.trans_dist::BadAddressError 49 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39176 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1170427 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 94 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1209697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83433 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83433 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1293130 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 68530 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31401600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31470130 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40428 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1177677 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 98 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1218203 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83445 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83445 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1301648 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73538 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31530048 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31603586 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34128370 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 4361 # Total snoops (count) -system.membus.snoopTraffic 28480 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 478637 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001444 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.037968 # Request fanout histogram +system.membus.pkt_size::total 34261826 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 11676 # Total snoops (count) +system.membus.snoopTraffic 28672 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 484282 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001355 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.036780 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 477946 99.86% 99.86% # Request fanout histogram -system.membus.snoop_fanout::1 691 0.14% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 483626 99.86% 99.86% # Request fanout histogram +system.membus.snoop_fanout::1 656 0.14% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 478637 # Request fanout histogram -system.membus.reqLayer0.occupancy 34935499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 484282 # Request fanout histogram +system.membus.reqLayer0.occupancy 36370000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1350989532 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1352579532 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 59500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 62000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2172548749 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2178718000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 925113 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 960113 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5110475 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2554732 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 342217 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1055 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 987 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 5113699 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2556514 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 337557 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1071 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1003 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 7194 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2261145 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12394 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12394 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 911435 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1144537 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 834683 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 5633 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1816 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 7449 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 1 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302973 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302973 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1145857 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1108145 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 47 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 240 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3045120 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4050284 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 390880 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 209583 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7695867 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 129904512 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 135990364 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 16664640 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 6622614 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 289182130 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 363206 # Total snoops (count) -system.toL2Bus.snoopTraffic 6121792 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 2928698 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.120181 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.325532 # Request fanout histogram +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2265500 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13019 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13019 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 906543 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1152402 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 825837 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 10249 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 5740 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 15989 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 300358 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 300358 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1153745 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1104612 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 49 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 203 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2726862 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3834313 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 732820 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 401077 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7695072 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 116326272 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 128153608 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31253696 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13151546 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 288885122 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 379909 # Total snoops (count) +system.toL2Bus.snoopTraffic 6725760 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 2940742 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.121053 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.326514 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2577056 87.99% 87.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 351320 12.00% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 312 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 10 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2585068 87.91% 87.91% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 355364 12.08% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 309 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2928698 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4546181919 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2940742 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4550461413 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 291385 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 301885 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1524803969 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1365446887 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2026499354 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1921756875 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 197300876 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 368286347 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 108970290 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 208891088 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -2187,185 +2184,194 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1907672102500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 197565 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 70781 40.59% 40.59% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.66% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1927 1.10% 41.77% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 20 0.01% 41.78% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 101534 58.22% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 174393 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 69444 49.27% 49.27% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1927 1.37% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 20 0.01% 50.74% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 69424 49.26% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 140946 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1863377945500 97.69% 97.69% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 65817500 0.00% 97.70% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 580544500 0.03% 97.73% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 11361000 0.00% 97.73% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 43328343000 2.27% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1907364011500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981111 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6504 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 179089 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 63660 40.34% 40.34% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.42% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1926 1.22% 41.64% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 175 0.11% 41.75% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 91921 58.25% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 157813 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 62631 49.19% 49.19% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1926 1.51% 50.81% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 175 0.14% 50.95% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 62456 49.05% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 127319 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1863112245000 97.74% 97.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 65536000 0.00% 97.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 577434000 0.03% 97.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 84972500 0.00% 97.78% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 42413276000 2.22% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1906253463500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983836 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.683751 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808209 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.76% 3.76% # number of syscalls executed -system.cpu0.kern.syscall::3 18 8.45% 12.21% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.88% 14.08% # number of syscalls executed -system.cpu0.kern.syscall::6 32 15.02% 29.11% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.47% 29.58% # number of syscalls executed -system.cpu0.kern.syscall::17 8 3.76% 33.33% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.69% 38.03% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.82% 40.85% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.47% 41.31% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.41% 42.72% # number of syscalls executed -system.cpu0.kern.syscall::33 6 2.82% 45.54% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.94% 46.48% # number of syscalls executed -system.cpu0.kern.syscall::45 33 15.49% 61.97% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.41% 63.38% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.69% 68.08% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.69% 72.77% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.47% 73.24% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.82% 76.06% # number of syscalls executed -system.cpu0.kern.syscall::71 21 9.86% 85.92% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.41% 87.32% # number of syscalls executed -system.cpu0.kern.syscall::74 5 2.35% 89.67% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.47% 90.14% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.41% 91.55% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.23% 95.77% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.94% 96.71% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.94% 97.65% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.47% 98.12% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.94% 99.06% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.94% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 213 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.679453 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.806771 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.93% 3.93% # number of syscalls executed +system.cpu0.kern.syscall::3 15 8.43% 12.36% # number of syscalls executed +system.cpu0.kern.syscall::4 4 2.25% 14.61% # number of syscalls executed +system.cpu0.kern.syscall::6 26 14.61% 29.21% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.56% 29.78% # number of syscalls executed +system.cpu0.kern.syscall::17 6 3.37% 33.15% # number of syscalls executed +system.cpu0.kern.syscall::19 7 3.93% 37.08% # number of syscalls executed +system.cpu0.kern.syscall::20 4 2.25% 39.33% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.56% 39.89% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.69% 41.57% # number of syscalls executed +system.cpu0.kern.syscall::33 6 3.37% 44.94% # number of syscalls executed +system.cpu0.kern.syscall::41 2 1.12% 46.07% # number of syscalls executed +system.cpu0.kern.syscall::45 29 16.29% 62.36% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.69% 64.04% # number of syscalls executed +system.cpu0.kern.syscall::48 8 4.49% 68.54% # number of syscalls executed +system.cpu0.kern.syscall::54 8 4.49% 73.03% # number of syscalls executed +system.cpu0.kern.syscall::59 6 3.37% 76.40% # number of syscalls executed +system.cpu0.kern.syscall::71 17 9.55% 85.96% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.69% 87.64% # number of syscalls executed +system.cpu0.kern.syscall::74 4 2.25% 89.89% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.56% 90.45% # number of syscalls executed +system.cpu0.kern.syscall::90 2 1.12% 91.57% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.93% 95.51% # number of syscalls executed +system.cpu0.kern.syscall::97 2 1.12% 96.63% # number of syscalls executed +system.cpu0.kern.syscall::98 2 1.12% 97.75% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.56% 98.31% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.56% 98.88% # number of syscalls executed +system.cpu0.kern.syscall::147 2 1.12% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 178 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 120 0.07% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3815 2.08% 2.15% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.18% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.18% # number of callpals executed -system.cpu0.kern.callpal::swpipl 167656 91.61% 93.80% # number of callpals executed -system.cpu0.kern.callpal::rdps 6177 3.38% 97.17% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal::wrusp 2 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.00% 97.18% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed -system.cpu0.kern.callpal::rti 4658 2.55% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 369 0.20% 99.93% # number of callpals executed -system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 183007 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7158 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1253 # number of protection mode switches +system.cpu0.kern.callpal::wripir 278 0.17% 0.17% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3399 2.05% 2.22% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.25% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.26% # number of callpals executed +system.cpu0.kern.callpal::swpipl 151231 91.28% 93.54% # number of callpals executed +system.cpu0.kern.callpal::rdps 5900 3.56% 97.10% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::wrusp 2 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.11% # number of callpals executed +system.cpu0.kern.callpal::rti 4349 2.63% 99.73% # number of callpals executed +system.cpu0.kern.callpal::callsys 315 0.19% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 132 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 165676 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6738 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1097 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1253 -system.cpu0.kern.mode_good::user 1253 +system.cpu0.kern.mode_good::kernel 1097 +system.cpu0.kern.mode_good::user 1097 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.175049 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.162808 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.297943 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1905453819000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1901068000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.280026 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1904214078500 99.91% 99.91% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1672761500 0.09% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3816 # number of times the context was actually changed +system.cpu0.kern.swap_context 3400 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2323 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 40320 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 10930 33.84% 33.84% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1925 5.96% 39.80% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 120 0.37% 40.18% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 19320 59.82% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 32295 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 10890 45.94% 45.94% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1925 8.12% 54.06% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 120 0.51% 54.57% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 10770 45.43% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 23705 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1876314481500 98.36% 98.36% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 564739500 0.03% 98.39% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 58247500 0.00% 98.39% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 30733817000 1.61% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1907671285500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.996340 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2490 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 60423 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 18641 37.27% 37.27% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1925 3.85% 41.12% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 278 0.56% 41.67% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 29176 58.33% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 50020 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 18293 47.50% 47.50% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1925 5.00% 52.50% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 278 0.72% 53.22% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 18016 46.78% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 38512 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1873859043000 98.29% 98.29% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 564907000 0.03% 98.32% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 133677500 0.01% 98.32% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 31975089500 1.68% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1906532717000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.981331 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.557453 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.734015 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 12 10.62% 10.62% # number of syscalls executed -system.cpu1.kern.syscall::6 10 8.85% 19.47% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.88% 20.35% # number of syscalls executed -system.cpu1.kern.syscall::17 7 6.19% 26.55% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.65% 29.20% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.65% 31.86% # number of syscalls executed -system.cpu1.kern.syscall::33 5 4.42% 36.28% # number of syscalls executed -system.cpu1.kern.syscall::45 21 18.58% 54.87% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.65% 57.52% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.88% 58.41% # number of syscalls executed -system.cpu1.kern.syscall::71 33 29.20% 87.61% # number of syscalls executed -system.cpu1.kern.syscall::74 11 9.73% 97.35% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.65% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 113 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.617494 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.769932 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.68% 0.68% # number of syscalls executed +system.cpu1.kern.syscall::3 15 10.14% 10.81% # number of syscalls executed +system.cpu1.kern.syscall::6 16 10.81% 21.62% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.68% 22.30% # number of syscalls executed +system.cpu1.kern.syscall::17 9 6.08% 28.38% # number of syscalls executed +system.cpu1.kern.syscall::19 3 2.03% 30.41% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.35% 31.76% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.03% 33.78% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.03% 35.81% # number of syscalls executed +system.cpu1.kern.syscall::33 5 3.38% 39.19% # number of syscalls executed +system.cpu1.kern.syscall::45 25 16.89% 56.08% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.03% 58.11% # number of syscalls executed +system.cpu1.kern.syscall::48 2 1.35% 59.46% # number of syscalls executed +system.cpu1.kern.syscall::54 2 1.35% 60.81% # number of syscalls executed +system.cpu1.kern.syscall::58 1 0.68% 61.49% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.68% 62.16% # number of syscalls executed +system.cpu1.kern.syscall::71 37 25.00% 87.16% # number of syscalls executed +system.cpu1.kern.syscall::74 12 8.11% 95.27% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.68% 95.95% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.35% 97.30% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.03% 99.32% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.68% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 148 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 20 0.06% 0.06% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed -system.cpu1.kern.callpal::swpctx 449 1.34% 1.41% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 1.42% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.44% # number of callpals executed -system.cpu1.kern.callpal::swpipl 27672 82.56% 84.00% # number of callpals executed -system.cpu1.kern.callpal::rdps 2585 7.71% 91.71% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.71% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.01% 91.73% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.74% # number of callpals executed -system.cpu1.kern.callpal::rti 2577 7.69% 99.42% # number of callpals executed -system.cpu1.kern.callpal::callsys 148 0.44% 99.87% # number of callpals executed -system.cpu1.kern.callpal::imb 44 0.13% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 175 0.33% 0.34% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1166 2.23% 2.57% # number of callpals executed +system.cpu1.kern.callpal::tbi 5 0.01% 2.58% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.59% # number of callpals executed +system.cpu1.kern.callpal::swpipl 44628 85.35% 87.94% # number of callpals executed +system.cpu1.kern.callpal::rdps 2858 5.47% 93.41% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.41% # number of callpals executed +system.cpu1.kern.callpal::wrusp 5 0.01% 93.42% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.42% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.43% # number of callpals executed +system.cpu1.kern.callpal::rti 3189 6.10% 99.52% # number of callpals executed +system.cpu1.kern.callpal::callsys 200 0.38% 99.91% # number of callpals executed +system.cpu1.kern.callpal::imb 48 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 33518 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 911 # number of protection mode switches -system.cpu1.kern.mode_switch::user 493 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2088 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 538 -system.cpu1.kern.mode_good::user 493 -system.cpu1.kern.mode_good::idle 45 -system.cpu1.kern.mode_switch_good::kernel 0.590560 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 52290 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1624 # number of protection mode switches +system.cpu1.kern.mode_switch::user 640 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2399 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 844 +system.cpu1.kern.mode_good::user 640 +system.cpu1.kern.mode_good::idle 204 +system.cpu1.kern.mode_switch_good::kernel 0.519704 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.021552 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.308133 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 2257888000 0.12% 0.12% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 790670500 0.04% 0.16% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1904622719000 99.84% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 450 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.085035 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.361999 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4862135000 0.26% 0.26% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1013458000 0.05% 0.31% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1900657116000 99.69% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1167 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 39a06dc53..f5019500b 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,113 +1,113 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.876794 # Number of seconds simulated -sim_ticks 1876794488000 # Number of ticks simulated -final_tick 1876794488000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.862042 # Number of seconds simulated +sim_ticks 1862042063000 # Number of ticks simulated +final_tick 1862042063000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152079 # Simulator instruction rate (inst/s) -host_op_rate 152079 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5387044029 # Simulator tick rate (ticks/s) -host_mem_usage 330796 # Number of bytes of host memory used -host_seconds 348.39 # Real time elapsed on the host -sim_insts 52982943 # Number of instructions simulated -sim_ops 52982943 # Number of ops (including micro ops) simulated +host_inst_rate 137297 # Simulator instruction rate (inst/s) +host_op_rate 137297 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4825772422 # Simulator tick rate (ticks/s) +host_mem_usage 338492 # Number of bytes of host memory used +host_seconds 385.85 # Real time elapsed on the host +sim_insts 52976505 # Number of instructions simulated +sim_ops 52976505 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 961728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24880448 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 963392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24881792 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25843136 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 961728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 961728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7527680 # Number of bytes written to this memory -system.physmem.bytes_written::total 7527680 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15027 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388757 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25846144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 963392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 963392 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7528832 # Number of bytes written to this memory +system.physmem.bytes_written::total 7528832 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15053 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388778 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403799 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117620 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117620 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 512431 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13256885 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13769827 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 512431 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512431 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4010924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4010924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4010924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 512431 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13256885 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17780751 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403799 # Number of read requests accepted -system.physmem.writeReqs 117620 # Number of write requests accepted -system.physmem.readBursts 403799 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117620 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25835776 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue -system.physmem.bytesWritten 7525824 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25843136 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7527680 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 403846 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117638 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117638 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 517385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13362637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13880537 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 517385 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 517385 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4043320 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4043320 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4043320 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 517385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13362637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17923857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403846 # Number of read requests accepted +system.physmem.writeReqs 117638 # Number of write requests accepted +system.physmem.readBursts 403846 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117638 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25839232 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6912 # Total number of bytes read from write queue +system.physmem.bytesWritten 7527104 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25846144 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7528832 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 108 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25625 # Per bank write bursts -system.physmem.perBankRdBursts::1 25421 # Per bank write bursts -system.physmem.perBankRdBursts::2 25559 # Per bank write bursts -system.physmem.perBankRdBursts::3 25464 # Per bank write bursts -system.physmem.perBankRdBursts::4 25431 # Per bank write bursts -system.physmem.perBankRdBursts::5 24732 # Per bank write bursts -system.physmem.perBankRdBursts::6 24935 # Per bank write bursts -system.physmem.perBankRdBursts::7 25090 # Per bank write bursts -system.physmem.perBankRdBursts::8 24946 # Per bank write bursts -system.physmem.perBankRdBursts::9 25020 # Per bank write bursts -system.physmem.perBankRdBursts::10 25560 # Per bank write bursts -system.physmem.perBankRdBursts::11 24886 # Per bank write bursts -system.physmem.perBankRdBursts::12 24460 # Per bank write bursts -system.physmem.perBankRdBursts::13 25266 # Per bank write bursts -system.physmem.perBankRdBursts::14 25703 # Per bank write bursts -system.physmem.perBankRdBursts::15 25586 # Per bank write bursts -system.physmem.perBankWrBursts::0 7949 # Per bank write bursts -system.physmem.perBankWrBursts::1 7513 # Per bank write bursts -system.physmem.perBankWrBursts::2 7969 # Per bank write bursts -system.physmem.perBankWrBursts::3 7485 # Per bank write bursts -system.physmem.perBankWrBursts::4 7367 # Per bank write bursts -system.physmem.perBankWrBursts::5 6667 # Per bank write bursts -system.physmem.perBankWrBursts::6 6767 # Per bank write bursts -system.physmem.perBankWrBursts::7 6715 # Per bank write bursts -system.physmem.perBankWrBursts::8 7150 # Per bank write bursts -system.physmem.perBankWrBursts::9 6697 # Per bank write bursts -system.physmem.perBankWrBursts::10 7421 # Per bank write bursts -system.physmem.perBankWrBursts::11 6978 # Per bank write bursts -system.physmem.perBankWrBursts::12 7150 # Per bank write bursts -system.physmem.perBankWrBursts::13 7899 # Per bank write bursts -system.physmem.perBankWrBursts::14 8060 # Per bank write bursts -system.physmem.perBankWrBursts::15 7804 # Per bank write bursts +system.physmem.perBankRdBursts::0 25618 # Per bank write bursts +system.physmem.perBankRdBursts::1 25426 # Per bank write bursts +system.physmem.perBankRdBursts::2 25537 # Per bank write bursts +system.physmem.perBankRdBursts::3 25512 # Per bank write bursts +system.physmem.perBankRdBursts::4 25419 # Per bank write bursts +system.physmem.perBankRdBursts::5 24740 # Per bank write bursts +system.physmem.perBankRdBursts::6 24937 # Per bank write bursts +system.physmem.perBankRdBursts::7 25096 # Per bank write bursts +system.physmem.perBankRdBursts::8 24930 # Per bank write bursts +system.physmem.perBankRdBursts::9 25035 # Per bank write bursts +system.physmem.perBankRdBursts::10 25569 # Per bank write bursts +system.physmem.perBankRdBursts::11 24892 # Per bank write bursts +system.physmem.perBankRdBursts::12 24450 # Per bank write bursts +system.physmem.perBankRdBursts::13 25273 # Per bank write bursts +system.physmem.perBankRdBursts::14 25713 # Per bank write bursts +system.physmem.perBankRdBursts::15 25591 # Per bank write bursts +system.physmem.perBankWrBursts::0 7930 # Per bank write bursts +system.physmem.perBankWrBursts::1 7514 # Per bank write bursts +system.physmem.perBankWrBursts::2 7945 # Per bank write bursts +system.physmem.perBankWrBursts::3 7523 # Per bank write bursts +system.physmem.perBankWrBursts::4 7351 # Per bank write bursts +system.physmem.perBankWrBursts::5 6673 # Per bank write bursts +system.physmem.perBankWrBursts::6 6769 # Per bank write bursts +system.physmem.perBankWrBursts::7 6726 # Per bank write bursts +system.physmem.perBankWrBursts::8 7138 # Per bank write bursts +system.physmem.perBankWrBursts::9 6708 # Per bank write bursts +system.physmem.perBankWrBursts::10 7428 # Per bank write bursts +system.physmem.perBankWrBursts::11 6991 # Per bank write bursts +system.physmem.perBankWrBursts::12 7147 # Per bank write bursts +system.physmem.perBankWrBursts::13 7895 # Per bank write bursts +system.physmem.perBankWrBursts::14 8063 # Per bank write bursts +system.physmem.perBankWrBursts::15 7810 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 1876789160500 # Total gap between requests +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 1862036687500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403799 # Read request sizes (log2) +system.physmem.readPktSize::6 403846 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117620 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 315619 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 35764 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28247 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23961 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 77 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117638 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 315267 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 36112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23939 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -149,192 +149,195 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6001 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6473 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7602 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 160 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62139 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 536.886657 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 331.247155 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 411.697741 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13677 22.01% 22.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10478 16.86% 38.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4968 7.99% 46.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2775 4.47% 51.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2441 3.93% 55.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1588 2.56% 57.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3776 6.08% 63.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1174 1.89% 65.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21262 34.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62139 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5217 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 77.374545 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2903.927058 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5214 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::46 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 32 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61611 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 541.558358 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 333.246769 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.180517 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13396 21.74% 21.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10505 17.05% 38.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5359 8.70% 47.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2621 4.25% 51.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2461 3.99% 55.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1425 2.31% 58.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1507 2.45% 60.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1351 2.19% 62.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22986 37.31% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61611 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5236 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 77.104660 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2917.579007 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5233 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5217 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5217 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.539965 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.244136 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.635763 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4619 88.54% 88.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 29 0.56% 89.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 25 0.48% 89.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 38 0.73% 90.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 214 4.10% 94.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 9 0.17% 94.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 11 0.21% 94.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 34 0.65% 95.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 184 3.53% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.10% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 5 0.10% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 4 0.08% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 6 0.12% 99.35% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5236 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5236 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.461994 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.033018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.013556 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4631 88.45% 88.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 42 0.80% 89.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 243 4.64% 93.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 21 0.40% 94.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 6 0.11% 94.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 10 0.19% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 6 0.11% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 2 0.04% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 20 0.38% 95.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 23 0.44% 95.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 185 3.53% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 2 0.04% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 3 0.06% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 1 0.02% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 7 0.13% 99.35% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::136-143 1 0.02% 99.37% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::144-151 1 0.02% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 4 0.08% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 8 0.15% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.08% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 3 0.06% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.04% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 2 0.04% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 6 0.12% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 2 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5217 # Writes before turning the bus around for reads -system.physmem.totQLat 4201005000 # Total ticks spent queuing -system.physmem.totMemAccLat 11770080000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2018420000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10406.67 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::152-159 3 0.06% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 2 0.04% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 11 0.21% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 1 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.04% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 3 0.06% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 7 0.13% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5236 # Writes before turning the bus around for reads +system.physmem.totQLat 3726058000 # Total ticks spent queuing +system.physmem.totMemAccLat 11296145500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2018690000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9228.90 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29156.67 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.01 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 27978.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.88 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.98 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.46 # Average write queue length when enqueuing -system.physmem.readRowHits 363845 # Number of row buffer hits during reads -system.physmem.writeRowHits 95291 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.13 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.02 # Row buffer hit rate for writes -system.physmem.avgGap 3599387.75 # Average gap between requests -system.physmem.pageHitRate 88.07 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 233399880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 127351125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1577604600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 378639360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 122582793840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 61740410985 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1071915840750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1258556040540 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.589641 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1783024934000 # Time in different power states -system.physmem_0.memoryStateTime::REF 62670140000 # Time in different power states +system.physmem.avgWrQLen 25.95 # Average write queue length when enqueuing +system.physmem.readRowHits 364089 # Number of row buffer hits during reads +system.physmem.writeRowHits 95648 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.31 # Row buffer hit rate for writes +system.physmem.avgGap 3570649.70 # Average gap between requests +system.physmem.pageHitRate 88.18 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 230882400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125977500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1577823000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 378632880 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 121619072640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 56327619735 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1067810937000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1248070945155 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.272471 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1776230272500 # Time in different power states +system.physmem_0.memoryStateTime::REF 62177440000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31095099750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 23627517500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 236370960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 128972250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1571130600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 383350320 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 122582793840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61477234290 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1072146705750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1258526558010 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.573928 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1783410314000 # Time in different power states -system.physmem_1.memoryStateTime::REF 62670140000 # Time in different power states +system.physmem_1.actEnergy 234896760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 128167875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1571286600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 383486400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 121619072640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 56258103960 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1067871924000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1248066938235 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.270314 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1776335363750 # Time in different power states +system.physmem_1.memoryStateTime::REF 62177440000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30709733500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23523591750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 19569408 # Number of BP lookups -system.cpu.branchPred.condPredicted 16632311 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 593173 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12870136 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5420664 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 19539848 # Number of BP lookups +system.cpu.branchPred.condPredicted 16614646 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 591620 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12579114 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5416634 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 42.118156 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1123230 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 42865 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6372302 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 563108 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5809194 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 264983 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 43.060537 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1121926 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 41569 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6087322 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 563395 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5523927 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 264320 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 11131372 # DTB read hits -system.cpu.dtb.read_misses 49301 # DTB read misses -system.cpu.dtb.read_acv 623 # DTB read access violations -system.cpu.dtb.read_accesses 996761 # DTB read accesses -system.cpu.dtb.write_hits 6776847 # DTB write hits -system.cpu.dtb.write_misses 12217 # DTB write misses -system.cpu.dtb.write_acv 418 # DTB write access violations -system.cpu.dtb.write_accesses 345142 # DTB write accesses -system.cpu.dtb.data_hits 17908219 # DTB hits -system.cpu.dtb.data_misses 61518 # DTB misses -system.cpu.dtb.data_acv 1041 # DTB access violations -system.cpu.dtb.data_accesses 1341903 # DTB accesses -system.cpu.itb.fetch_hits 1817383 # ITB hits -system.cpu.itb.fetch_misses 10321 # ITB misses -system.cpu.itb.fetch_acv 767 # ITB acv -system.cpu.itb.fetch_accesses 1827704 # ITB accesses +system.cpu.dtb.read_hits 11126873 # DTB read hits +system.cpu.dtb.read_misses 49288 # DTB read misses +system.cpu.dtb.read_acv 612 # DTB read access violations +system.cpu.dtb.read_accesses 995471 # DTB read accesses +system.cpu.dtb.write_hits 6773971 # DTB write hits +system.cpu.dtb.write_misses 12183 # DTB write misses +system.cpu.dtb.write_acv 423 # DTB write access violations +system.cpu.dtb.write_accesses 345274 # DTB write accesses +system.cpu.dtb.data_hits 17900844 # DTB hits +system.cpu.dtb.data_misses 61471 # DTB misses +system.cpu.dtb.data_acv 1035 # DTB access violations +system.cpu.dtb.data_accesses 1340745 # DTB accesses +system.cpu.itb.fetch_hits 1815480 # ITB hits +system.cpu.itb.fetch_misses 10441 # ITB misses +system.cpu.itb.fetch_acv 750 # ITB acv +system.cpu.itb.fetch_accesses 1825921 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -347,148 +350,148 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numPwrStateTransitions 12876 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 6438 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 279467835.818577 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 439243252.658256 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 6438 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 81000 # Distribution of time spent in the clock gated state +system.cpu.numPwrStateTransitions 12878 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 6439 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 279534848.967231 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 439378966.267034 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 6439 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 96000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 6438 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 77580561000 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1799213927000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 155167561 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::total 6439 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 62117170500 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1799924892500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 124240781 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30150844 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85742172 # Number of instructions fetch has processed -system.cpu.fetch.Branches 19569408 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7107002 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 116772481 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1681668 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 87 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 29150 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 207083 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 421165 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 751 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9930605 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 406777 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 30188704 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85612379 # Number of instructions fetch has processed +system.cpu.fetch.Branches 19539848 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7101955 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 86725868 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1678156 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 61 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 31498 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 207275 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 432547 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 339 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9909625 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 405389 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 148422395 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.577690 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.864310 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 118425370 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.722923 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.060283 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 132578342 89.33% 89.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1033201 0.70% 90.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2106811 1.42% 91.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 971505 0.65% 92.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2908700 1.96% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 663530 0.45% 94.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 808471 0.54% 95.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1037122 0.70% 95.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6314713 4.25% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 102607090 86.64% 86.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1029926 0.87% 87.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2106958 1.78% 89.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 967243 0.82% 90.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2899427 2.45% 92.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 665654 0.56% 93.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 809857 0.68% 93.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1032032 0.87% 94.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6307183 5.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148422395 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126118 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.552578 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24118440 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 111208587 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 10245196 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2044112 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 806059 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 738327 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 35573 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 74062953 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 114064 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 806059 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25129468 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 79314805 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20217508 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11209636 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 11744917 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 71031430 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 202187 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2134257 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 304114 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 7385918 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 47856784 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 85577316 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 85396639 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168224 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38182032 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9674744 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1729903 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 277398 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13945265 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 11667584 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7222268 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1740236 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1128330 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 62719117 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2208284 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 60532785 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 94680 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11944453 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5319004 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1547012 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148422395 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.407841 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.141989 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 118425370 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.157274 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.689084 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24239485 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 81100635 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 10246732 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2034421 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 804096 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 734883 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 35786 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 73972445 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 113808 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 804096 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25248689 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 52456334 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19565246 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11202200 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9148803 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 70966243 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 196842 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2117370 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 228092 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4881037 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 47806174 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 85505184 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 85324382 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168350 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38176913 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 9629253 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1728484 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 276268 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13926032 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 11656323 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7221031 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1724354 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1093863 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 62666856 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2206869 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 60507866 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 96262 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11897215 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5284366 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1545682 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 118425370 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.510937 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.257755 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 123871811 83.46% 83.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10428219 7.03% 90.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4419616 2.98% 93.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3188761 2.15% 95.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3243069 2.19% 97.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1605515 1.08% 98.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1096686 0.74% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 430660 0.29% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 138058 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 93896241 79.29% 79.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10410761 8.79% 88.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4424184 3.74% 91.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3178503 2.68% 94.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3240709 2.74% 97.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1606797 1.36% 98.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1097474 0.93% 99.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 434045 0.37% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 136656 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148422395 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 118425370 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 206261 16.62% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 637065 51.34% 67.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 397617 32.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 206587 16.63% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 638209 51.38% 68.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 397270 31.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 7280 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 40910867 67.58% 67.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 62087 0.10% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 7277 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 40893641 67.58% 67.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 62155 0.10% 67.70% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38559 0.06% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38558 0.06% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued @@ -514,95 +517,95 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.77% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.77% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.77% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 11677582 19.29% 87.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6883616 11.37% 98.43% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949158 1.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 11671611 19.29% 87.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6881999 11.37% 98.43% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 948989 1.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 60532785 # Type of FU issued -system.cpu.iq.rate 0.390112 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1240943 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020500 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 270086631 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 76534291 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 58304379 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 736956 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 359180 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 336827 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 61370896 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 395552 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 686477 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 60507866 # Type of FU issued +system.cpu.iq.rate 0.487021 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1242066 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.020527 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 240042364 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 76433076 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 58286910 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 737065 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 359346 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 336745 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 61347086 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 395569 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 690461 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2574541 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4210 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 22293 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 843973 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2564224 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3975 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 22069 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 843181 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18024 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 466103 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17987 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 463704 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 806059 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 75493298 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1202730 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 68906340 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 204916 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 11667584 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 7222268 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1958885 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 46577 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 953145 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 22293 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 228745 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 630471 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 859216 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 59676170 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 11213777 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 856614 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 804096 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 49123510 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 920451 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 68850753 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 204809 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 11656323 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 7221031 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1958834 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 45972 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 671584 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 22069 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 229357 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 628132 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 857489 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 59656852 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 11208773 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 851013 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3978939 # number of nop insts executed -system.cpu.iew.exec_refs 18023142 # number of memory reference insts executed -system.cpu.iew.exec_branches 9384066 # Number of branches executed -system.cpu.iew.exec_stores 6809365 # Number of stores executed -system.cpu.iew.exec_rate 0.384592 # Inst execution rate -system.cpu.iew.wb_sent 58885265 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 58641206 # cumulative count of insts written-back -system.cpu.iew.wb_producers 29760600 # num instructions producing a value -system.cpu.iew.wb_consumers 41260135 # num instructions consuming a value -system.cpu.iew.wb_rate 0.377922 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.721292 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 12542077 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661272 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 769434 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 146251910 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.384089 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.283290 # Number of insts commited each cycle +system.cpu.iew.exec_nop 3977028 # number of nop insts executed +system.cpu.iew.exec_refs 18015122 # number of memory reference insts executed +system.cpu.iew.exec_branches 9379233 # Number of branches executed +system.cpu.iew.exec_stores 6806349 # Number of stores executed +system.cpu.iew.exec_rate 0.480171 # Inst execution rate +system.cpu.iew.wb_sent 58867691 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 58623655 # cumulative count of insts written-back +system.cpu.iew.wb_producers 29756177 # num instructions producing a value +system.cpu.iew.wb_consumers 41250197 # num instructions consuming a value +system.cpu.iew.wb_rate 0.471855 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.721358 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 12492004 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661187 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 767634 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 116265516 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.483093 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.421972 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 126403677 86.43% 86.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7969213 5.45% 91.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4187918 2.86% 94.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2256490 1.54% 96.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1756984 1.20% 97.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 633259 0.43% 97.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 482491 0.33% 98.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 524954 0.36% 98.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2036924 1.39% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 96403146 82.92% 82.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7978599 6.86% 89.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4192375 3.61% 93.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2264506 1.95% 95.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1757271 1.51% 96.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 632678 0.54% 97.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 482043 0.41% 97.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 513720 0.44% 98.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2041178 1.76% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 146251910 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56173766 # Number of instructions committed -system.cpu.commit.committedOps 56173766 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 116265516 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56167063 # Number of instructions committed +system.cpu.commit.committedOps 56167063 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15471338 # Number of memory references committed -system.cpu.commit.loads 9093043 # Number of loads committed -system.cpu.commit.membars 226379 # Number of memory barriers committed -system.cpu.commit.branches 8441154 # Number of branches committed +system.cpu.commit.refs 15469949 # Number of memory references committed +system.cpu.commit.loads 9092099 # Number of loads committed +system.cpu.commit.membars 226348 # Number of memory barriers committed +system.cpu.commit.branches 8440307 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52023017 # Number of committed integer instructions. -system.cpu.commit.function_calls 740601 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3198096 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36220454 64.48% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60663 0.11% 70.28% # Class of committed instruction +system.cpu.commit.int_insts 52016709 # Number of committed integer instructions. +system.cpu.commit.function_calls 740521 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3197831 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36215597 64.48% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60674 0.11% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction @@ -630,554 +633,544 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9319422 16.59% 86.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6384252 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 949158 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9318447 16.59% 86.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6383804 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 948989 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56173766 # Class of committed instruction -system.cpu.commit.bw_lim_events 2036924 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 212681294 # The number of ROB reads -system.cpu.rob.rob_writes 139606986 # The number of ROB writes -system.cpu.timesIdled 557347 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6745166 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3598421416 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52982943 # Number of Instructions Simulated -system.cpu.committedOps 52982943 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.928632 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.928632 # CPI: Total CPI of All Threads -system.cpu.ipc 0.341456 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.341456 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 77864960 # number of integer regfile reads -system.cpu.int_regfile_writes 42584488 # number of integer regfile writes -system.cpu.fp_regfile_reads 166613 # number of floating regfile reads -system.cpu.fp_regfile_writes 175794 # number of floating regfile writes -system.cpu.misc_regfile_reads 2001927 # number of misc regfile reads -system.cpu.misc_regfile_writes 939529 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1405900 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.992670 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 12627832 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1406412 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.978757 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.992670 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999986 # Average percentage of cache occupancy +system.cpu.commit.op_class_0::total 56167063 # Class of committed instruction +system.cpu.commit.bw_lim_events 2041178 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 182633884 # The number of ROB reads +system.cpu.rob.rob_writes 139481914 # The number of ROB writes +system.cpu.timesIdled 555871 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5815411 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599843346 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52976505 # Number of Instructions Simulated +system.cpu.committedOps 52976505 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.345205 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.345205 # CPI: Total CPI of All Threads +system.cpu.ipc 0.426402 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.426402 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 77842014 # number of integer regfile reads +system.cpu.int_regfile_writes 42572961 # number of integer regfile writes +system.cpu.fp_regfile_reads 166584 # number of floating regfile reads +system.cpu.fp_regfile_writes 175742 # number of floating regfile writes +system.cpu.misc_regfile_reads 2001057 # number of misc regfile reads +system.cpu.misc_regfile_writes 939419 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1405448 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994324 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 12624146 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1405960 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.979022 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 26885500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994324 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 414 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 67144149 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 67144149 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 8017767 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 8017767 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4181578 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4181578 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 212474 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 212474 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215675 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215675 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 12199345 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 12199345 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 12199345 # number of overall hits -system.cpu.dcache.overall_hits::total 12199345 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1817411 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1817411 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1966241 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1966241 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23192 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23192 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 96 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 96 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3783652 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3783652 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3783652 # number of overall misses -system.cpu.dcache.overall_misses::total 3783652 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57696836500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57696836500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 116764719993 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 116764719993 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 411714000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 411714000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 1875000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 1875000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 174461556493 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 174461556493 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 174461556493 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 174461556493 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9835178 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9835178 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6147819 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6147819 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235666 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 235666 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215771 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215771 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15982997 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15982997 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15982997 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15982997 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184787 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.184787 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319827 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.319827 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.098410 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.098410 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000445 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000445 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.236730 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.236730 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.236730 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.236730 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31746.719097 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31746.719097 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59384.744796 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59384.744796 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17752.414626 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17752.414626 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19531.250000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19531.250000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46109.302994 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46109.302994 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46109.302994 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46109.302994 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7149027 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5119 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 133846 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 35 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.412332 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 146.257143 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 843569 # number of writebacks -system.cpu.dcache.writebacks::total 843569 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717041 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 717041 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1676919 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1676919 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6351 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 6351 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2393960 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2393960 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2393960 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2393960 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1100370 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1100370 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289322 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 289322 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16841 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 16841 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 96 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 96 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1389692 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1389692 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1389692 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1389692 # number of overall MSHR misses +system.cpu.dcache.tags.tag_accesses 67117469 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 67117469 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 8015814 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 8015814 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4179783 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4179783 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 212605 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 212605 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215671 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215671 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 12195597 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 12195597 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 12195597 # number of overall hits +system.cpu.dcache.overall_hits::total 12195597 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1813103 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1813103 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1967603 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1967603 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23208 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23208 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 90 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 90 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3780706 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3780706 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3780706 # number of overall misses +system.cpu.dcache.overall_misses::total 3780706 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 42125006500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 42125006500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 80961387023 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 80961387023 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 351774000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 351774000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 1258000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 1258000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 123086393523 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 123086393523 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 123086393523 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 123086393523 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9828917 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9828917 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147386 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147386 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235813 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 235813 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215761 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215761 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15976303 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15976303 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15976303 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15976303 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184466 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.184466 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.320071 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.320071 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.098417 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.098417 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000417 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000417 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.236645 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.236645 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.236645 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.236645 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23233.653300 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23233.653300 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41147.216701 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41147.216701 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15157.445708 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15157.445708 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13977.777778 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13977.777778 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32556.457319 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32556.457319 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32556.457319 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32556.457319 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4549830 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3359 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 133574 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 36 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.062243 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 93.305556 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 843871 # number of writebacks +system.cpu.dcache.writebacks::total 843871 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 713283 # 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mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086948 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.086948 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40652.542327 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40652.542327 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63378.619545 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63378.619545 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12743.156582 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12743.156582 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 18531.250000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 18531.250000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45383.917418 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45383.917418 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220582.828283 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220582.828283 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92482.243330 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92482.243330 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1074186 # number of replacements -system.cpu.icache.tags.tagsinuse 507.868793 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 8786985 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1074694 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.176267 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 42323300500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 507.868793 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.991931 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.991931 # Average percentage of cache occupancy +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30901101000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30901101000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12647974805 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12647974805 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 208768500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 208768500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 1168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 1168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43549075805 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 43549075805 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43549075805 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 43549075805 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1535163500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1535163500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1535163500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 1535163500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.111896 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.111896 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047104 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047104 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.070819 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.070819 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000417 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000417 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086965 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.086965 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086965 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.086965 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28096.507610 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28096.507610 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43679.225062 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43679.225062 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12501.107784 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12501.107784 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12977.777778 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12977.777778 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31344.138453 # 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number of replacements +system.cpu.icache.tags.tagsinuse 509.176961 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 8765751 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1075522 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.150229 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 28399256500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.176961 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994486 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994486 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 366 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 300 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11005600 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11005600 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 8786985 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8786985 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8786985 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8786985 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8786985 # number of overall hits -system.cpu.icache.overall_hits::total 8786985 # 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number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9930600 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9930600 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9930600 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9930600 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9930600 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9930600 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115161 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.115161 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.115161 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.115161 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.115161 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.115161 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14866.496136 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14866.496136 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14866.496136 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14866.496136 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14866.496136 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14866.496136 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 12933 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10985459 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10985459 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 8765751 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8765751 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8765751 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8765751 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8765751 # number of overall hits +system.cpu.icache.overall_hits::total 8765751 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1143868 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1143868 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1143868 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1143868 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1143868 # number of overall misses +system.cpu.icache.overall_misses::total 1143868 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15979138992 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15979138992 # 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number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 307500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 307500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9179285500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9179285500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1123478500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1123478500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17540240000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17540240000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1123478500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26719525500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27843004000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1123478500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26719525500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27843004000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1448524000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1448524000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1448524000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1448524000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.097561 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.097561 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382246 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382246 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013998 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013998 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248230 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248230 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013998 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276831 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.162919 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013998 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276831 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.162919 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 38437.500000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 38437.500000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80029.342017 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80029.342017 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74629.899030 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74629.899030 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63892.586157 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63892.586157 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74629.899030 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68647.843412 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68870.594637 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74629.899030 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68647.843412 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68870.594637 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209022.222222 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209022.222222 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87640.609874 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87640.609874 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4962480 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2480820 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2159 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 950 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 950 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2188672 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9599 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 961198 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1074186 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 824987 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 80 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 96 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 176 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 299827 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 299827 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1075000 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106802 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 43 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3223811 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4252378 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7476189 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137523904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144052988 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 281576892 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 422541 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7562240 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2920171 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001264 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.035530 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 2188821 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 919997 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1075014 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 824089 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 82 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 90 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 172 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 300066 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 300066 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1075840 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106100 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 45 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 254 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3226322 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4251016 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7477338 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137630848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144043380 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 281674228 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 339580 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4905856 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2837598 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001208 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.034736 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2916480 99.87% 99.87% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3691 0.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2834170 99.88% 99.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3428 0.12% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2920171 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4411678000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2837598 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4413188000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1613546403 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1614811393 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2121618679 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2121037981 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1191,12 +1184,12 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51151 # Transaction distribution -system.iobus.trans_dist::WriteResp 51151 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5054 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51150 # Transaction distribution +system.iobus.trans_dist::WriteResp 51150 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1205,11 +1198,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1812 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33058 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116508 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20216 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1218,50 +1211,50 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44156 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2705764 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5364000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 5361000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 818000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 820500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 177000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 177500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14181000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14040000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2178000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2177500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6052000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6050500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 91500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215700163 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216173801 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23459000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.249213 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.258860 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1726973394000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.249213 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078076 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078076 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1712294555000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.258860 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078679 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078679 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1270,14 +1263,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21828883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21828883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5246443280 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5246443280 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5268272163 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5268272163 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5268272163 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5268272163 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21845883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21845883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858784918 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4858784918 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4880630801 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4880630801 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4880630801 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4880630801 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1294,19 +1287,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126178.514451 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126178.514451 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126262.112052 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126262.112052 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126261.765440 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126261.765440 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126261.765440 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126261.765440 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126276.780347 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126276.780347 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116932.636648 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 116932.636648 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 116971.379293 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 116971.379293 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 116971.379293 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 116971.379293 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 8 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks @@ -1318,14 +1311,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13178883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13178883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3167048471 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3167048471 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3180227354 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3180227354 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3180227354 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3180227354 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13195883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13195883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778792164 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2778792164 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2791988047 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2791988047 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2791988047 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2791988047 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1334,70 +1327,75 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76178.514451 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76218.917766 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76218.917766 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76276.780347 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76276.780347 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66875.052079 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66875.052079 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66914.033481 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 66914.033481 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66914.033481 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 66914.033481 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 825555 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 380464 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 414 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 296606 # Transaction distribution -system.membus.trans_dist::WriteReq 9599 # Transaction distribution -system.membus.trans_dist::WriteResp 9599 # Transaction distribution -system.membus.trans_dist::WritebackDirty 117620 # Transaction distribution -system.membus.trans_dist::CleanEvict 261864 # Transaction distribution -system.membus.trans_dist::UpgradeReq 278 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution +system.membus.trans_dist::ReadResp 296639 # Transaction distribution +system.membus.trans_dist::WriteReq 9598 # Transaction distribution +system.membus.trans_dist::WriteResp 9598 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117638 # Transaction distribution +system.membus.trans_dist::CleanEvict 261892 # Transaction distribution +system.membus.trans_dist::UpgradeReq 135 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 114558 # Transaction distribution -system.membus.trans_dist::ReadExResp 114558 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289719 # Transaction distribution -system.membus.trans_dist::BadAddressError 43 # Transaction distribution +system.membus.trans_dist::ReadExReq 114572 # Transaction distribution +system.membus.trans_dist::ReadExResp 114572 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289754 # Transaction distribution +system.membus.trans_dist::BadAddressError 45 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33058 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145930 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 86 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179074 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145919 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 90 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179065 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1262499 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44156 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30713088 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30757244 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1262490 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30717248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30761396 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33414972 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33419124 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 438 # Total snoops (count) system.membus.snoopTraffic 27840 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 842137 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::samples 462541 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001500 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.038706 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 842137 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 461847 99.85% 99.85% # Request fanout histogram +system.membus.snoop_fanout::1 694 0.15% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 842137 # Request fanout histogram -system.membus.reqLayer0.occupancy 28883000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 462541 # Request fanout histogram +system.membus.reqLayer0.occupancy 28740000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1314388710 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1314155780 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 54000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 57000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2138626000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2139053000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 918617 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1429,52 +1427,52 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1862042063000 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6438 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211036 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74670 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 210996 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74658 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1881 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105584 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182266 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73303 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105558 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182227 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73291 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1881 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73303 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818987792000 96.92% 96.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 67503500 0.00% 96.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 563118000 0.03% 96.95% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 57175249500 3.05% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1876793663000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73291 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148593 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1818067214500 97.64% 97.64% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 67498000 0.00% 97.64% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 564111500 0.03% 97.67% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 43342412500 2.33% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1862041236500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981690 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694262 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815391 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694320 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815428 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1513,29 +1511,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175147 91.23% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175110 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5106 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191994 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5854 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1740 +system.cpu.kern.callpal::total 191955 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326273 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326269 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394302 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 30164955000 1.61% 1.61% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2918722500 0.16% 1.76% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1843709977500 98.24% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29461996000 1.58% 1.58% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2701361000 0.15% 1.73% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1829877871500 98.27% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index d7da6ec5c..848d1d5ab 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.841599 # Number of seconds simulated -sim_ticks 1841599161000 # Number of ticks simulated -final_tick 1841599161000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.842573 # Number of seconds simulated +sim_ticks 1842573194000 # Number of ticks simulated +final_tick 1842573194000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 220916 # Simulator instruction rate (inst/s) -host_op_rate 220916 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6097623299 # Simulator tick rate (ticks/s) -host_mem_usage 332848 # Number of bytes of host memory used -host_seconds 302.02 # Real time elapsed on the host -sim_insts 66720805 # Number of instructions simulated -sim_ops 66720805 # Number of ops (including micro ops) simulated +host_inst_rate 206946 # Simulator instruction rate (inst/s) +host_op_rate 206946 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5715573944 # Simulator tick rate (ticks/s) +host_mem_usage 339016 # Number of bytes of host memory used +host_seconds 322.38 # Real time elapsed on the host +sim_insts 66714903 # Number of instructions simulated +sim_ops 66714903 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 472448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20115392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 147008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2145088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 298752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2611904 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.inst 469248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20132864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 150208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2123008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 298368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2617024 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25791552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 472448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 147008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 298752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 918208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7488832 # Number of bytes written to this memory -system.physmem.bytes_written::total 7488832 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7382 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 314303 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2297 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 33517 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4668 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 40811 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25791680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 469248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 150208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 298368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 917824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7488960 # Number of bytes written to this memory +system.physmem.bytes_written::total 7488960 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7332 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 314576 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2347 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 33172 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4662 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 40891 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 402993 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117013 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117013 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 256542 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10922785 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 79826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1164796 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 162224 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1418280 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 402995 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117015 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117015 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 254670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10926493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 81521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1152197 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 161930 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1420309 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14004976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 256542 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 79826 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 162224 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498593 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4066483 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4066483 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4066483 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 256542 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10922785 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 79826 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1164796 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 162224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1418280 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13997642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 254670 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 81521 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 161930 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498121 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4064403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4064403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4064403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 254670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10926493 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 81521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1152197 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 161930 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1420309 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18071459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 81308 # Number of read requests accepted -system.physmem.writeReqs 46917 # Number of write requests accepted -system.physmem.readBursts 81308 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 46917 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5202560 # Total number of bytes read from DRAM +system.physmem.bw_total::total 18062045 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 81087 # Number of read requests accepted +system.physmem.writeReqs 46731 # Number of write requests accepted +system.physmem.readBursts 81087 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 46731 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5188416 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 1152 # Total number of bytes read from write queue -system.physmem.bytesWritten 3000896 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5203712 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 3002688 # Total written bytes from the system interface side +system.physmem.bytesWritten 2989056 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5189568 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2990784 # Total written bytes from the system interface side system.physmem.servicedByWrQ 18 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 4879 # Per bank write bursts -system.physmem.perBankRdBursts::1 4860 # Per bank write bursts -system.physmem.perBankRdBursts::2 4840 # Per bank write bursts -system.physmem.perBankRdBursts::3 5116 # Per bank write bursts -system.physmem.perBankRdBursts::4 5145 # Per bank write bursts -system.physmem.perBankRdBursts::5 5201 # Per bank write bursts -system.physmem.perBankRdBursts::6 5134 # Per bank write bursts -system.physmem.perBankRdBursts::7 5033 # Per bank write bursts -system.physmem.perBankRdBursts::8 5242 # Per bank write bursts -system.physmem.perBankRdBursts::9 4887 # Per bank write bursts -system.physmem.perBankRdBursts::10 5474 # Per bank write bursts -system.physmem.perBankRdBursts::11 5136 # Per bank write bursts -system.physmem.perBankRdBursts::12 4904 # Per bank write bursts -system.physmem.perBankRdBursts::13 4973 # Per bank write bursts +system.physmem.perBankRdBursts::0 4742 # Per bank write bursts +system.physmem.perBankRdBursts::1 4753 # Per bank write bursts +system.physmem.perBankRdBursts::2 4837 # Per bank write bursts +system.physmem.perBankRdBursts::3 5252 # Per bank write bursts +system.physmem.perBankRdBursts::4 5163 # Per bank write bursts +system.physmem.perBankRdBursts::5 5213 # Per bank write bursts +system.physmem.perBankRdBursts::6 5141 # Per bank write bursts +system.physmem.perBankRdBursts::7 5015 # Per bank write bursts +system.physmem.perBankRdBursts::8 5238 # Per bank write bursts +system.physmem.perBankRdBursts::9 4880 # Per bank write bursts +system.physmem.perBankRdBursts::10 5475 # Per bank write bursts +system.physmem.perBankRdBursts::11 5008 # Per bank write bursts +system.physmem.perBankRdBursts::12 4911 # Per bank write bursts +system.physmem.perBankRdBursts::13 4972 # Per bank write bursts system.physmem.perBankRdBursts::14 5564 # Per bank write bursts -system.physmem.perBankRdBursts::15 4902 # Per bank write bursts -system.physmem.perBankWrBursts::0 2770 # Per bank write bursts -system.physmem.perBankWrBursts::1 2825 # Per bank write bursts -system.physmem.perBankWrBursts::2 2866 # Per bank write bursts -system.physmem.perBankWrBursts::3 3058 # Per bank write bursts -system.physmem.perBankWrBursts::4 2994 # Per bank write bursts -system.physmem.perBankWrBursts::5 2828 # Per bank write bursts -system.physmem.perBankWrBursts::6 3105 # Per bank write bursts -system.physmem.perBankWrBursts::7 2723 # Per bank write bursts -system.physmem.perBankWrBursts::8 3290 # Per bank write bursts -system.physmem.perBankWrBursts::9 2741 # Per bank write bursts +system.physmem.perBankRdBursts::15 4905 # Per bank write bursts +system.physmem.perBankWrBursts::0 2655 # Per bank write bursts +system.physmem.perBankWrBursts::1 2725 # Per bank write bursts +system.physmem.perBankWrBursts::2 2864 # Per bank write bursts +system.physmem.perBankWrBursts::3 3189 # Per bank write bursts +system.physmem.perBankWrBursts::4 3009 # Per bank write bursts +system.physmem.perBankWrBursts::5 2838 # Per bank write bursts +system.physmem.perBankWrBursts::6 3113 # Per bank write bursts +system.physmem.perBankWrBursts::7 2705 # Per bank write bursts +system.physmem.perBankWrBursts::8 3288 # Per bank write bursts +system.physmem.perBankWrBursts::9 2746 # Per bank write bursts system.physmem.perBankWrBursts::10 3262 # Per bank write bursts -system.physmem.perBankWrBursts::11 2912 # Per bank write bursts -system.physmem.perBankWrBursts::12 2689 # Per bank write bursts -system.physmem.perBankWrBursts::13 2734 # Per bank write bursts -system.physmem.perBankWrBursts::14 3349 # Per bank write bursts -system.physmem.perBankWrBursts::15 2743 # Per bank write bursts +system.physmem.perBankWrBursts::11 2782 # Per bank write bursts +system.physmem.perBankWrBursts::12 2699 # Per bank write bursts +system.physmem.perBankWrBursts::13 2735 # Per bank write bursts +system.physmem.perBankWrBursts::14 3348 # Per bank write bursts +system.physmem.perBankWrBursts::15 2746 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 6 # Number of times write queue was full causing retry -system.physmem.totGap 1840587284000 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 1841561317000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 81308 # Read request sizes (log2) +system.physmem.readPktSize::6 81087 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 46917 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 63682 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5539 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 4493 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 24 # What read queue length does an incoming req see +system.physmem.writePktSize::6 46731 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 63494 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7529 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4444 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -154,14 +154,14 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 57 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 50 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 38 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 36 # What write queue length does an incoming req see @@ -169,191 +169,189 @@ system.physmem.wrQLenPdf::11 36 # Wh system.physmem.wrQLenPdf::12 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1705 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 1920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2602 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 54 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 21624 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 379.368110 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.960357 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 378.240859 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7179 33.20% 33.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4878 22.56% 55.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1948 9.01% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1045 4.83% 69.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 873 4.04% 73.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 450 2.08% 75.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 417 1.93% 77.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 373 1.72% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4461 20.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 21624 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2049 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 39.666179 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 981.071588 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 2047 99.90% 99.90% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::45 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 21474 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 380.808047 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 217.054900 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 378.494212 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7105 33.09% 33.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4792 22.32% 55.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1974 9.19% 64.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1058 4.93% 69.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 851 3.96% 73.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 468 2.18% 75.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 396 1.84% 77.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 380 1.77% 79.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4450 20.72% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 21474 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2032 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 39.890256 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 985.167686 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 2030 99.90% 99.90% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2049 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2049 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.883846 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.590123 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.999579 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 33 1.61% 1.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 8 0.39% 2.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 1 0.05% 2.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 3 0.15% 2.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 1695 82.72% 84.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 48 2.34% 87.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 10 0.49% 87.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 15 0.73% 88.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 91 4.44% 92.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 8 0.39% 93.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 1 0.05% 93.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 4 0.20% 93.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 2 0.10% 93.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 3 0.15% 93.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.10% 93.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.10% 94.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 2 0.10% 94.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.05% 94.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 2 0.10% 94.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 13 0.63% 94.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 4 0.20% 95.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 77 3.76% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.05% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.10% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.10% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.05% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 2 0.10% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.05% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.05% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.05% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.05% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.05% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 4 0.20% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.05% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.05% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.05% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 4 0.20% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2049 # Writes before turning the bus around for reads -system.physmem.totQLat 885699750 # Total ticks spent queuing -system.physmem.totMemAccLat 2409887250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 406450000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10895.56 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 2032 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2032 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.984252 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.590209 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.991562 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 34 1.67% 1.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 7 0.34% 2.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 3 0.15% 2.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 2 0.10% 2.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 1678 82.58% 84.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 43 2.12% 86.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 12 0.59% 87.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 18 0.89% 88.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 100 4.92% 93.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.10% 93.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 5 0.25% 93.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 3 0.15% 93.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 1 0.05% 93.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.10% 94.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.05% 94.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.10% 94.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 2 0.10% 94.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 1 0.05% 94.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.05% 94.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 7 0.34% 94.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.10% 94.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.10% 94.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 82 4.04% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.05% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.10% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.10% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 1 0.05% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.10% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.05% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.10% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.05% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.05% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.05% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 7 0.34% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 1 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2032 # Writes before turning the bus around for reads +system.physmem.totQLat 878117500 # Total ticks spent queuing +system.physmem.totMemAccLat 2398161250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 405345000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10831.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29645.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.83 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.63 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.83 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.63 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29581.73 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.82 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.62 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.82 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.62 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.69 # Average write queue length when enqueuing -system.physmem.readRowHits 69553 # Number of row buffer hits during reads -system.physmem.writeRowHits 37002 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.56 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.87 # Row buffer hit rate for writes -system.physmem.avgGap 14354355.89 # Average gap between requests -system.physmem.pageHitRate 83.11 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 80733240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 43918875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 313622400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 150135120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 89060552880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 35737868835 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 798596823000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 923983654350 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.983586 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1308907007000 # Time in different power states -system.physmem_0.memoryStateTime::REF 45531980000 # Time in different power states +system.physmem.avgWrQLen 7.72 # Average write queue length when enqueuing +system.physmem.readRowHits 69338 # Number of row buffer hits during reads +system.physmem.writeRowHits 36961 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.09 # Row buffer hit rate for writes +system.physmem.avgGap 14407683.71 # Average gap between requests +system.physmem.pageHitRate 83.18 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 80173800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 43646625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 312904800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 149675040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 89124122880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 35767572390 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 797968033500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 923446129035 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.080170 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1309854007000 # Time in different power states +system.physmem_0.memoryStateTime::REF 45564480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9262769000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9260985250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 82744200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 44962500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 320439600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 153705600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 89060552880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 35470252125 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 802756182000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 927888838905 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.649647 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1309307344000 # Time in different power states -system.physmem_1.memoryStateTime::REF 45531980000 # Time in different power states +system.physmem_1.actEnergy 82169640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 44677875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 319433400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 152966880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 89124122880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 35452017540 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 802163554500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 927338942715 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.741345 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1310300112750 # Time in different power states +system.physmem_1.memoryStateTime::REF 45564480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8896844750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8843530000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4808616 # DTB read hits -system.cpu0.dtb.read_misses 6111 # DTB read misses +system.cpu0.dtb.read_hits 4806164 # DTB read hits +system.cpu0.dtb.read_misses 6050 # DTB read misses system.cpu0.dtb.read_acv 122 # DTB read access violations -system.cpu0.dtb.read_accesses 428608 # DTB read accesses -system.cpu0.dtb.write_hits 3411554 # DTB write hits -system.cpu0.dtb.write_misses 685 # DTB write misses +system.cpu0.dtb.read_accesses 427464 # DTB read accesses +system.cpu0.dtb.write_hits 3411517 # DTB write hits +system.cpu0.dtb.write_misses 679 # DTB write misses system.cpu0.dtb.write_acv 84 # DTB write access violations -system.cpu0.dtb.write_accesses 164458 # DTB write accesses -system.cpu0.dtb.data_hits 8220170 # DTB hits -system.cpu0.dtb.data_misses 6796 # DTB misses +system.cpu0.dtb.write_accesses 163616 # DTB write accesses +system.cpu0.dtb.data_hits 8217681 # DTB hits +system.cpu0.dtb.data_misses 6729 # DTB misses system.cpu0.dtb.data_acv 206 # DTB access violations -system.cpu0.dtb.data_accesses 593066 # DTB accesses -system.cpu0.itb.fetch_hits 2729287 # ITB hits -system.cpu0.itb.fetch_misses 3056 # ITB misses +system.cpu0.dtb.data_accesses 591080 # DTB accesses +system.cpu0.itb.fetch_hits 2722802 # ITB hits +system.cpu0.itb.fetch_misses 3018 # ITB misses system.cpu0.itb.fetch_acv 101 # ITB acv -system.cpu0.itb.fetch_accesses 2732343 # ITB accesses +system.cpu0.itb.fetch_accesses 2725820 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -366,42 +364,42 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 6508 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 3254 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 553026714.363860 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 1352809149.832599 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 3254 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 213500 # Distribution of time spent in the clock gated state +system.cpu0.numPwrStateTransitions 6514 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 3257 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 552798033.019036 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 1352688826.519808 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 3257 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 142000 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 3905515000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 3254 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 42050232460 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1799548928540 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 928788202 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::total 3257 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 42110000457 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 1800463193543 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 928783152 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6425 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211368 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74795 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6426 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211388 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74798 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105681 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182557 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73428 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105692 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182572 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73431 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73428 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148937 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818752965500 98.76% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39793500 0.00% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 370197000 0.02% 98.78% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22435471000 1.22% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841598427000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 73431 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148944 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1819731049500 98.76% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39465000 0.00% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 370305500 0.02% 98.78% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22431640000 1.22% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1842572460000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694808 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815838 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694764 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815810 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -440,500 +438,498 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu0.kern.callpal::swpctx 4175 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175300 91.20% 93.41% # number of callpals executed -system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175313 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed +system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192212 # number of callpals executed +system.cpu0.kern.callpal::total 192227 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1906 -system.cpu0.kern.mode_good::user 1737 +system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1907 +system.cpu0.kern.mode_good::user 1738 system.cpu0.kern.mode_good::idle 169 -system.cpu0.kern.mode_switch_good::kernel 0.321851 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.322020 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.390854 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29766458500 1.62% 1.62% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2570000000 0.14% 1.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809261966500 98.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::idle 0.080668 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.390979 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29732108000 1.61% 1.61% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2585852000 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1810254498000 98.25% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4176 # number of times the context was actually changed -system.cpu0.committedInsts 30028359 # Number of instructions committed -system.cpu0.committedOps 30028359 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 27949209 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 163605 # Number of float alu accesses -system.cpu0.num_func_calls 796078 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3573160 # number of instructions that are conditional controls -system.cpu0.num_int_insts 27949209 # number of integer instructions -system.cpu0.num_fp_insts 163605 # number of float instructions -system.cpu0.num_int_register_reads 38472094 # number of times the integer registers were read -system.cpu0.num_int_register_writes 20603467 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 84586 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 86140 # number of times the floating registers were written -system.cpu0.num_mem_refs 8249833 # number of memory refs -system.cpu0.num_load_insts 4829697 # Number of load instructions -system.cpu0.num_store_insts 3420136 # Number of store instructions -system.cpu0.num_idle_cycles 907169648.432742 # Number of idle cycles -system.cpu0.num_busy_cycles 21618553.567258 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023276 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976724 # Percentage of idle cycles -system.cpu0.Branches 4625246 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1572413 5.24% 5.24% # Class of executed instruction -system.cpu0.op_class::IntAlu 19517057 64.98% 70.22% # Class of executed instruction -system.cpu0.op_class::IntMult 31821 0.11% 70.32% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 70.32% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12868 0.04% 70.36% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 70.36% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1602 0.01% 70.37% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.37% # Class of executed instruction -system.cpu0.op_class::MemRead 4960051 16.51% 86.88% # Class of executed instruction -system.cpu0.op_class::MemWrite 3423231 11.40% 98.28% # Class of executed instruction -system.cpu0.op_class::IprAccess 516318 1.72% 100.00% # Class of executed instruction +system.cpu0.committedInsts 30003730 # Number of instructions committed +system.cpu0.committedOps 30003730 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 27925731 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 163756 # Number of float alu accesses +system.cpu0.num_func_calls 796110 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3567009 # number of instructions that are conditional controls +system.cpu0.num_int_insts 27925731 # number of integer instructions +system.cpu0.num_fp_insts 163756 # number of float instructions +system.cpu0.num_int_register_reads 38434691 # number of times the integer registers were read +system.cpu0.num_int_register_writes 20585928 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 84641 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 86208 # number of times the floating registers were written +system.cpu0.num_mem_refs 8247251 # number of memory refs +system.cpu0.num_load_insts 4827160 # Number of load instructions +system.cpu0.num_store_insts 3420091 # Number of store instructions +system.cpu0.num_idle_cycles 907147772.055444 # Number of idle cycles +system.cpu0.num_busy_cycles 21635379.944556 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023294 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976706 # Percentage of idle cycles +system.cpu0.Branches 4619076 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1571431 5.24% 5.24% # Class of executed instruction +system.cpu0.op_class::IntAlu 19496987 64.97% 70.20% # Class of executed instruction +system.cpu0.op_class::IntMult 31839 0.11% 70.31% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 70.31% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12846 0.04% 70.35% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1596 0.01% 70.36% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.36% # Class of executed instruction +system.cpu0.op_class::MemRead 4957504 16.52% 86.88% # Class of executed instruction +system.cpu0.op_class::MemWrite 3423190 11.41% 98.28% # Class of executed instruction +system.cpu0.op_class::IprAccess 515272 1.72% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 30035361 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1394566 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997816 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13521910 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1395078 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.692583 # Average number of references to valid blocks. +system.cpu0.op_class::total 30010665 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 1394329 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997818 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13513290 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1394841 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.688050 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 257.707457 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 77.564418 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 176.725941 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.503335 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.151493 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.345168 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 257.899506 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 77.334042 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 176.764270 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.503710 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.151043 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.345243 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 64423039 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 64423039 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 3984765 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1069804 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2772856 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7827425 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3123452 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 820342 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1358314 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5302108 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 113859 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19272 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 59831 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 192962 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122665 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21310 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55350 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199325 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7108217 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1890146 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 4131170 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 13129533 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7108217 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1890146 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 4131170 # number of overall hits -system.cpu0.dcache.overall_hits::total 13129533 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 711198 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 95313 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 558903 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1365414 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 164044 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 43456 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 643142 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 850642 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9353 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2169 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7565 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19087 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 26 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 27 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 875242 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 138769 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1202045 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2216056 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 875242 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 138769 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1202045 # number of overall misses -system.cpu0.dcache.overall_misses::total 2216056 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2254809000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 8236813000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 10491622000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1752799000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 19370305557 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 21123104557 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28695000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 118437000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 147132000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 416000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 416000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 4007608000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 27607118557 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 31614726557 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 4007608000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 27607118557 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 31614726557 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4695963 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1165117 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 3331759 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 9192839 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3287496 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 863798 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2001456 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6152750 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 123212 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21441 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 67396 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 212049 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 122666 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21310 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 55376 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199352 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 7983459 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 2028915 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 5333215 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15345589 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 7983459 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 2028915 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 5333215 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15345589 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.151449 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.081806 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.167750 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.148530 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049899 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050308 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.321337 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.138254 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075910 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.101161 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.112247 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090012 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000470 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000135 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109632 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.068396 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.225388 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.144410 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109632 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.068396 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.225388 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.144410 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23656.888357 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14737.464283 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 7683.839480 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40335.028535 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30118.240695 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 24831.955813 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13229.598893 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15655.915400 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7708.492691 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15407.407407 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28879.706563 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 22966.792888 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14266.212838 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 28879.706563 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22966.792888 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14266.212838 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 997927 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2476 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 58775 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 19 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.978766 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 130.315789 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 836681 # number of writebacks -system.cpu0.dcache.writebacks::total 836681 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 289767 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 289767 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 548232 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 548232 # 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number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 69860500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96386500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 390000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 390000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3868839000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7487550240 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11356389240 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3868839000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7487550240 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11356389240 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 248693500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 375591500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 624285000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 248693500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 375591500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 624285000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.081806 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.080779 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039645 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050308 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047420 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022488 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.101161 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.082305 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.036388 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000470 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.068396 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.068260 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032766 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.068396 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.068260 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032766 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 22656.888357 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16506.047129 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 18114.653902 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39335.028535 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32084.909282 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34361.922293 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12229.598893 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12594.285199 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12491.770347 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 15000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27879.706563 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20567.593766 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22585.621431 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27879.706563 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20567.593766 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22585.621431 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 219888.152078 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 217860.498840 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 218663.747811 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 97107.965638 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 99971.120575 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 98810.541311 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 969876 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.205246 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 39683030 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 970387 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 40.894025 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10200405500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 261.920563 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 65.077972 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 184.206711 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.511564 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.127105 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.359779 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998448 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 1713 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 2844 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 1429 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 2015 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3444 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2560 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3728 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6288 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2154855500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4439209000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6594064500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1679571000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3050724099 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4730295099 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 26658500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 69598500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96257000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 194000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 194000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3834426500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7489933099 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11324359599 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3834426500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7489933099 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11324359599 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 248626500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 373633000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 622259500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 248626500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 373633000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 622259500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.081506 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.080873 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039638 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.049939 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047430 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022440 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100656 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.082460 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.036450 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000271 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000075 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.068069 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.068314 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032740 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.068069 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.068314 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032740 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 22668.134145 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16495.951455 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 18107.105198 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38909.581615 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32145.030283 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34259.874260 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12228.669725 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12544.790916 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12455.615942 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 12933.333333 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12933.333333 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27740.068872 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20575.947900 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22547.660583 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27740.068872 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20575.947900 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22547.660583 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 219828.912467 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 218116.170461 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 218797.292546 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 97119.726562 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 100223.444206 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 98959.844148 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 970146 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.204815 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 39666884 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 970657 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 40.866015 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10200765500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 263.084411 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 64.947265 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 183.173139 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.513837 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.126850 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.357760 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998447 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 41646260 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 41646260 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 29526010 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7417850 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2739170 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 39683030 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29526010 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7417850 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2739170 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 39683030 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29526010 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7417850 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2739170 # number of overall hits -system.cpu0.icache.overall_hits::total 39683030 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 509351 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 126603 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 356690 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 992644 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 509351 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 126603 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 356690 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 992644 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 509351 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 126603 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 356690 # number of overall misses -system.cpu0.icache.overall_misses::total 992644 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1812461000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4955400483 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6767861483 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1812461000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4955400483 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6767861483 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1812461000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4955400483 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6767861483 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30035361 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7544453 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3095860 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 40675674 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30035361 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7544453 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3095860 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 40675674 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30035361 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7544453 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3095860 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 40675674 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016958 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016781 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.115215 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.024404 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016958 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016781 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.115215 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.024404 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016958 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016781 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.115215 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.024404 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14316.098355 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13892.737343 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6818.014800 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14316.098355 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13892.737343 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6818.014800 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14316.098355 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13892.737343 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6818.014800 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4716 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 41630359 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 41630359 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 29500548 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7433858 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2732478 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 39666884 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29500548 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7433858 # 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number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 7561080 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 3087765 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 40659510 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016998 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016826 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.115063 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.024413 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016998 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016826 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.115063 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.024413 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016998 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016826 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.115063 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.024413 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14340.059109 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13898.822597 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6812.678677 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14340.059109 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13898.822597 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6812.678677 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14340.059109 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13898.822597 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6812.678677 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4393 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 235 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 224 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.068085 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.611607 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 969876 # 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number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 461235 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 126603 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 334632 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 461235 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1685858000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4399066985 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6084924985 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1685858000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4399066985 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6084924985 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1685858000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4399066985 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6084924985 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016781 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.108090 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011339 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016781 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.108090 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011339 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016781 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.108090 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011339 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13316.098355 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13145.984201 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13192.678320 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13316.098355 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13145.984201 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13192.678320 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13316.098355 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13145.984201 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13192.678320 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 970146 # number of writebacks +system.cpu0.icache.writebacks::total 970146 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 21777 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 21777 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 21777 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 21777 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 21777 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 21777 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 127222 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 333510 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 460732 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 127222 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 333510 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 460732 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 127222 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 333510 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 460732 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1697149000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4385581487 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6082730487 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1697149000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4385581487 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6082730487 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1697149000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4385581487 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6082730487 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016826 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.108010 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011331 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016826 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.108010 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011331 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016826 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.108010 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011331 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13340.059109 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13149.775080 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13202.318239 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13340.059109 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13149.775080 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13202.318239 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13340.059109 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13149.775080 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13202.318239 # average overall mshr miss latency system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1184324 # DTB read hits -system.cpu1.dtb.read_misses 1316 # DTB read misses +system.cpu1.dtb.read_hits 1185765 # DTB read hits +system.cpu1.dtb.read_misses 1350 # DTB read misses system.cpu1.dtb.read_acv 34 # DTB read access violations -system.cpu1.dtb.read_accesses 141546 # DTB read accesses -system.cpu1.dtb.write_hits 885341 # DTB write hits -system.cpu1.dtb.write_misses 169 # DTB write misses -system.cpu1.dtb.write_acv 22 # DTB write access violations -system.cpu1.dtb.write_accesses 57820 # DTB write accesses -system.cpu1.dtb.data_hits 2069665 # DTB hits -system.cpu1.dtb.data_misses 1485 # DTB misses -system.cpu1.dtb.data_acv 56 # DTB access violations -system.cpu1.dtb.data_accesses 199366 # DTB accesses -system.cpu1.itb.fetch_hits 852668 # ITB hits -system.cpu1.itb.fetch_misses 656 # ITB misses -system.cpu1.itb.fetch_acv 33 # ITB acv -system.cpu1.itb.fetch_accesses 853324 # ITB accesses +system.cpu1.dtb.read_accesses 142577 # DTB read accesses +system.cpu1.dtb.write_hits 886140 # DTB write hits +system.cpu1.dtb.write_misses 164 # DTB write misses +system.cpu1.dtb.write_acv 19 # DTB write access violations +system.cpu1.dtb.write_accesses 58302 # DTB write accesses +system.cpu1.dtb.data_hits 2071905 # DTB hits +system.cpu1.dtb.data_misses 1514 # DTB misses +system.cpu1.dtb.data_acv 53 # DTB access violations +system.cpu1.dtb.data_accesses 200879 # DTB accesses +system.cpu1.itb.fetch_hits 858318 # ITB hits +system.cpu1.itb.fetch_misses 678 # ITB misses +system.cpu1.itb.fetch_acv 29 # ITB acv +system.cpu1.itb.fetch_accesses 858996 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -946,17 +942,17 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numPwrStateTransitions 2293 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 1147 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1553407081.081081 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 1902806399.455202 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1147 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 6635637500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 1147 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 59841239000 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1781757922000 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 953375365 # number of cpu cycles simulated +system.cpu1.numPwrStateTransitions 2295 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 1148 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1552918826.219512 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 1902969233.500840 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 1148 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 123500 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 6633070500 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 1148 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 59822381500 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1782750812500 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 953371043 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -976,94 +972,94 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu1.committedInsts 7542911 # Number of instructions committed -system.cpu1.committedOps 7542911 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7009980 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 44709 # Number of float alu accesses -system.cpu1.num_func_calls 205791 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 911955 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7009980 # number of integer instructions -system.cpu1.num_fp_insts 44709 # number of float instructions -system.cpu1.num_int_register_reads 9753806 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5113025 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24116 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24503 # number of times the floating registers were written -system.cpu1.num_mem_refs 2076660 # number of memory refs -system.cpu1.num_load_insts 1189039 # Number of load instructions -system.cpu1.num_store_insts 887621 # Number of store instructions -system.cpu1.num_idle_cycles 923368497.825425 # Number of idle cycles -system.cpu1.num_busy_cycles 30006867.174575 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031474 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968526 # Percentage of idle cycles -system.cpu1.Branches 1183564 # Number of branches fetched -system.cpu1.op_class::No_OpClass 404590 5.36% 5.36% # Class of executed instruction -system.cpu1.op_class::IntAlu 4887103 64.78% 70.14% # Class of executed instruction -system.cpu1.op_class::IntMult 8470 0.11% 70.25% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 70.25% # Class of executed instruction -system.cpu1.op_class::FloatAdd 5131 0.07% 70.32% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 70.32% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 70.32% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 70.32% # Class of executed instruction -system.cpu1.op_class::FloatDiv 810 0.01% 70.33% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::MemRead 1217523 16.14% 86.47% # Class of executed instruction -system.cpu1.op_class::MemWrite 888839 11.78% 98.25% # Class of executed instruction -system.cpu1.op_class::IprAccess 131986 1.75% 100.00% # Class of executed instruction +system.cpu1.committedInsts 7559512 # Number of instructions committed +system.cpu1.committedOps 7559512 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7024268 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 44783 # Number of float alu accesses +system.cpu1.num_func_calls 206891 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 914000 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7024268 # number of integer instructions +system.cpu1.num_fp_insts 44783 # number of float instructions +system.cpu1.num_int_register_reads 9773567 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5124259 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24150 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24568 # number of times the floating registers were written +system.cpu1.num_mem_refs 2078876 # number of memory refs +system.cpu1.num_load_insts 1190479 # Number of load instructions +system.cpu1.num_store_insts 888397 # Number of store instructions +system.cpu1.num_idle_cycles 923345266.952757 # Number of idle cycles +system.cpu1.num_busy_cycles 30025776.047243 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031494 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968506 # Percentage of idle cycles +system.cpu1.Branches 1187005 # Number of branches fetched +system.cpu1.op_class::No_OpClass 406253 5.37% 5.37% # Class of executed instruction +system.cpu1.op_class::IntAlu 4898849 64.79% 70.16% # Class of executed instruction +system.cpu1.op_class::IntMult 8443 0.11% 70.27% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction +system.cpu1.op_class::FloatAdd 5163 0.07% 70.34% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction +system.cpu1.op_class::FloatDiv 816 0.01% 70.35% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::MemRead 1219110 16.12% 86.48% # Class of executed instruction +system.cpu1.op_class::MemWrite 889613 11.77% 98.24% # Class of executed instruction +system.cpu1.op_class::IprAccess 132832 1.76% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7544452 # Class of executed instruction -system.cpu2.branchPred.lookups 10195062 # Number of BP lookups -system.cpu2.branchPred.condPredicted 9245801 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 194837 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 7645666 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 5489178 # Number of BTB hits +system.cpu1.op_class::total 7561079 # Class of executed instruction +system.cpu2.branchPred.lookups 10182069 # Number of BP lookups +system.cpu2.branchPred.condPredicted 9237326 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 193435 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 7648921 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 5487936 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 71.794635 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 367323 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 14555 # Number of incorrect RAS predictions. -system.cpu2.branchPred.indirectLookups 1840410 # Number of indirect predictor lookups. -system.cpu2.branchPred.indirectHits 186758 # Number of indirect target hits. -system.cpu2.branchPred.indirectMisses 1653652 # Number of indirect misses. -system.cpu2.branchPredindirectMispredicted 86236 # Number of mispredicted indirect branches. +system.cpu2.branchPred.BTBHitPct 71.747845 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 365631 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 14350 # Number of incorrect RAS predictions. +system.cpu2.branchPred.indirectLookups 1844704 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 187088 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 1657616 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 85690 # Number of mispredicted indirect branches. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3794321 # DTB read hits -system.cpu2.dtb.read_misses 14980 # DTB read misses -system.cpu2.dtb.read_acv 154 # DTB read access violations -system.cpu2.dtb.read_accesses 231448 # DTB read accesses -system.cpu2.dtb.write_hits 2188085 # DTB write hits -system.cpu2.dtb.write_misses 3764 # DTB write misses +system.cpu2.dtb.read_hits 3799673 # DTB read hits +system.cpu2.dtb.read_misses 14845 # DTB read misses +system.cpu2.dtb.read_acv 160 # DTB read access violations +system.cpu2.dtb.read_accesses 231351 # DTB read accesses +system.cpu2.dtb.write_hits 2187859 # DTB write hits +system.cpu2.dtb.write_misses 3782 # DTB write misses system.cpu2.dtb.write_acv 156 # DTB write access violations -system.cpu2.dtb.write_accesses 84759 # DTB write accesses -system.cpu2.dtb.data_hits 5982406 # DTB hits -system.cpu2.dtb.data_misses 18744 # DTB misses -system.cpu2.dtb.data_acv 310 # DTB access violations -system.cpu2.dtb.data_accesses 316207 # DTB accesses -system.cpu2.itb.fetch_hits 533759 # ITB hits -system.cpu2.itb.fetch_misses 2736 # ITB misses -system.cpu2.itb.fetch_acv 191 # ITB acv -system.cpu2.itb.fetch_accesses 536495 # ITB accesses +system.cpu2.dtb.write_accesses 85049 # DTB write accesses +system.cpu2.dtb.data_hits 5987532 # DTB hits +system.cpu2.dtb.data_misses 18627 # DTB misses +system.cpu2.dtb.data_acv 316 # DTB access violations +system.cpu2.dtb.data_accesses 316400 # DTB accesses +system.cpu2.itb.fetch_hits 533981 # ITB hits +system.cpu2.itb.fetch_misses 2772 # ITB misses +system.cpu2.itb.fetch_acv 207 # ITB acv +system.cpu2.itb.fetch_accesses 536753 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1076,265 +1072,263 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numPwrStateTransitions 3116 # Number of power state transitions -system.cpu2.pwrStateClkGateDist::samples 1558 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::mean 289379505.134788 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::stdev 445107312.150922 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::1000-5e+10 1558 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::min_value 3000 # Distribution of time spent in the clock gated state +system.cpu2.numPwrStateTransitions 3110 # Number of power state transitions +system.cpu2.pwrStateClkGateDist::samples 1555 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::mean 290577901.929260 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::stdev 445615554.555058 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::1000-5e+10 1555 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::min_value 35500 # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::total 1558 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateResidencyTicks::ON 1390745892000 # Cumulative time (in ticks) in various power states -system.cpu2.pwrStateResidencyTicks::CLK_GATED 450853269000 # Cumulative time (in ticks) in various power states -system.cpu2.numCycles 30327275 # number of cpu cycles simulated +system.cpu2.pwrStateClkGateDist::total 1555 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateResidencyTicks::ON 1390724556500 # Cumulative time (in ticks) in various power states +system.cpu2.pwrStateResidencyTicks::CLK_GATED 451848637500 # Cumulative time (in ticks) in various power states +system.cpu2.numCycles 30294700 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9354335 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 40099246 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 10195062 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6043259 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 18967134 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 549482 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 7 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 11119 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1939 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 54610 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 90342 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 596 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3095865 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 133552 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 28754585 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.394534 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.444600 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9331724 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 40046932 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 10182069 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6040655 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 18950980 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 546368 # Number of cycles fetch has spent squashing +system.cpu2.fetch.MiscStallCycles 10813 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1967 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 55421 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 90541 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 526 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3087771 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 132437 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 28714918 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.394639 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.444168 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 19879004 69.13% 69.13% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 339943 1.18% 70.32% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 516791 1.80% 72.11% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4053539 14.10% 86.21% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 887171 3.09% 89.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 213563 0.74% 90.04% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 261735 0.91% 90.95% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 444517 1.55% 92.49% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2158322 7.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 19847963 69.12% 69.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 338255 1.18% 70.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 516605 1.80% 72.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4056347 14.13% 86.22% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 883774 3.08% 89.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 213492 0.74% 90.05% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 260077 0.91% 90.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 443832 1.55% 92.50% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2154573 7.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 28754585 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.336168 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.322217 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7569976 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 12996616 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 7107544 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 570612 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 263955 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 225265 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 11264 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36283979 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 35882 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 263955 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7872857 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4931794 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5918579 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7355041 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2166486 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35279837 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 60983 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 402801 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 76926 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 1084115 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 23748051 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 43586446 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 43526101 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 56436 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 20540056 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 3207995 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 542145 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 75307 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3912291 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3917277 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2333144 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 542030 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 329847 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32377023 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 701408 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 31676973 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 27053 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 3928896 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1754776 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 507029 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 28754585 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.101632 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.635117 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 28714918 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.336101 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.321912 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7553623 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 12980509 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7101757 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 570685 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 262482 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 224592 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 11278 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36245198 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 35745 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 262482 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7856240 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4908054 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5914164 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7349808 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2178317 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35245227 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 60989 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 402200 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 73644 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 1098810 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 23726835 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 43551141 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 43490937 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 56291 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 20541823 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 3185012 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 542390 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 75158 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3906024 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3910206 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2331407 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 534571 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 330323 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32351146 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 700049 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 31671278 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 26658 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 3899534 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1737148 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 505950 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 28714918 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.102956 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.635713 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 17376990 60.43% 60.43% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2804831 9.75% 70.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1408095 4.90% 75.08% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4807285 16.72% 91.80% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1079199 3.75% 95.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 630267 2.19% 97.75% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 421060 1.46% 99.21% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 175258 0.61% 99.82% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 51600 0.18% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 17343310 60.40% 60.40% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2798035 9.74% 70.14% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1407296 4.90% 75.04% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4809954 16.75% 91.79% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1078748 3.76% 95.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 629909 2.19% 97.74% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 420699 1.47% 99.21% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 175678 0.61% 99.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 51289 0.18% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 28754585 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 28714918 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 83759 19.66% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 19.66% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 210235 49.34% 69.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 132097 31.00% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 83963 19.65% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 19.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 211212 49.43% 69.08% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 132122 30.92% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 2450 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 25141274 79.37% 79.38% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20994 0.07% 79.44% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 79.44% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 20528 0.06% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.51% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3966361 12.52% 92.03% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2221145 7.01% 99.04% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 302997 0.96% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 2449 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 25130857 79.35% 79.36% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21000 0.07% 79.42% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 79.42% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 20519 0.06% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.49% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3970834 12.54% 92.03% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2221095 7.01% 99.04% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 303300 0.96% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 31676973 # Type of FU issued -system.cpu2.iq.rate 1.044504 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 426091 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.013451 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 92299555 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 36885759 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 30885842 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 262120 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 128344 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 120451 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 31960571 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 140043 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 222851 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 31671278 # Type of FU issued +system.cpu2.iq.rate 1.045440 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 427297 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.013492 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 92249666 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 36829058 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 30874313 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 261763 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 128201 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 120289 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 31956268 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 139858 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 223032 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 843917 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1448 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 6897 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 272853 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 835467 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1428 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 6657 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 271687 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4760 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 213103 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4727 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 223048 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 263955 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4308277 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 202891 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 34565468 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 70386 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3917277 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2333144 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 625709 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 13182 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 148814 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 6897 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 76158 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 205534 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 281692 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 31394525 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3819678 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 282448 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 262482 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4297358 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 190047 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 34535423 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 71039 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3910206 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2331407 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 624892 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 12907 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 136174 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 6657 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 75410 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 204692 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 280102 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 31389945 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3824957 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 281333 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1487037 # number of nop insts executed -system.cpu2.iew.exec_refs 6017890 # number of memory reference insts executed -system.cpu2.iew.exec_branches 6848661 # Number of branches executed -system.cpu2.iew.exec_stores 2198212 # Number of stores executed -system.cpu2.iew.exec_rate 1.035191 # Inst execution rate -system.cpu2.iew.wb_sent 31083503 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 31006293 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 17785830 # num instructions producing a value -system.cpu2.iew.wb_consumers 21615859 # num instructions consuming a value -system.cpu2.iew.wb_rate 1.022390 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.822814 # average fanout of values written-back -system.cpu2.commit.commitSquashedInsts 4127890 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 194379 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 252373 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 28042775 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.083004 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.865926 # Number of insts commited each cycle +system.cpu2.iew.exec_nop 1484228 # number of nop insts executed +system.cpu2.iew.exec_refs 6022953 # number of memory reference insts executed +system.cpu2.iew.exec_branches 6845679 # Number of branches executed +system.cpu2.iew.exec_stores 2197996 # Number of stores executed +system.cpu2.iew.exec_rate 1.036153 # Inst execution rate +system.cpu2.iew.wb_sent 31070665 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 30994602 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 17781356 # num instructions producing a value +system.cpu2.iew.wb_consumers 21603769 # num instructions consuming a value +system.cpu2.iew.wb_rate 1.023103 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.823067 # average fanout of values written-back +system.cpu2.commit.commitSquashedInsts 4096171 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 194099 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 251035 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 28008857 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.084369 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.866736 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 18161783 64.76% 64.76% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2276613 8.12% 72.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1151869 4.11% 76.99% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 4491226 16.02% 93.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 562178 2.00% 95.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 204579 0.73% 95.74% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 167176 0.60% 96.34% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 177068 0.63% 96.97% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 850283 3.03% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 18128303 64.72% 64.72% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2274965 8.12% 72.85% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1151627 4.11% 76.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 4494039 16.05% 93.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 560514 2.00% 95.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 204888 0.73% 95.74% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 167574 0.60% 96.33% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 175902 0.63% 96.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 851045 3.04% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 28042775 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 30370432 # Number of instructions committed -system.cpu2.commit.committedOps 30370432 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 28008857 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 30371950 # Number of instructions committed +system.cpu2.commit.committedOps 30371950 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5133651 # Number of memory references committed -system.cpu2.commit.loads 3073360 # Number of loads committed -system.cpu2.commit.membars 68499 # Number of memory barriers committed -system.cpu2.commit.branches 6541282 # Number of branches committed -system.cpu2.commit.fp_insts 116010 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 28852886 # Number of committed integer instructions. -system.cpu2.commit.function_calls 241096 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1223345 4.03% 4.03% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 23598567 77.70% 81.73% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 20428 0.07% 81.80% # Class of committed instruction +system.cpu2.commit.refs 5134459 # Number of memory references committed +system.cpu2.commit.loads 3074739 # Number of loads committed +system.cpu2.commit.membars 68371 # Number of memory barriers committed +system.cpu2.commit.branches 6541536 # Number of branches committed +system.cpu2.commit.fp_insts 115785 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 28855389 # Number of committed integer instructions. +system.cpu2.commit.function_calls 240551 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1222737 4.03% 4.03% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 23599707 77.70% 81.73% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20441 0.07% 81.80% # Class of committed instruction system.cpu2.commit.op_class_0::IntDiv 0 0.00% 81.80% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 20084 0.07% 81.86% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 20074 0.07% 81.86% # Class of committed instruction system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 81.86% # Class of committed instruction system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 81.86% # Class of committed instruction system.cpu2.commit.op_class_0::FloatMult 0 0.00% 81.86% # Class of committed instruction @@ -1360,29 +1354,29 @@ system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 81.87% system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 81.87% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3141859 10.35% 92.21% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2061928 6.79% 99.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 302997 1.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3143110 10.35% 92.21% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2061357 6.79% 99.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 303300 1.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 30370432 # Class of committed instruction -system.cpu2.commit.bw_lim_events 850283 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 61616016 # The number of ROB reads -system.cpu2.rob.rob_writes 69709723 # The number of ROB writes -system.cpu2.timesIdled 166720 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1572690 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1745481695 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 29149535 # Number of Instructions Simulated -system.cpu2.committedOps 29149535 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.040403 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.040403 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.961166 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.961166 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 41087551 # number of integer regfile reads -system.cpu2.int_regfile_writes 22005301 # number of integer regfile writes -system.cpu2.fp_regfile_reads 71153 # number of floating regfile reads -system.cpu2.fp_regfile_writes 74234 # number of floating regfile writes -system.cpu2.misc_regfile_reads 4377642 # number of misc regfile reads -system.cpu2.misc_regfile_writes 272877 # number of misc regfile writes +system.cpu2.commit.op_class_0::total 30371950 # Class of committed instruction +system.cpu2.commit.bw_lim_events 851045 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 61550290 # The number of ROB reads +system.cpu2.rob.rob_writes 69643370 # The number of ROB writes +system.cpu2.timesIdled 166665 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1579782 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1747467532 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 29151661 # Number of Instructions Simulated +system.cpu2.committedOps 29151661 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.039210 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.039210 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.962269 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.962269 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 41082611 # number of integer regfile reads +system.cpu2.int_regfile_writes 21995152 # number of integer regfile writes +system.cpu2.fp_regfile_reads 71087 # number of floating regfile reads +system.cpu2.fp_regfile_writes 74140 # number of floating regfile writes +system.cpu2.misc_regfile_reads 4380582 # number of misc regfile reads +system.cpu2.misc_regfile_writes 272883 # number of misc regfile writes system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1395,12 +1389,12 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7317 # Transaction distribution system.iobus.trans_dist::ReadResp 7317 # Transaction distribution -system.iobus.trans_dist::WriteReq 51362 # Transaction distribution -system.iobus.trans_dist::WriteResp 51362 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5192 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51363 # Transaction distribution +system.iobus.trans_dist::WriteResp 51363 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5194 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1409,11 +1403,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1825 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33908 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33910 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 117358 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20768 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 117360 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20776 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1422,42 +1416,42 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9128 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 45568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 45576 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2707176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2373500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2707184 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2361000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 135500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 133500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 56000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5872500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5888500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 2528000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 2490000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 89904673 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 89817179 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9173000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9132000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17468000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17450000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.254561 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.262350 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 1693898501000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.254561 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078410 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078410 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::tsunami.ide 1.262350 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078897 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078897 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1466,14 +1460,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9598462 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9598462 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 2019796211 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 2019796211 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 2029394673 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 2029394673 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 2029394673 # number of overall miss cycles -system.iocache.overall_miss_latency::total 2029394673 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9479963 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9479963 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 2017910216 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 2017910216 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 2027390179 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 2027390179 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 2027390179 # number of overall miss cycles +system.iocache.overall_miss_latency::total 2027390179 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1490,14 +1484,14 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 55482.439306 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 55482.439306 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 48608.880704 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 48608.880704 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 48637.379820 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 48637.379820 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 48637.379820 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 48637.379820 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54797.473988 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 54797.473988 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 48563.491914 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 48563.491914 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 48589.339221 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 48589.339221 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 48589.339221 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 48589.339221 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1506,487 +1500,464 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::tsunami.ide 17280 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 17280 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 17350 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 17350 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 17350 # 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Average number of references to valid blocks. +system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 17264 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 17264 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 17333 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 17333 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 17333 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 17333 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6029963 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 6029963 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1153715348 # 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average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 66909.670051 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 337759 # number of replacements +system.l2c.tags.tagsinuse 65519.967313 # Cycle average of tags in use +system.l2c.tags.total_refs 4324806 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 403281 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.724051 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54641.026539 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2330.416055 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2713.129703 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 574.927105 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 600.162086 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2250.445944 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2311.215132 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.833756 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.035559 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.041399 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008773 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009158 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.034339 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.035266 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998250 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 987 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5975 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2686 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55336 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38533534 # Number of tag accesses -system.l2c.tags.data_accesses 38533534 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 836681 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 836681 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 969577 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 969577 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 234482500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 352216500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 586699000 # number of overall MSHR uncacheable cycles +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.294118 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.172414 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.407099 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.252377 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.137371 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018448 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.013981 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.007220 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.160920 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.061975 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.029900 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018448 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.236601 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.013981 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.110912 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034332 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018448 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.236601 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.013981 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.110912 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034332 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 50500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 50500 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66582.176189 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 79447.540778 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 74005.704932 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72409.458884 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73657.872158 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73239.834499 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 65233.096881 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 65633.844617 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 65441.862601 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72409.458884 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65946.703793 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73657.872158 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73712.701588 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 70495.345745 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72409.458884 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65946.703793 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73657.872158 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73712.701588 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 70495.345745 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 207323.165340 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 205613.835377 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 206293.600563 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91594.726562 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 94478.674893 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 93304.548346 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 823847 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 379580 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 408 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7144 # Transaction distribution -system.membus.trans_dist::ReadResp 295138 # Transaction distribution -system.membus.trans_dist::WriteReq 9810 # Transaction distribution -system.membus.trans_dist::WriteResp 9810 # Transaction distribution -system.membus.trans_dist::WritebackDirty 117013 # Transaction distribution -system.membus.trans_dist::CleanEvict 261704 # Transaction distribution -system.membus.trans_dist::UpgradeReq 179 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.membus.trans_dist::UpgradeResp 113 # Transaction distribution -system.membus.trans_dist::ReadExReq 115428 # Transaction distribution -system.membus.trans_dist::ReadExResp 115428 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288010 # Transaction distribution -system.membus.trans_dist::BadAddressError 16 # Transaction distribution +system.membus.trans_dist::ReadResp 295118 # Transaction distribution +system.membus.trans_dist::WriteReq 9811 # Transaction distribution +system.membus.trans_dist::WriteResp 9811 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117015 # Transaction distribution +system.membus.trans_dist::CleanEvict 261705 # Transaction distribution +system.membus.trans_dist::UpgradeReq 133 # Transaction distribution +system.membus.trans_dist::UpgradeResp 97 # Transaction distribution +system.membus.trans_dist::ReadExReq 115450 # Transaction distribution +system.membus.trans_dist::ReadExResp 115450 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 287989 # Transaction distribution +system.membus.trans_dist::BadAddressError 15 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 24272 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143724 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1177664 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 107800 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 107800 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1285464 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30633664 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 30679232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2664320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33343552 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 157 # Total snoops (count) -system.membus.snoopTraffic 9856 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 742227 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001296 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.035978 # Request fanout histogram +system.membus.trans_dist::InvalidateResp 24288 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143669 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 30 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1177609 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 107817 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 107817 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1285426 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30634176 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 30679752 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2664384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33344136 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 152 # Total snoops (count) +system.membus.snoopTraffic 9536 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 742383 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001299 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.036012 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 741265 99.87% 99.87% # Request fanout histogram -system.membus.snoop_fanout::1 962 0.13% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 741419 99.87% 99.87% # Request fanout histogram +system.membus.snoop_fanout::1 964 0.13% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 742227 # Request fanout histogram -system.membus.reqLayer0.occupancy 10965500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 742383 # Request fanout histogram +system.membus.reqLayer0.occupancy 10929000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 390337877 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 389109129 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 19000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 19500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 436169750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 434990750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 370538 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 365537 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 4730181 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2364664 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1672 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1038 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1038 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 4730225 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2364683 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1647 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1041 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1041 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 7144 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2070392 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 9810 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 866358 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 969876 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 609667 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 31 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 27 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 58 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302472 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302472 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 970586 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1092680 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 41 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2910960 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4218835 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7129795 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124183936 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142881728 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 267065664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 338688 # Total snoops (count) -system.toL2Bus.snoopTraffic 4852416 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 4114055 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.000998 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.031568 # Request fanout histogram +system.toL2Bus.trans_dist::ReadResp 2070475 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 9811 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 9811 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 866906 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 970146 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 608698 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 15 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 44 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302414 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302414 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 970849 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1092499 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 15 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 40 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2911790 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4218095 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7129885 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124220224 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142912456 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 267132680 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 338659 # Total snoops (count) +system.toL2Bus.snoopTraffic 4850432 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 4115169 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.000990 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.031456 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4109951 99.90% 99.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 4104 0.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4111093 99.90% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 4076 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4114055 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1826321500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4115169 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1824758000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 100962 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 98963 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 692196311 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 691417859 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 770446828 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 769604277 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -2018,29 +1989,29 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1842573194000 # Cumulative time (in ticks) in various power states system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 43f49bfd8..14253ba3e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,161 +1,161 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.647778 # Number of seconds simulated -sim_ticks 2647778082500 # Number of ticks simulated -final_tick 2647778082500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.848172 # Number of seconds simulated +sim_ticks 2848172284000 # Number of ticks simulated +final_tick 2848172284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109262 # Simulator instruction rate (inst/s) -host_op_rate 132319 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2267003011 # Simulator tick rate (ticks/s) -host_mem_usage 618500 # Number of bytes of host memory used -host_seconds 1167.96 # Real time elapsed on the host -sim_insts 127613917 # Number of instructions simulated -sim_ops 154544077 # Number of ops (including micro ops) simulated +host_inst_rate 135409 # Simulator instruction rate (inst/s) +host_op_rate 163982 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3007675070 # Simulator tick rate (ticks/s) +host_mem_usage 625764 # Number of bytes of host memory used +host_seconds 946.97 # Real time elapsed on the host +sim_insts 128228197 # Number of instructions simulated +sim_ops 155285827 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 8192 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 8960 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1505216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1244784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8319232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 374976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 749140 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 607232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1677760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1343340 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8401088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 221184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 660436 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 438272 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12811716 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1505216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 374976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1880192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9040448 # Number of bytes written to this memory +system.physmem.bytes_read::total 12753472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1677760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 221184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1898944 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9008896 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 9058012 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 128 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 9026460 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 140 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 23519 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 19972 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 129988 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 30 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 11726 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 9488 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26215 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21511 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 131267 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 22 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3456 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10340 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6848 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 200726 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 141257 # Number of write requests responded to by this memory +system.physmem.num_reads::total 199815 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 140764 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 145648 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3094 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 568483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 470124 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3141967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 141619 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 282932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 229336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4838667 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 568483 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 141619 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 710102 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3414353 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6618 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3420986 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3414353 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3094 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 568483 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 476742 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3141967 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 141619 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 282947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 229336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 8259653 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 200726 # Number of read requests accepted -system.physmem.writeReqs 145648 # Number of write requests accepted -system.physmem.readBursts 200726 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 145648 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12837568 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue -system.physmem.bytesWritten 9070080 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12811716 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9058012 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_writes::total 145155 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 589065 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 471650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2949642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 494 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 77658 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 231881 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 153878 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4477774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 589065 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 77658 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 666724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3163045 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6153 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3169211 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3163045 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 589065 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 477803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2949642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 77658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 231895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 153878 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7646985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 199815 # Number of read requests accepted +system.physmem.writeReqs 145155 # Number of write requests accepted +system.physmem.readBursts 199815 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 145155 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12777984 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10176 # Total number of bytes read from write queue +system.physmem.bytesWritten 9038976 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12753472 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9026460 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12684 # Per bank write bursts -system.physmem.perBankRdBursts::1 12558 # Per bank write bursts -system.physmem.perBankRdBursts::2 12677 # Per bank write bursts -system.physmem.perBankRdBursts::3 12470 # Per bank write bursts -system.physmem.perBankRdBursts::4 15173 # Per bank write bursts -system.physmem.perBankRdBursts::5 12439 # Per bank write bursts -system.physmem.perBankRdBursts::6 12705 # Per bank write bursts -system.physmem.perBankRdBursts::7 12895 # Per bank write bursts -system.physmem.perBankRdBursts::8 12483 # Per bank write bursts -system.physmem.perBankRdBursts::9 12862 # Per bank write bursts -system.physmem.perBankRdBursts::10 12103 # Per bank write bursts -system.physmem.perBankRdBursts::11 11319 # Per bank write bursts -system.physmem.perBankRdBursts::12 11938 # Per bank write bursts -system.physmem.perBankRdBursts::13 12281 # Per bank write bursts -system.physmem.perBankRdBursts::14 12069 # Per bank write bursts -system.physmem.perBankRdBursts::15 11931 # Per bank write bursts -system.physmem.perBankWrBursts::0 9144 # Per bank write bursts -system.physmem.perBankWrBursts::1 9177 # Per bank write bursts -system.physmem.perBankWrBursts::2 9224 # Per bank write bursts -system.physmem.perBankWrBursts::3 8920 # Per bank write bursts -system.physmem.perBankWrBursts::4 8442 # Per bank write bursts -system.physmem.perBankWrBursts::5 8744 # Per bank write bursts -system.physmem.perBankWrBursts::6 9263 # Per bank write bursts -system.physmem.perBankWrBursts::7 9163 # Per bank write bursts -system.physmem.perBankWrBursts::8 8908 # Per bank write bursts -system.physmem.perBankWrBursts::9 9183 # Per bank write bursts -system.physmem.perBankWrBursts::10 8711 # Per bank write bursts -system.physmem.perBankWrBursts::11 8187 # Per bank write bursts -system.physmem.perBankWrBursts::12 8717 # Per bank write bursts -system.physmem.perBankWrBursts::13 8673 # Per bank write bursts -system.physmem.perBankWrBursts::14 8851 # Per bank write bursts -system.physmem.perBankWrBursts::15 8413 # Per bank write bursts +system.physmem.perBankRdBursts::0 12196 # Per bank write bursts +system.physmem.perBankRdBursts::1 12508 # Per bank write bursts +system.physmem.perBankRdBursts::2 12943 # Per bank write bursts +system.physmem.perBankRdBursts::3 12617 # Per bank write bursts +system.physmem.perBankRdBursts::4 14662 # Per bank write bursts +system.physmem.perBankRdBursts::5 11885 # Per bank write bursts +system.physmem.perBankRdBursts::6 12499 # Per bank write bursts +system.physmem.perBankRdBursts::7 12704 # Per bank write bursts +system.physmem.perBankRdBursts::8 12537 # Per bank write bursts +system.physmem.perBankRdBursts::9 12319 # Per bank write bursts +system.physmem.perBankRdBursts::10 11826 # Per bank write bursts +system.physmem.perBankRdBursts::11 10998 # Per bank write bursts +system.physmem.perBankRdBursts::12 12485 # Per bank write bursts +system.physmem.perBankRdBursts::13 13119 # Per bank write bursts +system.physmem.perBankRdBursts::14 12369 # Per bank write bursts +system.physmem.perBankRdBursts::15 11989 # Per bank write bursts +system.physmem.perBankWrBursts::0 8816 # Per bank write bursts +system.physmem.perBankWrBursts::1 9166 # Per bank write bursts +system.physmem.perBankWrBursts::2 9495 # Per bank write bursts +system.physmem.perBankWrBursts::3 9136 # Per bank write bursts +system.physmem.perBankWrBursts::4 8038 # Per bank write bursts +system.physmem.perBankWrBursts::5 8411 # Per bank write bursts +system.physmem.perBankWrBursts::6 8988 # Per bank write bursts +system.physmem.perBankWrBursts::7 8984 # Per bank write bursts +system.physmem.perBankWrBursts::8 9026 # Per bank write bursts +system.physmem.perBankWrBursts::9 8762 # Per bank write bursts +system.physmem.perBankWrBursts::10 8598 # Per bank write bursts +system.physmem.perBankWrBursts::11 8287 # Per bank write bursts +system.physmem.perBankWrBursts::12 9114 # Per bank write bursts +system.physmem.perBankWrBursts::13 9118 # Per bank write bursts +system.physmem.perBankWrBursts::14 8888 # Per bank write bursts +system.physmem.perBankWrBursts::15 8407 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 30 # Number of times write queue was full causing retry -system.physmem.totGap 2647777471000 # Total gap between requests +system.physmem.numWrRetry 34 # Number of times write queue was full causing retry +system.physmem.totGap 2848171745000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 553 # Read request sizes (log2) +system.physmem.readPktSize::2 552 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 200145 # Read request sizes (log2) +system.physmem.readPktSize::6 199235 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 141257 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 87468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 62195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7877 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4696 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 756 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 239 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 140764 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 87471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61591 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9741 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6337 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5222 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4637 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3767 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 267 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 180 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -185,165 +185,162 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 90 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 94963 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 230.695997 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 131.239554 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 294.689609 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 52509 55.29% 55.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18085 19.04% 74.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6234 6.56% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3686 3.88% 84.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2895 3.05% 87.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1483 1.56% 89.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 908 0.96% 90.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1023 1.08% 91.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8140 8.57% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 94963 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7063 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.398839 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 555.406402 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7061 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6626 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 88 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 88570 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 246.323767 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 141.050118 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 301.878369 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 44937 50.74% 50.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18529 20.92% 71.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6585 7.43% 79.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3856 4.35% 83.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3004 3.39% 86.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1517 1.71% 88.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 921 1.04% 89.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1037 1.17% 90.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8184 9.24% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 88570 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7038 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.368144 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 555.266808 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7037 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7063 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7063 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.065128 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.613340 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.212436 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5945 84.17% 84.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 392 5.55% 89.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 71 1.01% 90.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 48 0.68% 91.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 279 3.95% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 27 0.38% 95.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 19 0.27% 96.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 25 0.35% 96.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 16 0.23% 96.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 12 0.17% 96.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.04% 96.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 7 0.10% 96.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 160 2.27% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.08% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.06% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 5 0.07% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 7 0.10% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 4 0.06% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 3 0.04% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.01% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.11% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.01% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 7038 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7038 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.067349 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.571017 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.392738 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5944 84.46% 84.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 388 5.51% 89.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 60 0.85% 90.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 46 0.65% 91.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 266 3.78% 95.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 21 0.30% 95.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 22 0.31% 95.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 25 0.36% 96.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 15 0.21% 96.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 13 0.18% 96.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.06% 96.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 13 0.18% 96.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 149 2.12% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.07% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 7 0.10% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 11 0.16% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 6 0.09% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 4 0.06% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 7 0.10% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 9 0.13% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.11% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.04% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.01% 99.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-163 4 0.06% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7063 # Writes before turning the bus around for reads -system.physmem.totQLat 5391615341 # Total ticks spent queuing -system.physmem.totMemAccLat 9152621591 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1002935000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26879.19 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::176-179 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7038 # Writes before turning the bus around for reads +system.physmem.totQLat 5532611303 # Total ticks spent queuing +system.physmem.totMemAccLat 9276161303 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 998280000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27710.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45629.19 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.85 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.43 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.42 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46460.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.49 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.17 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.48 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.36 # Average write queue length when enqueuing -system.physmem.readRowHits 166580 # Number of row buffer hits during reads -system.physmem.writeRowHits 80763 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.05 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 56.97 # Row buffer hit rate for writes -system.physmem.avgGap 7644273.16 # Average gap between requests -system.physmem.pageHitRate 72.25 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 370341720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 202071375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 808080000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 467058960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 172939896480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 79567681680 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1518869897250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1773225027465 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.703351 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2526645938707 # Time in different power states -system.physmem_0.memoryStateTime::REF 88415080000 # Time in different power states +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.18 # Average write queue length when enqueuing +system.physmem.readRowHits 165300 # Number of row buffer hits during reads +system.physmem.writeRowHits 87019 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.79 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 61.60 # Row buffer hit rate for writes +system.physmem.avgGap 8256288.21 # Average gap between requests +system.physmem.pageHitRate 74.01 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 339738840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 185373375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 795709200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 460300320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186028705200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83305465515 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1635827969250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1906943261700 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.532441 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2721218544299 # Time in different power states +system.physmem_0.memoryStateTime::REF 95106700000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32716967293 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31846334451 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 347578560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 189651000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 756490800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 451286640 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 172939896480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 78874475895 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1519477980750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1773037360125 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.632470 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2527659145749 # Time in different power states -system.physmem_1.memoryStateTime::REF 88415080000 # Time in different power states +system.physmem_1.actEnergy 329850360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 179977875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 761599800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 454896000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186028705200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82993384530 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1636101724500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1906850138265 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.499746 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2721674822130 # Time in different power states +system.physmem_1.memoryStateTime::REF 95106700000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 31702650501 # Time in different power states +system.physmem_1.memoryStateTime::ACT 31390664370 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory @@ -353,39 +350,39 @@ system.realview.nvmem.bytes_inst_read::total 1344 system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 193 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 314 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 508 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 193 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 314 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 508 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 193 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 314 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 508 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 292 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 472 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 292 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 472 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 34732065 # Number of BP lookups -system.cpu0.branchPred.condPredicted 16497595 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1496295 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 19609177 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 10269070 # Number of BTB hits +system.cpu0.branchPred.lookups 20844041 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13655604 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1017556 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 13118749 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 8767800 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 52.368695 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 11117365 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 739154 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4170441 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 3984607 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 185834 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 94839 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 66.834117 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3422259 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 208349 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 764708 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 581484 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 183224 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 100888 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -415,61 +412,61 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 65243 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 65243 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44492 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 20751 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 65243 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 65243 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 65243 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6699 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12206.821914 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11332.778692 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 5808.192470 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6323 94.39% 94.39% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 330 4.93% 99.31% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 32 0.48% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 7 0.10% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 3 0.04% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.04% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6699 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 67283 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 67283 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46446 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 20837 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 67283 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 67283 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 67283 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6844 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12453.243717 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11569.675575 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5895.982503 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6363 92.97% 92.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 412 6.02% 98.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 59 0.86% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 3 0.04% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.07% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6844 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 338010000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 338010000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 338010000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5176 77.27% 77.27% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1523 22.73% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6699 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65243 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5263 76.90% 76.90% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1581 23.10% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6844 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67283 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65243 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6699 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67283 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6844 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6699 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 71942 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6844 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 74127 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 23418517 # DTB read hits -system.cpu0.dtb.read_misses 59363 # DTB read misses -system.cpu0.dtb.write_hits 17357852 # DTB write hits -system.cpu0.dtb.write_misses 5880 # DTB write misses +system.cpu0.dtb.read_hits 17352300 # DTB read hits +system.cpu0.dtb.read_misses 60872 # DTB read misses +system.cpu0.dtb.write_hits 14551648 # DTB write hits +system.cpu0.dtb.write_misses 6411 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3435 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1178 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1722 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3450 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1427 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1946 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 516 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 23477880 # DTB read accesses -system.cpu0.dtb.write_accesses 17363732 # DTB write accesses +system.cpu0.dtb.perms_faults 519 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17413172 # DTB read accesses +system.cpu0.dtb.write_accesses 14558059 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 40776369 # DTB hits -system.cpu0.dtb.misses 65243 # DTB misses -system.cpu0.dtb.accesses 40841612 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 31903948 # DTB hits +system.cpu0.dtb.misses 67283 # DTB misses +system.cpu0.dtb.accesses 31971231 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -499,41 +496,42 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 4001 # Table walker walks requested -system.cpu0.itb.walker.walksShort 4001 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 3992 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3992 # Table walker walks initiated with short descriptors system.cpu0.itb.walker.walksShortTerminationLevel::Level1 306 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3695 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 4001 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 4001 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 4001 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2427 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12648.125258 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11968.911523 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 4734.087286 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 373 15.37% 15.37% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1885 77.67% 93.04% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 118 4.86% 97.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 27 1.11% 99.01% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 22 0.91% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3686 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3992 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3992 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3992 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2438 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12900.533224 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 12073.120538 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5370.959057 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 392 16.08% 16.08% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1803 73.95% 90.03% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 168 6.89% 96.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 38 1.56% 98.48% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 34 1.39% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2427 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2438 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 337545500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 337545500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 337545500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2126 87.60% 87.60% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 301 12.40% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2427 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2137 87.65% 87.65% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 301 12.35% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2438 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4001 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4001 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3992 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3992 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2427 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2427 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6428 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 68314752 # ITB inst hits -system.cpu0.itb.inst_misses 4001 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2438 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2438 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6430 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 38811638 # ITB inst hits +system.cpu0.itb.inst_misses 3992 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -542,795 +540,802 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2164 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2175 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7135 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7061 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 68318753 # ITB inst accesses -system.cpu0.itb.hits 68314752 # DTB hits -system.cpu0.itb.misses 4001 # DTB misses -system.cpu0.itb.accesses 68318753 # DTB accesses -system.cpu0.numPwrStateTransitions 4126 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 2063 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1227700157.144935 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 21500702795.368797 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1198 58.07% 58.07% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 860 41.69% 99.76% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.81% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.05% 99.85% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 3 0.15% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 38815630 # ITB inst accesses +system.cpu0.itb.hits 38811638 # DTB hits +system.cpu0.itb.misses 3992 # DTB misses +system.cpu0.itb.accesses 38815630 # DTB accesses +system.cpu0.numPwrStateTransitions 3698 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1849 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1494392801.532720 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23960009045.887756 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1074 58.09% 58.09% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 768 41.54% 99.62% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.68% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.05% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499984309000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 2063 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 115032658310 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2532745424190 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 230068064 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 499963441540 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1849 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 85039993966 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2763132290034 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 170082548 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 106706103 # Number of instructions committed -system.cpu0.committedOps 129024022 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 8506641 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 2063 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5065528558 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.156091 # CPI: cycles per instruction -system.cpu0.ipc 0.463802 # IPC: instructions per cycle -system.cpu0.op_class_0::No_OpClass 2272 0.00% 0.00% # Class of committed instruction -system.cpu0.op_class_0::IntAlu 87919988 68.14% 68.14% # Class of committed instruction -system.cpu0.op_class_0::IntMult 105727 0.08% 68.23% # Class of committed instruction -system.cpu0.op_class_0::IntDiv 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::FloatAdd 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::FloatCmp 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::FloatCvt 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::FloatMult 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::FloatDiv 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::FloatSqrt 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdAdd 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdAddAcc 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdAlu 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdCmp 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdCvt 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdMisc 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdMult 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdMultAcc 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdShift 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdSqrt 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMisc 7151 0.01% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMult 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 68.23% # Class of committed instruction -system.cpu0.op_class_0::MemRead 22900542 17.75% 85.98% # Class of committed instruction -system.cpu0.op_class_0::MemWrite 18088342 14.02% 100.00% # Class of committed instruction +system.cpu0.committedInsts 79775908 # Number of instructions committed +system.cpu0.committedOps 96002231 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 5290576 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1849 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5526291371 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.132004 # CPI: cycles per instruction +system.cpu0.ipc 0.469042 # IPC: instructions per cycle +system.cpu0.op_class_0::No_OpClass 2273 0.00% 0.00% # Class of committed instruction +system.cpu0.op_class_0::IntAlu 63778191 66.43% 66.44% # Class of committed instruction +system.cpu0.op_class_0::IntMult 92152 0.10% 66.53% # Class of committed instruction +system.cpu0.op_class_0::IntDiv 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatAdd 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatCmp 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatCvt 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatMult 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatDiv 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdAdd 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdAlu 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdCmp 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdCvt 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdMisc 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdMult 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdMultAcc 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdShift 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdSqrt 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.53% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMisc 8115 0.01% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.54% # Class of committed instruction +system.cpu0.op_class_0::MemRead 16825163 17.53% 84.07% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 15296337 15.93% 100.00% # Class of committed instruction system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.op_class_0::total 129024022 # Class of committed instruction +system.cpu0.op_class_0::total 96002231 # Class of committed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 2063 # number of quiesce instructions executed -system.cpu0.tickCycles 178511666 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 51556398 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 681177 # number of replacements -system.cpu0.dcache.tags.tagsinuse 487.337065 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 39381714 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 681689 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 57.770793 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 1849 # number of quiesce instructions executed +system.cpu0.tickCycles 121004168 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 49078380 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 716277 # number of replacements +system.cpu0.dcache.tags.tagsinuse 496.364938 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 30460734 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 716789 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 42.496096 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 356009000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 487.337065 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.951830 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.951830 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.364938 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.969463 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.969463 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 81578447 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 81578447 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 21978387 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 21978387 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 16273218 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 16273218 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 306177 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 306177 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 357355 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 357355 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 352292 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 352292 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 38251605 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 38251605 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 38557782 # number of overall hits -system.cpu0.dcache.overall_hits::total 38557782 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 418335 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 418335 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 561531 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 561531 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 131453 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 131453 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20802 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20802 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21460 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 21460 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 979866 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 979866 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1111319 # number of overall misses -system.cpu0.dcache.overall_misses::total 1111319 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5562272000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5562272000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10028849500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10028849500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 328076000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 328076000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 523772000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 523772000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 516000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 516000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 15591121500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 15591121500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 15591121500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 15591121500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 22396722 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 22396722 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 16834749 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 16834749 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 437630 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 437630 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 378157 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 378157 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 373752 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 373752 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 39231471 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 39231471 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 39669101 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 39669101 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.018678 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.018678 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033355 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.033355 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.300375 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300375 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055009 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055009 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.057418 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.057418 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024977 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.024977 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028015 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.028015 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13296.214756 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13296.214756 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17859.832316 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17859.832316 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15771.368138 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15771.368138 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24406.896552 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24406.896552 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 63863131 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63863131 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 15863909 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 15863909 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 13436402 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 13436402 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320993 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 320993 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365530 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 365530 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361278 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361278 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 29300311 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 29300311 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 29621304 # number of overall hits +system.cpu0.dcache.overall_hits::total 29621304 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 439369 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 439369 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 580672 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 580672 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 135956 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 135956 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21086 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21086 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20448 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20448 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1020041 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1020041 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1155997 # number of overall misses +system.cpu0.dcache.overall_misses::total 1155997 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6148409000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6148409000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10121621500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10121621500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 324178500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 324178500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 483049500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 483049500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 688000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 688000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 16270030500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 16270030500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 16270030500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 16270030500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16303278 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16303278 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 14017074 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 14017074 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456949 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 456949 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386616 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386616 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381726 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381726 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 30320352 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 30320352 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 30777301 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 30777301 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.026950 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.026950 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041426 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.041426 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.297530 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.297530 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054540 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054540 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053567 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053567 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033642 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.033642 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037560 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.037560 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13993.725092 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13993.725092 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17430.875778 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17430.875778 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15374.110784 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15374.110784 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23623.312793 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23623.312793 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15911.483305 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15911.483305 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14029.384452 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14029.384452 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15950.369152 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15950.369152 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14074.457373 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14074.457373 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 681177 # number of writebacks -system.cpu0.dcache.writebacks::total 681177 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 44450 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 44450 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 246335 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 246335 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14695 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14695 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 290785 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 290785 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 290785 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 290785 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 373885 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 373885 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 315196 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 315196 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 98829 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 98829 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6107 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6107 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21460 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 21460 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 689081 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 689081 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 787910 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 787910 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29629 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29629 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26357 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26357 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 55986 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 55986 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4452451000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4452451000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5571993500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5571993500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1619437000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1619437000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94023500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94023500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 502325000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 502325000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 503000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 503000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10024444500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10024444500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11643881500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11643881500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6101487500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6101487500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6101487500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6101487500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016694 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016694 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018723 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018723 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225828 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225828 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016149 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016149 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.057418 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.057418 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017564 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.017564 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019862 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.019862 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11908.610937 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11908.610937 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17677.868691 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17677.868691 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16386.253023 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16386.253023 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15396.020960 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15396.020960 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23407.502330 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23407.502330 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 716277 # number of writebacks +system.cpu0.dcache.writebacks::total 716277 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 44943 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 44943 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 255413 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 255413 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14625 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14625 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 300356 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 300356 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 300356 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 300356 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 394426 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 394426 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325259 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 325259 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102388 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 102388 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6461 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6461 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20448 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20448 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 719685 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 719685 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 822073 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 822073 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20384 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20384 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19085 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19085 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39469 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39469 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5005155000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5005155000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5561809000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5561809000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1663563000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1663563000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 98784500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 98784500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 462621500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 462621500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 668000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 668000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10566964000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10566964000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12230527000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 12230527000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4556252000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4556252000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4556252000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4556252000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024193 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024193 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023204 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023204 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224069 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224069 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016712 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016712 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053567 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053567 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023736 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023736 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026710 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026710 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12689.718731 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12689.718731 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17099.631371 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17099.631371 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16247.636442 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16247.636442 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15289.351494 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15289.351494 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22624.290884 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22624.290884 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14547.556093 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14547.556093 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14778.187230 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14778.187230 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 205929.579129 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205929.579129 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 108982.379523 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 108982.379523 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1887196 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.757846 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 66419655 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1887708 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 35.185344 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6638125000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.757846 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999527 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999527 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14682.762598 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14682.762598 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14877.665365 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14877.665365 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223520.996860 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223520.996860 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115438.749398 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115438.749398 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1970602 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.774874 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 36833218 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1971114 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 18.686498 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6638665000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774874 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999560 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999560 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 138502472 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 138502472 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 66419655 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 66419655 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 66419655 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 66419655 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 66419655 # number of overall hits -system.cpu0.icache.overall_hits::total 66419655 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1887721 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1887721 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1887721 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1887721 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1887721 # number of overall misses -system.cpu0.icache.overall_misses::total 1887721 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 17836461000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 17836461000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 17836461000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 17836461000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 17836461000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 17836461000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 68307376 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 68307376 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 68307376 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 68307376 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 68307376 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 68307376 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.027636 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.027636 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.027636 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.027636 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.027636 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.027636 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9448.674354 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9448.674354 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9448.674354 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9448.674354 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9448.674354 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9448.674354 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 79579816 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 79579816 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 36833218 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 36833218 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 36833218 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 36833218 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 36833218 # number of overall hits +system.cpu0.icache.overall_hits::total 36833218 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1971127 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1971127 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1971127 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1971127 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1971127 # number of overall misses +system.cpu0.icache.overall_misses::total 1971127 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 19380486500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 19380486500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 19380486500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 19380486500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 19380486500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 19380486500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 38804345 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 38804345 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 38804345 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 38804345 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 38804345 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 38804345 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050797 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.050797 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050797 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.050797 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050797 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.050797 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9832.185597 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9832.185597 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9832.185597 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9832.185597 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9832.185597 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9832.185597 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1887196 # number of writebacks -system.cpu0.icache.writebacks::total 1887196 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1887721 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1887721 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1887721 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1887721 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1887721 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1887721 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1970602 # number of writebacks +system.cpu0.icache.writebacks::total 1970602 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1971127 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1971127 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1971127 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1971127 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1971127 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1971127 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3448 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 3448 # 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number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 18394923500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 18394923500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 18394923500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 18394923500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 319413000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 319413000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 319413000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 319413000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027636 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027636 # 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average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050797 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050797 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050797 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.050797 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050797 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.050797 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9332.185851 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9332.185851 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9332.185851 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9332.185851 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9332.185851 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9332.185851 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92637.180974 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92637.180974 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92637.180974 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92637.180974 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1767222 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1767306 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 74 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1842994 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1843099 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 91 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 225214 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 281957 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16020.304669 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 4495555 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 298080 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 15.081706 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 234669 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 289615 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15618.929391 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2598682 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 305234 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 8.513737 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15153.098614 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.898882 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.073768 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 805.233405 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.924872 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003778 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.049148 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.977802 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1000 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15110 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 18 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 315 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 390 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 277 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 14506.516440 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 65.609020 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.093662 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1046.710270 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.885407 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004004 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063886 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.953304 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 240 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15363 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 27 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 131 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 75 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 335 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4038 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7911 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2755 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.061035 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.922241 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 85783129 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 85783129 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77844 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5474 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 83318 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 465182 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 465182 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 2062277 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 2062277 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 213330 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 213330 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1827339 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1827339 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 378100 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 378100 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77844 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5474 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1827339 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 591430 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 2502087 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 77844 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5474 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1827339 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 591430 # number of overall hits -system.cpu0.l2cache.overall_hits::total 2502087 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 760 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 121 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 881 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 57605 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 57605 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 21456 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 21456 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44266 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 44266 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 60382 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 60382 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 100716 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 100716 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 760 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 121 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 60382 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 144982 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 206245 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 760 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 121 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 60382 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 144982 # number of overall misses -system.cpu0.l2cache.overall_misses::total 206245 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 27717500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2799500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 30517000 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 116554500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 116554500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 30031000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 30031000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 482498 # 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mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999951 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999951 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.161648 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.161648 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.031959 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.031959 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.209586 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.209586 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009669 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.021626 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.031959 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.192817 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075029 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009669 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.021626 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.031959 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.192817 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.163902 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.163902 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.046599 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.046599 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.226148 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.226148 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.011434 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.032736 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.046599 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.204489 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.088642 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.011434 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.032736 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.046599 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.204489 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.166430 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30470.394737 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17136.363636 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28639.046538 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56558.077101 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56558.077101 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19461.965107 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19461.965107 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15860.109060 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15860.109060 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 101124.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 101124.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40772.358309 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40772.358309 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43199.340284 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43199.340284 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23209.032047 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23209.032047 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30470.394737 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17136.363636 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43199.340284 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28359.545844 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32766.548688 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30470.394737 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17136.363636 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43199.340284 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28359.545844 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56558.077101 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45832.549870 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.181851 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29462.621885 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17290.055249 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27466.938406 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 54426.267559 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 54426.267559 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17296.446835 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17296.446835 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15079.795510 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15079.795510 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 515999 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 515999 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39199.922757 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39199.922757 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 38321.366749 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 38321.366749 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24124.678165 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24124.678165 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29462.621885 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17290.055249 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38321.366749 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28328.993195 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31984.995219 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29462.621885 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17290.055249 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38321.366749 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28328.993195 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 54426.267559 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 43487.383325 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84637.180974 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197926.474063 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 186117.014844 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215516.311813 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196580.794730 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84637.180974 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 104746.963527 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103580.315981 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 5292246 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2668157 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 40914 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 334901 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 330475 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4426 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 126809 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2542571 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 26357 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 26357 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 693110 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 2103191 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 223137 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 294264 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 92982 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43850 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 116200 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 14 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 275510 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 272175 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1887721 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 569608 # Transaction distribution +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111304.682156 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109162.185148 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 5528539 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2785631 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 42665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 220679 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 216467 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4212 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 119671 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2643248 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19085 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19085 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 716138 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 2204203 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 105351 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 312801 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 88645 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43001 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 114336 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 287716 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284337 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1971127 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 603215 # Transaction distribution system.cpu0.toL2Bus.trans_dist::InvalidateReq 3113 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5669533 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2525108 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13291 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 164598 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 8372530 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 241815296 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 94996751 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22380 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 314416 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 337148843 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1025467 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 18711896 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 3771293 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.106316 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.312026 # Request fanout histogram +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5919751 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2595390 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13207 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 168847 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 8697195 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 252491264 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99508828 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22116 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 322908 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 352345116 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 940127 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 19140516 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 3787201 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.076346 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.269706 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 3374771 89.49% 89.49% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 392096 10.40% 99.88% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 4426 0.12% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 3502276 92.48% 92.48% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 280713 7.41% 99.89% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4212 0.11% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3771293 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 5293903990 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3787201 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 5519275492 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 114422325 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 116183079 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2837181638 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2962129461 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1188012916 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1227256511 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7701489 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7683988 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 86027432 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 88134970 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 5469499 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3374978 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 316517 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 3346860 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 2136825 # Number of BTB hits +system.cpu1.branchPred.lookups 19426531 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6224342 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 651829 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 10038478 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3634441 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 63.845664 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 972408 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 68961 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 195238 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 132437 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 62801 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 28788 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 36.205100 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 8674574 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 447731 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 3678807 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 3614078 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 64729 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 23620 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1360,59 +1365,66 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 30404 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 30404 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 23807 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6597 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 30404 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 30404 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 30404 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2736 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12207.419591 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11247.456123 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 8821.385005 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 2714 99.20% 99.20% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 14 0.51% 99.71% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 4 0.15% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 3 0.11% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2736 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1954228032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1954228032 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1954228032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 2033 74.31% 74.31% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 703 25.69% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2736 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30404 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 27735 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 27735 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 21301 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6434 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 27735 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 27735 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 27735 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2744 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12429.118076 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11482.413236 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6276.586572 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 644 23.47% 23.47% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1820 66.33% 89.80% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 198 7.22% 97.01% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 63 2.30% 99.31% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 9 0.33% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 4 0.15% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 1 0.04% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.04% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::90112-98303 1 0.04% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2744 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1939283032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1939283032 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1939283032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 2036 74.20% 74.20% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 708 25.80% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2744 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 27735 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30404 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2736 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 27735 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2744 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2736 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 33140 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2744 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 30479 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 5173966 # DTB read hits -system.cpu1.dtb.read_misses 27871 # DTB read misses -system.cpu1.dtb.write_hits 4222414 # DTB write hits -system.cpu1.dtb.write_misses 2533 # DTB write misses +system.cpu1.dtb.read_hits 11374009 # DTB read hits +system.cpu1.dtb.read_misses 25676 # DTB read misses +system.cpu1.dtb.write_hits 7084428 # DTB write hits +system.cpu1.dtb.write_misses 2059 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2009 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 306 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 555 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1996 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 172 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 434 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 5201837 # DTB read accesses -system.cpu1.dtb.write_accesses 4224947 # DTB write accesses +system.cpu1.dtb.perms_faults 262 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 11399685 # DTB read accesses +system.cpu1.dtb.write_accesses 7086487 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 9396380 # DTB hits -system.cpu1.dtb.misses 30404 # DTB misses -system.cpu1.dtb.accesses 9426784 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 18458437 # DTB hits +system.cpu1.dtb.misses 27735 # DTB misses +system.cpu1.dtb.accesses 18486172 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1442,44 +1454,46 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 2488 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2488 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 182 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2306 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2488 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2488 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2488 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1135 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12427.312775 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11760.899210 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5007.072010 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 4 0.35% 0.35% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 156 13.74% 14.10% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 686 60.44% 74.54% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 210 18.50% 93.04% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 30 2.64% 95.68% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.18% 95.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 21 1.85% 97.71% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 8 0.70% 98.41% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 15 1.32% 99.74% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.26% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1135 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1954817532 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1954817532 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1954817532 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 965 85.02% 85.02% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 170 14.98% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1135 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 2480 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2480 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 180 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2300 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2480 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2480 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2480 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1130 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12659.734513 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11853.270475 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5315.711785 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 183 16.19% 16.19% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 614 54.34% 70.53% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 213 18.85% 89.38% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 45 3.98% 93.36% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 23 2.04% 95.40% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 28 2.48% 97.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 15 1.33% 99.20% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.18% 99.38% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 4 0.35% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::53248-57343 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1130 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1939872532 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1939872532 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1939872532 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 965 85.40% 85.40% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 165 14.60% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1130 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2488 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2488 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2480 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2480 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1135 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1135 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 3623 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 10174079 # ITB inst hits -system.cpu1.itb.inst_misses 2488 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1130 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1130 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 3610 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 39704875 # ITB inst hits +system.cpu1.itb.inst_misses 2480 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1488,778 +1502,777 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1107 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1100 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1891 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1840 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 10176567 # ITB inst accesses -system.cpu1.itb.hits 10174079 # DTB hits -system.cpu1.itb.misses 2488 # DTB misses -system.cpu1.itb.accesses 10176567 # DTB accesses -system.cpu1.numPwrStateTransitions 5445 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2723 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 962192053.212266 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 19383110303.670654 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1861 68.34% 68.34% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 855 31.40% 99.74% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 3 0.11% 99.85% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 4 0.15% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 39707355 # ITB inst accesses +system.cpu1.itb.hits 39704875 # DTB hits +system.cpu1.itb.misses 2480 # DTB misses +system.cpu1.itb.accesses 39707355 # DTB accesses +system.cpu1.numPwrStateTransitions 5533 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2767 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1008221990.514637 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25700822378.312321 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1966 71.05% 71.05% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 797 28.80% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 499966911836 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2723 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 27729121603 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2620048960897 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 55461727 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 949980874116 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2767 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 58422036246 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2789750247754 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 116847616 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 20907814 # Number of instructions committed -system.cpu1.committedOps 25520055 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 1855956 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2723 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5239453402 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.652679 # CPI: cycles per instruction -system.cpu1.ipc 0.376977 # IPC: instructions per cycle -system.cpu1.op_class_0::No_OpClass 67 0.00% 0.00% # Class of committed instruction -system.cpu1.op_class_0::IntAlu 16137166 63.23% 63.23% # Class of committed instruction -system.cpu1.op_class_0::IntMult 34169 0.13% 63.37% # Class of committed instruction -system.cpu1.op_class_0::IntDiv 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::FloatAdd 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::FloatCmp 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::FloatCvt 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::FloatMult 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::FloatDiv 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::FloatSqrt 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdAdd 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdAddAcc 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdAlu 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdCmp 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdCvt 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdMisc 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdMult 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdMultAcc 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdShift 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdSqrt 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 63.37% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMisc 4083 0.02% 63.38% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMult 0 0.00% 63.38% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 63.38% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 63.38% # Class of committed instruction -system.cpu1.op_class_0::MemRead 4989153 19.55% 82.93% # Class of committed instruction -system.cpu1.op_class_0::MemWrite 4355417 17.07% 100.00% # Class of committed instruction +system.cpu1.committedInsts 48452289 # Number of instructions committed +system.cpu1.committedOps 59283596 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 5163197 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2767 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5578862239 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.411602 # CPI: cycles per instruction +system.cpu1.ipc 0.414662 # IPC: instructions per cycle +system.cpu1.op_class_0::No_OpClass 66 0.00% 0.00% # Class of committed instruction +system.cpu1.op_class_0::IntAlu 40834570 68.88% 68.88% # Class of committed instruction +system.cpu1.op_class_0::IntMult 45625 0.08% 68.96% # Class of committed instruction +system.cpu1.op_class_0::IntDiv 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::FloatAdd 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::FloatCmp 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::FloatCvt 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::FloatMult 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::FloatDiv 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::FloatSqrt 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdAdd 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdAddAcc 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdAlu 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdCmp 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdCvt 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdMisc 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdMult 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdMultAcc 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdShift 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdSqrt 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMisc 3333 0.01% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMult 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 68.96% # Class of committed instruction +system.cpu1.op_class_0::MemRead 11200779 18.89% 87.86% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 7199223 12.14% 100.00% # Class of committed instruction system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.op_class_0::total 25520055 # Class of committed instruction +system.cpu1.op_class_0::total 59283596 # Class of committed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2723 # number of quiesce instructions executed -system.cpu1.tickCycles 37036327 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 18425400 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 231690 # number of replacements -system.cpu1.dcache.tags.tagsinuse 479.724430 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 8932333 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 232024 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 38.497453 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 109862994000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.724430 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.936962 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.936962 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 334 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 70 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.652344 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 18884551 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 18884551 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 4750067 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 4750067 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3901959 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3901959 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 65733 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 65733 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87399 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 87399 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79392 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 79392 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 8652026 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 8652026 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 8717759 # number of overall hits -system.cpu1.dcache.overall_hits::total 8717759 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 172325 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 172325 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 169730 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 169730 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34831 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 34831 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17668 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17668 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23402 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23402 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 342055 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 342055 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 376886 # number of overall misses -system.cpu1.dcache.overall_misses::total 376886 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2622225500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2622225500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4369952500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4369952500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 333352000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 333352000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 570866500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 570866500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 547000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 547000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6992178000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6992178000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6992178000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6992178000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 4922392 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 4922392 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4071689 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4071689 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 100564 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 100564 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105067 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 105067 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102794 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 102794 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 8994081 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 8994081 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 9094645 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 9094645 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035008 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035008 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.041685 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.041685 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.346357 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.346357 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.168159 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.168159 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.227659 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.227659 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038031 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.038031 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041440 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.041440 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15216.744523 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15216.744523 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25746.494432 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 25746.494432 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18867.557165 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18867.557165 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24393.919323 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24393.919323 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2767 # number of quiesce instructions executed +system.cpu1.tickCycles 94150450 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 22697166 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 195596 # number of replacements +system.cpu1.dcache.tags.tagsinuse 473.279573 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 18031187 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 195963 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 92.013222 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 91237126000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.279573 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.924374 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.924374 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 367 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 57 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.716797 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 36965565 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 36965565 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 10998874 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 10998874 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6796614 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6796614 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50142 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 50142 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80008 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 80008 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71567 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71567 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 17795488 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 17795488 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 17845630 # number of overall hits +system.cpu1.dcache.overall_hits::total 17845630 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 148727 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 148727 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 145387 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 145387 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30687 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30687 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16966 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 16966 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23611 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23611 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 294114 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 294114 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 324801 # number of overall misses +system.cpu1.dcache.overall_misses::total 324801 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2356620500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2356620500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3915884500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3915884500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 322199000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 322199000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 556849500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 556849500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 389000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 389000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6272505000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6272505000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6272505000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6272505000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 11147601 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 11147601 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6942001 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6942001 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80829 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 80829 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96974 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 96974 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95178 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 95178 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 18089602 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 18089602 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 18170431 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 18170431 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.013342 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.013342 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.020943 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.020943 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.379653 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.379653 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174954 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174954 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248072 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248072 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.016259 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.016259 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.017875 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.017875 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15845.276917 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15845.276917 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26934.213513 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 26934.213513 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18990.864081 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18990.864081 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23584.325103 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23584.325103 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20441.677508 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20441.677508 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18552.501287 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18552.501287 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21326.781452 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 21326.781452 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19311.840173 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 19311.840173 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 231690 # number of writebacks -system.cpu1.dcache.writebacks::total 231690 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 6182 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 6182 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 63208 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 63208 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12205 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12205 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 69390 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 69390 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 69390 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 69390 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166143 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 166143 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106522 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 106522 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 33373 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 33373 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5463 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5463 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23402 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23402 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 272665 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 272665 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 306038 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 306038 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5399 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5399 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 4698 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 4698 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10097 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10097 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2348457500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2348457500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2649909000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2649909000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 556338500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 556338500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 95279500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 95279500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 547474500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 547474500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 537000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 537000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4998366500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4998366500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5554705000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5554705000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 994956000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 994956000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 994956000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 994956000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033752 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033752 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026162 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026162 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.331858 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.331858 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051995 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051995 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.227659 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.227659 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030316 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.030316 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033650 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033650 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14135.157665 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14135.157665 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24876.635812 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24876.635812 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16670.317322 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16670.317322 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17440.874977 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17440.874977 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23394.346637 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23394.346637 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 195596 # number of writebacks +system.cpu1.dcache.writebacks::total 195596 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 5710 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 5710 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52879 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 52879 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12082 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12082 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 58589 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 58589 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 58589 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 58589 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 143017 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 143017 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92508 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 92508 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29859 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29859 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4884 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4884 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23611 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23611 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 235525 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 235525 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 265384 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 265384 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14595 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14595 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11928 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11928 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26523 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26523 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2115141000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2115141000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2362860000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2362860000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 507235000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 507235000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82984000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 82984000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 533247500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 533247500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 380000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 380000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4478001000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4478001000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4985236000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4985236000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2537758000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2537758000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2537758000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2537758000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.012829 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.012829 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013326 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013326 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.369409 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.369409 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050364 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050364 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248072 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248072 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013020 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.013020 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014605 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.014605 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14789.437619 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14789.437619 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25542.223375 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25542.223375 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16987.675408 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16987.675408 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16990.990991 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16990.990991 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22584.706281 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22584.706281 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # 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Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 21383287 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 21383287 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 9132995 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 9132995 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 9132995 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 9132995 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 9132995 # number of overall hits -system.cpu1.icache.overall_hits::total 9132995 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 1039099 # 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miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9024.467832 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9024.467832 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9024.467832 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9024.467832 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9024.467832 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9024.467832 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 80354432 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 80354432 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 38754409 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 38754409 # 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number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8680888000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8680888000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8680888000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 39702947 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 39702947 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 39702947 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 39702947 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 39702947 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 39702947 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023891 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.023891 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023891 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.023891 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023891 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.023891 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9151.861075 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9151.861075 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9151.861075 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9151.861075 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9151.861075 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9151.861075 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 1038587 # number of writebacks -system.cpu1.icache.writebacks::total 1038587 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 1039099 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 1039099 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 1039099 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 1039099 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 1039099 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 1039099 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 948026 # number of writebacks +system.cpu1.icache.writebacks::total 948026 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 948538 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 948538 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 948538 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 948538 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 948538 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 948538 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8857766000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8857766000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8857766000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8857766000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8857766000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8857766000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10704000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10704000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10704000 # 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average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8524.467832 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8524.467832 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8524.467832 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95571.428571 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95571.428571 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95571.428571 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95571.428571 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 276399 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 276459 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 53 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8206619000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8206619000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8206619000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8206619000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8206619000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8206619000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10719000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10719000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10719000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10719000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023891 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023891 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023891 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023891 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023891 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023891 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8651.861075 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8651.861075 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8651.861075 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8651.861075 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8651.861075 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8651.861075 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95705.357143 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95705.357143 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95705.357143 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95705.357143 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 199515 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 199547 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 28 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 69493 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 70219 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15563.656432 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 2283330 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 85023 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 26.855439 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 59237 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 51581 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14798.019682 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1058904 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 65844 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 16.082012 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14385.822816 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 54.124799 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.170471 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1123.538345 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.878041 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003304 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000010 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.068575 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.949930 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1056 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 14409.418299 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 42.207150 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.101777 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 346.292455 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.879481 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002576 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.021136 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.903199 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 289 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_blocks::1023 42 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13706 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 291 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 761 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13932 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 101 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 185 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 19 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5206 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 8191 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.064453 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1267 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7924 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4741 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017639 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002563 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.836548 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 42757972 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 42757972 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 32984 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 3253 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 36237 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 134317 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 134317 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 1113970 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 1113970 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 37754 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 37754 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 1012452 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 1012452 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 130088 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 130088 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 32984 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 3253 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 1012452 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 167842 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 1216531 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 32984 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 3253 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 1012452 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 167842 # number of overall hits -system.cpu1.l2cache.overall_hits::total 1216531 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 703 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 237 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 940 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 31976 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 31976 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23401 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23401 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 36794 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 36794 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 26647 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 26647 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 74889 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 74889 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 703 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 237 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 26647 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 111683 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 139270 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 703 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 237 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 26647 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 111683 # number of overall misses -system.cpu1.l2cache.overall_misses::total 139270 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 17920000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4860500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 22780500 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 79820500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 79820500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 32048000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 32048000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 521000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 521000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1478483000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1478483000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 1147386500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 1147386500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1827426992 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1827426992 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 17920000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4860500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 1147386500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 3305909992 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 4476076992 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 17920000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4860500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 1147386500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3305909992 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 4476076992 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 33687 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 3490 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 37177 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 134317 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 134317 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 1113970 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 1113970 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31976 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 31976 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23401 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23401 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 74548 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 74548 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 1039099 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 1039099 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 204977 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 204977 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 33687 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 3490 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 1039099 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 279525 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 1355801 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 33687 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 3490 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 1039099 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 279525 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 1355801 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020869 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.067908 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.025284 # miss rate for ReadReq accesses +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.850342 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 39538104 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 39538104 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 30011 # 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mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.084289 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.037418 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.455149 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.130971 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19490.753912 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14508.438819 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18234.574468 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33841.925300 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33841.925300 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17731.251564 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17731.251564 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15823.768172 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15823.768172 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 461000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 461000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33516.002523 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33516.002523 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 37071.173709 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 37071.173709 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 18372.364794 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 18372.364794 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19490.753912 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14508.438819 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 37071.173709 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23337.007561 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25937.202726 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19490.753912 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14508.438819 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 37071.173709 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23337.007561 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33841.925300 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27663.625832 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87571.428571 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176280.237081 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174477.408819 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87571.428571 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 94259.383975 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 94186.012342 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 2654318 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1335711 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 21986 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 212975 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 211032 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1943 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 47306 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1331970 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 4698 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 4698 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 177822 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 1135956 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 137781 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 47279 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 75014 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42924 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 89713 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 14 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 82844 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 80563 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 1039099 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 293637 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 3117009 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1002647 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8284 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70688 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 4198628 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 132979072 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 35729427 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13960 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 134748 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 168857207 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 473910 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 5785960 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 1814338 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.136111 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.346015 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.140483 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17462.988827 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14280.612245 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16536.633663 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37807.650847 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 37807.650847 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15389.853763 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15389.853763 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15022.489518 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15022.489518 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33746.242913 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33746.242913 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29370.675082 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29370.675082 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17415.614768 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17415.614768 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17462.988827 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14280.612245 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29370.675082 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22570.243538 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24182.610894 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17462.988827 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14280.612245 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29370.675082 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22570.243538 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37807.650847 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26237.654282 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87705.357143 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165877.423775 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165282.110560 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87705.357143 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 91278.550692 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 91263.525436 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 2396557 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1207646 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 20286 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 118595 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 110586 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8009 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 53656 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1217922 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11928 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11928 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 153983 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 1025852 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 34704 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 31184 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 74094 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41981 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86038 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 20 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 69927 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 67092 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 948538 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 295426 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 64 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2845326 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 911410 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8268 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 64898 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3829902 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 121387264 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30723028 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13952 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 122916 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 152247160 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 369470 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 5053360 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1597738 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.098519 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.314386 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1569330 86.50% 86.50% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 243065 13.40% 99.89% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1943 0.11% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1448339 90.65% 90.65% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 141390 8.85% 99.50% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 8009 0.50% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1814338 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 2620766990 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1597738 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2375408982 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 87124018 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79990687 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1558968196 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 456771923 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1423068313 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 409788212 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4794998 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4783493 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 37016968 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 34178481 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 31014 # Transaction distribution -system.iobus.trans_dist::ReadResp 31014 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 31003 # Transaction distribution +system.iobus.trans_dist::ReadResp 31003 # Transaction distribution system.iobus.trans_dist::WriteReq 59422 # Transaction distribution system.iobus.trans_dist::WriteResp 59422 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) @@ -2268,7 +2281,7 @@ system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -2281,17 +2294,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72960 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72960 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180872 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180850 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2304,94 +2317,94 @@ system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321280 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321280 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484074 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48375000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2483972 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 48331500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 113500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 329000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 333000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 27500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 13000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 13500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 92000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 88500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 619500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 620000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 19500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 45500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 47000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6358000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6355500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38893000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 39060500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187720844 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187669353 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84714000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36784000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 36462 # number of replacements -system.iocache.tags.tagsinuse 14.359878 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 36449 # number of replacements +system.iocache.tags.tagsinuse 14.473969 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36478 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 271405535000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.359878 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.897492 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.897492 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 271637878000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.473969 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.904623 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.904623 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328320 # Number of tag accesses -system.iocache.tags.data_accesses 328320 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ide 256 # number of ReadReq misses -system.iocache.ReadReq_misses::total 256 # number of ReadReq misses +system.iocache.tags.tag_accesses 328203 # Number of tag accesses +system.iocache.tags.data_accesses 328203 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses +system.iocache.ReadReq_misses::total 243 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36480 # number of demand (read+write) misses -system.iocache.demand_misses::total 36480 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36480 # number of overall misses -system.iocache.overall_misses::total 36480 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 33042377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 33042377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4307289467 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4307289467 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4340331844 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4340331844 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4340331844 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4340331844 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 256 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 256 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 36467 # number of demand (read+write) misses +system.iocache.demand_misses::total 36467 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36467 # number of overall misses +system.iocache.overall_misses::total 36467 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 31680877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31680877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4302277476 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4302277476 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4333958353 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4333958353 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4333958353 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4333958353 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36480 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36480 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36480 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36480 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36467 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36467 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36467 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36467 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2400,38 +2413,38 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 129071.785156 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 129071.785156 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118907.063466 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118907.063466 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118978.394846 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118978.394846 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118978.394846 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118978.394846 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 130373.979424 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 130373.979424 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118768.702407 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118768.702407 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 118846.034853 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118846.034853 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 118846.034853 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118846.034853 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.666667 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 4.166667 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 256 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 256 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 36480 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 36480 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 36480 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 36480 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 20242377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 20242377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2493740476 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2493740476 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2513982853 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2513982853 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2513982853 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2513982853 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 36467 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 36467 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 36467 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 36467 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19530877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19530877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2488777487 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2488777487 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2508308364 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2508308364 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2508308364 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2508308364 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2440,590 +2453,592 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79071.785156 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 79071.785156 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68842.217204 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68842.217204 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68914.003646 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68914.003646 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68914.003646 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68914.003646 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 135113 # number of replacements -system.l2c.tags.tagsinuse 63251.941629 # Cycle average of tags in use -system.l2c.tags.total_refs 475115 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 198978 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.387777 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 14216.048080 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 74.910809 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.033810 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7426.792759 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2102.106662 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29896.915616 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 20.238831 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3811.016358 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1509.520853 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4194.357849 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.216920 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001143 # Average percentage of cache occupancy +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80373.979424 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 80373.979424 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68705.208895 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68705.208895 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68782.964434 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68782.964434 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68782.964434 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68782.964434 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 143192 # number of replacements +system.l2c.tags.tagsinuse 65154.235518 # Cycle average of tags in use +system.l2c.tags.total_refs 608270 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 208652 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.915237 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 94157771000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 6329.103935 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 78.467327 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.034862 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8953.646572 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6857.938638 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35058.708510 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 16.060603 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2144.069552 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3463.562714 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2252.642806 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.096574 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001197 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.113324 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.032076 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.456191 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000309 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.058151 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.023033 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.064001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.965148 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 27324 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 89 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 36452 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 105 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4822 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 22394 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 88 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 417 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3262 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 32736 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.416931 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.001358 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.556213 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6444953 # Number of tag accesses -system.l2c.tags.data_accesses 6444953 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 270033 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 270033 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 32996 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 3857 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 36853 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2004 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 1040 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3044 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3941 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1936 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5877 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 357 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 67 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 40247 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 47388 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 44871 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 179 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 29 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 20863 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 12359 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 8223 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 174583 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 357 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 67 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 40247 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 51329 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 44871 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 179 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 29 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 20863 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 14295 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 8223 # number of demand (read+write) hits -system.l2c.demand_hits::total 180460 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 357 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 67 # number of overall hits -system.l2c.overall_hits::cpu0.inst 40247 # number of overall hits -system.l2c.overall_hits::cpu0.data 51329 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 44871 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 179 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 29 # number of overall hits -system.l2c.overall_hits::cpu1.inst 20863 # number of overall hits -system.l2c.overall_hits::cpu1.data 14295 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 8223 # number of overall hits -system.l2c.overall_hits::total 180460 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 9513 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4300 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13813 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 964 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1203 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2167 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11039 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8960 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19999 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 128 # number of ReadSharedReq misses +system.l2c.tags.occ_percent::cpu0.inst 0.136622 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.104644 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.534953 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000245 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.032716 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.052850 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.034373 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994175 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 31682 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 69 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 33709 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 141 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4562 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 26979 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 67 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1943 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 31665 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.483429 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.001053 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.514359 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6826219 # Number of tag accesses +system.l2c.tags.data_accesses 6826219 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 268100 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 268100 # 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average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24555.555556 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89296.286449 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73405.045024 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 82394.810730 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80892.857143 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 70918.459566 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78947.545160 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91570.072857 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 92050 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73433.246875 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79279.651021 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109721.537416 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 88793.314688 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80875 # average overall mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71387.918298 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79887.660955 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92756.068382 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 83477.272727 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73091.748585 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80309.869434 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116100.999562 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 89676.133235 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80892.857143 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70918.459566 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84623.329098 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91570.072857 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 92050 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73433.246875 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74043.911922 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109721.537416 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 88063.668908 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80875 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71387.918298 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84907.878559 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92756.068382 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 83477.272727 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73091.748585 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74516.612069 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116100.999562 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 88935.335554 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80892.857143 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70918.459566 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84623.329098 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91570.072857 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 92050 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73433.246875 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74043.911922 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109721.537416 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 88063.668908 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71387.918298 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84907.878559 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92756.068382 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 83477.272727 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73091.748585 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74516.612069 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116100.999562 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 88935.335554 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63637.035963 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179924.347835 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66571.428571 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158365.363232 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 166188.791033 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197515.134419 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66705.357143 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 147906.284265 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 166371.405958 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63637.035963 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 95219.849641 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66571.428571 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 84658.163265 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 92079.185841 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 535318 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 308111 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 583 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102007.866934 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66705.357143 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81381.919306 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 92183.762527 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 516977 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 290556 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 569 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 38585 # Transaction distribution -system.membus.trans_dist::ReadResp 215902 # Transaction distribution -system.membus.trans_dist::WriteReq 31055 # Transaction distribution -system.membus.trans_dist::WriteResp 31055 # Transaction distribution -system.membus.trans_dist::WritebackDirty 141257 # Transaction distribution -system.membus.trans_dist::CleanEvict 18818 # Transaction distribution -system.membus.trans_dist::UpgradeReq 79128 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 41795 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 38536 # Transaction distribution +system.membus.trans_dist::ReadResp 214874 # Transaction distribution +system.membus.trans_dist::WriteReq 31013 # Transaction distribution +system.membus.trans_dist::WriteResp 31013 # Transaction distribution +system.membus.trans_dist::WritebackDirty 140764 # Transaction distribution +system.membus.trans_dist::CleanEvict 19586 # Transaction distribution +system.membus.trans_dist::UpgradeReq 64644 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 38971 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 40708 # Transaction distribution -system.membus.trans_dist::ReadExResp 19870 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 177317 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 40377 # Transaction distribution +system.membus.trans_dist::ReadExResp 19925 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 176338 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14304 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 675920 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 798178 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72957 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72957 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 871135 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14120 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 656690 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 778768 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72931 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72931 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 851699 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19551584 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19744330 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19461788 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19654168 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22062474 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 126237 # Total snoops (count) -system.membus.snoopTraffic 37184 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 444815 # Request fanout histogram -system.membus.snoop_fanout::mean 0.011558 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.106883 # Request fanout histogram +system.membus.pkt_size::total 21972312 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123613 # Total snoops (count) +system.membus.snoopTraffic 36288 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 426105 # Request fanout histogram +system.membus.snoop_fanout::mean 0.011500 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.106618 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 439674 98.84% 98.84% # Request fanout histogram -system.membus.snoop_fanout::1 5141 1.16% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 421205 98.85% 98.85% # Request fanout histogram +system.membus.snoop_fanout::1 4900 1.15% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 444815 # Request fanout histogram -system.membus.reqLayer0.occupancy 94951000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 426105 # Request fanout histogram +system.membus.reqLayer0.occupancy 95080500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12539499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12459499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1031011447 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1008366249 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1149570495 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1144784655 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1412877 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1337127 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3055,77 +3070,77 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 1073312 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 580718 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 172518 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 20634 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 19568 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 1066 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2647778082500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 38588 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 515387 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31055 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 375084 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 144219 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 115852 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 44839 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 160691 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51833 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51833 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 476801 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4556 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1253209 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 392983 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1646192 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34630659 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7267527 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 41898186 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 395888 # Total snoops (count) -system.toL2Bus.snoopTraffic 16395788 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 898686 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.386698 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.489423 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1122676 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 592030 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 210689 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 28909 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 27742 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1167 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848172284000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 38539 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 569123 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31013 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31013 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 372658 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 153621 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 113203 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 44029 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 157232 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 29 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51954 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51954 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 530586 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4329 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1344687 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 405982 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1750669 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 38363344 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7028808 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 45392152 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 398871 # Total snoops (count) +system.toL2Bus.snoopTraffic 16195724 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 956902 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.408687 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.494066 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 552232 61.45% 61.45% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 345388 38.43% 99.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1066 0.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 566996 59.25% 59.25% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 388739 40.62% 99.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1167 0.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 898686 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 930017339 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 956902 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 952868265 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 361623 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 342123 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 658710189 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 724877328 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 272587474 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 285789223 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 60905542e..4972770ec 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.858997 # Number of seconds simulated -sim_ticks 2858997339500 # Number of ticks simulated -final_tick 2858997339500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.853344 # Number of seconds simulated +sim_ticks 2853343899500 # Number of ticks simulated +final_tick 2853343899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120078 # Simulator instruction rate (inst/s) -host_op_rate 145187 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3059253370 # Simulator tick rate (ticks/s) -host_mem_usage 579060 # Number of bytes of host memory used -host_seconds 934.54 # Real time elapsed on the host -sim_insts 112217626 # Number of instructions simulated -sim_ops 135683579 # Number of ops (including micro ops) simulated +host_inst_rate 139312 # Simulator instruction rate (inst/s) +host_op_rate 168444 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3544495637 # Simulator tick rate (ticks/s) +host_mem_usage 589148 # Number of bytes of host memory used +host_seconds 805.01 # Real time elapsed on the host +sim_insts 112146750 # Number of instructions simulated +sim_ops 135598813 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 8000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1706880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9150764 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 7680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1675712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9177004 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10866732 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1706880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1706880 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7954240 # Number of bytes written to this memory +system.physmem.bytes_read::total 10861420 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1675712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1675712 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7976832 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7971764 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 125 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26670 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143502 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7994356 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 120 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26183 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143912 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170314 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124285 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170231 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124638 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 128666 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 597020 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3200690 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 129019 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 587280 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3216228 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3800889 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 597020 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 597020 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2782178 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6129 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2788308 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2782178 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2798 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 597020 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3206819 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3806558 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 587280 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 587280 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2795608 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6142 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2801750 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2795608 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 587280 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3222369 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6589197 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170314 # Number of read requests accepted -system.physmem.writeReqs 128666 # Number of write requests accepted -system.physmem.readBursts 170314 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 128666 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10892160 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7936 # Total number of bytes read from write queue -system.physmem.bytesWritten 7984576 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10866732 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7971764 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 124 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::total 6608308 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170231 # Number of read requests accepted +system.physmem.writeReqs 129019 # Number of write requests accepted +system.physmem.readBursts 170231 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 129019 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10886144 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8640 # Total number of bytes read from write queue +system.physmem.bytesWritten 8006976 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10861420 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7994356 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 135 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10846 # Per bank write bursts -system.physmem.perBankRdBursts::1 10861 # Per bank write bursts -system.physmem.perBankRdBursts::2 10970 # Per bank write bursts -system.physmem.perBankRdBursts::3 10944 # Per bank write bursts -system.physmem.perBankRdBursts::4 13948 # Per bank write bursts -system.physmem.perBankRdBursts::5 10354 # Per bank write bursts -system.physmem.perBankRdBursts::6 10606 # Per bank write bursts -system.physmem.perBankRdBursts::7 10917 # Per bank write bursts -system.physmem.perBankRdBursts::8 10091 # Per bank write bursts -system.physmem.perBankRdBursts::9 10226 # Per bank write bursts -system.physmem.perBankRdBursts::10 9938 # Per bank write bursts -system.physmem.perBankRdBursts::11 9330 # Per bank write bursts -system.physmem.perBankRdBursts::12 10171 # Per bank write bursts -system.physmem.perBankRdBursts::13 10932 # Per bank write bursts -system.physmem.perBankRdBursts::14 10237 # Per bank write bursts -system.physmem.perBankRdBursts::15 9819 # Per bank write bursts -system.physmem.perBankWrBursts::0 8179 # Per bank write bursts -system.physmem.perBankWrBursts::1 8215 # Per bank write bursts -system.physmem.perBankWrBursts::2 8623 # Per bank write bursts -system.physmem.perBankWrBursts::3 8456 # Per bank write bursts -system.physmem.perBankWrBursts::4 7543 # Per bank write bursts -system.physmem.perBankWrBursts::5 7549 # Per bank write bursts -system.physmem.perBankWrBursts::6 7648 # Per bank write bursts -system.physmem.perBankWrBursts::7 8016 # Per bank write bursts -system.physmem.perBankWrBursts::8 7706 # Per bank write bursts -system.physmem.perBankWrBursts::9 7733 # Per bank write bursts -system.physmem.perBankWrBursts::10 7506 # Per bank write bursts -system.physmem.perBankWrBursts::11 7211 # Per bank write bursts -system.physmem.perBankWrBursts::12 7604 # Per bank write bursts -system.physmem.perBankWrBursts::13 8124 # Per bank write bursts -system.physmem.perBankWrBursts::14 7522 # Per bank write bursts -system.physmem.perBankWrBursts::15 7124 # Per bank write bursts +system.physmem.perBankRdBursts::0 10508 # Per bank write bursts +system.physmem.perBankRdBursts::1 10518 # Per bank write bursts +system.physmem.perBankRdBursts::2 10699 # Per bank write bursts +system.physmem.perBankRdBursts::3 10590 # Per bank write bursts +system.physmem.perBankRdBursts::4 13367 # Per bank write bursts +system.physmem.perBankRdBursts::5 10649 # Per bank write bursts +system.physmem.perBankRdBursts::6 10947 # Per bank write bursts +system.physmem.perBankRdBursts::7 11320 # Per bank write bursts +system.physmem.perBankRdBursts::8 10289 # Per bank write bursts +system.physmem.perBankRdBursts::9 10353 # Per bank write bursts +system.physmem.perBankRdBursts::10 10214 # Per bank write bursts +system.physmem.perBankRdBursts::11 9210 # Per bank write bursts +system.physmem.perBankRdBursts::12 10497 # Per bank write bursts +system.physmem.perBankRdBursts::13 11112 # Per bank write bursts +system.physmem.perBankRdBursts::14 10041 # Per bank write bursts +system.physmem.perBankRdBursts::15 9782 # Per bank write bursts +system.physmem.perBankWrBursts::0 7781 # Per bank write bursts +system.physmem.perBankWrBursts::1 7920 # Per bank write bursts +system.physmem.perBankWrBursts::2 8383 # Per bank write bursts +system.physmem.perBankWrBursts::3 8149 # Per bank write bursts +system.physmem.perBankWrBursts::4 7457 # Per bank write bursts +system.physmem.perBankWrBursts::5 7755 # Per bank write bursts +system.physmem.perBankWrBursts::6 7974 # Per bank write bursts +system.physmem.perBankWrBursts::7 8419 # Per bank write bursts +system.physmem.perBankWrBursts::8 7882 # Per bank write bursts +system.physmem.perBankWrBursts::9 7909 # Per bank write bursts +system.physmem.perBankWrBursts::10 7627 # Per bank write bursts +system.physmem.perBankWrBursts::11 7117 # Per bank write bursts +system.physmem.perBankWrBursts::12 7926 # Per bank write bursts +system.physmem.perBankWrBursts::13 8274 # Per bank write bursts +system.physmem.perBankWrBursts::14 7391 # Per bank write bursts +system.physmem.perBankWrBursts::15 7145 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 12 # Number of times write queue was full causing retry -system.physmem.totGap 2858996896000 # Total gap between requests +system.physmem.numWrRetry 4 # Number of times write queue was full causing retry +system.physmem.totGap 2853343449000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 543 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169757 # Read request sizes (log2) +system.physmem.readPktSize::6 169674 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 124285 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 162889 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7005 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 284 # What read queue length does an incoming req see +system.physmem.writePktSize::6 124638 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 162184 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 281 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -160,160 +160,164 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7032 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61663 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 306.126397 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 182.384465 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.388642 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22560 36.59% 36.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14992 24.31% 60.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6700 10.87% 71.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3651 5.92% 77.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2898 4.70% 82.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1667 2.70% 85.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1045 1.69% 86.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1093 1.77% 88.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7057 11.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61663 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6083 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.977314 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 575.322656 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6082 99.98% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6083 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6083 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.509453 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.487861 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.653648 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5420 89.10% 89.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 90 1.48% 90.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 39 0.64% 91.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 27 0.44% 91.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 35 0.58% 92.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 16 0.26% 92.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 41 0.67% 93.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.12% 93.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 151 2.48% 95.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 6 0.10% 95.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.13% 96.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 13 0.21% 96.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 69 1.13% 97.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.07% 97.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.05% 97.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 36 0.59% 98.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 90 1.48% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.03% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 10 0.16% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 3 0.05% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6083 # Writes before turning the bus around for reads -system.physmem.totQLat 1877618250 # Total ticks spent queuing -system.physmem.totMemAccLat 5068680750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 850950000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11032.48 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7605 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 60538 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 312.085896 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 184.679507 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.366687 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22012 36.36% 36.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14640 24.18% 60.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6552 10.82% 71.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3435 5.67% 77.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2639 4.36% 81.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1745 2.88% 84.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1057 1.75% 86.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1062 1.75% 87.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7396 12.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60538 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6241 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.253805 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 580.495916 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6239 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6241 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6241 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.046307 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.379346 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.281323 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5473 87.69% 87.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 55 0.88% 88.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 66 1.06% 89.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 37 0.59% 90.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 284 4.55% 94.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 48 0.77% 95.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 17 0.27% 95.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 11 0.18% 95.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 9 0.14% 96.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.10% 96.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.06% 96.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 13 0.21% 96.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 157 2.52% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.06% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.05% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 5 0.08% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 5 0.08% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.06% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 8 0.13% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 15 0.24% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.05% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6241 # Writes before turning the bus around for reads +system.physmem.totQLat 1691091750 # Total ticks spent queuing +system.physmem.totMemAccLat 4880391750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 850480000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9941.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29782.48 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.79 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28691.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.82 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.81 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.80 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.79 # Average write queue length when enqueuing -system.physmem.readRowHits 139443 # Number of row buffer hits during reads -system.physmem.writeRowHits 93842 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.93 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.21 # Row buffer hit rate for writes -system.physmem.avgGap 9562502.16 # Average gap between requests -system.physmem.pageHitRate 79.09 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 244104840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 133192125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 697678800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 416203920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186735603600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 86851227465 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1639211384250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1914289395000 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.567370 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2726812979000 # Time in different power states -system.physmem_0.memoryStateTime::REF 95468100000 # Time in different power states +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.93 # Average write queue length when enqueuing +system.physmem.readRowHits 140142 # Number of row buffer hits during reads +system.physmem.writeRowHits 94524 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.39 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.54 # Row buffer hit rate for writes +system.physmem.avgGap 9534982.29 # Average gap between requests +system.physmem.pageHitRate 79.49 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 235894680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 128712375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 691064400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 413670240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186366389040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83561921055 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1638705050250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1910102702040 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.426569 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2725994839000 # Time in different power states +system.physmem_0.memoryStateTime::REF 95279340000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 36713387250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32067469750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 222067440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 121167750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 629795400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 392234400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186735603600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 85246386480 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1640619139500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1913966394570 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.454393 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2729170897750 # Time in different power states -system.physmem_1.memoryStateTime::REF 95468100000 # Time in different power states +system.physmem_1.actEnergy 221772600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 121006875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 635676600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 397036080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186366389040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82367679285 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1639752630750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1909862191230 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.342278 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2727746913750 # Time in different power states +system.physmem_1.memoryStateTime::REF 95279340000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 34358196250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30317548250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory @@ -326,30 +330,30 @@ system.realview.nvmem.bw_inst_read::cpu.inst 179 system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 31086887 # Number of BP lookups -system.cpu.branchPred.condPredicted 16880230 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2489626 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18671153 # Number of BTB lookups -system.cpu.branchPred.BTBHits 10424859 # Number of BTB hits +system.cpu.branchPred.lookups 31062999 # Number of BP lookups +system.cpu.branchPred.condPredicted 16869066 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2486744 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18728785 # Number of BTB lookups +system.cpu.branchPred.BTBHits 10415318 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 55.834040 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7822517 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1524102 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3081262 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2891722 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 189540 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 109414 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 55.611285 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7833584 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1520957 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3075291 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2886933 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 188358 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 109527 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -379,57 +383,59 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 67741 # Table walker walks requested -system.cpu.dtb.walker.walksShort 67741 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 45017 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22724 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 67741 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 67741 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 67741 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7842 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 12675.784239 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 10493.995103 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 8407.754568 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 7835 99.91% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-163839 6 0.08% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7842 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 517795000 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 517795000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 517795000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6453 82.29% 82.29% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1389 17.71% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7842 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 67741 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 68003 # Table walker walks requested +system.cpu.dtb.walker.walksShort 68003 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 44606 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23397 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 68003 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 68003 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 68003 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7897 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 10035.266557 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 8419.099443 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 6813.200210 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 7021 88.91% 88.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 869 11.00% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 5 0.06% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7897 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 271390000 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 271390000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 271390000 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6503 82.35% 82.35% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1394 17.65% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7897 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 68003 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 67741 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7842 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 68003 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7897 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7842 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 75583 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7897 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 75900 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24787454 # DTB read hits -system.cpu.dtb.read_misses 60877 # DTB read misses -system.cpu.dtb.write_hits 19460962 # DTB write hits -system.cpu.dtb.write_misses 6864 # DTB write misses +system.cpu.dtb.read_hits 24771188 # DTB read hits +system.cpu.dtb.read_misses 61134 # DTB read misses +system.cpu.dtb.write_hits 19449290 # DTB write hits +system.cpu.dtb.write_misses 6869 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4270 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1452 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1793 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4279 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1418 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1775 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 741 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24848331 # DTB read accesses -system.cpu.dtb.write_accesses 19467826 # DTB write accesses +system.cpu.dtb.perms_faults 770 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24832322 # DTB read accesses +system.cpu.dtb.write_accesses 19456159 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44248416 # DTB hits -system.cpu.dtb.misses 67741 # DTB misses -system.cpu.dtb.accesses 44316157 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 44220478 # DTB hits +system.cpu.dtb.misses 68003 # DTB misses +system.cpu.dtb.accesses 44288481 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -459,37 +465,39 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 5895 # Table walker walks requested -system.cpu.itb.walker.walksShort 5895 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 321 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 5574 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 5895 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 5895 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 5895 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3205 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 12907.644306 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 10876.938214 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7322.763550 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-16383 2473 77.16% 77.16% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-32767 731 22.81% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3205 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 517140500 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 517140500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 517140500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2896 90.36% 90.36% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 309 9.64% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3205 # Table walker page sizes translated +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 5856 # Table walker walks requested +system.cpu.itb.walker.walksShort 5856 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 325 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5531 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5856 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5856 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5856 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3193 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 10411.838396 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 8598.635311 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 6896.589649 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1843 57.72% 57.72% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 807 25.27% 82.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 535 16.76% 99.75% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::24576-32767 7 0.22% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3193 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 270980500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 270980500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 270980500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2883 90.29% 90.29% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 310 9.71% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3193 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5895 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 5895 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5856 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5856 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3205 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3205 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 9100 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 57517109 # ITB inst hits -system.cpu.itb.inst_misses 5895 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3193 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3193 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 9049 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 57483193 # ITB inst hits +system.cpu.itb.inst_misses 5856 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -498,45 +506,45 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2926 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2912 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8405 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8279 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57523004 # ITB inst accesses -system.cpu.itb.hits 57517109 # DTB hits -system.cpu.itb.misses 5895 # DTB misses -system.cpu.itb.accesses 57523004 # DTB accesses -system.cpu.numPwrStateTransitions 6068 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 3034 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 887205873.057680 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17434832353.062756 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 2969 97.86% 97.86% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 59 1.94% 99.80% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 57489049 # ITB inst accesses +system.cpu.itb.hits 57483193 # DTB hits +system.cpu.itb.misses 5856 # DTB misses +system.cpu.itb.accesses 57489049 # DTB accesses +system.cpu.numPwrStateTransitions 6066 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 888351102.639301 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17445509399.919735 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 2969 97.89% 97.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 58 1.91% 99.80% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 499967463084 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 3034 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 167214720643 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2691782618857 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 334432391 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 499967553028 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 158975005195 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2694368894305 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 317952965 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112217626 # Number of instructions committed -system.cpu.committedOps 135683579 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7838903 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 3034 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5383627132 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.980213 # CPI: cycles per instruction -system.cpu.ipc 0.335547 # IPC: instructions per cycle +system.cpu.committedInsts 112146750 # Number of instructions committed +system.cpu.committedOps 135598813 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7821624 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 3033 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 5388799101 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.835151 # CPI: cycles per instruction +system.cpu.ipc 0.352715 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 2337 0.00% 0.00% # Class of committed instruction -system.cpu.op_class_0::IntAlu 90974393 67.05% 67.05% # Class of committed instruction -system.cpu.op_class_0::IntMult 113069 0.08% 67.13% # Class of committed instruction +system.cpu.op_class_0::IntAlu 90918529 67.05% 67.05% # Class of committed instruction +system.cpu.op_class_0::IntMult 113133 0.08% 67.13% # Class of committed instruction system.cpu.op_class_0::IntDiv 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::FloatAdd 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::FloatCmp 0 0.00% 67.13% # Class of committed instruction @@ -560,666 +568,663 @@ system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.13% # Cl system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.13% # Class of committed instruction system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.13% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 8525 0.01% 67.14% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 8487 0.01% 67.14% # Class of committed instruction system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.14% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.14% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.14% # Class of committed instruction -system.cpu.op_class_0::MemRead 24296976 17.91% 85.05% # Class of committed instruction -system.cpu.op_class_0::MemWrite 20288279 14.95% 100.00% # Class of committed instruction +system.cpu.op_class_0::MemRead 24279497 17.91% 85.05% # Class of committed instruction +system.cpu.op_class_0::MemWrite 20276830 14.95% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 135683579 # Class of committed instruction +system.cpu.op_class_0::total 135598813 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3034 # number of quiesce instructions executed -system.cpu.tickCycles 218593350 # Number of cycles that the object actually ticked -system.cpu.idleCycles 115839041 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 844257 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.899744 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42705909 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 844769 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.553357 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 594757500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.899744 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed +system.cpu.tickCycles 217828985 # Number of cycles that the object actually ticked +system.cpu.idleCycles 100123980 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 845168 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.946266 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42678256 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 845680 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.466200 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 322165500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.946266 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999895 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999895 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 176476854 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 176476854 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 23143905 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23143905 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18298058 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18298058 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 356964 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 356964 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443845 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443845 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460247 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460247 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41441963 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41441963 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41798927 # number of overall hits -system.cpu.dcache.overall_hits::total 41798927 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 464900 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 464900 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 548479 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 548479 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 169396 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 169396 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22217 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22217 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 176368054 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 176368054 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 23126363 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23126363 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18288488 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18288488 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 357151 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 357151 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443374 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443374 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 459996 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 459996 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41414851 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41414851 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41772002 # number of overall hits +system.cpu.dcache.overall_hits::total 41772002 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 466466 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 466466 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 547177 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 547177 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 169147 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 169147 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22423 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22423 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 1013379 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1013379 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1182775 # number of overall misses -system.cpu.dcache.overall_misses::total 1182775 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7474682000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7474682000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 35725670480 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 35725670480 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 298069500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 298069500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 167000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 43200352480 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 43200352480 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 43200352480 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 43200352480 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23608805 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23608805 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 18846537 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18846537 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 526360 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 526360 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466062 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 466062 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460249 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460249 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42455342 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42455342 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42981702 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42981702 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.019692 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.019692 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029102 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029102 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.321825 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.321825 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047670 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.047670 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 1013643 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1013643 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1182790 # number of overall misses +system.cpu.dcache.overall_misses::total 1182790 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6859105500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6859105500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23368526480 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23368526480 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 290513500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 290513500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 169000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 169000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30227631980 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30227631980 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30227631980 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30227631980 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23592829 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23592829 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18835665 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18835665 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 526298 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 526298 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465797 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 465797 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 459998 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 459998 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42428494 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42428494 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42954792 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42954792 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.019772 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.019772 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029050 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029050 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.321390 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.321390 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048139 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048139 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023869 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023869 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.027518 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.027518 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16078.042590 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16078.042590 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65135.894866 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65135.894866 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13416.280326 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13416.280326 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83500 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83500 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 42630.005635 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 42630.005635 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36524.573549 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36524.573549 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 235 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.023891 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023891 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.027536 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.027536 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14704.406109 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14704.406109 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42707.435583 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42707.435583 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12956.049592 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12956.049592 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 84500 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 84500 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29820.786983 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29820.786983 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25556.211990 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25556.211990 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 210 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 22 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.681818 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 701092 # number of writebacks -system.cpu.dcache.writebacks::total 701092 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45747 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 45747 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 249493 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 249493 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 13970 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 13970 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 295240 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 295240 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 295240 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 295240 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 419153 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 419153 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298986 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 298986 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121200 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 121200 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8247 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8247 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 700399 # number of writebacks +system.cpu.dcache.writebacks::total 700399 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45619 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 45619 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 248851 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 248851 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14095 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14095 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 294470 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 294470 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 294470 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 294470 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 420847 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 420847 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298326 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 298326 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 121014 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 121014 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8328 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8328 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 718139 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 718139 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 839339 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 839339 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31130 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 31130 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6559792500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6559792500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19260233000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19260233000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1701865000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1701865000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 115452000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 115452000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 165000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 165000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25820025500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25820025500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27521890500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27521890500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6298878000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6298878000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6298878000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6298878000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017754 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017754 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015864 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015864 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.230261 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.230261 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017695 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017695 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 719173 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 719173 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 840187 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 840187 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31128 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 31128 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27583 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 27583 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6004353500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6004353500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12472700000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12472700000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1605906500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1605906500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 111255000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 111255000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 167000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 167000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18477053500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18477053500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20082960000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20082960000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6301797000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6301797000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6301797000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6301797000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017838 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017838 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015838 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015838 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.229934 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.229934 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017879 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017879 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016915 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016915 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019528 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019528 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15650.114636 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15650.114636 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64418.511235 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64418.511235 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14041.790429 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14041.790429 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13999.272463 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13999.272463 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82500 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35954.077832 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35954.077832 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32789.957931 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32789.957931 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202341.085769 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202341.085769 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107280.682631 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107280.682631 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 2894242 # number of replacements -system.cpu.icache.tags.tagsinuse 511.201941 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 54613603 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 2894754 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.866406 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 18510731500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.201941 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998441 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998441 # Average percentage of cache occupancy +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016950 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016950 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019560 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019560 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14267.307359 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14267.307359 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41808.960667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41808.960667 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13270.419125 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13270.419125 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13359.149856 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13359.149856 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 83500 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 83500 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25692.084519 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25692.084519 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23902.964459 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23902.964459 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 202447.860447 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202447.860447 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107335.882543 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107335.882543 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 2889133 # number of replacements +system.cpu.icache.tags.tagsinuse 511.392140 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 54584955 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2889645 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.889848 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 15688442500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.392140 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998813 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998813 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 200 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60403134 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60403134 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 54613603 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 54613603 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37561515000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 37561515000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37561515000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 37561515000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 485617000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 485617000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 485617000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 485617000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050336 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050336 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050336 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.050336 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050336 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.050336 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12975.665391 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12975.665391 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12975.665391 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12975.665391 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12975.665391 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12975.665391 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 129222.192656 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129222.192656 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129222.192656 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129222.192656 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 96413 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65014.111647 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 7029815 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 161656 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 43.486261 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 47147.953940 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 65.794382 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.010019 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 12263.315434 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5537.037871 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.719421 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001004 # Average percentage of cache occupancy +system.cpu.icache.writebacks::writebacks 2889133 # number of writebacks +system.cpu.icache.writebacks::total 2889133 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2889657 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36355958500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 36355958500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36355958500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 36355958500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 258265000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 258265000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 258265000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 258265000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050277 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050277 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050277 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.050277 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050277 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.050277 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12581.409662 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12581.409662 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12581.409662 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12581.409662 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12581.409662 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12581.409662 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 79052.647689 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 79052.647689 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 79052.647689 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 79052.647689 # average overall mshr uncacheable latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 96859 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65151.144064 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 7317028 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 162271 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 45.091409 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 94922732000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 70.044406 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.023437 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 12290.016649 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 52791.059572 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001069 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.187123 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.084488 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.992037 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 54 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65189 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 54 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2263 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6860 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55955 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000824 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994705 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 60474648 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 60474648 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 73812 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4869 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 78681 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 701092 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 701092 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 2843365 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 2843365 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 49 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 49 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 165406 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 165406 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2871798 # 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mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007919 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007919 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026052 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.026052 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001691 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000411 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007919 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.171748 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.044036 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001691 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000411 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007919 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.171748 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.044036 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 130548 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122750 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 130425.196850 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68012.614260 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68012.614260 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118834.485210 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118834.485210 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120722.462156 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120722.462156 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122110.166527 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122110.166527 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 130548 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122750 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120722.462156 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119157.147485 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119379.058302 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 130548 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120722.462156 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119157.147485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119379.058302 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113622.405535 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189838.580148 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181628.869525 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113622.405535 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100651.888817 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 101432.129594 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 7509695 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3770160 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58111 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 594 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 594 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437328 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437328 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007934 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007934 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026388 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.026388 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001767 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000302 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007934 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.169986 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.043821 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001767 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000302 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007934 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.169986 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.043821 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75741.666667 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 73500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75723.140496 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19100 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19100 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 72000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 72000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69230.609718 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69230.609718 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70851.594190 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70851.594190 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74260.848602 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74260.848602 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75741.666667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 73500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70851.594190 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69738.609330 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69895.927005 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75741.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 73500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70851.594190 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69738.609330 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69895.927005 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63513.774105 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189945.451041 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 177936.371566 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63513.774105 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100707.226925 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98746.676240 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 7504035 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3768706 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58030 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 170 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 170 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 136822 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3580395 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 825389 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2894242 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 151717 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2784 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 137182 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3577165 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 788847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2889133 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 153180 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2809 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2786 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296207 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296207 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 2894766 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 548829 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8691264 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2657074 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16340 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 164402 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11529080 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370735360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99133929 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 19484 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 295748 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 470184521 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 192671 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 8062744 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 4076067 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.021486 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.144999 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2811 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295522 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295522 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 2889657 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 550405 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 4412 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8674948 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2659767 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14702 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 159313 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11508730 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370049536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 99142941 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13260 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 271652 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 469477389 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 133226 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5798108 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 4004431 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.022424 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.148057 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3988487 97.85% 97.85% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 87580 2.15% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3914637 97.76% 97.76% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 89794 2.24% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4076067 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7431755500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4004431 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7421943500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 275377 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4348377811 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4339894977 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1313662211 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1315039189 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 11470497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 11390493 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 90488952 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 91431936 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1270,66 +1275,66 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 46348000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46364500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 107000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 330500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 30500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 15000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 85500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 88000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 623500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 618000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 22000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 51000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 50000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6076000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6096500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38906500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 39117500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187130005 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187733842 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.038429 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.032370 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 275018797000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.038429 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064902 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064902 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270830421000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.032370 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064523 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064523 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328122 # Number of tag accesses system.iocache.tags.data_accesses 328122 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses system.iocache.ReadReq_misses::total 234 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -1338,14 +1343,14 @@ system.iocache.demand_misses::realview.ide 36458 # system.iocache.demand_misses::total 36458 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36458 # number of overall misses system.iocache.overall_misses::total 36458 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29054877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29054877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4548884128 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4548884128 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4577939005 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4577939005 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4577939005 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4577939005 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29494377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29494377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4278402465 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4278402465 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4307896842 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4307896842 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4307896842 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4307896842 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1362,14 +1367,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124166.141026 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124166.141026 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125576.527385 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125576.527385 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125567.475040 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125567.475040 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125567.475040 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125567.475040 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 126044.346154 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126044.346154 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118109.608685 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118109.608685 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 118160.536563 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118160.536563 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 118160.536563 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118160.536563 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1386,14 +1391,14 @@ system.iocache.demand_mshr_misses::realview.ide 36458 system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17354877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17354877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736261614 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2736261614 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2753616491 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2753616491 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2753616491 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2753616491 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17794377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17794377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2465093924 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2465093924 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2482888301 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2482888301 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2482888301 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2482888301 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1402,84 +1407,90 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74166.141026 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74166.141026 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75537.257454 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75537.257454 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75528.457156 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75528.457156 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75528.457156 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75528.457156 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 34888 # Transaction distribution -system.membus.trans_dist::ReadResp 72464 # Transaction distribution -system.membus.trans_dist::WriteReq 27584 # Transaction distribution -system.membus.trans_dist::WriteResp 27584 # Transaction distribution -system.membus.trans_dist::WritebackDirty 124285 # Transaction distribution -system.membus.trans_dist::CleanEvict 8552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4603 # Transaction distribution +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76044.346154 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76044.346154 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68051.400287 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68051.400287 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68102.701766 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68102.701766 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68102.701766 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68102.701766 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 336558 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 137845 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 488 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 34395 # Transaction distribution +system.membus.trans_dist::ReadResp 72195 # Transaction distribution +system.membus.trans_dist::WriteReq 27583 # Transaction distribution +system.membus.trans_dist::WriteResp 27583 # Transaction distribution +system.membus.trans_dist::WritebackDirty 124638 # Transaction distribution +system.membus.trans_dist::CleanEvict 8645 # Transaction distribution +system.membus.trans_dist::UpgradeReq 128 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 128933 # Transaction distribution -system.membus.trans_dist::ReadExResp 128933 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 37576 # Transaction distribution +system.membus.trans_dist::ReadExReq 129117 # Transaction distribution +system.membus.trans_dist::ReadExResp 129117 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 37800 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450661 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558229 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446466 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554028 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 631126 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 626925 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4148 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16521376 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16685161 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16538656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16702429 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19002281 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19019549 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 504 # Total snoops (count) system.membus.snoopTraffic 32128 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 402659 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::samples 265249 # Request fanout histogram +system.membus.snoop_fanout::mean 0.018541 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.134898 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 402659 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 260331 98.15% 98.15% # Request fanout histogram +system.membus.snoop_fanout::1 4918 1.85% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 402659 # Request fanout histogram -system.membus.reqLayer0.occupancy 92669500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 265249 # Request fanout histogram +system.membus.reqLayer0.occupancy 92904500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 8000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1708000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1693000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 910164615 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 906764526 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 990045000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 989491000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1264123 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1228623 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1511,28 +1522,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2858997339500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2853343899500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 410d93856..e59cf51bf 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.832894 # Number of seconds simulated -sim_ticks 2832894126500 # Number of ticks simulated -final_tick 2832894126500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.827853 # Number of seconds simulated +sim_ticks 2827853096000 # Number of ticks simulated +final_tick 2827853096000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74117 # Simulator instruction rate (inst/s) -host_op_rate 89897 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1856270381 # Simulator tick rate (ticks/s) -host_mem_usage 579324 # Number of bytes of host memory used -host_seconds 1526.12 # Real time elapsed on the host -sim_insts 113111333 # Number of instructions simulated -sim_ops 137193850 # Number of ops (including micro ops) simulated +host_inst_rate 70378 # Simulator instruction rate (inst/s) +host_op_rate 85367 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1758794234 # Simulator tick rate (ticks/s) +host_mem_usage 588628 # Number of bytes of host memory used +host_seconds 1607.84 # Real time elapsed on the host +sim_insts 113155640 # Number of instructions simulated +sim_ops 137255479 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1321536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9400296 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1322240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9790440 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10724584 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1321536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1321536 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8031104 # Number of bytes written to this memory +system.physmem.bytes_read::total 11115048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1322240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1322240 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8407168 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8048628 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22896 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 147400 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8424692 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22907 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 153496 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170339 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 125486 # Number of write requests responded to by this memory +system.physmem.num_reads::total 176440 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131362 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 129867 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 474 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 466497 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3318266 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 135743 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 362 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 136 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 467577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3462146 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3785734 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 466497 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 466497 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2834947 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6186 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2841133 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2834947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 474 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 466497 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3324452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3930561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 467577 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 467577 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2972986 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6197 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2979183 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2972986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 362 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 467577 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3468343 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6626867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170340 # Number of read requests accepted -system.physmem.writeReqs 129867 # Number of write requests accepted -system.physmem.readBursts 170340 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 129867 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10892352 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue -system.physmem.bytesWritten 8061056 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10724648 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8048628 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::total 6909744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 176441 # Number of read requests accepted +system.physmem.writeReqs 135743 # Number of write requests accepted +system.physmem.readBursts 176441 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 135743 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11282432 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9792 # Total number of bytes read from write queue +system.physmem.bytesWritten 8437824 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11115112 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8424692 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3886 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11036 # Per bank write bursts -system.physmem.perBankRdBursts::1 10507 # Per bank write bursts -system.physmem.perBankRdBursts::2 10862 # Per bank write bursts -system.physmem.perBankRdBursts::3 11068 # Per bank write bursts -system.physmem.perBankRdBursts::4 13101 # Per bank write bursts -system.physmem.perBankRdBursts::5 10327 # Per bank write bursts -system.physmem.perBankRdBursts::6 10639 # Per bank write bursts -system.physmem.perBankRdBursts::7 10985 # Per bank write bursts -system.physmem.perBankRdBursts::8 10460 # Per bank write bursts -system.physmem.perBankRdBursts::9 10167 # Per bank write bursts -system.physmem.perBankRdBursts::10 10435 # Per bank write bursts -system.physmem.perBankRdBursts::11 9511 # Per bank write bursts -system.physmem.perBankRdBursts::12 9930 # Per bank write bursts -system.physmem.perBankRdBursts::13 10756 # Per bank write bursts -system.physmem.perBankRdBursts::14 10401 # Per bank write bursts -system.physmem.perBankRdBursts::15 10008 # Per bank write bursts -system.physmem.perBankWrBursts::0 8291 # Per bank write bursts -system.physmem.perBankWrBursts::1 7865 # Per bank write bursts -system.physmem.perBankWrBursts::2 8399 # Per bank write bursts -system.physmem.perBankWrBursts::3 8558 # Per bank write bursts -system.physmem.perBankWrBursts::4 7751 # Per bank write bursts -system.physmem.perBankWrBursts::5 7713 # Per bank write bursts -system.physmem.perBankWrBursts::6 7781 # Per bank write bursts -system.physmem.perBankWrBursts::7 8111 # Per bank write bursts -system.physmem.perBankWrBursts::8 7871 # Per bank write bursts -system.physmem.perBankWrBursts::9 7662 # Per bank write bursts -system.physmem.perBankWrBursts::10 7844 # Per bank write bursts -system.physmem.perBankWrBursts::11 7196 # Per bank write bursts -system.physmem.perBankWrBursts::12 7582 # Per bank write bursts -system.physmem.perBankWrBursts::13 8119 # Per bank write bursts -system.physmem.perBankWrBursts::14 7846 # Per bank write bursts -system.physmem.perBankWrBursts::15 7365 # Per bank write bursts +system.physmem.perBankRdBursts::0 11743 # Per bank write bursts +system.physmem.perBankRdBursts::1 11227 # Per bank write bursts +system.physmem.perBankRdBursts::2 11041 # Per bank write bursts +system.physmem.perBankRdBursts::3 10652 # Per bank write bursts +system.physmem.perBankRdBursts::4 13485 # Per bank write bursts +system.physmem.perBankRdBursts::5 11002 # Per bank write bursts +system.physmem.perBankRdBursts::6 11432 # Per bank write bursts +system.physmem.perBankRdBursts::7 11844 # Per bank write bursts +system.physmem.perBankRdBursts::8 10383 # Per bank write bursts +system.physmem.perBankRdBursts::9 10947 # Per bank write bursts +system.physmem.perBankRdBursts::10 10471 # Per bank write bursts +system.physmem.perBankRdBursts::11 9569 # Per bank write bursts +system.physmem.perBankRdBursts::12 10361 # Per bank write bursts +system.physmem.perBankRdBursts::13 11110 # Per bank write bursts +system.physmem.perBankRdBursts::14 10361 # Per bank write bursts +system.physmem.perBankRdBursts::15 10660 # Per bank write bursts +system.physmem.perBankWrBursts::0 8764 # Per bank write bursts +system.physmem.perBankWrBursts::1 8604 # Per bank write bursts +system.physmem.perBankWrBursts::2 8676 # Per bank write bursts +system.physmem.perBankWrBursts::3 8310 # Per bank write bursts +system.physmem.perBankWrBursts::4 8074 # Per bank write bursts +system.physmem.perBankWrBursts::5 8230 # Per bank write bursts +system.physmem.perBankWrBursts::6 8228 # Per bank write bursts +system.physmem.perBankWrBursts::7 8800 # Per bank write bursts +system.physmem.perBankWrBursts::8 7938 # Per bank write bursts +system.physmem.perBankWrBursts::9 8472 # Per bank write bursts +system.physmem.perBankWrBursts::10 8080 # Per bank write bursts +system.physmem.perBankWrBursts::11 7388 # Per bank write bursts +system.physmem.perBankWrBursts::12 8035 # Per bank write bursts +system.physmem.perBankWrBursts::13 8487 # Per bank write bursts +system.physmem.perBankWrBursts::14 7854 # Per bank write bursts +system.physmem.perBankWrBursts::15 7901 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 17 # Number of times write queue was full causing retry -system.physmem.totGap 2832893894500 # Total gap between requests +system.physmem.numWrRetry 4 # Number of times write queue was full causing retry +system.physmem.totGap 2827852861000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 2996 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166788 # Read request sizes (log2) +system.physmem.readPktSize::6 172889 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 125486 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 150867 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 16439 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 721 # What read queue length does an incoming req see +system.physmem.writePktSize::6 131362 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 155219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 17999 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 829 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -160,164 +160,164 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 56 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62108 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 305.167515 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.813202 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.494619 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 23016 37.06% 37.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15104 24.32% 61.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6524 10.50% 71.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3665 5.90% 77.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2528 4.07% 81.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1637 2.64% 84.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1479 2.38% 86.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1102 1.77% 88.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7053 11.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62108 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6142 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.706936 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 569.623530 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6141 99.98% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6142 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6142 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.507001 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.506831 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.607971 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5435 88.49% 88.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 129 2.10% 90.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 31 0.50% 91.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 49 0.80% 91.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 32 0.52% 92.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 17 0.28% 92.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 48 0.78% 93.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 14 0.23% 93.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 140 2.28% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 11 0.18% 96.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.13% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.13% 96.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 65 1.06% 97.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.02% 97.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 21 0.34% 97.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 93 1.51% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.05% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.05% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.18% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 7 0.11% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6142 # Writes before turning the bus around for reads -system.physmem.totQLat 2108320500 # Total ticks spent queuing -system.physmem.totMemAccLat 5299439250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 850965000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12387.82 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 10 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64990 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 303.434251 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.571710 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 325.070143 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24166 37.18% 37.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15993 24.61% 61.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6821 10.50% 72.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3792 5.83% 78.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2758 4.24% 82.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1633 2.51% 84.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1086 1.67% 86.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1085 1.67% 88.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7656 11.78% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64990 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6662 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.461423 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 559.657587 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6661 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6662 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6662 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.790003 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.288798 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.351415 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5875 88.19% 88.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 70 1.05% 89.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 75 1.13% 90.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 36 0.54% 90.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 259 3.89% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 62 0.93% 95.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 25 0.38% 96.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 19 0.29% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 9 0.14% 96.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 7 0.11% 96.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.05% 96.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.06% 96.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 160 2.40% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.09% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 8 0.12% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 2 0.03% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 6 0.09% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.05% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 10 0.15% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.12% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6662 # Writes before turning the bus around for reads +system.physmem.totQLat 2116192000 # Total ticks spent queuing +system.physmem.totMemAccLat 5421592000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 881440000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12004.17 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31137.82 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.79 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.84 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30754.17 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.99 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.93 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.98 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.42 # Average write queue length when enqueuing -system.physmem.readRowHits 139937 # Number of row buffer hits during reads -system.physmem.writeRowHits 94101 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.22 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes -system.physmem.avgGap 9436468.49 # Average gap between requests -system.physmem.pageHitRate 79.02 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 243454680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 132837375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 690495000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 417759120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185030401920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83647548450 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1626357251250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1896519747795 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.465335 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2705450093000 # Time in different power states -system.physmem_0.memoryStateTime::REF 94596320000 # Time in different power states +system.physmem.avgWrQLen 23.03 # Average write queue length when enqueuing +system.physmem.readRowHits 145153 # Number of row buffer hits during reads +system.physmem.writeRowHits 97985 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.31 # Row buffer hit rate for writes +system.physmem.avgGap 9058288.90 # Average gap between requests +system.physmem.pageHitRate 78.90 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 256087440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 139730250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 720922800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 438605280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184701363600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 81077227785 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1625589296250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1892923233405 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.386141 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2704185411500 # Time in different power states +system.physmem_0.memoryStateTime::REF 94428100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32840757000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 29235954750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 226081800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 123358125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 637002600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 398422800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185030401920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82216233135 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1627612791000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1896244291380 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.368099 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2707556632500 # Time in different power states -system.physmem_1.memoryStateTime::REF 94596320000 # Time in different power states +system.physmem_1.actEnergy 235236960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 128353500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 654115800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 415724400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184701363600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 80292349755 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1626277785750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1892704929765 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.308944 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2705344853000 # Time in different power states +system.physmem_1.memoryStateTime::REF 94428100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30741160500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 28080129500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory @@ -330,30 +330,30 @@ system.realview.nvmem.bw_inst_read::cpu.inst 40 system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46812529 # Number of BP lookups -system.cpu.branchPred.condPredicted 23980713 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1174980 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29461889 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13525990 # Number of BTB hits +system.cpu.branchPred.lookups 46859222 # Number of BP lookups +system.cpu.branchPred.condPredicted 23995015 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1174256 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29489294 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13535968 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 45.910125 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11726513 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 34925 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 7916092 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 7770128 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 145964 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 60126 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 45.901296 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11745095 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 35189 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 7931554 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 7786304 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 145250 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 60170 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -383,47 +383,47 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.cpu.checker.dtb.walker.walks 9712 # Table walker walks requested -system.cpu.checker.dtb.walker.walksShort 9712 # Table walker walks initiated with short descriptors -system.cpu.checker.dtb.walker.walkWaitTime::samples 9712 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::0 9712 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::total 9712 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walksPending::samples 375751000 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::0 375751000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::total 375751000 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walkPageSizes::4K 6218 82.38% 82.38% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::1M 1330 17.62% 100.00% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::total 7548 # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9712 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.cpu.checker.dtb.walker.walks 9867 # Table walker walks requested +system.cpu.checker.dtb.walker.walksShort 9867 # Table walker walks initiated with short descriptors +system.cpu.checker.dtb.walker.walkWaitTime::samples 9867 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::0 9867 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::total 9867 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walksPending::samples 230261000 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::0 230261000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::total 230261000 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walkPageSizes::4K 6312 81.94% 81.94% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::1M 1391 18.06% 100.00% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::total 7703 # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9867 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9712 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7548 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9867 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7703 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7548 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 17260 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7703 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 17570 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 24578721 # DTB read hits -system.cpu.checker.dtb.read_misses 8315 # DTB read misses -system.cpu.checker.dtb.write_hits 19634427 # DTB write hits -system.cpu.checker.dtb.write_misses 1397 # DTB write misses +system.cpu.checker.dtb.read_hits 24589623 # DTB read hits +system.cpu.checker.dtb.read_misses 8439 # DTB read misses +system.cpu.checker.dtb.write_hits 19639356 # DTB write hits +system.cpu.checker.dtb.write_misses 1428 # DTB write misses system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 4219 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 4257 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 1636 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 1816 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 24587036 # DTB read accesses -system.cpu.checker.dtb.write_accesses 19635824 # DTB write accesses +system.cpu.checker.dtb.read_accesses 24598062 # DTB read accesses +system.cpu.checker.dtb.write_accesses 19640784 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 44213148 # DTB hits -system.cpu.checker.dtb.misses 9712 # DTB misses -system.cpu.checker.dtb.accesses 44222860 # DTB accesses -system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.cpu.checker.dtb.hits 44228979 # DTB hits +system.cpu.checker.dtb.misses 9867 # DTB misses +system.cpu.checker.dtb.accesses 44238846 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -453,27 +453,27 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.cpu.checker.itb.walker.walks 4825 # Table walker walks requested -system.cpu.checker.itb.walker.walksShort 4825 # Table walker walks initiated with short descriptors -system.cpu.checker.itb.walker.walkWaitTime::samples 4825 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::0 4825 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::total 4825 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walksPending::samples 375090000 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::0 375090000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::total 375090000 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walkPageSizes::4K 2798 88.26% 88.26% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::1M 372 11.74% 100.00% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::total 3170 # Table walker page sizes translated +system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.cpu.checker.itb.walker.walks 4826 # Table walker walks requested +system.cpu.checker.itb.walker.walksShort 4826 # Table walker walks initiated with short descriptors +system.cpu.checker.itb.walker.walkWaitTime::samples 4826 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::0 4826 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::total 4826 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walksPending::samples 229845000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::0 229845000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::total 229845000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walkPageSizes::4K 2798 88.24% 88.24% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::1M 373 11.76% 100.00% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::total 3171 # Table walker page sizes translated system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 4825 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 4825 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 4826 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 4826 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 3170 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 3170 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin::total 7995 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 115810053 # ITB inst hits -system.cpu.checker.itb.inst_misses 4825 # ITB inst misses +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 3171 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 3171 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin::total 7997 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.inst_hits 115857502 # ITB inst hits +system.cpu.checker.itb.inst_misses 4826 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses system.cpu.checker.itb.write_hits 0 # DTB write hits @@ -482,22 +482,22 @@ system.cpu.checker.itb.flush_tlb 128 # Nu system.cpu.checker.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 2912 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.flush_entries 2913 # Number of entries that have been flushed from TLB system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 115814878 # ITB inst accesses -system.cpu.checker.itb.hits 115810053 # DTB hits -system.cpu.checker.itb.misses 4825 # DTB misses -system.cpu.checker.itb.accesses 115814878 # DTB accesses -system.cpu.checker.pwrStateResidencyTicks::ON 2832894126500 # Cumulative time (in ticks) in various power states -system.cpu.checker.numCycles 139044613 # number of cpu cycles simulated +system.cpu.checker.itb.inst_accesses 115862328 # ITB inst accesses +system.cpu.checker.itb.hits 115857502 # DTB hits +system.cpu.checker.itb.misses 4826 # DTB misses +system.cpu.checker.itb.accesses 115862328 # DTB accesses +system.cpu.checker.pwrStateResidencyTicks::ON 2827853096000 # Cumulative time (in ticks) in various power states +system.cpu.checker.numCycles 139109385 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -527,82 +527,83 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 72186 # Table walker walks requested -system.cpu.dtb.walker.walksShort 72186 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29334 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23181 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 19671 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 52515 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 467.713986 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 2821.743931 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-8191 51203 97.50% 97.50% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::8192-16383 905 1.72% 99.22% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::16384-24575 322 0.61% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::24576-32767 40 0.08% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-40959 18 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::40960-49151 21 0.04% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::57344-65535 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 72426 # Table walker walks requested +system.cpu.dtb.walker.walksShort 72426 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29716 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23400 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 19310 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 53116 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 407.485503 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 2469.018740 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-8191 51917 97.74% 97.74% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-16383 937 1.76% 99.51% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::16384-24575 190 0.36% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::24576-32767 37 0.07% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-40959 15 0.03% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::40960-49151 16 0.03% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::57344-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::90112-98303 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 52515 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 17658 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 12583.333333 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 10066.135653 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 8522.119991 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 17438 98.75% 98.75% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-65535 214 1.21% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-163839 4 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-360447 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 17658 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 131358619316 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.629965 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.490082 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 131298865316 99.95% 99.95% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 40695500 0.03% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 8747000 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 6751500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 1053500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 584000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 1412000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 501000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walkWaitTime::total 53116 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 17396 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 9637.387905 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 7803.906851 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 6813.601039 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 15561 89.45% 89.45% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 1740 10.00% 99.45% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-49151 86 0.49% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::49152-65535 2 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-81919 1 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::245760-262143 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 17396 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 117727604724 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.629848 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.489627 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 117677681224 99.96% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 34838500 0.03% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 7318000 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 4585500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 935500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 533500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 1306000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 397000 0.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::16-17 9500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 131358619316 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6349 82.25% 82.25% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1370 17.75% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7719 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72186 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walksPending::total 117727604724 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6471 81.85% 81.85% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1435 18.15% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7906 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72426 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72186 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7719 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72426 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7906 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7719 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 79905 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7906 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 80332 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25413003 # DTB read hits -system.cpu.dtb.read_misses 62542 # DTB read misses -system.cpu.dtb.write_hits 19866296 # DTB write hits -system.cpu.dtb.write_misses 9644 # DTB write misses +system.cpu.dtb.read_hits 25423365 # DTB read hits +system.cpu.dtb.read_misses 62664 # DTB read misses +system.cpu.dtb.write_hits 19868926 # DTB write hits +system.cpu.dtb.write_misses 9762 # DTB write misses system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4253 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 366 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2075 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4289 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 358 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2236 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1321 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25475545 # DTB read accesses -system.cpu.dtb.write_accesses 19875940 # DTB write accesses +system.cpu.dtb.perms_faults 1258 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25486029 # DTB read accesses +system.cpu.dtb.write_accesses 19878688 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45279299 # DTB hits -system.cpu.dtb.misses 72186 # DTB misses -system.cpu.dtb.accesses 45351485 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 45292291 # DTB hits +system.cpu.dtb.misses 72426 # DTB misses +system.cpu.dtb.accesses 45364717 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -632,59 +633,58 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 12817 # Table walker walks requested -system.cpu.itb.walker.walksShort 12817 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 3407 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 7692 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 1718 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 11099 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 742.229030 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 3116.397220 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-4095 10521 94.79% 94.79% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::4096-8191 119 1.07% 95.86% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::8192-12287 227 2.05% 97.91% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::12288-16383 123 1.11% 99.02% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::16384-20479 47 0.42% 99.44% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::20480-24575 47 0.42% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::28672-32767 6 0.05% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::36864-40959 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::40960-45055 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::53248-57343 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::57344-61439 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 11099 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 5040 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 12026.488095 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 9684.197840 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7608.176186 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-16383 4071 80.77% 80.77% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-32767 955 18.95% 99.72% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-49151 11 0.22% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::49152-65535 1 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 5040 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 23984374916 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.642154 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.479545 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 8584682500 35.79% 35.79% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 15397812416 64.20% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 1792000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 88000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 23984374916 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2987 89.92% 89.92% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 335 10.08% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3322 # Table walker page sizes translated +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 12855 # Table walker walks requested +system.cpu.itb.walker.walksShort 12855 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 3590 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7693 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 1572 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 11283 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 605.778605 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 2805.757421 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-8191 10907 96.67% 96.67% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-16383 327 2.90% 99.57% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::16384-24575 40 0.35% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::24576-32767 5 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::40960-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-73727 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::81920-90111 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 11283 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 4887 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 8961.019030 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 7007.167188 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7172.888707 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 3327 68.08% 68.08% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 829 16.96% 85.04% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 682 13.96% 99.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::24576-32767 38 0.78% 99.77% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-40959 1 0.02% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::40960-49151 7 0.14% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::49152-57343 1 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::81920-90111 2 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 4887 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 23237381212 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.774797 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.417824 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 5234024500 22.52% 22.52% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 18002578212 77.47% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 696500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 46500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 35500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 23237381212 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2980 89.89% 89.89% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 335 10.11% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3315 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12817 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 12817 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12855 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 12855 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3322 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3322 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 16139 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 65982481 # ITB inst hits -system.cpu.itb.inst_misses 12817 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3315 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3315 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 16170 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 66060204 # ITB inst hits +system.cpu.itb.inst_misses 12855 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -693,112 +693,113 @@ system.cpu.itb.flush_tlb 128 # Nu system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3021 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3013 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2147 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2175 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 65995298 # ITB inst accesses -system.cpu.itb.hits 65982481 # DTB hits -system.cpu.itb.misses 12817 # DTB misses -system.cpu.itb.accesses 65995298 # DTB accesses -system.cpu.numPwrStateTransitions 6074 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 3037 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 886948130.312150 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17421700028.084686 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 2966 97.66% 97.66% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 65 2.14% 99.80% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 66073059 # ITB inst accesses +system.cpu.itb.hits 66060204 # DTB hits +system.cpu.itb.misses 12855 # DTB misses +system.cpu.itb.accesses 66073059 # DTB accesses +system.cpu.numPwrStateTransitions 6076 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 3038 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 887319797.866359 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17420812025.908409 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 2966 97.63% 97.63% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 66 2.17% 99.80% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.07% 99.90% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 499972891000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 3037 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 139232654742 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2693661471758 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 278465363 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 499973328096 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 3038 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 132175550082 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2695677545918 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 264351157 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104979858 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184015649 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46812529 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33022631 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 161497089 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6057652 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 189263 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 8972 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 337056 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 558097 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 172 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 65981271 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1027864 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6246 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 270599333 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.829251 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.216918 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 105007140 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184198118 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46859222 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33067367 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 149125653 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6062128 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 177509 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 8064 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 342285 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 500656 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 149 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 66059105 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1061874 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6140 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 258192520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.869926 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.232240 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 171686790 63.45% 63.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29154260 10.77% 74.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14034299 5.19% 79.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55723984 20.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 159207105 61.66% 61.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29153243 11.29% 72.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14041371 5.44% 78.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55790801 21.61% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 270599333 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.168109 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.660821 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 77964907 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 121895477 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64303176 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3866825 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2568948 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3406986 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 467982 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 156982730 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3511045 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2568948 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83721940 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11815597 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 76560081 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62413108 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 33519659 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146432544 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 918349 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 465966 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 65322 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 18586 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 30762818 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150226924 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 676971311 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 163962292 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10893 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141750491 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8476427 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2839737 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2644396 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13885386 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26339908 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21214343 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1703941 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2126584 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143224778 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2118002 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143047064 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 260478 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8148926 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14278560 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 121950 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 270599333 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.528631 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.865147 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 258192520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.177261 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.696793 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 78121728 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 109293057 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64347286 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3858820 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2571629 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3404933 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 467397 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157054266 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3508469 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2571629 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83876272 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10707182 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 75777880 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62454434 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 22805123 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146493829 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 914752 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 447933 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 65579 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 19295 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 20059867 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150297562 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 677265731 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164029738 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 11047 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141819290 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8478266 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2841903 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2646616 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13881588 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26350743 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21216202 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1694356 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2155521 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143287156 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2116266 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143106706 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 261772 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8147939 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14286308 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 122067 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 258192520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.554264 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.878016 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 182394036 67.40% 67.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45259787 16.73% 84.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 31866202 11.78% 95.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10262392 3.79% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 816883 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 169987358 65.84% 65.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45210540 17.51% 83.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31907168 12.36% 95.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10268019 3.98% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 819402 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -806,44 +807,44 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 270599333 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 258192520 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7342152 32.76% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 32 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5622313 25.09% 57.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9444091 42.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7338606 32.76% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 32 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5623411 25.10% 57.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9440852 42.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 95850690 67.01% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 114288 0.08% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 95896760 67.01% 67.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 115009 0.08% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued @@ -867,99 +868,99 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8577 0.01% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26130891 18.27% 85.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 20940281 14.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8592 0.01% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26141404 18.27% 85.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 20942604 14.63% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143047064 # Type of FU issued -system.cpu.iq.rate 0.513698 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22408588 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.156652 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 579326888 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 153497201 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 139997351 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35639 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13116 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 11369 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165429916 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23399 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 323958 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 143106706 # Type of FU issued +system.cpu.iq.rate 0.541351 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22402901 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.156547 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 567034934 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 153556562 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140052264 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35671 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13288 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 11499 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 165483986 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23284 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 324130 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1433781 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 712 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18665 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 622043 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1434023 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 698 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18538 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 619510 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 88844 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6344 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 88631 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6598 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2568948 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1241907 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 544667 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145523405 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2571629 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 994929 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 316385 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145584227 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26339908 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21214343 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1094304 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17849 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 508298 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18665 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 277238 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471000 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 748238 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142148555 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25736254 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 826428 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26350743 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21216202 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1093451 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17658 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 280514 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18538 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 277676 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 470698 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 748374 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142207045 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25746206 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 827350 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 180625 # number of nop insts executed -system.cpu.iew.exec_refs 46564673 # number of memory reference insts executed -system.cpu.iew.exec_branches 26492434 # Number of branches executed -system.cpu.iew.exec_stores 20828419 # Number of stores executed -system.cpu.iew.exec_rate 0.510471 # Inst execution rate -system.cpu.iew.wb_sent 141779361 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140008720 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63240555 # num instructions producing a value -system.cpu.iew.wb_consumers 95712709 # num instructions consuming a value -system.cpu.iew.wb_rate 0.502787 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660733 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 7366290 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1996052 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 715102 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 267708008 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.513054 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.118068 # Number of insts commited each cycle +system.cpu.iew.exec_nop 180805 # number of nop insts executed +system.cpu.iew.exec_refs 46576895 # number of memory reference insts executed +system.cpu.iew.exec_branches 26509940 # Number of branches executed +system.cpu.iew.exec_stores 20830689 # Number of stores executed +system.cpu.iew.exec_rate 0.537948 # Inst execution rate +system.cpu.iew.wb_sent 141837731 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140063763 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63261975 # num instructions producing a value +system.cpu.iew.wb_consumers 95760288 # num instructions consuming a value +system.cpu.iew.wb_rate 0.529840 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660628 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 7362260 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1994199 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 714821 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 255299551 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.538232 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.139550 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 194252968 72.56% 72.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43305040 16.18% 88.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15457612 5.77% 94.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4371808 1.63% 96.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6428406 2.40% 98.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1610065 0.60% 99.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 797962 0.30% 99.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 411830 0.15% 99.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1072317 0.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 181839086 71.23% 71.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43295063 16.96% 88.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15470047 6.06% 94.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4367483 1.71% 95.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6400805 2.51% 98.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1643674 0.64% 99.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 799411 0.31% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 417134 0.16% 99.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1066848 0.42% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 267708008 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113266238 # Number of instructions committed -system.cpu.commit.committedOps 137348755 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 255299551 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113310545 # Number of instructions committed +system.cpu.commit.committedOps 137410384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45498427 # Number of memory references committed -system.cpu.commit.loads 24906127 # Number of loads committed -system.cpu.commit.membars 814995 # Number of memory barriers committed -system.cpu.commit.branches 26026646 # Number of branches committed -system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120175202 # Number of committed integer instructions. -system.cpu.commit.function_calls 4885014 # Number of function calls committed. +system.cpu.commit.refs 45513412 # Number of memory references committed +system.cpu.commit.loads 24916720 # Number of loads committed +system.cpu.commit.membars 814165 # Number of memory barriers committed +system.cpu.commit.branches 26044798 # Number of branches committed +system.cpu.commit.fp_insts 11492 # Number of committed floating point instructions. +system.cpu.commit.int_insts 120233477 # Number of committed integer instructions. +system.cpu.commit.function_calls 4891928 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91728959 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 112792 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91774855 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 113526 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction @@ -983,693 +984,689 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 8577 0.01% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24906127 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20592300 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8591 0.01% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24916720 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20596692 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137348755 # Class of committed instruction -system.cpu.commit.bw_lim_events 1072317 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 389160423 # The number of ROB reads -system.cpu.rob.rob_writes 292308325 # The number of ROB writes -system.cpu.timesIdled 890756 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7866030 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5387322891 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113111333 # Number of Instructions Simulated -system.cpu.committedOps 137193850 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.461870 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.461870 # CPI: Total CPI of All Threads -system.cpu.ipc 0.406195 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.406195 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155535200 # number of integer regfile reads -system.cpu.int_regfile_writes 88495254 # number of integer regfile writes -system.cpu.fp_regfile_reads 9528 # number of floating regfile reads +system.cpu.commit.op_class_0::total 137410384 # Class of committed instruction +system.cpu.commit.bw_lim_events 1066848 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 376774257 # The number of ROB reads +system.cpu.rob.rob_writes 292425270 # The number of ROB writes +system.cpu.timesIdled 893722 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6158637 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5391355036 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113155640 # Number of Instructions Simulated +system.cpu.committedOps 137255479 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.336173 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.336173 # CPI: Total CPI of All Threads +system.cpu.ipc 0.428050 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.428050 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155596461 # number of integer regfile reads +system.cpu.int_regfile_writes 88540194 # number of integer regfile writes +system.cpu.fp_regfile_reads 9674 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 502191760 # number of cc regfile reads -system.cpu.cc_regfile_writes 53133619 # number of cc regfile writes -system.cpu.misc_regfile_reads 461629806 # number of misc regfile reads -system.cpu.misc_regfile_writes 1521804 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 838109 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.925913 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40060330 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 838621 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.769290 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.925913 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy +system.cpu.cc_regfile_reads 502394912 # number of cc regfile reads +system.cpu.cc_regfile_writes 53149715 # number of cc regfile writes +system.cpu.misc_regfile_reads 449419252 # number of misc regfile reads +system.cpu.misc_regfile_writes 1520020 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 839084 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.954165 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40069527 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 839596 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.724771 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 270911500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.954165 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999910 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999910 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 358 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179138470 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179138470 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 23266826 # 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number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 130358500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 208000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 208000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19316454479 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19316454479 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20939138479 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20939138479 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6279502000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6279502000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6279502000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6279502000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017270 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017270 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015684 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015684 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228351 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228351 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017900 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017900 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # 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average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14175.624990 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15049.484414 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15049.484414 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36956.469024 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36956.469024 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33690.033758 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33690.033758 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201620.819814 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201620.819814 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106895.365671 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106895.365671 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1886431 # number of replacements -system.cpu.icache.tags.tagsinuse 511.154202 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 64000082 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1886943 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 33.917337 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 16319051500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.154202 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998348 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998348 # Average percentage of cache occupancy +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016566 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016566 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019101 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019101 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14221.769121 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14221.769121 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44683.609554 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44683.609554 # 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Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 13715039500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.341026 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998713 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998713 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 221 # 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number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1978185 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1978185 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1978185 # number of overall misses -system.cpu.icache.overall_misses::total 1978185 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28158737492 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28158737492 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28158737492 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28158737492 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28158737492 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28158737492 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 65978267 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 65978267 # 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average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14234.633006 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14234.633006 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14234.633006 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14234.633006 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14234.633006 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5390 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 67944454 # Number of tag accesses +system.cpu.icache.tags.data_accesses 67944454 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 64075895 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 64075895 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 64075895 # 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number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26984355494 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26984355494 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26984355494 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66056101 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66056101 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66056101 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66056101 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66056101 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66056101 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029978 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.029978 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.029978 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.029978 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.029978 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.029978 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13627.044607 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13627.044607 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13627.044607 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13627.044607 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13627.044607 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13627.044607 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2643 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 176 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 125 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 30.625000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.144000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1886431 # number of writebacks -system.cpu.icache.writebacks::total 1886431 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91184 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 91184 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 91184 # 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mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000587 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010546 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.182624 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.062049 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 73666.666667 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 80886.363636 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19136.363636 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19136.363636 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 73500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 73500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71114.599669 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71114.599669 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73238.927388 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73238.927388 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76205.075398 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76205.075398 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 73666.666667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73238.927388 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71590.136565 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71780.813182 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 73666.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73238.927388 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.136565 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71780.813182 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63773.060273 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189237.783917 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 178198.505713 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63773.060273 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100328.805505 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98550.004861 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5488560 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2760615 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 44763 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 238 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 238 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 128619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2557060 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 821637 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1886431 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 149968 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2806 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 129622 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2559974 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 791350 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1887810 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 151157 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2768 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2811 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 297337 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 297337 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887001 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 541532 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5666337 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2638583 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30857 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 133499 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8469276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241541168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98417449 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 48264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 231212 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 340238093 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 194794 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 8145576 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3054607 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.024758 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.155386 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2773 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 297834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 297834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1888354 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 542004 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 4368 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5670459 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2641503 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 29194 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 130873 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8472029 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241718384 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98487773 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 217428 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 340464457 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 139207 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6232532 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2995964 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.025358 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.157210 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2978982 97.52% 97.52% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 75625 2.48% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2919992 97.46% 97.46% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 75972 2.54% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3054607 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5400960498 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2995964 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5405204997 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 258877 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 383377 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2834452098 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2836467127 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1304519551 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1305988986 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 18799483 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 18982487 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 75755880 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 76565899 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 30172 # Transaction distribution -system.iobus.trans_dist::ReadResp 30172 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 30182 # Transaction distribution +system.iobus.trans_dist::ReadResp 30182 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) @@ -1692,9 +1689,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72894 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72894 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178372 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178392 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) @@ -1715,22 +1712,22 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321016 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321016 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480141 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 43088500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 43094500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 326000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 325500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 28000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 92500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 91500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 651500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 649500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1752,56 +1749,56 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6158500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6172500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33063500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 33854000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187149991 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187760330 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36738000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 36413 # number of replacements -system.iocache.tags.tagsinuse 1.005857 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 36423 # number of replacements +system.iocache.tags.tagsinuse 1.000676 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36429 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 256506730000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.005857 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062866 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062866 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 252706881000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.000676 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062542 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062542 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328023 # Number of tag accesses -system.iocache.tags.data_accesses 328023 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses -system.iocache.ReadReq_misses::total 223 # number of ReadReq misses +system.iocache.tags.tag_accesses 328113 # Number of tag accesses +system.iocache.tags.data_accesses 328113 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_misses::realview.ide 233 # number of ReadReq misses +system.iocache.ReadReq_misses::total 233 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36447 # number of demand (read+write) misses -system.iocache.demand_misses::total 36447 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36447 # number of overall misses -system.iocache.overall_misses::total 36447 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28156877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28156877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4551348114 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4551348114 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4579504991 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4579504991 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4579504991 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4579504991 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 223 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 223 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 36457 # number of demand (read+write) misses +system.iocache.demand_misses::total 36457 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36457 # number of overall misses +system.iocache.overall_misses::total 36457 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 28964877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28964877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4277512453 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4277512453 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4306477330 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4306477330 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4306477330 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4306477330 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 233 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 233 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36447 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36447 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36447 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36447 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36457 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36457 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36457 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36457 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -1810,14 +1807,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 126264.022422 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126264.022422 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125644.548200 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125644.548200 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125648.338437 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125648.338437 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125648.338437 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125648.338437 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 124312.776824 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124312.776824 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118085.039007 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118085.039007 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 118124.841046 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118124.841046 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 118124.841046 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118124.841046 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1826,22 +1823,22 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 223 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 233 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 233 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 36447 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 36447 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 36447 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 36447 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17006877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17006877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2738747578 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2738747578 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2755754455 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2755754455 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2755754455 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2755754455 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 36457 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 36457 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 36457 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 36457 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17314877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17314877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2464212681 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2464212681 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2481527558 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2481527558 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2481527558 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2481527558 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1850,84 +1847,90 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76264.022422 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76264.022422 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75605.884993 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75605.884993 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75609.911790 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75609.911790 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75609.911790 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75609.911790 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 34132 # Transaction distribution -system.membus.trans_dist::ReadResp 67530 # Transaction distribution -system.membus.trans_dist::WriteReq 27585 # Transaction distribution -system.membus.trans_dist::WriteResp 27585 # Transaction distribution -system.membus.trans_dist::WritebackDirty 125486 # Transaction distribution -system.membus.trans_dist::CleanEvict 7993 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4611 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74312.776824 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74312.776824 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68027.072687 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68027.072687 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68067.245193 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68067.245193 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68067.245193 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68067.245193 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 349590 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 144366 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 482 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 34130 # Transaction distribution +system.membus.trans_dist::ReadResp 68622 # Transaction distribution +system.membus.trans_dist::WriteReq 27584 # Transaction distribution +system.membus.trans_dist::WriteResp 27584 # Transaction distribution +system.membus.trans_dist::WritebackDirty 131362 # Transaction distribution +system.membus.trans_dist::CleanEvict 8484 # Transaction distribution +system.membus.trans_dist::UpgradeReq 130 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 133874 # Transaction distribution -system.membus.trans_dist::ReadExResp 133874 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 33399 # Transaction distribution +system.membus.trans_dist::ReadExReq 138891 # Transaction distribution +system.membus.trans_dist::ReadExResp 138891 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34493 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 451368 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558936 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72875 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72875 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 631811 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465445 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 573007 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72895 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72895 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 645902 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16456092 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16619481 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17222620 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17385997 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18936601 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 487 # Total snoops (count) -system.membus.snoopTraffic 31040 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 403324 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size::total 19703117 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 497 # Total snoops (count) +system.membus.snoopTraffic 31680 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 271454 # Request fanout histogram +system.membus.snoop_fanout::mean 0.017933 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.132708 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 403324 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 266586 98.21% 98.21% # Request fanout histogram +system.membus.snoop_fanout::1 4868 1.79% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 403324 # Request fanout histogram -system.membus.reqLayer0.occupancy 83656500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 271454 # Request fanout histogram +system.membus.reqLayer0.occupancy 84464500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1736499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1723499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 876921354 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 908168519 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 979994750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1012308500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1182123 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1273123 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1959,30 +1962,30 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index d38a658b5..ab0dc0047 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,167 +1,167 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.825947 # Number of seconds simulated -sim_ticks 2825947406000 # Number of ticks simulated -final_tick 2825947406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.826111 # Number of seconds simulated +sim_ticks 2826111083000 # Number of ticks simulated +final_tick 2826111083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 132633 # Simulator instruction rate (inst/s) -host_op_rate 160894 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3120208803 # Simulator tick rate (ticks/s) -host_mem_usage 618508 # Number of bytes of host memory used -host_seconds 905.69 # Real time elapsed on the host -sim_insts 120124543 # Number of instructions simulated -sim_ops 145720076 # Number of ops (including micro ops) simulated +host_inst_rate 93135 # Simulator instruction rate (inst/s) +host_op_rate 112984 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2190118612 # Simulator tick rate (ticks/s) +host_mem_usage 627176 # Number of bytes of host memory used +host_seconds 1290.39 # Real time elapsed on the host +sim_insts 120180681 # Number of instructions simulated +sim_ops 145794019 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 1664 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 1920 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1303616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1321960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8513856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 181024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 635732 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 529024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1301824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1315176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8404800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 186528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 599252 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 416192 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12488540 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1303616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 181024 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1484640 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8962368 # Number of bytes written to this memory +system.physmem.bytes_read::total 12227420 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1301824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 186528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1488352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8794944 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8979932 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 26 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8812508 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 30 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 22616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21176 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 133029 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2896 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9954 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 8266 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 22588 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21070 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 131325 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2982 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9384 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6503 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 197989 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 140037 # Number of write requests responded to by this memory +system.physmem.num_reads::total 193909 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 137421 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 144428 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 589 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 141812 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 679 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 461302 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 467794 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3012744 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 136 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 64058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 224962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 187202 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 460641 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 465366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2973981 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 66002 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 212041 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 147267 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4419240 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 461302 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 64058 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 525360 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3171456 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4326589 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 460641 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 66002 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 526643 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3112031 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6201 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3177671 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3171456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 589 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3118245 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3112031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 679 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 461302 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 473995 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3012744 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 136 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 64058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 224977 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 187202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 460641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 471567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2973981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 66002 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 212055 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 147267 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7596911 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 197990 # Number of read requests accepted -system.physmem.writeReqs 144428 # Number of write requests accepted -system.physmem.readBursts 197990 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 144428 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12662400 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8960 # Total number of bytes read from write queue -system.physmem.bytesWritten 8992448 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12488604 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8979932 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 140 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 7444834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 193910 # Number of read requests accepted +system.physmem.writeReqs 141812 # Number of write requests accepted +system.physmem.readBursts 193910 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 141812 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12399936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10304 # Total number of bytes read from write queue +system.physmem.bytesWritten 8824960 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12227484 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8812508 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12407 # Per bank write bursts -system.physmem.perBankRdBursts::1 12295 # Per bank write bursts -system.physmem.perBankRdBursts::2 12935 # Per bank write bursts -system.physmem.perBankRdBursts::3 12653 # Per bank write bursts -system.physmem.perBankRdBursts::4 14543 # Per bank write bursts -system.physmem.perBankRdBursts::5 12106 # Per bank write bursts -system.physmem.perBankRdBursts::6 12653 # Per bank write bursts -system.physmem.perBankRdBursts::7 12509 # Per bank write bursts -system.physmem.perBankRdBursts::8 12223 # Per bank write bursts -system.physmem.perBankRdBursts::9 12064 # Per bank write bursts -system.physmem.perBankRdBursts::10 11718 # Per bank write bursts -system.physmem.perBankRdBursts::11 11008 # Per bank write bursts -system.physmem.perBankRdBursts::12 11914 # Per bank write bursts -system.physmem.perBankRdBursts::13 13060 # Per bank write bursts -system.physmem.perBankRdBursts::14 12107 # Per bank write bursts -system.physmem.perBankRdBursts::15 11655 # Per bank write bursts -system.physmem.perBankWrBursts::0 9105 # Per bank write bursts -system.physmem.perBankWrBursts::1 9127 # Per bank write bursts -system.physmem.perBankWrBursts::2 9615 # Per bank write bursts -system.physmem.perBankWrBursts::3 9150 # Per bank write bursts -system.physmem.perBankWrBursts::4 8481 # Per bank write bursts -system.physmem.perBankWrBursts::5 8750 # Per bank write bursts -system.physmem.perBankWrBursts::6 8993 # Per bank write bursts -system.physmem.perBankWrBursts::7 8806 # Per bank write bursts -system.physmem.perBankWrBursts::8 8720 # Per bank write bursts -system.physmem.perBankWrBursts::9 8569 # Per bank write bursts -system.physmem.perBankWrBursts::10 8518 # Per bank write bursts -system.physmem.perBankWrBursts::11 8119 # Per bank write bursts -system.physmem.perBankWrBursts::12 8743 # Per bank write bursts -system.physmem.perBankWrBursts::13 9182 # Per bank write bursts -system.physmem.perBankWrBursts::14 8573 # Per bank write bursts -system.physmem.perBankWrBursts::15 8056 # Per bank write bursts +system.physmem.perBankRdBursts::0 12140 # Per bank write bursts +system.physmem.perBankRdBursts::1 12135 # Per bank write bursts +system.physmem.perBankRdBursts::2 12398 # Per bank write bursts +system.physmem.perBankRdBursts::3 12886 # Per bank write bursts +system.physmem.perBankRdBursts::4 14558 # Per bank write bursts +system.physmem.perBankRdBursts::5 12353 # Per bank write bursts +system.physmem.perBankRdBursts::6 12494 # Per bank write bursts +system.physmem.perBankRdBursts::7 12590 # Per bank write bursts +system.physmem.perBankRdBursts::8 12207 # Per bank write bursts +system.physmem.perBankRdBursts::9 12490 # Per bank write bursts +system.physmem.perBankRdBursts::10 11644 # Per bank write bursts +system.physmem.perBankRdBursts::11 10772 # Per bank write bursts +system.physmem.perBankRdBursts::12 11273 # Per bank write bursts +system.physmem.perBankRdBursts::13 11534 # Per bank write bursts +system.physmem.perBankRdBursts::14 11359 # Per bank write bursts +system.physmem.perBankRdBursts::15 10916 # Per bank write bursts +system.physmem.perBankWrBursts::0 8885 # Per bank write bursts +system.physmem.perBankWrBursts::1 8987 # Per bank write bursts +system.physmem.perBankWrBursts::2 9257 # Per bank write bursts +system.physmem.perBankWrBursts::3 9509 # Per bank write bursts +system.physmem.perBankWrBursts::4 8433 # Per bank write bursts +system.physmem.perBankWrBursts::5 8902 # Per bank write bursts +system.physmem.perBankWrBursts::6 9078 # Per bank write bursts +system.physmem.perBankWrBursts::7 8908 # Per bank write bursts +system.physmem.perBankWrBursts::8 8674 # Per bank write bursts +system.physmem.perBankWrBursts::9 9007 # Per bank write bursts +system.physmem.perBankWrBursts::10 8474 # Per bank write bursts +system.physmem.perBankWrBursts::11 8031 # Per bank write bursts +system.physmem.perBankWrBursts::12 8318 # Per bank write bursts +system.physmem.perBankWrBursts::13 8000 # Per bank write bursts +system.physmem.perBankWrBursts::14 7983 # Per bank write bursts +system.physmem.perBankWrBursts::15 7444 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 6 # Number of times write queue was full causing retry -system.physmem.totGap 2825947136000 # Total gap between requests +system.physmem.numWrRetry 9 # Number of times write queue was full causing retry +system.physmem.totGap 2826110796000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 551 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 3086 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 194325 # Read request sizes (log2) +system.physmem.readPktSize::6 190245 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 140037 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 60161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 72217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8715 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7515 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5382 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4740 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 989 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 744 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 304 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 137421 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 59620 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 70390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15526 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12745 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8439 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6358 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4584 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1421 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 930 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 679 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 302 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -189,165 +189,162 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 26 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 92378 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 234.414947 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.500025 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 299.048436 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50794 54.98% 54.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17715 19.18% 74.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5941 6.43% 80.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3366 3.64% 84.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2816 3.05% 87.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1529 1.66% 88.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 925 1.00% 89.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 990 1.07% 91.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8302 8.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 92378 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6992 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.296339 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 556.591514 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6990 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 19 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 84734 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 250.487785 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 142.325533 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 306.970890 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 42837 50.55% 50.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17738 20.93% 71.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6168 7.28% 78.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3519 4.15% 82.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2713 3.20% 86.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1549 1.83% 87.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 945 1.12% 89.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1056 1.25% 90.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8209 9.69% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 84734 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6846 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.300175 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 562.386287 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6844 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6992 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6992 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.095395 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.609227 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.295574 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5854 83.72% 83.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 392 5.61% 89.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 80 1.14% 90.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 62 0.89% 91.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 277 3.96% 95.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 20 0.29% 95.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 15 0.21% 95.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 24 0.34% 96.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 25 0.36% 96.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 12 0.17% 96.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 9 0.13% 96.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 14 0.20% 97.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 142 2.03% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.06% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 10 0.14% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 7 0.10% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 6 0.09% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.03% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.04% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 3 0.04% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.01% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.20% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.03% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.04% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6992 # Writes before turning the bus around for reads -system.physmem.totQLat 6748582846 # Total ticks spent queuing -system.physmem.totMemAccLat 10458270346 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 989250000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34109.59 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6846 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6846 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.141689 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.636499 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.164291 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5708 83.38% 83.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 378 5.52% 88.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 91 1.33% 90.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 47 0.69% 90.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 276 4.03% 94.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 33 0.48% 95.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 21 0.31% 95.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 23 0.34% 96.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 19 0.28% 96.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 10 0.15% 96.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.03% 96.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 9 0.13% 96.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 166 2.42% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 9 0.13% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 11 0.16% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 6 0.09% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.04% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.03% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 3 0.04% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.03% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 3 0.04% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 7 0.10% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.04% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6846 # Writes before turning the bus around for reads +system.physmem.totQLat 6600075879 # Total ticks spent queuing +system.physmem.totMemAccLat 10232869629 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 968745000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34065.08 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 52859.59 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.18 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.42 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.18 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 52815.08 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.39 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.33 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing -system.physmem.readRowHits 165284 # Number of row buffer hits during reads -system.physmem.writeRowHits 80694 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.42 # Row buffer hit rate for writes -system.physmem.avgGap 8252916.42 # Average gap between requests -system.physmem.pageHitRate 72.69 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 361058040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 197005875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 796387800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 466734960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184576766400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 79734690540 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1625622381750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1891755025365 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.424618 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2704272847388 # Time in different power states -system.physmem_0.memoryStateTime::REF 94364400000 # Time in different power states +system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.81 # Average write queue length when enqueuing +system.physmem.readRowHits 161373 # Number of row buffer hits during reads +system.physmem.writeRowHits 85531 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.29 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.02 # Row buffer hit rate for writes +system.physmem.avgGap 8418008.94 # Average gap between requests +system.physmem.pageHitRate 74.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 338612400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 184758750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 792121200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 466294320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184587446160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 79311033765 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1626092117250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1891772383845 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.392029 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2705053539598 # Time in different power states +system.physmem_0.memoryStateTime::REF 94369860000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 27304587612 # Time in different power states +system.physmem_0.memoryStateTime::ACT 26681946652 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 337319640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 184053375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 746834400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 443750400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184576766400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 79554512970 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1625780432250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1891623669435 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.378136 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2704538486760 # Time in different power states -system.physmem_1.memoryStateTime::REF 94364400000 # Time in different power states +system.physmem_1.actEnergy 301976640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 164769000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 719113200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 427232880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184587446160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 78534447525 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1626773333250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1891508318655 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.298592 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2706191706230 # Time in different power states +system.physmem_1.memoryStateTime::REF 94369860000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 27044516240 # Time in different power states +system.physmem_1.memoryStateTime::ACT 25549496770 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory @@ -366,30 +363,30 @@ system.realview.nvmem.bw_inst_read::total 102 # I system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 53058502 # Number of BP lookups -system.cpu0.branchPred.condPredicted 24374377 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 933450 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 32093175 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 13944864 # Number of BTB hits +system.cpu0.branchPred.lookups 23913557 # Number of BP lookups +system.cpu0.branchPred.condPredicted 15655751 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 926443 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 14584665 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 9536401 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 43.451182 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 15470259 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 33206 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 10120086 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 9964746 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 155340 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 48572 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 65.386493 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3854213 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 33180 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 1360238 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 1204672 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 155566 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 48773 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -419,84 +416,84 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 67164 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 67164 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25323 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 19031 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 22810 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 44354 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 458.594490 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 2953.911408 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 43233 97.47% 97.47% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 862 1.94% 99.42% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 108 0.24% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 108 0.24% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-40959 9 0.02% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 18 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-65535 14 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 65918 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 65918 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25327 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18922 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 21669 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 44249 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 506.926710 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 3129.335275 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-8191 43005 97.19% 97.19% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-16383 929 2.10% 99.29% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-24575 148 0.33% 99.62% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-32767 108 0.24% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-40959 23 0.05% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::40960-49151 20 0.05% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::57344-65535 13 0.03% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 44354 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 17047 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 11038.716490 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9658.702439 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6683.029230 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 15750 92.39% 92.39% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1185 6.95% 99.34% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 75 0.44% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 14 0.08% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.03% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 14 0.08% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::114688-131071 2 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-147455 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkWaitTime::total 44249 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 16055 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 11307.848022 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9898.999015 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6813.334576 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 14595 90.91% 90.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1294 8.06% 98.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 134 0.83% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 9 0.06% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 17 0.11% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::114688-131071 1 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 17047 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 85757506152 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.515718 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.512261 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 85699757152 99.93% 99.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 40650000 0.05% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 7189500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 4730000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 1448500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 1006500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 1064000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 1646000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 14500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 85757506152 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5272 77.42% 77.42% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1538 22.58% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6810 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67164 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 16055 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 85920956152 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.541941 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.508329 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 85862493152 99.93% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 40323000 0.05% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 8212500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 5190500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 2626000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 844500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 886000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 336500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 44000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 85920956152 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5102 78.63% 78.63% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1387 21.37% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6489 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65918 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67164 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6810 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65918 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6489 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6810 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 73974 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6489 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 72407 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 23645826 # DTB read hits -system.cpu0.dtb.read_misses 56383 # DTB read misses -system.cpu0.dtb.write_hits 17571331 # DTB write hits -system.cpu0.dtb.write_misses 10781 # DTB write misses +system.cpu0.dtb.read_hits 17729387 # DTB read hits +system.cpu0.dtb.read_misses 55806 # DTB read misses +system.cpu0.dtb.write_hits 14606301 # DTB write hits +system.cpu0.dtb.write_misses 10112 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3487 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 213 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2243 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3431 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 353 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2188 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 818 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 23702209 # DTB read accesses -system.cpu0.dtb.write_accesses 17582112 # DTB write accesses +system.cpu0.dtb.perms_faults 939 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17785193 # DTB read accesses +system.cpu0.dtb.write_accesses 14616413 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 41217157 # DTB hits -system.cpu0.dtb.misses 67164 # DTB misses -system.cpu0.dtb.accesses 41284321 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 32335688 # DTB hits +system.cpu0.dtb.misses 65918 # DTB misses +system.cpu0.dtb.accesses 32401606 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -526,59 +523,58 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 10883 # Table walker walks requested -system.cpu0.itb.walker.walksShort 10883 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3898 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5925 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 1060 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 9823 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 449.709865 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 2327.234590 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-4095 9434 96.04% 96.04% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::4096-8191 184 1.87% 97.91% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-12287 123 1.25% 99.17% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::12288-16383 44 0.45% 99.61% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-20479 7 0.07% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::20480-24575 18 0.18% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::28672-32767 4 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-36863 3 0.03% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 9823 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 3631 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 11923.299367 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11119.549027 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 4771.165368 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 614 16.91% 16.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 2801 77.14% 94.05% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 142 3.91% 97.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 43 1.18% 99.15% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 27 0.74% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 3 0.08% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 10845 # Table walker walks requested +system.cpu0.itb.walker.walksShort 10845 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3752 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6021 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 1072 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 9773 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 438.606364 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 2276.348067 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-4095 9409 96.28% 96.28% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::4096-8191 161 1.65% 97.92% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-12287 121 1.24% 99.16% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::12288-16383 47 0.48% 99.64% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-20479 7 0.07% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::20480-24575 16 0.16% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-28671 6 0.06% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-36863 4 0.04% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::36864-40959 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 9773 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 3657 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12272.627837 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11484.483595 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 4878.254960 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 514 14.06% 14.06% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 2884 78.86% 92.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 170 4.65% 97.57% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 55 1.50% 99.07% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 31 0.85% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.03% 99.97% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 3631 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 21332036712 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.795904 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.403169 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 4354826000 20.41% 20.41% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 16976239212 79.58% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 901500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 70000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 21332036712 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2243 87.24% 87.24% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 328 12.76% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2571 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 3657 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 21495635712 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.820169 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.384194 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 3866725500 17.99% 17.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 17627832712 82.01% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 1008500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 69000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 21495635712 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2254 87.20% 87.20% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 331 12.80% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2585 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10883 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10883 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10845 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10845 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2571 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2571 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 13454 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 72708520 # ITB inst hits -system.cpu0.itb.inst_misses 10883 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2585 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2585 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 13430 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 37503849 # ITB inst hits +system.cpu0.itb.inst_misses 10845 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -587,1047 +583,1055 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2280 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2291 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1927 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1944 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 72719403 # ITB inst accesses -system.cpu0.itb.hits 72708520 # DTB hits -system.cpu0.itb.misses 10883 # DTB misses -system.cpu0.itb.accesses 72719403 # DTB accesses -system.cpu0.numPwrStateTransitions 3678 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1839 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1481668762.034258 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23877600166.586662 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1061 57.69% 57.69% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 773 42.03% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 37514694 # ITB inst accesses +system.cpu0.itb.hits 37503849 # DTB hits +system.cpu0.itb.misses 10845 # DTB misses +system.cpu0.itb.accesses 37514694 # DTB accesses +system.cpu0.numPwrStateTransitions 3712 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1856 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1487215700.959052 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23895599673.728432 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1080 58.19% 58.19% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 769 41.43% 99.62% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 2 0.11% 99.73% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499971949600 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1839 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 101158552619 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2724788853381 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 202318013 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 499971395296 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1856 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 65838742020 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2760272340980 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 131678547 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 20370009 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 195788924 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 53058502 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 39379869 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 174489676 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 5690920 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 148682 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 56911 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 412776 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 413906 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 90774 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 72708226 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 258373 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 5359 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 198828194 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.203611 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.307839 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 19262499 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 112028029 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 23913557 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 14595286 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 106047706 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2739238 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 149116 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 57008 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 423158 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 407524 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 94244 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 37503537 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 259263 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 5228 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 127810874 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.056272 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.258048 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 93974548 47.26% 47.26% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 30342793 15.26% 62.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 14563641 7.32% 69.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 59947212 30.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 65678610 51.39% 51.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 21331326 16.69% 68.08% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 8731054 6.83% 74.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 32069884 25.09% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 198828194 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.262253 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.967729 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 25600367 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 106949118 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 58799478 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 4963264 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2515967 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 3058039 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 333585 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 154217934 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 3811468 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 2515967 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 34209280 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12450122 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 83570932 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 55016631 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 11065262 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 137539344 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 1033397 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1452682 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 164882 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 58749 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 6858829 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 141646141 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 634543216 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 152633070 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 9368 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 130461493 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 11184637 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 2697680 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 2556046 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 22573700 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 24576087 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 19059052 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1700091 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2321608 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 134608055 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1714170 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 132746710 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 453040 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10578491 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 21717645 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 121089 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 198828194 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.667645 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 0.963186 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 127810874 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.181606 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.850769 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 19867897 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 60850603 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 41086114 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 4967748 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1038512 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 3035925 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 335186 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 110135169 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 3776324 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1038512 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 25520251 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12577304 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 37369361 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 40264186 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 11041260 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 105172145 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 1006076 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1476626 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 165177 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 58768 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 6832387 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 109365921 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 480109573 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 120259513 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 9447 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 98266494 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 11099416 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1228555 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1085594 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12372656 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 18663457 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 16076197 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1697816 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2228906 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 102290291 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1693186 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 100457201 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 451571 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9045594 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 21384310 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 120136 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 127810874 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.785983 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.028831 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 122140771 61.43% 61.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 33611714 16.90% 78.34% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 31218891 15.70% 94.04% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 10730115 5.40% 99.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1126646 0.57% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 57 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 71664386 56.07% 56.07% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 23315575 18.24% 74.31% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 22454220 17.57% 91.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 9273638 7.26% 99.14% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1103003 0.86% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 52 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 198828194 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 127810874 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 10786366 43.89% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 65 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5629308 22.91% 66.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 8160859 33.21% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 9324082 40.55% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 74 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5582954 24.28% 64.83% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 8086742 35.17% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 89668905 67.55% 67.55% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 111084 0.08% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 8099 0.01% 67.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.64% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 24336393 18.33% 85.97% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 18619956 14.03% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 66279940 65.98% 65.98% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 93468 0.09% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 8018 0.01% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 18419781 18.34% 84.42% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 15653721 15.58% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 132746710 # Type of FU issued -system.cpu0.iq.rate 0.656129 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 24576598 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.185139 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 489318685 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 146908772 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 129217545 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 32566 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 11248 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 9717 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 157299800 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 21235 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 365614 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 100457201 # Type of FU issued +system.cpu0.iq.rate 0.762897 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 22993852 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.228892 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 352138149 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 113036952 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 98428366 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 32549 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 11294 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 9716 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 123427553 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 21227 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 365954 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1914996 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2485 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 19372 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 896753 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1901526 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2478 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 19250 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 882682 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 121022 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 362352 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 110051 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 360569 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2515967 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1594217 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 188418 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 136474692 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 1038512 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1592668 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 210705 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 104136429 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 24576087 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 19059052 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 876204 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 28441 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 136041 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 19372 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 261507 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 398935 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 660442 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 131715074 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 23894149 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 964599 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 18663457 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 16076197 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 876152 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 28505 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 158159 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 19250 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 253073 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 398879 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 651952 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 99436169 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 17977378 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 955231 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 152467 # number of nop insts executed -system.cpu0.iew.exec_refs 42353114 # number of memory reference insts executed -system.cpu0.iew.exec_branches 25555008 # Number of branches executed -system.cpu0.iew.exec_stores 18458965 # Number of stores executed -system.cpu0.iew.exec_rate 0.651030 # Inst execution rate -system.cpu0.iew.wb_sent 131158694 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 129227262 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 65946343 # num instructions producing a value -system.cpu0.iew.wb_consumers 106655009 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.638733 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.618315 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 9548145 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1593081 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 603957 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 195669167 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.643258 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.340979 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 152952 # number of nop insts executed +system.cpu0.iew.exec_refs 33471315 # number of memory reference insts executed +system.cpu0.iew.exec_branches 16838084 # Number of branches executed +system.cpu0.iew.exec_stores 15493937 # Number of stores executed +system.cpu0.iew.exec_rate 0.755143 # Inst execution rate +system.cpu0.iew.wb_sent 98890175 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 98438082 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 51269761 # num instructions producing a value +system.cpu0.iew.wb_consumers 84681895 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.747564 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.605439 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 8044326 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1573050 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 595336 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 126126769 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.753686 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.472161 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 135298586 69.15% 69.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 33412613 17.08% 86.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 12639367 6.46% 92.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3246710 1.66% 94.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 4896676 2.50% 96.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 2794942 1.43% 98.27% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1306268 0.67% 98.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 556762 0.28% 99.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1517243 0.78% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 81783872 64.84% 64.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 24707932 19.59% 84.43% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 8259395 6.55% 90.98% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3211630 2.55% 93.53% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 3438301 2.73% 96.25% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 1493917 1.18% 97.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1163537 0.92% 98.36% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 551177 0.44% 98.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1517008 1.20% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 195669167 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 103932879 # Number of instructions committed -system.cpu0.commit.committedOps 125865777 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 126126769 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 79016795 # Number of instructions committed +system.cpu0.commit.committedOps 95059926 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 40823389 # Number of memory references committed -system.cpu0.commit.loads 22661090 # Number of loads committed -system.cpu0.commit.membars 647148 # Number of memory barriers committed -system.cpu0.commit.branches 24954311 # Number of branches committed +system.cpu0.commit.refs 31955445 # Number of memory references committed +system.cpu0.commit.loads 16761930 # Number of loads committed +system.cpu0.commit.membars 647782 # Number of memory barriers committed +system.cpu0.commit.branches 16235143 # Number of branches committed system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 109885490 # Number of committed integer instructions. -system.cpu0.commit.function_calls 4835541 # Number of function calls committed. +system.cpu0.commit.int_insts 81982870 # Number of committed integer instructions. +system.cpu0.commit.function_calls 1931434 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 84925464 67.47% 67.47% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 108825 0.09% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 8099 0.01% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 22661090 18.00% 85.57% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 18162299 14.43% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 63005341 66.28% 66.28% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 91123 0.10% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 8017 0.01% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 16761930 17.63% 84.02% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 15193515 15.98% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 125865777 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1517243 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 306278084 # The number of ROB reads -system.cpu0.rob.rob_writes 273977566 # The number of ROB writes -system.cpu0.timesIdled 123981 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 3489819 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5449576943 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 103810827 # Number of Instructions Simulated -system.cpu0.committedOps 125743725 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.948911 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.948911 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.513107 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.513107 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 142709258 # number of integer regfile reads -system.cpu0.int_regfile_writes 81672792 # number of integer regfile writes +system.cpu0.commit.op_class_0::total 95059926 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1517008 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 223519030 # The number of ROB reads +system.cpu0.rob.rob_writes 207883288 # The number of ROB writes +system.cpu0.timesIdled 136700 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 3867673 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5520543918 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 78894743 # Number of Instructions Simulated +system.cpu0.committedOps 94937874 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.669041 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.669041 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.599147 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.599147 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 110427579 # number of integer regfile reads +system.cpu0.int_regfile_writes 59611828 # number of integer regfile writes system.cpu0.fp_regfile_reads 8185 # number of floating regfile reads system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes -system.cpu0.cc_regfile_reads 464864695 # number of cc regfile reads -system.cpu0.cc_regfile_writes 49723023 # number of cc regfile writes -system.cpu0.misc_regfile_reads 392114938 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1224736 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 709879 # number of replacements -system.cpu0.dcache.tags.tagsinuse 499.426037 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 37661762 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 710391 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 53.015539 # Average number of references to valid blocks. +system.cpu0.cc_regfile_reads 350340790 # number of cc regfile reads +system.cpu0.cc_regfile_writes 41062621 # number of cc regfile writes +system.cpu0.misc_regfile_reads 252371624 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1225237 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 711089 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.347987 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 28802334 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 711601 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 40.475398 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 278078500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.426037 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.975441 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.975441 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.347987 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.965523 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.965523 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 81162963 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 81162963 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 21452365 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 21452365 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 14987011 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 14987011 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 308699 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 308699 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363086 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 363086 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361018 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361018 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 36439376 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 36439376 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 36748075 # number of overall hits -system.cpu0.dcache.overall_hits::total 36748075 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 646473 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 646473 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1887751 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1887751 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147620 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 147620 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25081 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 25081 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20154 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20154 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2534224 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2534224 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2681844 # number of overall misses -system.cpu0.dcache.overall_misses::total 2681844 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8640238000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 8640238000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29904279351 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 29904279351 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 399794500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 399794500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 485945500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 485945500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 390500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 390500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 38544517351 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 38544517351 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 38544517351 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 38544517351 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 22098838 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 22098838 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 16874762 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 16874762 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456319 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 456319 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388167 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 388167 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381172 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381172 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 38973600 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 38973600 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 39429919 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 39429919 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029254 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.029254 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.111868 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.111868 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323502 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323502 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064614 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064614 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052874 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052874 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.065024 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.065024 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.068015 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.068015 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13365.195453 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13365.195453 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15841.220241 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15841.220241 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15940.133966 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15940.133966 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24111.615560 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24111.615560 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 63463455 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63463455 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 15558905 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 15558905 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 12019658 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 12019658 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 308619 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 308619 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363044 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 363044 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361281 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361281 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 27578563 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 27578563 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 27887182 # number of overall hits +system.cpu0.dcache.overall_hits::total 27887182 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 648058 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 648058 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1895809 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1895809 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147818 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 147818 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25317 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 25317 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20174 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20174 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2543867 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2543867 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2691685 # number of overall misses +system.cpu0.dcache.overall_misses::total 2691685 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8928091500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 8928091500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29690163364 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 29690163364 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 404195500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 404195500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 475433000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 475433000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 570500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 570500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 38618254864 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 38618254864 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 38618254864 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 38618254864 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16206963 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16206963 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 13915467 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 13915467 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456437 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 456437 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388361 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 388361 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381455 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381455 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 30122430 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 30122430 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 30578867 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 30578867 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039986 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.039986 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136238 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.136238 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323852 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323852 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065189 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065189 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052887 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052887 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084451 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.084451 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088024 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.088024 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13776.685883 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13776.685883 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15660.946522 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15660.946522 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15965.378994 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15965.378994 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23566.620402 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23566.620402 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15209.593687 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15209.593687 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14372.393529 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14372.393529 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 691 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 4275244 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 43 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 201901 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.069767 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 21.174952 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 709879 # number of writebacks -system.cpu0.dcache.writebacks::total 709879 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 258972 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 258972 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1563802 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1563802 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18565 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18565 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1822774 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1822774 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1822774 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1822774 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 387501 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 387501 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323949 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 323949 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101413 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 101413 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6516 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6516 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20154 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20154 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 711450 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 711450 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 812863 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 812863 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31772 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31772 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28451 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28451 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60223 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60223 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4575351000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4575351000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6134433385 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6134433385 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1666291000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1666291000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 103051000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 103051000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 465800500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 465800500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 381500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 381500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10709784385 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10709784385 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12376075385 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 12376075385 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6621057500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6621057500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6621057500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6621057500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017535 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017535 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019197 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019197 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222241 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222241 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016787 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016787 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052874 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052874 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018255 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.018255 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020615 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.020615 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11807.326949 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11807.326949 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18936.417106 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18936.417106 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16430.743593 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16430.743593 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15815.070595 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15815.070595 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23112.062122 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23112.062122 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15180.925286 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15180.925286 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14347.241547 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14347.241547 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1034 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 4271446 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 202383 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.541667 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 21.105755 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 711089 # number of writebacks +system.cpu0.dcache.writebacks::total 711089 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 260039 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 260039 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1570278 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1570278 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18696 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18696 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1830317 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1830317 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1830317 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1830317 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 388019 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 388019 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325531 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 325531 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101607 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 101607 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6621 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6621 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20174 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20174 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 713550 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 713550 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 815157 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 815157 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20336 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20336 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19032 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19032 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39368 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39368 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4833813000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4833813000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5968230399 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5968230399 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1672759500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1672759500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104692000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104692000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 455274000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 455274000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 555500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 555500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10802043399 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10802043399 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12474802899 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 12474802899 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4534406000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4534406000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4534406000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4534406000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.023941 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.023941 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023393 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023393 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222609 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222609 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017049 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017049 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052887 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052887 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023688 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023688 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026658 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026658 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12457.670887 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12457.670887 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18333.831184 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18333.831184 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16463.034043 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16463.034043 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15812.112974 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15812.112974 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22567.363934 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22567.363934 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15053.460377 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15053.460377 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15225.290590 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15225.290590 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208392.845902 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208392.845902 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109942.339306 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109942.339306 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1252995 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.762307 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 71397425 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1253507 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 56.958138 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7880422000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.762307 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999536 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999536 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 146662859 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 146662859 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 71397425 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 71397425 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 71397425 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 71397425 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 71397425 # number of overall hits -system.cpu0.icache.overall_hits::total 71397425 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1307231 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1307231 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1307231 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1307231 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1307231 # number of overall misses -system.cpu0.icache.overall_misses::total 1307231 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13217921463 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13217921463 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13217921463 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13217921463 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13217921463 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13217921463 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 72704656 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 72704656 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 72704656 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 72704656 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 72704656 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 72704656 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017980 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.017980 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017980 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.017980 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017980 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.017980 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10111.389236 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10111.389236 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10111.389236 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10111.389236 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10111.389236 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10111.389236 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1578280 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 443 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 112202 # number of cycles access was blocked +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15138.453366 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15138.453366 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15303.558577 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15303.558577 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222974.331235 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222974.331235 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115179.993904 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115179.993904 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1254577 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.762789 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 36189840 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1255088 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 28.834504 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6511134000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.762789 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999537 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999537 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 130 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 76255085 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 76255085 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 36189843 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 36189843 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 36189843 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 36189843 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 36189843 # number of overall hits +system.cpu0.icache.overall_hits::total 36189843 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1310126 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1310126 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1310126 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1310126 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1310126 # number of overall misses +system.cpu0.icache.overall_misses::total 1310126 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13674177457 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13674177457 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13674177457 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13674177457 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13674177457 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13674177457 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 37499969 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 37499969 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 37499969 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 37499969 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 37499969 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 37499969 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034937 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.034937 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034937 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.034937 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034937 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.034937 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10437.299509 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10437.299509 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10437.299509 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10437.299509 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10437.299509 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10437.299509 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1615389 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 855 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 113956 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.066416 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 44.300000 # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1252995 # number of writebacks -system.cpu0.icache.writebacks::total 1252995 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53683 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 53683 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 53683 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 53683 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 53683 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 53683 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1253548 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1253548 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1253548 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1253548 # 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number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12423139434 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 269145498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 269145498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 269145498 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 269145498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017242 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017242 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017242 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.017242 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017242 # 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average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89625.540460 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89625.540460 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1837427 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1839978 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 2305 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1846782 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1849282 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 2270 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 236878 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 277234 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16111.552153 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3276769 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 293338 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 11.170626 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 236718 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 273792 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15633.615902 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1886952 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 289401 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.520199 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14693.899751 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.282247 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.429995 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1405.940159 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.896844 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000689 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000026 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.085812 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.983371 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1005 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 14449.190897 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.342760 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.746834 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1171.335411 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.881909 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000753 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000046 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.071493 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.954200 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 271 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15089 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 38 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 280 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 408 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 279 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 460 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4705 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7019 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2801 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.061340 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15328 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 66 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 120 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 81 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 311 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1438 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7629 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4500 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1450 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.016541 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.920959 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 66263541 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 66263541 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55477 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13130 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 68607 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 482403 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 482403 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 1449230 # 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number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007514 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.011370 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.008254 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4371369500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4617990500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008884 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013501 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009775 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999928 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999928 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.155984 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.155984 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042593 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042593 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.193770 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.193770 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007514 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.011370 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042593 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.180467 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.091953 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007514 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.011370 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042593 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.180467 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159667 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159667 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056741 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056741 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.216654 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.216654 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008884 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.013501 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056741 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.196574 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.106420 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008884 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.013501 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056741 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.196574 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.215216 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22405.952381 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17605.960265 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21136.602452 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60094.658138 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60094.658138 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19414.471651 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19414.471651 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15555.078648 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15555.078648 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 311500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 311500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 42865.667731 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 42865.667731 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 46298.252514 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 46298.252514 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24357.983048 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24357.983048 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22405.952381 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17605.960265 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 46298.252514 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29989.601735 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34500.278749 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22405.952381 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17605.960265 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 46298.252514 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29989.601735 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60094.658138 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49159.199531 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.233472 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22180.722892 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17444.751381 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20918.262150 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 57534.711912 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 57534.711912 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17299.214716 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17299.214716 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15017.203768 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15017.203768 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 110499.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 110499.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40813.341067 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40813.341067 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 40940.561110 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 40940.561110 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24257.326226 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24257.326226 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22180.722892 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17444.751381 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 40940.561110 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28995.783226 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32794.577145 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22180.722892 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17444.751381 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 40940.561110 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28995.783226 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 57534.711912 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46257.816810 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200383.954425 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 190171.675054 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 214957.194138 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 197865.825442 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105717.068230 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104596.526745 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 4076758 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2058809 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31269 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 324106 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 319070 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5036 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 113929 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1910818 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28451 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28451 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 712670 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1480466 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 204485 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 327834 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 86644 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42628 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 112569 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 27 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 35 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 287578 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284142 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1253548 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 576173 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3244 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3766063 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2610032 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29029 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119282 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6524406 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 160464624 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98586020 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53124 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 223588 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 259327356 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1029792 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 18816792 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 3154811 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.120834 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.330795 # Request fanout histogram +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111038.648141 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 108989.414930 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 4083931 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2062737 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 216422 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 214567 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1855 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 102316 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1901889 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19032 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19032 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 714747 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1482534 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 90142 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 335134 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 87548 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42677 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 113494 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 8 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 288350 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 285091 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1255148 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 586492 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3253 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3770830 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2574893 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29200 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119227 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6494150 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 160667312 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98708808 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53624 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 224224 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 259653968 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 933771 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 18925704 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 3041721 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.089004 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.286883 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2778640 88.08% 88.08% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 371135 11.76% 99.84% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 5036 0.16% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2772852 91.16% 91.16% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 267014 8.78% 99.94% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 1855 0.06% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3154811 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 4076288994 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3041721 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 4067278494 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 113402059 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 114026414 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1883892360 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1886176090 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1231592300 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1218391120 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 15761972 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 15802982 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 63433401 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 63205426 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 4691512 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2780704 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 269312 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2468444 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1570862 # Number of BTB hits +system.cpu1.branchPred.lookups 33853439 # Number of BP lookups +system.cpu1.branchPred.condPredicted 11509465 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 280542 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 18730917 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5987349 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 63.637741 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 878870 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7026 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 249224 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 213650 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 35574 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 10610 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 31.965061 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 12496464 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7318 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 9007806 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 8970953 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 36853 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 10907 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1657,90 +1661,89 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 21486 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 21486 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8656 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5913 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 6917 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 14569 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 593.417530 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3219.344489 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-4095 13924 95.57% 95.57% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::4096-8191 194 1.33% 96.90% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-12287 239 1.64% 98.54% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::12288-16383 88 0.60% 99.15% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-20479 24 0.16% 99.31% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::20480-24575 16 0.11% 99.42% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-28671 5 0.03% 99.46% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::28672-32767 66 0.45% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-36863 2 0.01% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::36864-40959 7 0.05% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 21636 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 21636 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8665 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5933 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 7038 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 14598 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 649.780792 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3376.631612 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-4095 13908 95.27% 95.27% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::4096-8191 186 1.27% 96.55% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::8192-12287 234 1.60% 98.15% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::12288-16383 108 0.74% 98.89% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-20479 46 0.32% 99.21% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::20480-24575 30 0.21% 99.41% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-28671 8 0.05% 99.47% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::28672-32767 66 0.45% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-36863 4 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::36864-40959 4 0.03% 99.97% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 14569 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5700 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11230.789474 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9917.122912 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6183.592938 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 1944 34.11% 34.11% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 3149 55.25% 89.35% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 398 6.98% 96.33% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 155 2.72% 99.05% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 22 0.39% 99.44% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 24 0.42% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 5 0.09% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::90112-98303 1 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 14598 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5531 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11435.002712 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10101.039860 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6336.393968 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 1833 33.14% 33.14% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 3041 54.98% 88.12% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 457 8.26% 96.38% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 138 2.50% 98.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 31 0.56% 99.44% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 23 0.42% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 4 0.07% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.02% 99.98% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5700 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 72594020264 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.245062 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.433850 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 72572506264 99.97% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 16659500 0.02% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 2233500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 1798000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 337000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 155000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 183000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 133000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 15000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 72594020264 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1956 73.89% 73.89% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 691 26.11% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2647 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21486 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::total 5531 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 68460974968 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.179525 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.388721 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 68438733968 99.97% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 17027000 0.02% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 2383000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 1817500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 437500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 205000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 153500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 216500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 1000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 68460974968 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1927 75.51% 75.51% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 625 24.49% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2552 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21636 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21486 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2647 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21636 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2552 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2647 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 24133 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2552 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 24188 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4198525 # DTB read hits -system.cpu1.dtb.read_misses 18524 # DTB read misses -system.cpu1.dtb.write_hits 3495808 # DTB write hits -system.cpu1.dtb.write_misses 2962 # DTB write misses +system.cpu1.dtb.read_hits 10130487 # DTB read hits +system.cpu1.dtb.read_misses 18672 # DTB read misses +system.cpu1.dtb.write_hits 6476473 # DTB write hits +system.cpu1.dtb.write_misses 2964 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1985 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 48 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 390 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1961 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 63 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 385 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 375 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4217049 # DTB read accesses -system.cpu1.dtb.write_accesses 3498770 # DTB write accesses +system.cpu1.dtb.perms_faults 370 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10149159 # DTB read accesses +system.cpu1.dtb.write_accesses 6479437 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7694333 # DTB hits -system.cpu1.dtb.misses 21486 # DTB misses -system.cpu1.dtb.accesses 7715819 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 16606960 # DTB hits +system.cpu1.dtb.misses 21636 # DTB misses +system.cpu1.dtb.accesses 16628596 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1770,62 +1773,57 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 5992 # Table walker walks requested -system.cpu1.itb.walker.walksShort 5992 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2735 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2646 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 611 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 5381 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 357.461438 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 2249.604382 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-2047 5186 96.38% 96.38% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::2048-4095 43 0.80% 97.18% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::4096-6143 39 0.72% 97.90% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::6144-8191 21 0.39% 98.29% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-10239 21 0.39% 98.68% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::10240-12287 16 0.30% 98.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::12288-14335 17 0.32% 99.29% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::14336-16383 9 0.17% 99.46% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-18431 6 0.11% 99.57% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::18432-20479 2 0.04% 99.61% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::20480-22527 6 0.11% 99.72% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::22528-24575 3 0.06% 99.78% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-26623 4 0.07% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::26624-28671 4 0.07% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::28672-30719 2 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::30720-32767 2 0.04% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 5381 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1781 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11779.618192 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10714.112038 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6875.589868 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-16383 1655 92.93% 92.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-32767 93 5.22% 98.15% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-49151 29 1.63% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-65535 1 0.06% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-81919 1 0.06% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-147455 2 0.11% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1781 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 16739710416 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.877376 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.328141 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 2053443264 12.27% 12.27% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 14685521152 87.73% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 746000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 16739710416 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 995 85.04% 85.04% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 175 14.96% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1170 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 6064 # Table walker walks requested +system.cpu1.itb.walker.walksShort 6064 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2840 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2623 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 601 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 5463 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 343.950211 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 2166.504505 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-4095 5312 97.24% 97.24% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::4096-8191 57 1.04% 98.28% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-12287 43 0.79% 99.07% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::12288-16383 29 0.53% 99.60% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-20479 6 0.11% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::20480-24575 5 0.09% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-28671 5 0.09% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::28672-32767 5 0.09% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-36863 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 5463 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1764 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12147.108844 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11115.999882 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5636.944380 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 277 15.70% 15.70% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 1298 73.58% 89.29% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 111 6.29% 95.58% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 59 3.34% 98.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-40959 9 0.51% 99.43% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-49151 7 0.40% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-57343 2 0.11% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1764 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 16901758916 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.861276 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.345783 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 2345411264 13.88% 13.88% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 14555617152 86.12% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 730500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 16901758916 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 989 85.04% 85.04% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 174 14.96% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1163 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5992 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5992 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6064 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6064 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1170 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1170 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 7162 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 8257878 # ITB inst hits -system.cpu1.itb.inst_misses 5992 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1163 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1163 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 7227 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 43493383 # ITB inst hits +system.cpu1.itb.inst_misses 6064 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1834,1032 +1832,1023 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1134 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1129 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 574 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 581 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8263870 # ITB inst accesses -system.cpu1.itb.hits 8257878 # DTB hits -system.cpu1.itb.misses 5992 # DTB misses -system.cpu1.itb.accesses 8263870 # DTB accesses -system.cpu1.numPwrStateTransitions 5517 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2759 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1017941071.285973 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25840669198.429722 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1966 71.26% 71.26% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 787 28.52% 99.78% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.86% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 43499447 # ITB inst accesses +system.cpu1.itb.hits 43493383 # DTB hits +system.cpu1.itb.misses 6064 # DTB misses +system.cpu1.itb.accesses 43499447 # DTB accesses +system.cpu1.numPwrStateTransitions 5513 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2757 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1005805033.413856 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25768715425.209221 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1955 70.91% 70.91% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 798 28.94% 99.85% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 959984595936 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2759 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 17447990322 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2808499415678 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 34896767 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 959983620244 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2757 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 53106605878 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2773004477122 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 106214002 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 8573013 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 24834691 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4691512 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 2663382 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 24575638 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 780918 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 78787 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 29336 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 166978 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 305850 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 23292 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8256698 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 107917 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2264 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 34143353 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.885357 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.219701 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 10283907 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 108683336 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 33853439 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 27454766 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 92513470 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3739662 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 81877 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 30058 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 180666 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 303073 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 23077 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 43492215 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 108878 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2205 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 105285959 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.278787 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.339334 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 20247760 59.30% 59.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 4892921 14.33% 73.63% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1671892 4.90% 78.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 7330780 21.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 48617714 46.18% 46.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 13927599 13.23% 59.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7511266 7.13% 66.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 35229380 33.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 34143353 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.134440 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.711662 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 7142387 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 16886237 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 8753269 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1097578 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 263882 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 709919 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 129188 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 23442151 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1047211 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 263882 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 8565513 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2371212 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11834998 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8406528 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 2701220 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 22274891 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 187368 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 265665 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 37047 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 14963 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1683318 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 22278743 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 103710935 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 25664622 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 1667 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 19882725 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2396018 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 407656 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 334437 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2896541 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 4450446 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 3799896 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 626454 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 628235 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 21459278 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 560382 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 21266552 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 92050 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2043308 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 4721488 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 43321 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 34143353 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.622861 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.949388 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 105285959 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.318729 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.023249 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 13161149 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 62754723 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 26539387 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1087783 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1742917 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 736717 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 129511 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 67619846 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1094387 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1742917 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17542611 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2352209 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 57806856 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 23225004 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 2616362 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 54744976 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 213737 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 258070 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 37169 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 15433 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1611507 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 54654605 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 258629758 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 58168286 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 1683 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 52142746 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 2511859 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1875660 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1802517 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 13071586 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 10382439 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6812181 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 622946 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 790955 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 53883918 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 580977 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 53654093 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 93763 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 3608749 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 5111945 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 44050 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 105285959 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.509603 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.847754 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 21621380 63.33% 63.33% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6152293 18.02% 81.34% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4252408 12.45% 93.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 1859652 5.45% 99.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 257613 0.75% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 72150462 68.53% 68.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 16497460 15.67% 84.20% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 13036209 12.38% 96.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3323109 3.16% 99.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 278707 0.26% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 12 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 34143353 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 105285959 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 1436712 29.87% 29.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 667 0.01% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1615148 33.58% 63.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 1757949 36.54% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2901953 45.47% 45.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 671 0.01% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1666030 26.11% 71.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 1813313 28.41% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 13152288 61.84% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 28200 0.13% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 3301 0.02% 61.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.99% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 4404606 20.71% 82.70% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 3678091 17.30% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 36596131 68.21% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 45838 0.09% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 3311 0.01% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 10338451 19.27% 87.57% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6670296 12.43% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 21266552 # Type of FU issued -system.cpu1.iq.rate 0.609413 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4810476 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.226199 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 81572724 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 24071099 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 20803651 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 6259 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 2054 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 1789 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 26072828 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 4134 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 87634 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 53654093 # Type of FU issued +system.cpu1.iq.rate 0.505151 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 6381967 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.118947 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 219063644 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 58081406 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 51689844 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 6231 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 2072 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 1788 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 60031897 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 4097 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 89933 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 411414 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 595 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 10207 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 255357 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 434041 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 639 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 9872 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 275866 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 40430 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 77958 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 52151 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 77961 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 263882 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 544522 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 96828 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 22060743 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 1742917 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 520776 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 103336 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 54505946 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 4450446 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 3799896 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 297241 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 7639 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 82763 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 10207 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 34804 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 119058 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 153862 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 21034955 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 4309085 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 210133 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 10382439 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6812181 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 296650 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 7746 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 89089 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 9872 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 44543 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 120099 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 164642 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 53411917 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 10242028 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 220561 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 41083 # number of nop insts executed -system.cpu1.iew.exec_refs 7936975 # number of memory reference insts executed -system.cpu1.iew.exec_branches 3061868 # Number of branches executed -system.cpu1.iew.exec_stores 3627890 # Number of stores executed -system.cpu1.iew.exec_rate 0.602777 # Inst execution rate -system.cpu1.iew.wb_sent 20903580 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 20805440 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 10431521 # num instructions producing a value -system.cpu1.iew.wb_consumers 16355895 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.596200 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.637784 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 1829884 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 517061 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 142735 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 33733433 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.593157 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.351929 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 41051 # number of nop insts executed +system.cpu1.iew.exec_refs 16861277 # number of memory reference insts executed +system.cpu1.iew.exec_branches 11793508 # Number of branches executed +system.cpu1.iew.exec_stores 6619249 # Number of stores executed +system.cpu1.iew.exec_rate 0.502871 # Inst execution rate +system.cpu1.iew.wb_sent 53270244 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 51691632 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 25129407 # num instructions producing a value +system.cpu1.iew.wb_consumers 38339279 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.486674 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.655448 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 3369485 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 536927 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 153628 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 103395222 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.492179 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.152090 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 24180502 71.68% 71.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 5607484 16.62% 88.30% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1690092 5.01% 93.31% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 667448 1.98% 95.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 524113 1.55% 96.85% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 341983 1.01% 97.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 221163 0.66% 98.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 119335 0.35% 98.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 381313 1.13% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 77830115 75.27% 75.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 14293086 13.82% 89.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6071280 5.87% 94.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 693599 0.67% 95.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1980010 1.91% 97.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 1625143 1.57% 99.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 382099 0.37% 99.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 124911 0.12% 99.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 394979 0.38% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 33733433 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 16346571 # Number of instructions committed -system.cpu1.commit.committedOps 20009206 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 103395222 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 41318794 # Number of instructions committed +system.cpu1.commit.committedOps 50889001 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 7583571 # Number of memory references committed -system.cpu1.commit.loads 4039032 # Number of loads committed -system.cpu1.commit.membars 208429 # Number of memory barriers committed -system.cpu1.commit.branches 2907402 # Number of branches committed +system.cpu1.commit.refs 16484713 # Number of memory references committed +system.cpu1.commit.loads 9948398 # Number of loads committed +system.cpu1.commit.membars 208127 # Number of memory barriers committed +system.cpu1.commit.branches 11637916 # Number of branches committed system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 17776817 # Number of committed integer instructions. -system.cpu1.commit.function_calls 462681 # Number of function calls committed. +system.cpu1.commit.int_insts 45745086 # Number of committed integer instructions. +system.cpu1.commit.function_calls 3368055 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 12395212 61.95% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 27122 0.14% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 3301 0.02% 62.10% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 62.10% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.10% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.10% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 4039032 20.19% 82.29% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 3544539 17.71% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 34356210 67.51% 67.51% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 44767 0.09% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 3311 0.01% 67.61% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.61% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.61% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.61% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 9948398 19.55% 87.16% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 6536315 12.84% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 20009206 # Class of committed instruction -system.cpu1.commit.bw_lim_events 381313 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 54211090 # The number of ROB reads -system.cpu1.rob.rob_writes 44079362 # The number of ROB writes -system.cpu1.timesIdled 55353 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 753414 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5616440201 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 16313716 # Number of Instructions Simulated -system.cpu1.committedOps 19976351 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.139106 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.139106 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.467485 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.467485 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 23597502 # number of integer regfile reads -system.cpu1.int_regfile_writes 13487852 # number of integer regfile writes +system.cpu1.commit.op_class_0::total 50889001 # Class of committed instruction +system.cpu1.commit.bw_lim_events 394979 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 137189075 # The number of ROB reads +system.cpu1.rob.rob_writes 110398979 # The number of ROB writes +system.cpu1.timesIdled 58975 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 928043 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5545446856 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 41285938 # Number of Instructions Simulated +system.cpu1.committedOps 50856145 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.572644 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.572644 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.388705 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.388705 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 55995090 # number of integer regfile reads +system.cpu1.int_regfile_writes 35603094 # number of integer regfile writes system.cpu1.fp_regfile_reads 1401 # number of floating regfile reads system.cpu1.fp_regfile_writes 516 # number of floating regfile writes -system.cpu1.cc_regfile_reads 75515975 # number of cc regfile reads -system.cpu1.cc_regfile_writes 6821727 # number of cc regfile writes -system.cpu1.misc_regfile_reads 68877879 # number of misc regfile reads -system.cpu1.misc_regfile_writes 387520 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 189327 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.259638 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 6803525 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 189662 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 35.871840 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 103705106000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.259638 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922382 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.922382 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 335 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 318 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.654297 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 15106665 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 15106665 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 3632818 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3632818 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2917516 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2917516 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48925 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 48925 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78194 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 78194 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70603 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 70603 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 6550334 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6550334 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6599259 # number of overall hits -system.cpu1.dcache.overall_hits::total 6599259 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 216356 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 216356 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 400081 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 400081 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30281 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30281 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18627 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 18627 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23453 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23453 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 616437 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 616437 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 646718 # number of overall misses -system.cpu1.dcache.overall_misses::total 646718 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3492190500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3492190500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10142172955 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 10142172955 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 366644000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 366644000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 571781000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 571781000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1485000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1485000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 13634363455 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 13634363455 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 13634363455 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 13634363455 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3849174 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3849174 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3317597 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3317597 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79206 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 79206 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96821 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96821 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94056 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 94056 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 7166771 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 7166771 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 7245977 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7245977 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.056208 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.056208 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.120594 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.120594 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382307 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382307 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.192386 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.192386 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.249351 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.249351 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.086013 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.086013 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.089252 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.089252 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16140.945941 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16140.945941 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25350.298952 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 25350.298952 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19683.470231 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19683.470231 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24379.866115 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24379.866115 # average StoreCondReq miss latency +system.cpu1.cc_regfile_reads 190376100 # number of cc regfile reads +system.cpu1.cc_regfile_writes 15518701 # number of cc regfile writes +system.cpu1.misc_regfile_reads 209095836 # number of misc regfile reads +system.cpu1.misc_regfile_writes 386203 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 187149 # number of replacements +system.cpu1.dcache.tags.tagsinuse 469.748213 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 15687000 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 187502 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 83.663108 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 93899473000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.748213 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.917477 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.917477 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 353 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 348 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.689453 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 32860265 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 32860265 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 9540081 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 9540081 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 5893568 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 5893568 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48959 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 48959 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77987 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 77987 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70168 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 70168 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 15433649 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 15433649 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 15482608 # number of overall hits +system.cpu1.dcache.overall_hits::total 15482608 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 215586 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 215586 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 396166 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 396166 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30156 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30156 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18335 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 18335 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23429 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23429 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 611752 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 611752 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 641908 # number of overall misses +system.cpu1.dcache.overall_misses::total 641908 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3514528500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3514528500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9742278459 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 9742278459 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 360181500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 360181500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 551095500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 551095500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 166500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 166500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 13256806959 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 13256806959 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 13256806959 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 13256806959 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9755667 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9755667 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6289734 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6289734 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79115 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 79115 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96322 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 96322 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 93597 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 93597 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 16045401 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 16045401 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 16124516 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 16124516 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022099 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.022099 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.062986 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.062986 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.381167 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.381167 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.190351 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.190351 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.250318 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250318 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038126 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.038126 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039809 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.039809 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16302.211183 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16302.211183 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24591.404762 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 24591.404762 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19644.477775 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19644.477775 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23521.938623 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23521.938623 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22118.016042 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 22118.016042 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21082.393648 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 21082.393648 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 336 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1512378 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 30 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 40281 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11.200000 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 37.545692 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 189327 # number of writebacks -system.cpu1.dcache.writebacks::total 189327 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79455 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 79455 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 309049 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 309049 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13259 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13259 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 388504 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 388504 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 388504 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 388504 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 136901 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 136901 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91032 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 91032 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28913 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 28913 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5368 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5368 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23453 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23453 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 227933 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 227933 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 256846 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 256846 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3081 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3081 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2438 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2438 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5519 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5519 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1914813500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1914813500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2474458965 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2474458965 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 498834500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 498834500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 96515500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 96515500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 548354000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 548354000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1459000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1459000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4389272465 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4389272465 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4888106965 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4888106965 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 442121000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 442121000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 442121000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 442121000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035566 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035566 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027439 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027439 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.365035 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.365035 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055443 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055443 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.249351 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.249351 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031804 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031804 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035447 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035447 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13986.848160 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13986.848160 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27182.298148 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27182.298148 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17252.948501 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17252.948501 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17979.787630 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17979.787630 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23380.974715 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23380.974715 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21670.230680 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 21670.230680 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20652.191527 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20652.191527 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 350 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1431753 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 38 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 39808 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.210526 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 35.966464 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 187150 # number of writebacks +system.cpu1.dcache.writebacks::total 187150 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79090 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 79090 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306284 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 306284 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13036 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13036 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 385374 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 385374 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 385374 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 385374 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 136496 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 136496 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 89882 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 89882 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28741 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 28741 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5299 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5299 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23429 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23429 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 226378 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 226378 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 255119 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 255119 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14517 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14517 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11855 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11855 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26372 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26372 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1963325500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1963325500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2363104967 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2363104967 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 488593500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 488593500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 93065000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 93065000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 527670500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 527670500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 162500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 162500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4326430467 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4326430467 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4815023967 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4815023967 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2528366000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2528366000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2528366000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2528366000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013991 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013991 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014290 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014290 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.363281 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.363281 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055013 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055013 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.250318 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250318 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014109 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.014109 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015822 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.015822 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14383.758498 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14383.758498 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26291.192530 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26291.192530 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16999.878223 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16999.878223 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17562.747688 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17562.747688 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22522.109352 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22522.109352 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19256.853834 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19256.853834 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19031.275414 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19031.275414 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143499.188575 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143499.188575 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80108.896539 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80108.896539 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 586343 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.448153 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 7647462 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 586855 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 13.031263 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 79062638500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.448153 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975485 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.975485 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19111.532335 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19111.532335 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18873.639231 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18873.639231 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174165.874492 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174165.874492 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95873.123009 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95873.123009 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 589510 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.449637 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 42880129 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 590022 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 72.675475 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 79021423000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.449637 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975488 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975488 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 17099739 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 17099739 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 7647462 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7647462 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7647462 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7647462 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7647462 # number of overall hits -system.cpu1.icache.overall_hits::total 7647462 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 608974 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 608974 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 608974 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 608974 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 608974 # number of overall misses -system.cpu1.icache.overall_misses::total 608974 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5478938231 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5478938231 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5478938231 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5478938231 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5478938231 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5478938231 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8256436 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8256436 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8256436 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8256436 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8256436 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8256436 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073757 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.073757 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073757 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.073757 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073757 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.073757 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8996.998609 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8996.998609 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8996.998609 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8996.998609 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8996.998609 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8996.998609 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 488402 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 32 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 41185 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.858735 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 32 # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 586343 # number of writebacks -system.cpu1.icache.writebacks::total 586343 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22107 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 22107 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 22107 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 22107 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 22107 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 22107 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 586867 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 586867 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 586867 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 586867 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 586867 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 586867 # number of overall MSHR misses +system.cpu1.icache.tags.tag_accesses 87573930 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 87573930 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 42880129 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 42880129 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 42880129 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 42880129 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 42880129 # number of overall hits +system.cpu1.icache.overall_hits::total 42880129 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 611823 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 611823 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 611823 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 611823 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 611823 # number of overall misses +system.cpu1.icache.overall_misses::total 611823 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5700309356 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5700309356 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5700309356 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5700309356 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5700309356 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5700309356 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 43491952 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 43491952 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 43491952 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 43491952 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 43491952 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 43491952 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014067 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014067 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014067 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014067 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014067 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014067 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9316.925575 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9316.925575 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9316.925575 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9316.925575 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9316.925575 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9316.925575 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 502398 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 42118 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.928344 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.writebacks::writebacks 589510 # number of writebacks +system.cpu1.icache.writebacks::total 589510 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 21797 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 21797 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 21797 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 21797 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 21797 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 21797 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 590026 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 590026 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 590026 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 590026 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 590026 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 590026 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 101 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 101 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5026245111 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5026245111 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5026245111 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5026245111 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5026245111 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5026245111 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9125500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9125500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9125500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 9125500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071080 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071080 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071080 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.071080 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071080 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.071080 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8564.538662 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8564.538662 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8564.538662 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8564.538662 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8564.538662 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8564.538662 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90351.485149 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90351.485149 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90351.485149 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90351.485149 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 204963 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 205672 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 636 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5243631193 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5243631193 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5243631193 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5243631193 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5243631193 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5243631193 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8747999 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8747999 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8747999 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8747999 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013566 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013566 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013566 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.013566 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013566 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.013566 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8887.118861 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8887.118861 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8887.118861 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8887.118861 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8887.118861 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8887.118861 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86613.851485 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86613.851485 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86613.851485 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86613.851485 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 195371 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 196016 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 576 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 59720 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 51812 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15242.895875 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1332238 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 66423 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 20.056878 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 57640 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 44567 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14592.313259 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 696647 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 58721 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 11.863677 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14783.108783 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 9.856539 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.176183 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 447.754371 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.902289 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000602 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000133 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.027329 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.930353 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 977 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 32 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13602 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 14 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 835 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 128 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 439 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8705 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4458 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.059631 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001953 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.830200 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 26728427 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 26728427 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16758 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6223 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 22981 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 115160 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 115160 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 648098 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 648098 # number of WritebackClean hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27344 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 27344 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 570840 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 570840 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 101859 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 101859 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16758 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 6223 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 570840 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 129203 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 723024 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16758 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 6223 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 570840 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 129203 # number of overall hits -system.cpu1.l2cache.overall_hits::total 723024 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 453 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 249 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 702 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29938 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29938 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23451 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23451 # 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number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4210000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 11970500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1022179654 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1022179654 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 459449500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 459449500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 351583000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 351583000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 132500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 132500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1131738499 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1131738499 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 769613500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 769613500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1195688496 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1195688496 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7760500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4210000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 769613500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2327426995 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 3109010995 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7760500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4210000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 769613500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2327426995 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1022179654 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4131190649 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7990000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2412179500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2420169500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7990000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2412179500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2420169500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.027680 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.044034 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.032168 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999957 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999957 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.548313 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.548313 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027283 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.027283 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.404520 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.404520 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026320 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.038473 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.027283 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.442648 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.142055 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026320 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.038473 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.027283 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.442648 # mshr miss rate for overall accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.550959 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.550959 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.041590 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041590 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.417775 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.417775 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.027680 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.044034 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.041590 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.452812 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153839 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.027680 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.044034 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.041590 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.452812 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.174524 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15886.313466 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 15329.317269 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15688.746439 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45067.816403 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45067.816403 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16719.386733 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16719.386733 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15872.713317 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15872.713317 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1264000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1264000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34904.520758 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34904.520758 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 35242.114796 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 35242.114796 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16647.638634 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16647.638634 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15886.313466 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 15329.317269 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 35242.114796 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22644.259296 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24286.916090 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15886.313466 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 15329.317269 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 35242.114796 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22644.259296 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45067.816403 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28152.992215 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82851.485149 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135484.582928 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133813.953488 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82851.485149 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75634.716434 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75764.412811 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 1659506 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 839728 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12423 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 183739 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 180899 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2840 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 31691 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 827645 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2438 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2438 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 153507 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 660509 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 108712 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 33822 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 71296 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41636 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86274 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 35 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 68587 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 66399 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 586867 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 252106 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 259 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1760267 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 848480 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14499 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37693 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2660939 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 75086288 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29768550 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 25888 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 68844 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 104949570 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 408766 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 5198376 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 1235773 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.169662 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.381410 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.183275 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15935.318275 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14368.600683 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15346.794872 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41062.935524 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41062.935524 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15478.018461 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15478.018461 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15006.316958 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15006.316958 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33744.960910 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33744.960910 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31362.871348 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31362.871348 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16784.184169 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16784.184169 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15935.318275 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14368.600683 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31362.871348 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22213.147876 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23897.821570 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15935.318275 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14368.600683 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31362.871348 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22213.147876 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41062.935524 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26654.734523 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 79108.910891 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166162.395812 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165560.918046 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 79108.910891 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 91467.446534 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 91420.296151 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 1661462 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 840058 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12360 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 115637 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 106952 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8685 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 43235 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 842502 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11855 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11855 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 146735 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 662812 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 29649 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 30154 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 72596 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41626 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86297 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 68185 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 65527 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 590026 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 275295 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 251 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1769762 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 885483 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14740 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38125 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2708110 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 75491792 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29665722 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 26616 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70376 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 105254506 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 347103 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 4899396 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1195777 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.122893 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.349738 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1028949 83.26% 83.26% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 203984 16.51% 99.77% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 2840 0.23% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1057509 88.44% 88.44% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 129583 10.84% 99.27% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 8685 0.73% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1235773 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1618384496 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1195777 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1635737987 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80334899 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 81718473 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 880530739 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 885241795 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 381648033 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 395391898 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 8035982 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 8093984 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 20499963 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 20543974 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 31012 # Transaction distribution system.iobus.trans_dist::ReadResp 31012 # Transaction distribution system.iobus.trans_dist::WriteReq 59421 # Transaction distribution @@ -2910,33 +2899,33 @@ system.iobus.pkt_size_system.bridge.master::total 162794 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484042 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40384000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 40381000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 112000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 328500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 325000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 31000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 89500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 92000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 582500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 575500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 51500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) @@ -2944,32 +2933,32 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6095500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6080500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33840000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 33803000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187690100 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187681355 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36458 # number of replacements -system.iocache.tags.tagsinuse 14.555462 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.555440 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 255127474000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.555462 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.909716 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.909716 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 255145986000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.555440 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.909715 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.909715 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328284 # Number of tag accesses system.iocache.tags.data_accesses 328284 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses system.iocache.ReadReq_misses::total 252 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -2978,14 +2967,14 @@ system.iocache.demand_misses::realview.ide 36476 # system.iocache.demand_misses::total 36476 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36476 # number of overall misses system.iocache.overall_misses::total 36476 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32581877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32581877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4303830223 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4303830223 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4336412100 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4336412100 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4336412100 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4336412100 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 32543877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32543877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4303510478 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4303510478 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4336054355 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4336054355 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4336054355 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4336054355 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -3002,19 +2991,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 129293.162698 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 129293.162698 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118811.567552 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118811.567552 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118883.981248 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118883.981248 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118883.981248 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118883.981248 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 129142.369048 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 129142.369048 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118802.740669 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118802.740669 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 118874.173566 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118874.173566 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 118874.173566 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118874.173566 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 5.333333 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks @@ -3026,14 +3015,14 @@ system.iocache.demand_mshr_misses::realview.ide 36476 system.iocache.demand_mshr_misses::total 36476 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36476 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36476 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19981877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19981877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2490259225 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2490259225 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2510241102 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2510241102 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2510241102 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2510241102 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19943877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19943877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2489987873 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2489987873 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2509931750 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2509931750 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2509931750 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2509931750 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -3042,620 +3031,618 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79293.162698 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 79293.162698 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68746.113764 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68746.113764 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68818.979658 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68818.979658 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68818.979658 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68818.979658 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 132786 # number of replacements -system.l2c.tags.tagsinuse 63192.932289 # Cycle average of tags in use -system.l2c.tags.total_refs 445408 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 196622 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.265301 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 13716.070006 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.287927 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.059977 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8086.686479 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2783.200527 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33654.604995 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.598228 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.910717 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1777.688460 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 638.769137 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2513.055836 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.209291 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000249 # Average percentage of cache occupancy +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79142.369048 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 79142.369048 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68738.622819 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68738.622819 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68810.498684 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68810.498684 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68810.498684 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68810.498684 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 136926 # number of replacements +system.l2c.tags.tagsinuse 65153.135165 # Cycle average of tags in use +system.l2c.tags.total_refs 554455 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 202299 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.740770 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 87124800000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 6156.009081 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 17.876446 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.073086 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8059.392106 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 7027.702710 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37061.403814 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.474451 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.906071 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1853.985065 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2995.751440 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1972.560896 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.093933 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000273 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.123393 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.042468 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.513529 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000070 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.122977 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.107234 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.565512 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000099 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.027125 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009747 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.038346 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.964248 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 29165 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 34651 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 193 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5622 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 23349 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 598 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6765 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 27255 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.445023 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000305 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.528732 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6142016 # Number of tag accesses -system.l2c.tags.data_accesses 6142016 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 267222 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 267222 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 32477 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2702 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 35179 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2050 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 948 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2998 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3952 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1344 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5296 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 189 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 79 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 33758 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 47203 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46059 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 69 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 37 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 13188 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 9867 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5574 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 156023 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 189 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 79 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 33758 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 51155 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 46059 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 69 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 37 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 13188 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 11211 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 5574 # number of demand (read+write) hits -system.l2c.demand_hits::total 161319 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 189 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 79 # number of overall hits -system.l2c.overall_hits::cpu0.inst 33758 # number of overall hits -system.l2c.overall_hits::cpu0.data 51155 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 46059 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 69 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 37 # number of overall hits -system.l2c.overall_hits::cpu1.inst 13188 # number of overall hits -system.l2c.overall_hits::cpu1.data 11211 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 5574 # number of overall hits -system.l2c.overall_hits::total 161319 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 9039 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2774 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11813 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 653 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1278 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1931 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11611 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8840 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 20451 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 26 # number of ReadSharedReq misses +system.l2c.tags.occ_percent::cpu1.inst 0.028290 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.045712 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030099 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994158 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 33193 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 24 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 32156 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 172 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5974 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 27047 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4634 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 27347 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.506485 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.490662 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6339538 # Number of tag accesses +system.l2c.tags.data_accesses 6339538 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 263091 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 263091 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 41407 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 4842 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 46249 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2692 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 2122 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 4814 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 3983 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1501 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5484 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 230 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 86 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 51619 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 58109 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47216 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 63 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 17 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 21642 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 11731 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5163 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 195876 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 230 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 86 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 51619 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 62092 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 47216 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 63 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 17 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 21642 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 13232 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 5163 # number of demand (read+write) hits +system.l2c.demand_hits::total 201360 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 230 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 86 # number of overall hits +system.l2c.overall_hits::cpu0.inst 51619 # number of overall hits +system.l2c.overall_hits::cpu0.data 62092 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 47216 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 63 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 17 # number of overall hits +system.l2c.overall_hits::cpu1.inst 21642 # number of overall hits +system.l2c.overall_hits::cpu1.data 13232 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 5163 # number of overall hits +system.l2c.overall_hits::total 201360 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 609 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 555 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1164 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 50 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 135 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 185 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11314 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 8283 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 19597 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 30 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 19633 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 9253 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133186 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 6 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 2822 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 1110 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 8266 # 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average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24906.494523 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25207.923356 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 92845.835931 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74468.778507 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 84902.303213 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 89788.461538 # average ReadSharedReq mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.014494 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.102835 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.024550 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.018235 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.059814 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.037007 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.739622 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.846586 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.781348 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.115385 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.033708 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.275149 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.139139 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735778 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.112676 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.055556 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.117868 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.084588 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.557432 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.466078 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.115385 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.033708 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.275149 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.250079 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735778 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.112676 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.055556 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.117868 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.414487 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.557432 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.486252 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.115385 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.033708 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.275149 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.250079 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735778 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.112676 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.055556 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.117868 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.414487 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.557432 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.486252 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23267.651888 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22047.747748 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22685.996564 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26990 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23811.111111 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24670.270270 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93715.264274 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74305.927804 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 85511.583406 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 86700 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72881.160118 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 81305.090241 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99848.908954 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 80833.333333 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 83500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76729.510335 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 84795.762849 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124673.871401 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96534.502071 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 89788.461538 # average overall mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73944.858586 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 82145.336563 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99723.724266 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 77375 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 75611.687414 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80673.431734 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 129570.407043 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96406.532990 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86700 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72881.160118 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 87727.616996 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99848.908954 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80833.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 83500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76729.510335 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75619.911850 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124673.871401 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 95312.867617 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 89788.461538 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73944.858586 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 88467.280064 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99723.724266 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77375 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75611.687414 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75042.809864 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 129570.407043 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 95286.265989 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86700 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72881.160118 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 87727.616996 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99848.908954 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80833.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 83500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76729.510335 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75619.911850 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124673.871401 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 95312.867617 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73944.858586 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 88467.280064 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99723.724266 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77375 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75611.687414 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75042.809864 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 129570.407043 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 95286.265989 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182383.088883 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64841.584158 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117600.389864 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167459.688043 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196956.087726 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61099.009901 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148192.365991 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167436.910471 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96220.306195 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64841.584158 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65622.552574 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 92322.603605 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 523570 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 298445 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 101739.966470 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61099.009901 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81567.901703 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 92312.727880 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 505464 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 284514 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 572 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 37954 # Transaction distribution -system.membus.trans_dist::ReadResp 212485 # Transaction distribution -system.membus.trans_dist::WriteReq 30889 # Transaction distribution -system.membus.trans_dist::WriteResp 30889 # Transaction distribution -system.membus.trans_dist::WritebackDirty 140037 # Transaction distribution -system.membus.trans_dist::CleanEvict 17084 # Transaction distribution -system.membus.trans_dist::UpgradeReq 74884 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40573 # Transaction distribution +system.membus.trans_dist::ReadResp 209195 # Transaction distribution +system.membus.trans_dist::WriteReq 30887 # Transaction distribution +system.membus.trans_dist::WriteResp 30887 # Transaction distribution +system.membus.trans_dist::WritebackDirty 137421 # Transaction distribution +system.membus.trans_dist::CleanEvict 16935 # Transaction distribution +system.membus.trans_dist::UpgradeReq 65286 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 38770 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 40212 # Transaction distribution -system.membus.trans_dist::ReadExResp 20363 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 174532 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 39566 # Transaction distribution +system.membus.trans_dist::ReadExResp 19573 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 171242 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13624 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 661033 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 782607 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13620 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 638853 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 760423 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 855556 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 833372 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27248 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19150328 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19340658 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18721784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18912106 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21658802 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 122046 # Total snoops (count) +system.membus.pkt_size::total 21230250 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123250 # Total snoops (count) system.membus.snoopTraffic 36480 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 435271 # Request fanout histogram -system.membus.snoop_fanout::mean 0.011878 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.108336 # Request fanout histogram +system.membus.snoop_fanout::samples 419934 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012350 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.110440 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 430101 98.81% 98.81% # Request fanout histogram -system.membus.snoop_fanout::1 5170 1.19% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 414748 98.77% 98.77% # Request fanout histogram +system.membus.snoop_fanout::1 5186 1.23% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 435271 # Request fanout histogram -system.membus.reqLayer0.occupancy 81633500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 419934 # Request fanout histogram +system.membus.reqLayer0.occupancy 81570000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11523000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11357000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1022470046 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 987545766 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1120816043 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1099710840 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1359381 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1385881 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3687,81 +3674,81 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 1014149 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 548985 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 155175 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 21000 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 20112 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 888 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1051858 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 557134 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 188416 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 28173 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 27109 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1064 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 37957 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 486750 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30889 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30889 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 371053 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 122899 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 109975 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 43571 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 153546 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 35 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 35 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50842 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50842 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 448796 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4596 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1244094 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 315957 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1560051 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34491784 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5674154 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 40165938 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 382861 # Total snoops (count) -system.toL2Bus.snoopTraffic 15835212 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 859470 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.375184 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.486300 # Request fanout histogram +system.toL2Bus.trans_dist::ReadResp 525508 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30887 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30887 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 364306 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 131438 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 111511 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 43584 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 155095 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50612 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50612 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 487554 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4612 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1267106 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 367019 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1634125 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36291756 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5905726 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 42197482 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 390713 # Total snoops (count) +system.toL2Bus.snoopTraffic 15836620 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 903686 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.404217 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.493133 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 537899 62.58% 62.58% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 320683 37.31% 99.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 888 0.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 539465 59.70% 59.70% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 363157 40.19% 99.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1064 0.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 859470 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 886309294 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 903686 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 901600874 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 356119 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 648979933 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 679704118 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 232794950 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 260937433 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1839 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 1856 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2759 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2757 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index f6937a594..fdcb3cf4d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.832894 # Number of seconds simulated -sim_ticks 2832894126500 # Number of ticks simulated -final_tick 2832894126500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.827853 # Number of seconds simulated +sim_ticks 2827853096000 # Number of ticks simulated +final_tick 2827853096000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 136161 # Simulator instruction rate (inst/s) -host_op_rate 165152 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3410188815 # Simulator tick rate (ticks/s) -host_mem_usage 579068 # Number of bytes of host memory used -host_seconds 830.71 # Real time elapsed on the host -sim_insts 113111333 # Number of instructions simulated -sim_ops 137193850 # Number of ops (including micro ops) simulated +host_inst_rate 94322 # Simulator instruction rate (inst/s) +host_op_rate 114411 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2357194570 # Simulator tick rate (ticks/s) +host_mem_usage 589152 # Number of bytes of host memory used +host_seconds 1199.67 # Real time elapsed on the host +sim_insts 113155640 # Number of instructions simulated +sim_ops 137255479 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1321536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9400296 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1322240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9790440 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10724584 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1321536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1321536 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8031104 # Number of bytes written to this memory +system.physmem.bytes_read::total 11115048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1322240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1322240 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8407168 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8048628 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22896 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 147400 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8424692 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22907 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 153496 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170339 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 125486 # Number of write requests responded to by this memory +system.physmem.num_reads::total 176440 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131362 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 129867 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 474 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 466497 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3318266 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 135743 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 362 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 136 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 467577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3462146 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3785734 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 466497 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 466497 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2834947 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6186 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2841133 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2834947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 474 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 466497 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3324452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3930561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 467577 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 467577 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2972986 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6197 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2979183 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2972986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 362 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 467577 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3468343 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6626867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170340 # Number of read requests accepted -system.physmem.writeReqs 129867 # Number of write requests accepted -system.physmem.readBursts 170340 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 129867 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10892352 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue -system.physmem.bytesWritten 8061056 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10724648 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8048628 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::total 6909744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 176441 # Number of read requests accepted +system.physmem.writeReqs 135743 # Number of write requests accepted +system.physmem.readBursts 176441 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 135743 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11282432 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9792 # Total number of bytes read from write queue +system.physmem.bytesWritten 8437824 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11115112 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8424692 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3886 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11036 # Per bank write bursts -system.physmem.perBankRdBursts::1 10507 # Per bank write bursts -system.physmem.perBankRdBursts::2 10862 # Per bank write bursts -system.physmem.perBankRdBursts::3 11068 # Per bank write bursts -system.physmem.perBankRdBursts::4 13101 # Per bank write bursts -system.physmem.perBankRdBursts::5 10327 # Per bank write bursts -system.physmem.perBankRdBursts::6 10639 # Per bank write bursts -system.physmem.perBankRdBursts::7 10985 # Per bank write bursts -system.physmem.perBankRdBursts::8 10460 # Per bank write bursts -system.physmem.perBankRdBursts::9 10167 # Per bank write bursts -system.physmem.perBankRdBursts::10 10435 # Per bank write bursts -system.physmem.perBankRdBursts::11 9511 # Per bank write bursts -system.physmem.perBankRdBursts::12 9930 # Per bank write bursts -system.physmem.perBankRdBursts::13 10756 # Per bank write bursts -system.physmem.perBankRdBursts::14 10401 # Per bank write bursts -system.physmem.perBankRdBursts::15 10008 # Per bank write bursts -system.physmem.perBankWrBursts::0 8291 # Per bank write bursts -system.physmem.perBankWrBursts::1 7865 # Per bank write bursts -system.physmem.perBankWrBursts::2 8399 # Per bank write bursts -system.physmem.perBankWrBursts::3 8558 # Per bank write bursts -system.physmem.perBankWrBursts::4 7751 # Per bank write bursts -system.physmem.perBankWrBursts::5 7713 # Per bank write bursts -system.physmem.perBankWrBursts::6 7781 # Per bank write bursts -system.physmem.perBankWrBursts::7 8111 # Per bank write bursts -system.physmem.perBankWrBursts::8 7871 # Per bank write bursts -system.physmem.perBankWrBursts::9 7662 # Per bank write bursts -system.physmem.perBankWrBursts::10 7844 # Per bank write bursts -system.physmem.perBankWrBursts::11 7196 # Per bank write bursts -system.physmem.perBankWrBursts::12 7582 # Per bank write bursts -system.physmem.perBankWrBursts::13 8119 # Per bank write bursts -system.physmem.perBankWrBursts::14 7846 # Per bank write bursts -system.physmem.perBankWrBursts::15 7365 # Per bank write bursts +system.physmem.perBankRdBursts::0 11743 # Per bank write bursts +system.physmem.perBankRdBursts::1 11227 # Per bank write bursts +system.physmem.perBankRdBursts::2 11041 # Per bank write bursts +system.physmem.perBankRdBursts::3 10652 # Per bank write bursts +system.physmem.perBankRdBursts::4 13485 # Per bank write bursts +system.physmem.perBankRdBursts::5 11002 # Per bank write bursts +system.physmem.perBankRdBursts::6 11432 # Per bank write bursts +system.physmem.perBankRdBursts::7 11844 # Per bank write bursts +system.physmem.perBankRdBursts::8 10383 # Per bank write bursts +system.physmem.perBankRdBursts::9 10947 # Per bank write bursts +system.physmem.perBankRdBursts::10 10471 # Per bank write bursts +system.physmem.perBankRdBursts::11 9569 # Per bank write bursts +system.physmem.perBankRdBursts::12 10361 # Per bank write bursts +system.physmem.perBankRdBursts::13 11110 # Per bank write bursts +system.physmem.perBankRdBursts::14 10361 # Per bank write bursts +system.physmem.perBankRdBursts::15 10660 # Per bank write bursts +system.physmem.perBankWrBursts::0 8764 # Per bank write bursts +system.physmem.perBankWrBursts::1 8604 # Per bank write bursts +system.physmem.perBankWrBursts::2 8676 # Per bank write bursts +system.physmem.perBankWrBursts::3 8310 # Per bank write bursts +system.physmem.perBankWrBursts::4 8074 # Per bank write bursts +system.physmem.perBankWrBursts::5 8230 # Per bank write bursts +system.physmem.perBankWrBursts::6 8228 # Per bank write bursts +system.physmem.perBankWrBursts::7 8800 # Per bank write bursts +system.physmem.perBankWrBursts::8 7938 # Per bank write bursts +system.physmem.perBankWrBursts::9 8472 # Per bank write bursts +system.physmem.perBankWrBursts::10 8080 # Per bank write bursts +system.physmem.perBankWrBursts::11 7388 # Per bank write bursts +system.physmem.perBankWrBursts::12 8035 # Per bank write bursts +system.physmem.perBankWrBursts::13 8487 # Per bank write bursts +system.physmem.perBankWrBursts::14 7854 # Per bank write bursts +system.physmem.perBankWrBursts::15 7901 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 17 # Number of times write queue was full causing retry -system.physmem.totGap 2832893894500 # Total gap between requests +system.physmem.numWrRetry 4 # Number of times write queue was full causing retry +system.physmem.totGap 2827852861000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 2996 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166788 # Read request sizes (log2) +system.physmem.readPktSize::6 172889 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 125486 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 150867 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 16439 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 721 # What read queue length does an incoming req see +system.physmem.writePktSize::6 131362 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 155219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 17999 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 829 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -160,164 +160,164 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 56 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62108 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 305.167515 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.813202 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.494619 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 23016 37.06% 37.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15104 24.32% 61.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6524 10.50% 71.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3665 5.90% 77.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2528 4.07% 81.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1637 2.64% 84.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1479 2.38% 86.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1102 1.77% 88.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7053 11.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62108 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6142 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.706936 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 569.623530 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6141 99.98% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6142 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6142 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.507001 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.506831 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.607971 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5435 88.49% 88.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 129 2.10% 90.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 31 0.50% 91.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 49 0.80% 91.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 32 0.52% 92.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 17 0.28% 92.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 48 0.78% 93.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 14 0.23% 93.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 140 2.28% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 11 0.18% 96.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.13% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.13% 96.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 65 1.06% 97.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.02% 97.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 21 0.34% 97.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 93 1.51% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.05% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.05% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.18% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 7 0.11% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6142 # Writes before turning the bus around for reads -system.physmem.totQLat 2108320500 # Total ticks spent queuing -system.physmem.totMemAccLat 5299439250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 850965000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12387.82 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 10 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64990 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 303.434251 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.571710 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 325.070143 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24166 37.18% 37.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15993 24.61% 61.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6821 10.50% 72.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3792 5.83% 78.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2758 4.24% 82.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1633 2.51% 84.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1086 1.67% 86.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1085 1.67% 88.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7656 11.78% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64990 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6662 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.461423 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 559.657587 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6661 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6662 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6662 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.790003 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.288798 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.351415 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5875 88.19% 88.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 70 1.05% 89.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 75 1.13% 90.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 36 0.54% 90.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 259 3.89% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 62 0.93% 95.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 25 0.38% 96.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 19 0.29% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 9 0.14% 96.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 7 0.11% 96.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.05% 96.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.06% 96.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 160 2.40% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.09% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 8 0.12% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 2 0.03% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 6 0.09% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.05% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 10 0.15% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.12% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6662 # Writes before turning the bus around for reads +system.physmem.totQLat 2116192000 # Total ticks spent queuing +system.physmem.totMemAccLat 5421592000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 881440000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12004.17 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31137.82 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.79 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.84 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30754.17 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.99 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.93 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.98 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.42 # Average write queue length when enqueuing -system.physmem.readRowHits 139937 # Number of row buffer hits during reads -system.physmem.writeRowHits 94101 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.22 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes -system.physmem.avgGap 9436468.49 # Average gap between requests -system.physmem.pageHitRate 79.02 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 243454680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 132837375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 690495000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 417759120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185030401920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83647548450 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1626357251250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1896519747795 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.465335 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2705450093000 # Time in different power states -system.physmem_0.memoryStateTime::REF 94596320000 # Time in different power states +system.physmem.avgWrQLen 23.03 # Average write queue length when enqueuing +system.physmem.readRowHits 145153 # Number of row buffer hits during reads +system.physmem.writeRowHits 97985 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.31 # Row buffer hit rate for writes +system.physmem.avgGap 9058288.90 # Average gap between requests +system.physmem.pageHitRate 78.90 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 256087440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 139730250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 720922800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 438605280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184701363600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 81077227785 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1625589296250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1892923233405 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.386141 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2704185411500 # Time in different power states +system.physmem_0.memoryStateTime::REF 94428100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32840757000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 29235954750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 226081800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 123358125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 637002600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 398422800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185030401920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82216233135 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1627612791000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1896244291380 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.368099 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2707556632500 # Time in different power states -system.physmem_1.memoryStateTime::REF 94596320000 # Time in different power states +system.physmem_1.actEnergy 235236960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 128353500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 654115800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 415724400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184701363600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 80292349755 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1626277785750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1892704929765 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.308944 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2705344853000 # Time in different power states +system.physmem_1.memoryStateTime::REF 94428100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30741160500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 28080129500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory @@ -330,30 +330,30 @@ system.realview.nvmem.bw_inst_read::cpu.inst 40 system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46812529 # Number of BP lookups -system.cpu.branchPred.condPredicted 23980713 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1174980 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29461889 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13525990 # Number of BTB hits +system.cpu.branchPred.lookups 46859222 # Number of BP lookups +system.cpu.branchPred.condPredicted 23995015 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1174256 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29489294 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13535968 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 45.910125 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11726513 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 34925 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 7916092 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 7770128 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 145964 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 60126 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 45.901296 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11745095 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 35189 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 7931554 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 7786304 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 145250 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 60170 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -383,82 +383,83 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 72186 # Table walker walks requested -system.cpu.dtb.walker.walksShort 72186 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29334 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23181 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 19671 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 52515 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 467.713986 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 2821.743931 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-8191 51203 97.50% 97.50% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::8192-16383 905 1.72% 99.22% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::16384-24575 322 0.61% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::24576-32767 40 0.08% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-40959 18 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::40960-49151 21 0.04% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::57344-65535 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 72426 # Table walker walks requested +system.cpu.dtb.walker.walksShort 72426 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29716 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23400 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 19310 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 53116 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 407.485503 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 2469.018740 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-8191 51917 97.74% 97.74% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-16383 937 1.76% 99.51% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::16384-24575 190 0.36% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::24576-32767 37 0.07% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-40959 15 0.03% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::40960-49151 16 0.03% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::57344-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::90112-98303 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 52515 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 17658 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 12583.333333 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 10066.135653 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 8522.119991 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 17438 98.75% 98.75% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-65535 214 1.21% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-163839 4 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-360447 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 17658 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 131358619316 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.629965 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.490082 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 131298865316 99.95% 99.95% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 40695500 0.03% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 8747000 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 6751500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 1053500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 584000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 1412000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 501000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walkWaitTime::total 53116 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 17396 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 9637.387905 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 7803.906851 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 6813.601039 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 15561 89.45% 89.45% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 1740 10.00% 99.45% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-49151 86 0.49% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::49152-65535 2 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-81919 1 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::245760-262143 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 17396 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 117727604724 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.629848 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.489627 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 117677681224 99.96% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 34838500 0.03% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 7318000 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 4585500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 935500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 533500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 1306000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 397000 0.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::16-17 9500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 131358619316 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6349 82.25% 82.25% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1370 17.75% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7719 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72186 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walksPending::total 117727604724 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6471 81.85% 81.85% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1435 18.15% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7906 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72426 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72186 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7719 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72426 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7906 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7719 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 79905 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7906 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 80332 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25413003 # DTB read hits -system.cpu.dtb.read_misses 62542 # DTB read misses -system.cpu.dtb.write_hits 19866296 # DTB write hits -system.cpu.dtb.write_misses 9644 # DTB write misses +system.cpu.dtb.read_hits 25423365 # DTB read hits +system.cpu.dtb.read_misses 62664 # DTB read misses +system.cpu.dtb.write_hits 19868926 # DTB write hits +system.cpu.dtb.write_misses 9762 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4253 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 366 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2075 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4289 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 358 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2236 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1321 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25475545 # DTB read accesses -system.cpu.dtb.write_accesses 19875940 # DTB write accesses +system.cpu.dtb.perms_faults 1258 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25486029 # DTB read accesses +system.cpu.dtb.write_accesses 19878688 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45279299 # DTB hits -system.cpu.dtb.misses 72186 # DTB misses -system.cpu.dtb.accesses 45351485 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 45292291 # DTB hits +system.cpu.dtb.misses 72426 # DTB misses +system.cpu.dtb.accesses 45364717 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -488,59 +489,58 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 12817 # Table walker walks requested -system.cpu.itb.walker.walksShort 12817 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 3407 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 7692 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 1718 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 11099 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 742.229030 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 3116.397220 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-4095 10521 94.79% 94.79% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::4096-8191 119 1.07% 95.86% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::8192-12287 227 2.05% 97.91% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::12288-16383 123 1.11% 99.02% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::16384-20479 47 0.42% 99.44% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::20480-24575 47 0.42% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::28672-32767 6 0.05% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::36864-40959 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::40960-45055 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::53248-57343 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::57344-61439 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 11099 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 5040 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 12026.488095 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 9684.197840 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7608.176186 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-16383 4071 80.77% 80.77% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-32767 955 18.95% 99.72% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-49151 11 0.22% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::49152-65535 1 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 5040 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 23984374916 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.642154 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.479545 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 8584682500 35.79% 35.79% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 15397812416 64.20% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 1792000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 88000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 23984374916 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2987 89.92% 89.92% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 335 10.08% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3322 # Table walker page sizes translated +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 12855 # Table walker walks requested +system.cpu.itb.walker.walksShort 12855 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 3590 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7693 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 1572 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 11283 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 605.778605 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 2805.757421 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-8191 10907 96.67% 96.67% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-16383 327 2.90% 99.57% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::16384-24575 40 0.35% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::24576-32767 5 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::40960-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-73727 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::81920-90111 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 11283 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 4887 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 8961.019030 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 7007.167188 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7172.888707 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 3327 68.08% 68.08% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 829 16.96% 85.04% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 682 13.96% 99.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::24576-32767 38 0.78% 99.77% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-40959 1 0.02% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::40960-49151 7 0.14% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::49152-57343 1 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::81920-90111 2 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 4887 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 23237381212 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.774797 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.417824 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 5234024500 22.52% 22.52% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 18002578212 77.47% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 696500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 46500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 35500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 23237381212 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2980 89.89% 89.89% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 335 10.11% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3315 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12817 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 12817 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12855 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 12855 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3322 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3322 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 16139 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 65982481 # ITB inst hits -system.cpu.itb.inst_misses 12817 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3315 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3315 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 16170 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 66060204 # ITB inst hits +system.cpu.itb.inst_misses 12855 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -549,112 +549,113 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3021 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3013 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2147 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2175 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 65995298 # ITB inst accesses -system.cpu.itb.hits 65982481 # DTB hits -system.cpu.itb.misses 12817 # DTB misses -system.cpu.itb.accesses 65995298 # DTB accesses -system.cpu.numPwrStateTransitions 6074 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 3037 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 886948130.312150 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17421700028.084686 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 2966 97.66% 97.66% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 65 2.14% 99.80% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 66073059 # ITB inst accesses +system.cpu.itb.hits 66060204 # DTB hits +system.cpu.itb.misses 12855 # DTB misses +system.cpu.itb.accesses 66073059 # DTB accesses +system.cpu.numPwrStateTransitions 6076 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 3038 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 887319797.866359 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17420812025.908409 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 2966 97.63% 97.63% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 66 2.17% 99.80% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.07% 99.90% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 499972891000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 3037 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 139232654742 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2693661471758 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 278465363 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 499973328096 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 3038 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 132175550082 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2695677545918 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 264351157 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104979858 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184015649 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46812529 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33022631 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 161497089 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6057652 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 189263 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 8972 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 337056 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 558097 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 172 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 65981271 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1027864 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6246 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 270599333 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.829251 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.216918 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 105007140 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184198118 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46859222 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33067367 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 149125653 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6062128 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 177509 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 8064 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 342285 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 500656 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 149 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 66059105 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1061874 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6140 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 258192520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.869926 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.232240 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 171686790 63.45% 63.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29154260 10.77% 74.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14034299 5.19% 79.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55723984 20.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 159207105 61.66% 61.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29153243 11.29% 72.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14041371 5.44% 78.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55790801 21.61% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 270599333 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.168109 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.660821 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 77964907 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 121895477 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64303176 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3866825 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2568948 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3406986 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 467982 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 156982730 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3511045 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2568948 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83721940 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11815597 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 76560081 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62413108 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 33519659 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146432544 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 918349 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 465966 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 65322 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 18586 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 30762818 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150226924 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 676971311 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 163962292 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10893 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141750491 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8476427 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2839737 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2644396 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13885386 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26339908 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21214343 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1703941 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2126584 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143224778 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2118002 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143047064 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 260478 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8148926 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14278560 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 121950 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 270599333 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.528631 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.865147 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 258192520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.177261 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.696793 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 78121728 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 109293057 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64347286 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3858820 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2571629 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3404933 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 467397 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157054266 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3508469 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2571629 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83876272 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10707182 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 75777880 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62454434 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 22805123 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146493829 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 914752 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 447933 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 65579 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 19295 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 20059867 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150297562 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 677265731 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164029738 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 11047 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141819290 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8478266 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2841903 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2646616 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13881588 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26350743 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21216202 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1694356 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2155521 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143287156 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2116266 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143106706 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 261772 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8147939 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14286308 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 122067 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 258192520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.554264 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.878016 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 182394036 67.40% 67.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45259787 16.73% 84.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 31866202 11.78% 95.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10262392 3.79% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 816883 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 169987358 65.84% 65.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45210540 17.51% 83.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31907168 12.36% 95.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10268019 3.98% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 819402 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -662,44 +663,44 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 270599333 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 258192520 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7342152 32.76% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 32 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5622313 25.09% 57.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9444091 42.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7338606 32.76% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 32 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5623411 25.10% 57.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9440852 42.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 95850690 67.01% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 114288 0.08% 67.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 95896760 67.01% 67.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 115009 0.08% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued @@ -723,99 +724,99 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8577 0.01% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26130891 18.27% 85.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 20940281 14.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8592 0.01% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26141404 18.27% 85.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 20942604 14.63% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143047064 # Type of FU issued -system.cpu.iq.rate 0.513698 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22408588 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.156652 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 579326888 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 153497201 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 139997351 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35639 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13116 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 11369 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165429916 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23399 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 323958 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 143106706 # Type of FU issued +system.cpu.iq.rate 0.541351 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22402901 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.156547 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 567034934 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 153556562 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140052264 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35671 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13288 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 11499 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 165483986 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23284 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 324130 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1433781 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 712 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18665 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 622043 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1434023 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 698 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18538 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 619510 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 88844 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6344 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 88631 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6598 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2568948 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1241907 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 544667 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145523405 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2571629 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 994929 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 316385 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145584227 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26339908 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21214343 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1094304 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17849 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 508298 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18665 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 277238 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471000 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 748238 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142148555 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25736254 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 826428 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26350743 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21216202 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1093451 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17658 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 280514 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18538 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 277676 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 470698 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 748374 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142207045 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25746206 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 827350 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 180625 # number of nop insts executed -system.cpu.iew.exec_refs 46564673 # number of memory reference insts executed -system.cpu.iew.exec_branches 26492434 # Number of branches executed -system.cpu.iew.exec_stores 20828419 # Number of stores executed -system.cpu.iew.exec_rate 0.510471 # Inst execution rate -system.cpu.iew.wb_sent 141779361 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140008720 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63240555 # num instructions producing a value -system.cpu.iew.wb_consumers 95712709 # num instructions consuming a value -system.cpu.iew.wb_rate 0.502787 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660733 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 7366290 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1996052 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 715102 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 267708008 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.513054 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.118068 # Number of insts commited each cycle +system.cpu.iew.exec_nop 180805 # number of nop insts executed +system.cpu.iew.exec_refs 46576895 # number of memory reference insts executed +system.cpu.iew.exec_branches 26509940 # Number of branches executed +system.cpu.iew.exec_stores 20830689 # Number of stores executed +system.cpu.iew.exec_rate 0.537948 # Inst execution rate +system.cpu.iew.wb_sent 141837731 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140063763 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63261975 # num instructions producing a value +system.cpu.iew.wb_consumers 95760288 # num instructions consuming a value +system.cpu.iew.wb_rate 0.529840 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660628 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 7362260 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1994199 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 714821 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 255299551 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.538232 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.139550 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 194252968 72.56% 72.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43305040 16.18% 88.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15457612 5.77% 94.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4371808 1.63% 96.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6428406 2.40% 98.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1610065 0.60% 99.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 797962 0.30% 99.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 411830 0.15% 99.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1072317 0.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 181839086 71.23% 71.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43295063 16.96% 88.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15470047 6.06% 94.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4367483 1.71% 95.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6400805 2.51% 98.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1643674 0.64% 99.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 799411 0.31% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 417134 0.16% 99.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1066848 0.42% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 267708008 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113266238 # Number of instructions committed -system.cpu.commit.committedOps 137348755 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 255299551 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113310545 # Number of instructions committed +system.cpu.commit.committedOps 137410384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45498427 # Number of memory references committed -system.cpu.commit.loads 24906127 # Number of loads committed -system.cpu.commit.membars 814995 # Number of memory barriers committed -system.cpu.commit.branches 26026646 # Number of branches committed -system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120175202 # Number of committed integer instructions. -system.cpu.commit.function_calls 4885014 # Number of function calls committed. +system.cpu.commit.refs 45513412 # Number of memory references committed +system.cpu.commit.loads 24916720 # Number of loads committed +system.cpu.commit.membars 814165 # Number of memory barriers committed +system.cpu.commit.branches 26044798 # Number of branches committed +system.cpu.commit.fp_insts 11492 # Number of committed floating point instructions. +system.cpu.commit.int_insts 120233477 # Number of committed integer instructions. +system.cpu.commit.function_calls 4891928 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91728959 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 112792 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91774855 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 113526 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction @@ -839,693 +840,689 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 8577 0.01% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24906127 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20592300 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8591 0.01% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24916720 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20596692 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137348755 # Class of committed instruction -system.cpu.commit.bw_lim_events 1072317 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 389160423 # The number of ROB reads -system.cpu.rob.rob_writes 292308325 # The number of ROB writes -system.cpu.timesIdled 890756 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7866030 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5387322891 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113111333 # Number of Instructions Simulated -system.cpu.committedOps 137193850 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.461870 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.461870 # CPI: Total CPI of All Threads -system.cpu.ipc 0.406195 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.406195 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155535200 # number of integer regfile reads -system.cpu.int_regfile_writes 88495253 # number of integer regfile writes -system.cpu.fp_regfile_reads 9528 # number of floating regfile reads +system.cpu.commit.op_class_0::total 137410384 # Class of committed instruction +system.cpu.commit.bw_lim_events 1066848 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 376774257 # The number of ROB reads +system.cpu.rob.rob_writes 292425270 # The number of ROB writes +system.cpu.timesIdled 893722 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6158637 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5391355036 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113155640 # Number of Instructions Simulated +system.cpu.committedOps 137255479 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.336173 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.336173 # CPI: Total CPI of All Threads +system.cpu.ipc 0.428050 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.428050 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155596461 # number of integer regfile reads +system.cpu.int_regfile_writes 88540193 # number of integer regfile writes +system.cpu.fp_regfile_reads 9674 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 502191757 # number of cc regfile reads -system.cpu.cc_regfile_writes 53133619 # number of cc regfile writes -system.cpu.misc_regfile_reads 461629806 # number of misc regfile reads -system.cpu.misc_regfile_writes 1521804 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 838109 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.925913 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40060330 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 838621 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.769290 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.925913 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy +system.cpu.cc_regfile_reads 502394909 # number of cc regfile reads +system.cpu.cc_regfile_writes 53149715 # number of cc regfile writes +system.cpu.misc_regfile_reads 449419252 # number of misc regfile reads +system.cpu.misc_regfile_writes 1520020 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 839084 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.954165 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40069527 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 839596 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.724771 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 270911500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.954165 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999910 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999910 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 358 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179138470 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179138470 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 23266826 # 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number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 130358500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 208000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 208000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19316454479 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19316454479 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20939138479 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20939138479 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6279502000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6279502000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6279502000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6279502000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017270 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017270 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015684 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015684 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228351 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228351 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017900 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017900 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # 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average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14175.624990 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15049.484414 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15049.484414 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36956.469024 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36956.469024 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33690.033758 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33690.033758 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201620.819814 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201620.819814 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106895.365671 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106895.365671 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1886431 # number of replacements -system.cpu.icache.tags.tagsinuse 511.154202 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 64000082 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1886943 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 33.917337 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 16319051500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.154202 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998348 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998348 # Average percentage of cache occupancy +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016566 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016566 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019101 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019101 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14221.769121 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14221.769121 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44683.609554 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44683.609554 # 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Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 13715039500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.341026 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998713 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998713 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 221 # 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number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1978185 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1978185 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1978185 # number of overall misses -system.cpu.icache.overall_misses::total 1978185 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28158737492 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28158737492 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28158737492 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28158737492 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28158737492 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28158737492 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 65978267 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 65978267 # 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average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14234.633006 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14234.633006 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14234.633006 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14234.633006 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14234.633006 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5390 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 67944454 # Number of tag accesses +system.cpu.icache.tags.data_accesses 67944454 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 64075895 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 64075895 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 64075895 # 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number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26984355494 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26984355494 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26984355494 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66056101 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66056101 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66056101 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66056101 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66056101 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66056101 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029978 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.029978 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.029978 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.029978 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.029978 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.029978 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13627.044607 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13627.044607 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13627.044607 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13627.044607 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13627.044607 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13627.044607 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2643 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 176 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 125 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 30.625000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.144000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1886431 # number of writebacks -system.cpu.icache.writebacks::total 1886431 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91184 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 91184 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 91184 # 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mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000587 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010546 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.182624 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.062049 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 73666.666667 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 80886.363636 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19136.363636 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19136.363636 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 73500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 73500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71114.599669 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71114.599669 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73238.927388 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73238.927388 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76205.075398 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76205.075398 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 73666.666667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73238.927388 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71590.136565 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71780.813182 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 73666.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73238.927388 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.136565 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71780.813182 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63773.060273 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189237.783917 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 178198.505713 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63773.060273 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100328.805505 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98550.004861 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5488560 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2760615 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 44763 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 238 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 238 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 128619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2557060 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 821637 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1886431 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 149968 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2806 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 129622 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2559974 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 791350 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1887810 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 151157 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2768 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2811 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 297337 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 297337 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887001 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 541532 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5666337 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2638583 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30857 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 133499 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8469276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241541168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98417449 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 48264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 231212 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 340238093 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 194794 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 8145576 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3054607 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.024758 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.155386 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2773 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 297834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 297834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1888354 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 542004 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 4368 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5670459 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2641503 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 29194 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 130873 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8472029 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241718384 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98487773 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 217428 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 340464457 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 139207 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6232532 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2995964 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.025358 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.157210 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2978982 97.52% 97.52% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 75625 2.48% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2919992 97.46% 97.46% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 75972 2.54% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3054607 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5400960498 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2995964 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5405204997 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 258877 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 383377 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2834452098 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2836467127 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1304519551 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1305988986 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 18799483 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 18982487 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 75755880 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 76565899 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 30172 # Transaction distribution -system.iobus.trans_dist::ReadResp 30172 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 30182 # Transaction distribution +system.iobus.trans_dist::ReadResp 30182 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) @@ -1548,9 +1545,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72894 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72894 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178372 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178392 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) @@ -1571,22 +1568,22 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321016 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321016 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480141 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 43088500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 43094500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 326000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 325500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 28000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 92500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 91500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 651500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 649500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1608,56 +1605,56 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6158500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6172500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33063500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 33854000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187149991 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187760330 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36738000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 36413 # number of replacements -system.iocache.tags.tagsinuse 1.005857 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 36423 # number of replacements +system.iocache.tags.tagsinuse 1.000676 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36429 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 256506730000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.005857 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062866 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062866 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 252706881000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.000676 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062542 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062542 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328023 # Number of tag accesses -system.iocache.tags.data_accesses 328023 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses -system.iocache.ReadReq_misses::total 223 # number of ReadReq misses +system.iocache.tags.tag_accesses 328113 # Number of tag accesses +system.iocache.tags.data_accesses 328113 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_misses::realview.ide 233 # number of ReadReq misses +system.iocache.ReadReq_misses::total 233 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36447 # number of demand (read+write) misses -system.iocache.demand_misses::total 36447 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36447 # number of overall misses -system.iocache.overall_misses::total 36447 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28156877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28156877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4551348114 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4551348114 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4579504991 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4579504991 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4579504991 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4579504991 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 223 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 223 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 36457 # number of demand (read+write) misses +system.iocache.demand_misses::total 36457 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36457 # number of overall misses +system.iocache.overall_misses::total 36457 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 28964877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28964877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4277512453 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4277512453 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4306477330 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4306477330 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4306477330 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4306477330 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 233 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 233 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36447 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36447 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36447 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36447 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36457 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36457 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36457 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36457 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -1666,14 +1663,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 126264.022422 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126264.022422 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125644.548200 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125644.548200 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125648.338437 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125648.338437 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125648.338437 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125648.338437 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 124312.776824 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124312.776824 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118085.039007 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118085.039007 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 118124.841046 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118124.841046 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 118124.841046 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118124.841046 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1682,22 +1679,22 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 223 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 233 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 233 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 36447 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 36447 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 36447 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 36447 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17006877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17006877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2738747578 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2738747578 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2755754455 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2755754455 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2755754455 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2755754455 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 36457 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 36457 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 36457 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 36457 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17314877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17314877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2464212681 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2464212681 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2481527558 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2481527558 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2481527558 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2481527558 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1706,84 +1703,90 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76264.022422 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76264.022422 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75605.884993 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75605.884993 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75609.911790 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75609.911790 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75609.911790 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75609.911790 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 34132 # Transaction distribution -system.membus.trans_dist::ReadResp 67530 # Transaction distribution -system.membus.trans_dist::WriteReq 27585 # Transaction distribution -system.membus.trans_dist::WriteResp 27585 # Transaction distribution -system.membus.trans_dist::WritebackDirty 125486 # Transaction distribution -system.membus.trans_dist::CleanEvict 7993 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4611 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74312.776824 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74312.776824 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68027.072687 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68027.072687 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68067.245193 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68067.245193 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68067.245193 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68067.245193 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 349590 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 144366 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 482 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 34130 # Transaction distribution +system.membus.trans_dist::ReadResp 68622 # Transaction distribution +system.membus.trans_dist::WriteReq 27584 # Transaction distribution +system.membus.trans_dist::WriteResp 27584 # Transaction distribution +system.membus.trans_dist::WritebackDirty 131362 # Transaction distribution +system.membus.trans_dist::CleanEvict 8484 # Transaction distribution +system.membus.trans_dist::UpgradeReq 130 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 133874 # Transaction distribution -system.membus.trans_dist::ReadExResp 133874 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 33399 # Transaction distribution +system.membus.trans_dist::ReadExReq 138891 # Transaction distribution +system.membus.trans_dist::ReadExResp 138891 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34493 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 451368 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558936 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72875 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72875 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 631811 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465445 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 573007 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72895 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72895 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 645902 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16456092 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16619481 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17222620 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17385997 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18936601 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 487 # Total snoops (count) -system.membus.snoopTraffic 31040 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 403324 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size::total 19703117 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 497 # Total snoops (count) +system.membus.snoopTraffic 31680 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 271454 # Request fanout histogram +system.membus.snoop_fanout::mean 0.017933 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.132708 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 403324 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 266586 98.21% 98.21% # Request fanout histogram +system.membus.snoop_fanout::1 4868 1.79% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 403324 # Request fanout histogram -system.membus.reqLayer0.occupancy 83656500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 271454 # Request fanout histogram +system.membus.reqLayer0.occupancy 84464500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1736499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1723499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 876921354 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 908168519 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 979994750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1012308500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1182123 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1273123 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1815,30 +1818,30 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 317b8f2e9..b158166a6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.823751 # Number of seconds simulated -sim_ticks 2823750824500 # Number of ticks simulated -final_tick 2823750824500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.823713 # Number of seconds simulated +sim_ticks 2823712531500 # Number of ticks simulated +final_tick 2823712531500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 215412 # Simulator instruction rate (inst/s) -host_op_rate 261296 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4949093514 # Simulator tick rate (ticks/s) -host_mem_usage 585976 # Number of bytes of host memory used -host_seconds 570.56 # Real time elapsed on the host -sim_insts 122905142 # Number of instructions simulated -sim_ops 149084969 # Number of ops (including micro ops) simulated +host_inst_rate 235362 # Simulator instruction rate (inst/s) +host_op_rate 285496 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5406413351 # Simulator tick rate (ticks/s) +host_mem_usage 591960 # Number of bytes of host memory used +host_seconds 522.29 # Real time elapsed on the host +sim_insts 122926882 # Number of instructions simulated +sim_ops 149111695 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 542180 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 3155236 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 537508 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 3136100 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 122688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 900352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 121472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 903168 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.dtb.walker 1792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 341632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1990912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.dtb.walker 4736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 343232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1991872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 4544 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 381248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 3510400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 387072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 3526656 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10952712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 542180 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 122688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 341632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 381248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1387748 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8236736 # Number of bytes written to this memory +system.physmem.bytes_read::total 10954952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 537508 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 121472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 343232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 387072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1389284 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8237952 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8254260 # Number of bytes written to this memory +system.physmem.bytes_written::total 8255476 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 16925 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 49820 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 16852 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 49521 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1917 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 14068 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1898 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 14112 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.dtb.walker 28 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5338 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 31108 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.dtb.walker 74 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5363 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 31123 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 71 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 5957 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 54850 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 6048 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 55104 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 180109 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 128699 # Number of write requests responded to by this memory +system.physmem.num_reads::total 180144 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 128718 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 133080 # Number of write requests responded to by this memory +system.physmem.num_writes::total 133099 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 113 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 192007 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1117392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 190355 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1110630 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 43449 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 318850 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 43019 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 319851 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.dtb.walker 635 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 120985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 705059 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.dtb.walker 1677 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 121553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 705409 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 1609 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu3.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 135015 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 1243169 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 137079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 1248943 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3878781 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 192007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 43449 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 120985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 135015 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 491456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2916949 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3879627 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 190355 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 43019 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 121553 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 137079 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 492006 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2917419 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6206 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2923155 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2916949 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2923625 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2917419 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 113 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 192007 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1123598 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 190355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1116836 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 43449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 318850 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 43019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 319851 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.dtb.walker 635 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 120985 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 705059 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.dtb.walker 1677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 121553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 705409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 1609 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu3.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 135015 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 1243169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 137079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 1248943 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6801936 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 113342 # Number of read requests accepted -system.physmem.writeReqs 68762 # Number of write requests accepted -system.physmem.readBursts 113342 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 68762 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 7247168 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue -system.physmem.bytesWritten 4399872 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 7253888 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4400768 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6803252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 113749 # Number of read requests accepted +system.physmem.writeReqs 69024 # Number of write requests accepted +system.physmem.readBursts 113749 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 69024 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 7272896 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7040 # Total number of bytes read from write queue +system.physmem.bytesWritten 4416768 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 7279936 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4417536 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 110 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 7506 # Per bank write bursts -system.physmem.perBankRdBursts::1 6787 # Per bank write bursts -system.physmem.perBankRdBursts::2 7407 # Per bank write bursts -system.physmem.perBankRdBursts::3 7543 # Per bank write bursts -system.physmem.perBankRdBursts::4 7335 # Per bank write bursts -system.physmem.perBankRdBursts::5 7022 # Per bank write bursts -system.physmem.perBankRdBursts::6 7619 # Per bank write bursts -system.physmem.perBankRdBursts::7 7707 # Per bank write bursts -system.physmem.perBankRdBursts::8 6869 # Per bank write bursts -system.physmem.perBankRdBursts::9 7531 # Per bank write bursts -system.physmem.perBankRdBursts::10 6987 # Per bank write bursts -system.physmem.perBankRdBursts::11 6354 # Per bank write bursts -system.physmem.perBankRdBursts::12 6401 # Per bank write bursts -system.physmem.perBankRdBursts::13 7189 # Per bank write bursts -system.physmem.perBankRdBursts::14 6831 # Per bank write bursts -system.physmem.perBankRdBursts::15 6149 # Per bank write bursts -system.physmem.perBankWrBursts::0 4366 # Per bank write bursts -system.physmem.perBankWrBursts::1 3966 # Per bank write bursts -system.physmem.perBankWrBursts::2 4487 # Per bank write bursts -system.physmem.perBankWrBursts::3 4689 # Per bank write bursts -system.physmem.perBankWrBursts::4 4379 # Per bank write bursts -system.physmem.perBankWrBursts::5 4312 # Per bank write bursts -system.physmem.perBankWrBursts::6 4615 # Per bank write bursts -system.physmem.perBankWrBursts::7 4485 # Per bank write bursts -system.physmem.perBankWrBursts::8 4160 # Per bank write bursts -system.physmem.perBankWrBursts::9 4849 # Per bank write bursts -system.physmem.perBankWrBursts::10 4371 # Per bank write bursts -system.physmem.perBankWrBursts::11 3905 # Per bank write bursts -system.physmem.perBankWrBursts::12 3814 # Per bank write bursts -system.physmem.perBankWrBursts::13 4615 # Per bank write bursts -system.physmem.perBankWrBursts::14 4128 # Per bank write bursts -system.physmem.perBankWrBursts::15 3607 # Per bank write bursts +system.physmem.perBankRdBursts::0 7641 # Per bank write bursts +system.physmem.perBankRdBursts::1 6876 # Per bank write bursts +system.physmem.perBankRdBursts::2 7409 # Per bank write bursts +system.physmem.perBankRdBursts::3 7470 # Per bank write bursts +system.physmem.perBankRdBursts::4 7337 # Per bank write bursts +system.physmem.perBankRdBursts::5 7030 # Per bank write bursts +system.physmem.perBankRdBursts::6 7627 # Per bank write bursts +system.physmem.perBankRdBursts::7 7716 # Per bank write bursts +system.physmem.perBankRdBursts::8 6884 # Per bank write bursts +system.physmem.perBankRdBursts::9 7545 # Per bank write bursts +system.physmem.perBankRdBursts::10 7008 # Per bank write bursts +system.physmem.perBankRdBursts::11 6374 # Per bank write bursts +system.physmem.perBankRdBursts::12 6408 # Per bank write bursts +system.physmem.perBankRdBursts::13 7193 # Per bank write bursts +system.physmem.perBankRdBursts::14 6835 # Per bank write bursts +system.physmem.perBankRdBursts::15 6286 # Per bank write bursts +system.physmem.perBankWrBursts::0 4484 # Per bank write bursts +system.physmem.perBankWrBursts::1 4020 # Per bank write bursts +system.physmem.perBankWrBursts::2 4489 # Per bank write bursts +system.physmem.perBankWrBursts::3 4613 # Per bank write bursts +system.physmem.perBankWrBursts::4 4310 # Per bank write bursts +system.physmem.perBankWrBursts::5 4320 # Per bank write bursts +system.physmem.perBankWrBursts::6 4621 # Per bank write bursts +system.physmem.perBankWrBursts::7 4483 # Per bank write bursts +system.physmem.perBankWrBursts::8 4167 # Per bank write bursts +system.physmem.perBankWrBursts::9 4860 # Per bank write bursts +system.physmem.perBankWrBursts::10 4381 # Per bank write bursts +system.physmem.perBankWrBursts::11 3929 # Per bank write bursts +system.physmem.perBankWrBursts::12 3827 # Per bank write bursts +system.physmem.perBankWrBursts::13 4631 # Per bank write bursts +system.physmem.perBankWrBursts::14 4137 # Per bank write bursts +system.physmem.perBankWrBursts::15 3740 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 2822178697500 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 2822140482500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 113342 # Read request sizes (log2) +system.physmem.readPktSize::6 113749 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 68762 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 85611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 24487 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2575 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 69024 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 85840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 24773 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2446 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 577 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -191,176 +191,172 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 67 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 66 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39262 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.647547 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.649192 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.383393 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15575 39.67% 39.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9414 23.98% 63.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3760 9.58% 73.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2064 5.26% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1515 3.86% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1018 2.59% 84.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 639 1.63% 86.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 658 1.68% 88.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4619 11.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39262 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3618 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 31.293256 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 632.321482 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 3616 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 3 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 39259 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 297.757559 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 173.671784 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.464821 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15432 39.31% 39.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9477 24.14% 63.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3788 9.65% 73.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2095 5.34% 78.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1555 3.96% 82.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1004 2.56% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 603 1.54% 86.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 654 1.67% 88.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4651 11.85% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39259 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3667 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.985274 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 628.070623 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 3665 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::36864-38911 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3618 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3618 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.001658 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.828073 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 10.498575 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 5 0.14% 0.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 2 0.06% 0.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 2 0.06% 0.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 2 0.06% 0.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3234 89.39% 89.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 43 1.19% 90.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 55 1.52% 92.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 37 1.02% 93.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 88 2.43% 95.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 33 0.91% 96.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 11 0.30% 97.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 11 0.30% 97.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 5 0.14% 97.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 7 0.19% 97.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.06% 97.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.14% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 54 1.49% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.08% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.03% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 4 0.11% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.06% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.03% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.03% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.06% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 3 0.08% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.06% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3618 # Writes before turning the bus around for reads -system.physmem.totQLat 1331922750 # Total ticks spent queuing -system.physmem.totMemAccLat 3455116500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 566185000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11762.26 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 3667 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3667 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.819744 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.710166 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 9.565148 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 9 0.25% 0.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 3 0.08% 0.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 3 0.08% 0.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 6 0.16% 0.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3283 89.53% 90.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 35 0.95% 91.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 47 1.28% 92.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 39 1.06% 93.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 88 2.40% 95.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 43 1.17% 96.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 6 0.16% 97.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 10 0.27% 97.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 7 0.19% 97.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 5 0.14% 97.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.11% 97.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 3 0.08% 97.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 62 1.69% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.03% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 1 0.03% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 4 0.11% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.03% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.11% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3667 # Writes before turning the bus around for reads +system.physmem.totQLat 1342938250 # Total ticks spent queuing +system.physmem.totMemAccLat 3473669500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 568195000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11817.58 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30512.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.57 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30567.58 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.58 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.57 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.58 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.94 # Average write queue length when enqueuing -system.physmem.readRowHits 93386 # Number of row buffer hits during reads -system.physmem.writeRowHits 49336 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.75 # Row buffer hit rate for writes -system.physmem.avgGap 15497620.58 # Average gap between requests -system.physmem.pageHitRate 78.42 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 157701600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 85878375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 459622800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 228737520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 179710355760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 72061196355 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1617839664000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1870543156410 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.633364 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2641056208250 # Time in different power states -system.physmem_0.memoryStateTime::REF 91876460000 # Time in different power states +system.physmem.avgWrQLen 27.55 # Average write queue length when enqueuing +system.physmem.readRowHits 93703 # Number of row buffer hits during reads +system.physmem.writeRowHits 49689 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.46 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.99 # Row buffer hit rate for writes +system.physmem.avgGap 15440685.89 # Average gap between requests +system.physmem.pageHitRate 78.50 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 158064480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 86055750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 461026800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 229003200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 179708321520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 72025489845 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1621445025000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1874112986595 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.488376 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2641083296250 # Time in different power states +system.physmem_0.memoryStateTime::REF 91875160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 18550863000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 18501220250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 139119120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 75726750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 423618000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 216749520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 179710355760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 71208324450 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1622163329250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1873937222850 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.425184 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2642291372250 # Time in different power states -system.physmem_1.memoryStateTime::REF 91876460000 # Time in different power states +system.physmem_1.actEnergy 138733560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 75508125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 425357400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 218194560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 179708321520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 71152837515 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1620392151000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1872111103680 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.495866 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2642358679500 # Time in different power states +system.physmem_1.memoryStateTime::REF 91875160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 17320352000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17221255250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -373,9 +369,9 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 7 system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -383,7 +379,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -413,49 +409,49 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 4996 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 4996 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 4996 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 4996 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 4996 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 56881650376 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.265666 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -15111501624 -26.57% -26.57% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 71993152000 126.57% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 56881650376 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 2808 68.21% 68.21% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1309 31.79% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4117 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4996 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 4966 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 4966 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 4966 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 4966 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 4966 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 56881367876 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.265672 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -15111782124 -26.57% -26.57% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 71993150000 126.57% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 56881367876 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 2795 68.22% 68.22% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1302 31.78% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4097 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4966 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4996 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4117 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4966 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4097 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4117 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 9113 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4097 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 9063 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12099084 # DTB read hits -system.cpu0.dtb.read_misses 4274 # DTB read misses -system.cpu0.dtb.write_hits 9151888 # DTB write hits -system.cpu0.dtb.write_misses 722 # DTB write misses +system.cpu0.dtb.read_hits 12103158 # DTB read hits +system.cpu0.dtb.read_misses 4250 # DTB read misses +system.cpu0.dtb.write_hits 9145748 # DTB write hits +system.cpu0.dtb.write_misses 716 # DTB write misses system.cpu0.dtb.flush_tlb 171 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 363 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 362 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2772 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 2759 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 821 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 823 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 173 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12103358 # DTB read accesses -system.cpu0.dtb.write_accesses 9152610 # DTB write accesses +system.cpu0.dtb.perms_faults 174 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12107408 # DTB read accesses +system.cpu0.dtb.write_accesses 9146464 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21250972 # DTB hits -system.cpu0.dtb.misses 4996 # DTB misses -system.cpu0.dtb.accesses 21255968 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 21248906 # DTB hits +system.cpu0.dtb.misses 4966 # DTB misses +system.cpu0.dtb.accesses 21253872 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -485,93 +481,93 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 2442 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2442 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walkWaitTime::samples 2442 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2442 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2442 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 56881650376 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.265668 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -15111616124 -26.57% -26.57% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 71993266500 126.57% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 56881650376 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1322 74.86% 74.86% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 444 25.14% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 1766 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 2431 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2431 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2431 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2431 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2431 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 56881367876 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.265674 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -15111901124 -26.57% -26.57% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 71993269000 126.57% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 56881367876 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1314 74.83% 74.83% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 442 25.17% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 1756 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2442 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2442 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2431 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2431 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1766 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1766 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 4208 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 56923800 # ITB inst hits -system.cpu0.itb.inst_misses 2442 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1756 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1756 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4187 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 56926912 # ITB inst hits +system.cpu0.itb.inst_misses 2431 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 171 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 363 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 362 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1703 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1695 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 56926242 # ITB inst accesses -system.cpu0.itb.hits 56923800 # DTB hits -system.cpu0.itb.misses 2442 # DTB misses -system.cpu0.itb.accesses 56926242 # DTB accesses -system.cpu0.numPwrStateTransitions 2560 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1280 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 2127325768.303125 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 53245910996.367020 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1265 98.83% 98.83% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 56929343 # ITB inst accesses +system.cpu0.itb.hits 56926912 # DTB hits +system.cpu0.itb.misses 2431 # DTB misses +system.cpu0.itb.accesses 56929343 # DTB accesses +system.cpu0.numPwrStateTransitions 2564 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1282 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 2124006318.198128 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 53204391855.203163 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1267 98.83% 98.83% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1000-5e+10 11 0.86% 99.69% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.08% 99.77% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.08% 99.84% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.08% 99.92% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::overflows 1 0.08% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 1799911049001 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1280 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 100773841072 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2722976983428 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 68778258 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 1799910947501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1282 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 100736431570 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2722976099930 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 68779411 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3086 # number of quiesce instructions executed -system.cpu0.committedInsts 55461787 # Number of instructions committed -system.cpu0.committedOps 67232154 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 59006752 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4424 # Number of float alu accesses -system.cpu0.num_func_calls 5784619 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7357566 # number of instructions that are conditional controls -system.cpu0.num_int_insts 59006752 # number of integer instructions -system.cpu0.num_fp_insts 4424 # number of float instructions -system.cpu0.num_int_register_reads 108803726 # number of times the integer registers were read -system.cpu0.num_int_register_writes 41133474 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3383 # number of times the floating registers were read +system.cpu0.kern.inst.quiesce 3087 # number of quiesce instructions executed +system.cpu0.committedInsts 55462034 # Number of instructions committed +system.cpu0.committedOps 67230601 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 59006165 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4380 # Number of float alu accesses +system.cpu0.num_func_calls 5788069 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7355854 # number of instructions that are conditional controls +system.cpu0.num_int_insts 59006165 # number of integer instructions +system.cpu0.num_fp_insts 4380 # number of float instructions +system.cpu0.num_int_register_reads 108801460 # number of times the integer registers were read +system.cpu0.num_int_register_writes 41139310 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3339 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1042 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 204599031 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 24717436 # number of times the CC registers were written -system.cpu0.num_mem_refs 21838245 # number of memory refs -system.cpu0.num_load_insts 12248234 # Number of load instructions -system.cpu0.num_store_insts 9590011 # Number of store instructions -system.cpu0.num_idle_cycles 64958382.766609 # Number of idle cycles -system.cpu0.num_busy_cycles 3819875.233391 # Number of busy cycles -system.cpu0.not_idle_fraction 0.055539 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.944461 # Percentage of idle cycles -system.cpu0.Branches 13458694 # Number of branches fetched +system.cpu0.num_cc_register_reads 204596465 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 24709161 # number of times the CC registers were written +system.cpu0.num_mem_refs 21836532 # number of memory refs +system.cpu0.num_load_insts 12252554 # Number of load instructions +system.cpu0.num_store_insts 9583978 # Number of store instructions +system.cpu0.num_idle_cycles 64960338.337804 # Number of idle cycles +system.cpu0.num_busy_cycles 3819072.662196 # Number of busy cycles +system.cpu0.not_idle_fraction 0.055526 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.944474 # Percentage of idle cycles +system.cpu0.Branches 13460127 # Number of branches fetched system.cpu0.op_class::No_OpClass 2178 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 46427379 67.95% 67.96% # Class of executed instruction -system.cpu0.op_class::IntMult 50783 0.07% 68.03% # Class of executed instruction +system.cpu0.op_class::IntAlu 46428516 67.96% 67.96% # Class of executed instruction +system.cpu0.op_class::IntMult 50840 0.07% 68.03% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 68.03% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 68.03% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 68.03% # Class of executed instruction @@ -595,550 +591,550 @@ system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.03% # Cl system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.03% # Class of executed instruction system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.03% # Class of executed instruction system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 3883 0.01% 68.04% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 3886 0.01% 68.04% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.04% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.04% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::MemRead 12248234 17.93% 85.96% # Class of executed instruction -system.cpu0.op_class::MemWrite 9590011 14.04% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 12252554 17.93% 85.97% # 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Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 833218 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.996713 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 45933242 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 833730 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 55.093666 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 482.041518 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.532588 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 4.805161 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu3.data 13.617445 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.941487 # 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number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu3.data 85895 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 388943 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 216992 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 74973 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 70646 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 88358 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 450969 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 218031 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 76624 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 73525 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu3.data 92476 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460656 # 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number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu3.data 220468 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 521514 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 112466 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 34991 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 102606 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu3.data 1224598 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1474661 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 53866 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 19687 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 19003 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu3.data 42601 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 135157 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 3704 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2351 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3769 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 8092 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 17916 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 193157378 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 193157378 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 11470530 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 3604905 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4052935 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu3.data 6701965 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 25830335 # 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number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 1612818000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3417318000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1243560500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2630255500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 4839784419 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8713600419 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 249854500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 223680000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 457627500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 931162000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 9093000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 27428500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 39926500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 76448000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 430500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 430500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2030512000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3647804000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 6452602419 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12130918419 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2280366500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3871484000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 6910229919 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13062080419 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 605119000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1489074500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1668784000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3762977500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 605119000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1489074500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 1668784000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3762977500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014260 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018147 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016236 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009089 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012863 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017049 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017910 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009210 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.252406 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.180557 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.230420 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.123190 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.009027 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019499 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.028813 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.010510 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000216 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000043 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013664 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017664 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.016968 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.009142 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.016502 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019551 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019173 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.010410 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15100.287825 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13584.883115 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14343.554899 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14270.934603 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35539.438713 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 47579.738066 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 50179.726270 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46666.418983 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12907.041017 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14340.300038 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15456.211159 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14422.309646 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13027.220630 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 18903.170227 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14367.218424 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15512.987013 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 21525 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21525 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23310.816706 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 28020.371167 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 30889.805779 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28464.240356 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21419.132289 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26556.666804 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 28973.831836 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26616.838519 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175447.665990 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 209522.231603 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 215021.775544 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205436.343288 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 96188.046416 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 121092.502236 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 119284.060043 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115506.706980 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1969655 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.471697 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 93089501 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1970167 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 47.249548 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 12499304500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 436.731895 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 12.926501 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 25.039106 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu3.inst 36.774196 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.852992 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.025247 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.048905 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu3.inst 0.071825 # Average percentage of cache occupancy +system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000291 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000061 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013772 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013629 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.024580 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu3.data 0.117441 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.042840 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.016213 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.016490 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.026861 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu3.data 0.119639 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.045229 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16094.048007 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14553.151549 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 15285.292618 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10241.080225 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36496.909143 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 48492.666170 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 49842.098949 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45643.443333 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12292.074989 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14930.651138 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13742.754964 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10966.019959 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 18870.370370 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 18196.428571 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24260.170086 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 33885.741444 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 44592.049720 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36414.597944 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19814.053160 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30648.797123 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 43320.747109 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34108.408945 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 335851 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 30410 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 12618 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 677 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 26.616817 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 44.918759 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 692039 # number of writebacks +system.cpu0.dcache.writebacks::total 692039 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 103 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 3007 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 107263 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 110373 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 47662 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 1129952 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1177614 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1644 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 2326 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 5317 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 9287 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 103 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 50669 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu3.data 1237215 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1287987 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 103 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 50669 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu3.data 1237215 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1287987 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 52014 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 75034 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 112443 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 239491 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 34780 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 55627 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 96488 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 186895 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 19172 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 15769 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 29454 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 64395 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 703 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 1452 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 2792 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4947 # 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number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 7112 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 7739 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 18275 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 2828 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 5192 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 6207 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 14227 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 6252 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 12304 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 13946 # 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average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46555.327414 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12903.687670 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14225.315492 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15399.181775 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14368.755338 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13128.022760 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 18795.110193 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14325.752149 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15467.353952 # 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Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.853048 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.025491 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.048234 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu3.inst 0.072195 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998968 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 260 # 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number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 17843952 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 10439690 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu3.inst 9892867 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 95102075 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 56925566 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 17843952 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 10439690 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu3.inst 9892867 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 95102075 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 56925566 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 17843952 # 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average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12847.623137 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12939.326204 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12857.723751 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12670.391220 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12847.623137 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12939.326204 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12857.723751 # average overall mshr miss latency +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1168,63 +1164,61 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 2014 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 2014 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 554 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1460 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 2014 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 2014 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 2014 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1648 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12287.621359 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10419.476914 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6887.691629 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::2048-4095 15 0.91% 0.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-6143 458 27.79% 28.70% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::6144-8191 116 7.04% 35.74% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::10240-12287 507 30.76% 66.50% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-14335 107 6.49% 73.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::14336-16383 75 4.55% 77.55% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-18431 12 0.73% 78.28% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::22528-24575 336 20.39% 98.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-26623 22 1.33% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1648 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 2001 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 2001 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 565 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1436 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 2001 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 2001 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 2001 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1629 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 10353.898097 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9102.917994 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5277.363913 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::2048-4095 15 0.92% 0.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-6143 529 32.47% 33.39% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::6144-8191 134 8.23% 41.62% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::10240-12287 516 31.68% 73.30% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-14335 268 16.45% 89.75% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::14336-16383 35 2.15% 91.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::22528-24575 132 8.10% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1629 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 1000016000 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1000016000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1000016000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1102 66.87% 66.87% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 546 33.13% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1648 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2014 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 1072 65.81% 65.81% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 557 34.19% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1629 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2001 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2014 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1648 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2001 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1629 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1648 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 3662 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1629 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 3630 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3812187 # DTB read hits -system.cpu1.dtb.read_misses 1742 # DTB read misses -system.cpu1.dtb.write_hits 2799792 # DTB write hits -system.cpu1.dtb.write_misses 272 # DTB write misses -system.cpu1.dtb.flush_tlb 153 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 180 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 3814262 # DTB read hits +system.cpu1.dtb.read_misses 1730 # DTB read misses +system.cpu1.dtb.write_hits 2798296 # DTB write hits +system.cpu1.dtb.write_misses 271 # DTB write misses +system.cpu1.dtb.flush_tlb 154 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 179 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1235 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1231 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 241 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 257 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 89 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3813929 # DTB read accesses -system.cpu1.dtb.write_accesses 2800064 # DTB write accesses +system.cpu1.dtb.perms_faults 87 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 3815992 # DTB read accesses +system.cpu1.dtb.write_accesses 2798567 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6611979 # DTB hits -system.cpu1.dtb.misses 2014 # DTB misses -system.cpu1.dtb.accesses 6613993 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 6612558 # DTB hits +system.cpu1.dtb.misses 2001 # DTB misses +system.cpu1.dtb.accesses 6614559 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1254,148 +1248,147 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 1033 # Table walker walks requested -system.cpu1.itb.walker.walksShort 1033 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 201 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 832 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 1033 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 1033 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 1033 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 763 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12903.669725 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10877.320310 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 7130.133618 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-6143 252 33.03% 33.03% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 198 25.95% 58.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 53 6.95% 65.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::14336-16383 68 8.91% 74.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-18431 1 0.13% 74.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 185 24.25% 99.21% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-26623 6 0.79% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 763 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 1010 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1010 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 203 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 807 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 1010 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1010 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1010 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 742 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 10898.247978 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 9294.148205 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6181.528328 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-6143 309 41.64% 41.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::6144-8191 2 0.27% 41.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 197 26.55% 68.46% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 117 15.77% 84.23% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::14336-16383 15 2.02% 86.25% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 102 13.75% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 742 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 562 73.66% 73.66% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 201 26.34% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 763 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 539 72.64% 72.64% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 203 27.36% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 742 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1033 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1033 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1010 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1010 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 763 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 763 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 1796 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 17843952 # ITB inst hits -system.cpu1.itb.inst_misses 1033 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 742 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 742 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 1752 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 17845521 # ITB inst hits +system.cpu1.itb.inst_misses 1010 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 153 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 180 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 154 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 179 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 730 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 709 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 17844985 # ITB inst accesses -system.cpu1.itb.hits 17843952 # DTB hits -system.cpu1.itb.misses 1033 # DTB misses -system.cpu1.itb.accesses 17844985 # DTB accesses -system.cpu1.numPwrStateTransitions 704 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 352 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 882103975.423295 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 11685879500.755745 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 347 98.58% 98.58% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 17846531 # ITB inst accesses +system.cpu1.itb.hits 17845521 # DTB hits +system.cpu1.itb.misses 1010 # DTB misses +system.cpu1.itb.accesses 17846531 # DTB accesses +system.cpu1.numPwrStateTransitions 702 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 351 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 884610555.122507 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 11702380509.763947 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 346 98.58% 98.58% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1000-5e+10 3 0.85% 99.43% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 2 0.57% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 156798535501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 352 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 2513250225151 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 310500599349 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 143831015 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 156798063501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 351 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 2513214226652 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 310498304848 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 143755305 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 17251961 # Number of instructions committed -system.cpu1.committedOps 20817165 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 18580086 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1666 # Number of float alu accesses -system.cpu1.num_func_calls 1994134 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2173480 # number of instructions that are conditional controls -system.cpu1.num_int_insts 18580086 # number of integer instructions -system.cpu1.num_fp_insts 1666 # number of float instructions -system.cpu1.num_int_register_reads 34430067 # number of times the integer registers were read -system.cpu1.num_int_register_writes 13026660 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1213 # number of times the floating registers were read +system.cpu1.committedInsts 17251469 # Number of instructions committed +system.cpu1.committedOps 20813754 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 18573481 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1582 # Number of float alu accesses +system.cpu1.num_func_calls 1994080 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2178225 # number of instructions that are conditional controls +system.cpu1.num_int_insts 18573481 # number of integer instructions +system.cpu1.num_fp_insts 1582 # number of float instructions +system.cpu1.num_int_register_reads 34424804 # number of times the integer registers were read +system.cpu1.num_int_register_writes 13020587 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1129 # number of times the floating registers were read system.cpu1.num_fp_register_writes 454 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 75796626 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 7400275 # number of times the CC registers were written -system.cpu1.num_mem_refs 6814833 # number of memory refs -system.cpu1.num_load_insts 3855659 # Number of load instructions -system.cpu1.num_store_insts 2959174 # Number of store instructions -system.cpu1.num_idle_cycles 136834040.067403 # Number of idle cycles -system.cpu1.num_busy_cycles 6996974.932597 # Number of busy cycles -system.cpu1.not_idle_fraction 0.048647 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.951353 # Percentage of idle cycles -system.cpu1.Branches 4280023 # Number of branches fetched -system.cpu1.op_class::No_OpClass 48 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 14598901 68.12% 68.12% # Class of executed instruction -system.cpu1.op_class::IntMult 16055 0.07% 68.20% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 990 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.20% # Class of executed instruction -system.cpu1.op_class::MemRead 3855659 17.99% 86.19% # Class of executed instruction -system.cpu1.op_class::MemWrite 2959174 13.81% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 75792524 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 7403118 # number of times the CC registers were written +system.cpu1.num_mem_refs 6816030 # number of memory refs +system.cpu1.num_load_insts 3857938 # Number of load instructions +system.cpu1.num_store_insts 2958092 # Number of store instructions +system.cpu1.num_idle_cycles 136763817.825679 # Number of idle cycles +system.cpu1.num_busy_cycles 6991487.174321 # Number of busy cycles +system.cpu1.not_idle_fraction 0.048635 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.951365 # Percentage of idle cycles +system.cpu1.Branches 4283308 # Number of branches fetched +system.cpu1.op_class::No_OpClass 49 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 14594706 68.11% 68.11% # Class of executed instruction +system.cpu1.op_class::IntMult 16119 0.08% 68.19% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 983 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.19% # Class of executed instruction +system.cpu1.op_class::MemRead 3857938 18.00% 86.20% # Class of executed instruction +system.cpu1.op_class::MemWrite 2958092 13.80% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 21430827 # Class of executed instruction -system.cpu2.branchPred.lookups 5563915 # Number of BP lookups -system.cpu2.branchPred.condPredicted 2829451 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 493242 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3244476 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 1661186 # Number of BTB hits +system.cpu1.op_class::total 21427887 # Class of executed instruction +system.cpu2.branchPred.lookups 5563559 # Number of BP lookups +system.cpu2.branchPred.condPredicted 2831152 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 495188 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3274111 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 1663178 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 51.200440 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 1571960 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 328162 # Number of incorrect RAS predictions. -system.cpu2.branchPred.indirectLookups 674670 # Number of indirect predictor lookups. -system.cpu2.branchPred.indirectHits 641704 # Number of indirect target hits. -system.cpu2.branchPred.indirectMisses 32966 # Number of indirect misses. -system.cpu2.branchPredindirectMispredicted 22004 # Number of mispredicted indirect branches. -system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu2.branchPred.BTBHitPct 50.797850 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 1571133 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 329841 # Number of incorrect RAS predictions. +system.cpu2.branchPred.indirectLookups 676012 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 643238 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 32774 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 22078 # Number of mispredicted indirect branches. +system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1425,59 +1418,58 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.cpu2.dtb.walker.walks 11911 # Table walker walks requested -system.cpu2.dtb.walker.walksShort 11911 # Table walker walks initiated with short descriptors -system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 7385 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4526 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walkWaitTime::samples 11911 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0 11911 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 11911 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 2027 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 12784.410459 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 11026.371953 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 6894.594481 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-8191 547 26.99% 26.99% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::8192-16383 1059 52.24% 79.23% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::16384-24575 401 19.78% 99.01% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::24576-32767 18 0.89% 99.90% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::81920-90111 2 0.10% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 2027 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.cpu2.dtb.walker.walks 12042 # Table walker walks requested +system.cpu2.dtb.walker.walksShort 12042 # Table walker walks initiated with short descriptors +system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 7406 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4636 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 12042 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 12042 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 12042 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 2043 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 11062.897699 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 9694.627890 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 6045.581336 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-8191 687 33.63% 33.63% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::8192-16383 1153 56.44% 90.06% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::16384-24575 200 9.79% 99.85% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::81920-90111 3 0.15% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 2043 # Table walker service (enqueue to completion) latency system.cpu2.dtb.walker.walksPending::samples 2000042500 # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::0 2000042500 100.00% 100.00% # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::total 2000042500 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 1245 61.42% 61.42% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::1M 782 38.58% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 2027 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 11911 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkPageSizes::4K 1264 61.87% 61.87% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::1M 779 38.13% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 2043 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 12042 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 11911 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2027 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 12042 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2043 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2027 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 13938 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2043 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 14085 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 4327855 # DTB read hits -system.cpu2.dtb.read_misses 10705 # DTB read misses -system.cpu2.dtb.write_hits 3342614 # DTB write hits -system.cpu2.dtb.write_misses 1206 # DTB write misses -system.cpu2.dtb.flush_tlb 153 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 143 # Number of times TLB was flushed by MVA +system.cpu2.dtb.read_hits 4331167 # DTB read hits +system.cpu2.dtb.read_misses 10867 # DTB read misses +system.cpu2.dtb.write_hits 3346265 # DTB write hits +system.cpu2.dtb.write_misses 1175 # DTB write misses +system.cpu2.dtb.flush_tlb 152 # Number of times complete TLB was flushed +system.cpu2.dtb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 1399 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 245 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 301 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 1411 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 255 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 303 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 123 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 4338560 # DTB read accesses -system.cpu2.dtb.write_accesses 3343820 # DTB write accesses +system.cpu2.dtb.perms_faults 127 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 4342034 # DTB read accesses +system.cpu2.dtb.write_accesses 3347440 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 7670469 # DTB hits -system.cpu2.dtb.misses 11911 # DTB misses -system.cpu2.dtb.accesses 7682380 # DTB accesses -system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu2.dtb.hits 7677432 # DTB hits +system.cpu2.dtb.misses 12042 # DTB misses +system.cpu2.dtb.accesses 7689474 # DTB accesses +system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1507,66 +1499,66 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.cpu2.itb.walker.walks 1348 # Table walker walks requested -system.cpu2.itb.walker.walksShort 1348 # Table walker walks initiated with short descriptors -system.cpu2.itb.walker.walksShortTerminationLevel::Level1 252 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1096 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walkWaitTime::samples 1348 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0 1348 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 1348 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 848 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 13074.292453 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 11434.302344 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 6448.856060 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::4096-6143 240 28.30% 28.30% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::6144-8191 2 0.24% 28.54% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::10240-12287 241 28.42% 56.96% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::12288-14335 61 7.19% 64.15% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::14336-16383 126 14.86% 79.01% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::22528-24575 176 20.75% 99.76% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::24576-26623 2 0.24% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 848 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.cpu2.itb.walker.walks 1330 # Table walker walks requested +system.cpu2.itb.walker.walksShort 1330 # Table walker walks initiated with short descriptors +system.cpu2.itb.walker.walksShortTerminationLevel::Level1 245 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1085 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 1330 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 1330 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 1330 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 845 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 11181.065089 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 9687.789458 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 6060.643085 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::4096-6143 346 40.95% 40.95% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::6144-8191 3 0.36% 41.30% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::10240-12287 226 26.75% 68.05% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::12288-14335 99 11.72% 79.76% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::14336-16383 48 5.68% 85.44% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::22528-24575 122 14.44% 99.88% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::24576-26623 1 0.12% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 845 # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walksPending::samples 2000028000 # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::0 2000028000 100.00% 100.00% # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::total 2000028000 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 600 70.75% 70.75% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::1M 248 29.25% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 848 # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::4K 603 71.36% 71.36% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::1M 242 28.64% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 845 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1348 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1348 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1330 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1330 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 848 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 848 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 2196 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 10441487 # ITB inst hits -system.cpu2.itb.inst_misses 1348 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 845 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 845 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 2175 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 10448237 # ITB inst hits +system.cpu2.itb.inst_misses 1330 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 153 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 143 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb 152 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 821 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 823 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1710 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1725 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 10442835 # ITB inst accesses -system.cpu2.itb.hits 10441487 # DTB hits -system.cpu2.itb.misses 1348 # DTB misses -system.cpu2.itb.accesses 10442835 # DTB accesses -system.cpu2.numPwrStateTransitions 1074 # Number of power state transitions -system.cpu2.pwrStateClkGateDist::samples 537 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::mean 5095328839.376163 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::stdev 41281959005.190056 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::underflows 492 91.62% 91.62% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::1000-5e+10 38 7.08% 98.70% # Distribution of time spent in the clock gated state +system.cpu2.itb.inst_accesses 10449567 # ITB inst accesses +system.cpu2.itb.hits 10448237 # DTB hits +system.cpu2.itb.misses 1330 # DTB misses +system.cpu2.itb.accesses 10449567 # DTB accesses +system.cpu2.numPwrStateTransitions 1076 # Number of power state transitions +system.cpu2.pwrStateClkGateDist::samples 538 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::mean 5085855532.985130 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::stdev 41244061935.633728 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::underflows 493 91.64% 91.64% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::1000-5e+10 38 7.06% 98.70% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::5e+10-1e+11 1 0.19% 98.88% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::1.5e+11-2e+11 1 0.19% 99.07% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::2e+11-2.5e+11 1 0.19% 99.26% # Distribution of time spent in the clock gated state @@ -1574,73 +1566,73 @@ system.cpu2.pwrStateClkGateDist::2.5e+11-3e+11 1 0.19% 99.44 system.cpu2.pwrStateClkGateDist::4.5e+11-5e+11 2 0.37% 99.81% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::5e+11-5.5e+11 1 0.19% 100.00% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::max_value 500052269001 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::total 537 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateResidencyTicks::ON 87559237755 # Cumulative time (in ticks) in various power states -system.cpu2.pwrStateResidencyTicks::CLK_GATED 2736191586745 # Cumulative time (in ticks) in various power states -system.cpu2.numCycles 141974504 # number of cpu cycles simulated +system.cpu2.pwrStateClkGateDist::max_value 500051113501 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::total 538 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateResidencyTicks::ON 87522254754 # Cumulative time (in ticks) in various power states +system.cpu2.pwrStateResidencyTicks::CLK_GATED 2736190276746 # Cumulative time (in ticks) in various power states +system.cpu2.numCycles 141975261 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 19185413 # Number of instructions committed -system.cpu2.committedOps 23254826 # Number of ops (including micro ops) committed -system.cpu2.discardedOps 1388377 # Number of ops (including micro ops) which were discarded before commit -system.cpu2.numFetchSuspends 540 # Number of times Execute suspended instruction fetching -system.cpu2.quiesceCycles 36744 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.cpi 7.400128 # CPI: cycles per instruction -system.cpu2.ipc 0.135133 # IPC: instructions per cycle -system.cpu2.op_class_0::No_OpClass 50 0.00% 0.00% # Class of committed instruction -system.cpu2.op_class_0::IntAlu 15529839 66.78% 66.78% # Class of committed instruction -system.cpu2.op_class_0::IntMult 18571 0.08% 66.86% # Class of committed instruction -system.cpu2.op_class_0::IntDiv 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::FloatAdd 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::FloatCmp 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::FloatCvt 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::FloatMult 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::FloatDiv 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::FloatSqrt 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdAdd 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdAddAcc 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdAlu 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdCmp 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdCvt 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdMisc 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdMult 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdMultAcc 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdShift 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdSqrt 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 66.86% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMisc 1326 0.01% 66.87% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction -system.cpu2.op_class_0::MemRead 4244552 18.25% 85.12% # Class of committed instruction -system.cpu2.op_class_0::MemWrite 3460488 14.88% 100.00% # Class of committed instruction +system.cpu2.committedInsts 19207075 # Number of instructions committed +system.cpu2.committedOps 23282264 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 1390064 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.numFetchSuspends 541 # Number of times Execute suspended instruction fetching +system.cpu2.quiesceCycles 36123 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 7.391821 # CPI: cycles per instruction +system.cpu2.ipc 0.135285 # IPC: instructions per cycle +system.cpu2.op_class_0::No_OpClass 48 0.00% 0.00% # Class of committed instruction +system.cpu2.op_class_0::IntAlu 15551874 66.80% 66.80% # Class of committed instruction +system.cpu2.op_class_0::IntMult 18578 0.08% 66.88% # Class of committed instruction +system.cpu2.op_class_0::IntDiv 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::FloatAdd 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::FloatCmp 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::FloatCvt 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::FloatMult 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::FloatDiv 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::FloatSqrt 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdAdd 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdAddAcc 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdAlu 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdCmp 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdCvt 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdMisc 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdMult 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdMultAcc 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdShift 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdSqrt 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMisc 1338 0.01% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction +system.cpu2.op_class_0::MemRead 4246805 18.24% 85.12% # Class of committed instruction +system.cpu2.op_class_0::MemWrite 3463621 14.88% 100.00% # Class of committed instruction system.cpu2.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.op_class_0::total 23254826 # Class of committed instruction +system.cpu2.op_class_0::total 23282264 # Class of committed instruction system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 38692637 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 103281867 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 13574263 # Number of BP lookups -system.cpu3.branchPred.condPredicted 7472946 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 296816 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 8409244 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 4443267 # Number of BTB hits +system.cpu2.tickCycles 38700481 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 103274780 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 13558463 # Number of BP lookups +system.cpu3.branchPred.condPredicted 7461726 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 297292 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 8389979 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 4437676 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 52.837889 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 3091382 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 16244 # Number of incorrect RAS predictions. -system.cpu3.branchPred.indirectLookups 2018293 # Number of indirect predictor lookups. -system.cpu3.branchPred.indirectHits 1956673 # Number of indirect target hits. -system.cpu3.branchPred.indirectMisses 61620 # Number of indirect misses. -system.cpu3.branchPredindirectMispredicted 18086 # Number of mispredicted indirect branches. -system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu3.branchPred.BTBHitPct 52.892576 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 3087767 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 16069 # Number of incorrect RAS predictions. +system.cpu3.branchPred.indirectLookups 2015433 # Number of indirect predictor lookups. +system.cpu3.branchPred.indirectHits 1953316 # Number of indirect target hits. +system.cpu3.branchPred.indirectMisses 62117 # Number of indirect misses. +system.cpu3.branchPredindirectMispredicted 18167 # Number of mispredicted indirect branches. +system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1670,92 +1662,93 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.cpu3.dtb.walker.walks 34289 # Table walker walks requested -system.cpu3.dtb.walker.walksShort 34289 # Table walker walks initiated with short descriptors -system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 10988 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 8074 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksSquashedBefore 15227 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 19062 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 480.983108 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 2977.429006 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-8191 18630 97.73% 97.73% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::8192-16383 285 1.50% 99.23% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::16384-24575 92 0.48% 99.71% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::24576-32767 31 0.16% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::32768-40959 6 0.03% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::40960-49151 14 0.07% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::49152-57343 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::57344-65535 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::65536-73727 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 19062 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkCompletionTime::samples 6433 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::mean 11737.913882 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::gmean 9614.193609 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::stdev 7621.962559 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::0-8191 2432 37.81% 37.81% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::8192-16383 2842 44.18% 81.98% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::16384-24575 955 14.85% 96.83% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::24576-32767 108 1.68% 98.51% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::32768-40959 45 0.70% 99.21% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::40960-49151 39 0.61% 99.81% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::49152-57343 6 0.09% 99.91% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::57344-65535 1 0.02% 99.92% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::65536-73727 2 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::81920-90111 3 0.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::total 6433 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -8544248564 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean 0.589102 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::stdev 0.347038 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-1 -8589968064 100.54% 100.54% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::2-3 32103000 -0.38% 100.16% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::4-5 6761500 -0.08% 100.08% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::6-7 2522000 -0.03% 100.05% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::8-9 1641500 -0.02% 100.03% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::10-11 647000 -0.01% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::12-13 437000 -0.01% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::14-15 926500 -0.01% 100.01% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::16-17 267500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::18-19 118000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::20-21 41000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::22-23 32500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::24-25 26000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::26-27 29500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::28-29 9000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::30-31 157500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -8544248564 # Table walker pending requests distribution -system.cpu3.dtb.walker.walkPageSizes::4K 1826 71.78% 71.78% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::1M 718 28.22% 100.00% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::total 2544 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 34289 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.cpu3.dtb.walker.walks 34483 # Table walker walks requested +system.cpu3.dtb.walker.walksShort 34483 # Table walker walks initiated with short descriptors +system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 10978 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 8165 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 15340 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 19143 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 456.015254 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 2830.743841 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-8191 18720 97.79% 97.79% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::8192-16383 307 1.60% 99.39% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::16384-24575 66 0.34% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::24576-32767 32 0.17% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::32768-40959 6 0.03% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::40960-49151 8 0.04% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::49152-57343 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::65536-73727 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::73728-81919 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::81920-90111 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::total 19143 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 6521 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 10311.301948 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 8555.831863 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 6751.449027 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-8191 2865 43.93% 43.93% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::8192-16383 2966 45.48% 89.42% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::16384-24575 551 8.45% 97.87% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::24576-32767 84 1.29% 99.16% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::32768-40959 31 0.48% 99.63% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::40960-49151 17 0.26% 99.89% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::57344-65535 1 0.02% 99.91% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::81920-90111 3 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::90112-98303 2 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::98304-106495 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::total 6521 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -8545598564 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean 0.743431 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::stdev 0.275134 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-1 -8589277064 100.51% 100.51% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::2-3 31465000 -0.37% 100.14% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-5 6055500 -0.07% 100.07% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::6-7 2113000 -0.02% 100.05% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-9 1651500 -0.02% 100.03% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::10-11 591000 -0.01% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-13 384000 -0.00% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::14-15 739000 -0.01% 100.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-17 231000 -0.00% 100.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::18-19 112500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-21 46500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::22-23 31000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-25 29500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::26-27 22000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::28-29 12000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::30-31 195000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -8545598564 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 1839 71.81% 71.81% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::1M 722 28.19% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 2561 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 34483 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 34289 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2544 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 34483 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2561 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2544 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 36833 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2561 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 37044 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 7476077 # DTB read hits -system.cpu3.dtb.read_misses 28705 # DTB read misses -system.cpu3.dtb.write_hits 5707301 # DTB write hits -system.cpu3.dtb.write_misses 5584 # DTB write misses +system.cpu3.dtb.read_hits 7471341 # DTB read hits +system.cpu3.dtb.read_misses 28725 # DTB read misses +system.cpu3.dtb.write_hits 5714088 # DTB write hits +system.cpu3.dtb.write_misses 5758 # DTB write misses system.cpu3.dtb.flush_tlb 157 # Number of times complete TLB was flushed -system.cpu3.dtb.flush_tlb_mva 231 # Number of times TLB was flushed by MVA +system.cpu3.dtb.flush_tlb_mva 225 # Number of times TLB was flushed by MVA system.cpu3.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 1654 # Number of entries that have been flushed from TLB -system.cpu3.dtb.align_faults 379 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 711 # Number of TLB faults due to prefetch +system.cpu3.dtb.flush_entries 1650 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 393 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 706 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 337 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 7504782 # DTB read accesses -system.cpu3.dtb.write_accesses 5712885 # DTB write accesses +system.cpu3.dtb.perms_faults 319 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 7500066 # DTB read accesses +system.cpu3.dtb.write_accesses 5719846 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 13183378 # DTB hits -system.cpu3.dtb.misses 34289 # DTB misses -system.cpu3.dtb.accesses 13217667 # DTB accesses -system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu3.dtb.hits 13185429 # DTB hits +system.cpu3.dtb.misses 34483 # DTB misses +system.cpu3.dtb.accesses 13219912 # DTB accesses +system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1785,220 +1778,221 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.cpu3.itb.walker.walks 4253 # Table walker walks requested -system.cpu3.itb.walker.walksShort 4253 # Table walker walks initiated with short descriptors -system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1354 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.cpu3.itb.walker.walks 4240 # Table walker walks requested +system.cpu3.itb.walker.walksShort 4240 # Table walker walks initiated with short descriptors +system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1366 # Level at which table walker walks with short descriptors terminate system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2463 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksSquashedBefore 436 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 3817 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 1262.509824 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 4945.350323 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-8191 3591 94.08% 94.08% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::8192-16383 162 4.24% 98.32% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::16384-24575 27 0.71% 99.03% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::24576-32767 17 0.45% 99.48% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-40959 8 0.21% 99.69% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::40960-49151 6 0.16% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::49152-57343 1 0.03% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::57344-65535 4 0.10% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::73728-81919 1 0.03% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 3817 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkCompletionTime::samples 1618 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 11355.377009 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 9318.464391 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 7299.331906 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::0-8191 704 43.51% 43.51% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::8192-16383 629 38.88% 82.39% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::16384-24575 254 15.70% 98.08% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::24576-32767 19 1.17% 99.26% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::32768-40959 8 0.49% 99.75% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::40960-49151 2 0.12% 99.88% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::49152-57343 1 0.06% 99.94% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksSquashedBefore 411 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 3829 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1196.395926 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 4662.983981 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-8191 3612 94.33% 94.33% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::8192-16383 152 3.97% 98.30% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::16384-24575 35 0.91% 99.22% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::24576-32767 19 0.50% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::32768-40959 3 0.08% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::40960-49151 2 0.05% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::49152-57343 2 0.05% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::57344-65535 1 0.03% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::65536-73727 2 0.05% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::81920-90111 1 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::total 3829 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkCompletionTime::samples 1597 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 10150.594865 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 8236.395815 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 7276.129645 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-8191 852 53.35% 53.35% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::8192-16383 514 32.19% 85.54% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::16384-24575 201 12.59% 98.12% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::24576-32767 13 0.81% 98.94% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::32768-40959 11 0.69% 99.62% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::40960-49151 3 0.19% 99.81% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::49152-57343 2 0.13% 99.94% # Table walker service (enqueue to completion) latency system.cpu3.itb.walker.walkCompletionTime::81920-90111 1 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::total 1618 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -4448372768 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean 0.737414 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::stdev 0.439006 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::0 -1166371868 26.22% 26.22% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 -3283428900 73.81% 100.03% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::2 1175000 -0.03% 100.01% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::3 224000 -0.01% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::4 29000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -4448372768 # Table walker pending requests distribution -system.cpu3.itb.walker.walkPageSizes::4K 844 71.40% 71.40% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::1M 338 28.60% 100.00% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::total 1182 # Table walker page sizes translated +system.cpu3.itb.walker.walkCompletionTime::total 1597 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksPending::samples -8763056564 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 0.696085 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::stdev 0.459515 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 -2661759664 30.37% 30.37% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -6102526900 69.64% 100.01% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 1039000 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 149500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 41500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -8763056564 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 846 71.33% 71.33% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::1M 340 28.67% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 1186 # Table walker page sizes translated system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4253 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4253 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4240 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4240 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1182 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1182 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 5435 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 9894210 # ITB inst hits -system.cpu3.itb.inst_misses 4253 # ITB inst misses +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1186 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1186 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 5426 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 9891489 # ITB inst hits +system.cpu3.itb.inst_misses 4240 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.write_hits 0 # DTB write hits system.cpu3.itb.write_misses 0 # DTB write misses system.cpu3.itb.flush_tlb 157 # Number of times complete TLB was flushed -system.cpu3.itb.flush_tlb_mva 231 # Number of times TLB was flushed by MVA +system.cpu3.itb.flush_tlb_mva 225 # Number of times TLB was flushed by MVA system.cpu3.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 1133 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_entries 1134 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 703 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.perms_faults 708 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 9898463 # ITB inst accesses -system.cpu3.itb.hits 9894210 # DTB hits -system.cpu3.itb.misses 4253 # DTB misses -system.cpu3.itb.accesses 9898463 # DTB accesses -system.cpu3.numPwrStateTransitions 1744 # Number of power state transitions -system.cpu3.pwrStateClkGateDist::samples 872 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::mean 24195228.891055 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::stdev 644254106.585039 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::underflows 857 98.28% 98.28% # Distribution of time spent in the clock gated state +system.cpu3.itb.inst_accesses 9895729 # ITB inst accesses +system.cpu3.itb.hits 9891489 # DTB hits +system.cpu3.itb.misses 4240 # DTB misses +system.cpu3.itb.accesses 9895729 # DTB accesses +system.cpu3.numPwrStateTransitions 1742 # Number of power state transitions +system.cpu3.pwrStateClkGateDist::samples 871 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::mean 24222914.443169 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::stdev 644616845.496373 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::underflows 856 98.28% 98.28% # Distribution of time spent in the clock gated state system.cpu3.pwrStateClkGateDist::1000-5e+10 15 1.72% 100.00% # Distribution of time spent in the clock gated state system.cpu3.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::max_value 18906661340 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::total 872 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateResidencyTicks::ON 2802652584907 # Cumulative time (in ticks) in various power states -system.cpu3.pwrStateResidencyTicks::CLK_GATED 21098239593 # Cumulative time (in ticks) in various power states -system.cpu3.numCycles 55802582 # number of cpu cycles simulated +system.cpu3.pwrStateClkGateDist::max_value 18906422924 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::total 871 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateResidencyTicks::ON 2802614373020 # Cumulative time (in ticks) in various power states +system.cpu3.pwrStateResidencyTicks::CLK_GATED 21098158480 # Cumulative time (in ticks) in various power states +system.cpu3.numCycles 55804206 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 20935031 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 53976458 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 13574263 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 9491322 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 32368112 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 1569845 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 63704 # Number of cycles fetch has spent waiting for tlb -system.cpu3.fetch.MiscStallCycles 1342 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.PendingDrainCycles 208 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 113598 # Number of stall cycles due to pending traps -system.cpu3.fetch.PendingQuiesceStallCycles 71390 # Number of stall cycles due to pending quiesce instructions -system.cpu3.fetch.IcacheWaitRetryStallCycles 235 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 9892868 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 204224 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 2239 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 54338522 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.198008 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.332788 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 20943122 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 53945813 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 13558463 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 9478759 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 32366624 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 1570295 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 59981 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 769 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 238 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 103755 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 71551 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 320 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 9890169 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 205274 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 2246 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 54331487 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.197628 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.332891 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 39853023 73.34% 73.34% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 1853402 3.41% 76.75% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 1194631 2.20% 78.95% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3690685 6.79% 85.74% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 942938 1.74% 87.48% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 608116 1.12% 88.60% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 2975810 5.48% 94.07% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 643271 1.18% 95.26% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 2576646 4.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 39855672 73.36% 73.36% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 1851434 3.41% 76.76% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 1194487 2.20% 78.96% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3686492 6.79% 85.75% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 943670 1.74% 87.48% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 608106 1.12% 88.60% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 2967627 5.46% 94.07% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 643917 1.19% 95.25% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 2580082 4.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 54338522 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.243255 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.967275 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 14662616 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 29996417 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 7962115 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 1015455 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 701676 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 1056216 # Number of times decode resolved a branch -system.cpu3.decode.BranchMispred 84320 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 46882791 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 277439 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 701676 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 15188976 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 3032843 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 21357872 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 8442903 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 5613994 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 45010257 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 711 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 1193798 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 109598 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 3924436 # Number of times rename has blocked due to SQ full -system.cpu3.rename.RenamedOperands 46943427 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 206658226 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 50584429 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 3918 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 39299455 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 7643972 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 719812 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 667882 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 5739952 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 7978184 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 6284983 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 1159177 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 1675680 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 43355264 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 518308 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 41274077 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 55092 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 6092748 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 14109869 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 54644 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 54338522 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.759573 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.457624 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 54331487 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.242965 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.966698 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 14668908 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 29986640 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 7957627 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 1016633 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 701473 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 1058313 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 84773 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 46874682 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 279635 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 701473 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 15195365 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 3032088 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 21321904 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 8439674 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 5640768 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 45002197 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 690 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 1195883 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 108366 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 3949949 # Number of times rename has blocked due to SQ full +system.cpu3.rename.RenamedOperands 46926978 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 206658489 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 50587166 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 3902 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 39299186 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 7627792 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 720809 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 668593 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 5741274 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 7971579 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 6293429 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 1156869 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 1562249 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 43347954 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 520206 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 41277545 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 55280 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 6083084 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 14076683 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 54734 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 54331487 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.759735 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.457545 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 38089201 70.10% 70.10% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 5343903 9.83% 79.93% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 4107112 7.56% 87.49% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 3342238 6.15% 93.64% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 1372760 2.53% 96.17% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 822455 1.51% 97.68% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 871489 1.60% 99.28% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 257925 0.47% 99.76% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 131439 0.24% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 38079008 70.09% 70.09% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 5345699 9.84% 79.93% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 4107348 7.56% 87.49% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 3341746 6.15% 93.64% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 1375872 2.53% 96.17% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 821998 1.51% 97.68% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 871189 1.60% 99.28% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 257716 0.47% 99.76% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 130911 0.24% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 54338522 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 54331487 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 64295 10.27% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 1 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 10.27% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 288567 46.11% 56.39% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 272927 43.61% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 64496 10.30% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 10.30% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 288888 46.14% 56.45% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 272662 43.55% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.FU_type_0::No_OpClass 61 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 27558257 66.77% 66.77% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 31168 0.08% 66.84% # Type of FU issued +system.cpu3.iq.FU_type_0::No_OpClass 62 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 27558666 66.76% 66.76% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 30979 0.08% 66.84% # Type of FU issued system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.84% # Type of FU issued system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.84% # Type of FU issued system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.84% # Type of FU issued @@ -2022,99 +2016,99 @@ system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.84% # Ty system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.84% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.84% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 2328 0.01% 66.85% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 2332 0.01% 66.85% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.85% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 66.85% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 66.85% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.85% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 7689945 18.63% 85.48% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 5992314 14.52% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 7685963 18.62% 85.47% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 5999538 14.53% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 41274077 # Type of FU issued -system.cpu3.iq.rate 0.739645 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 625790 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.015162 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 137559378 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 49989246 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 40120759 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 8180 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 4843 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 3492 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 41895381 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 4425 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 174238 # Number of loads that had data forwarded from stores +system.cpu3.iq.FU_type_0::total 41277545 # Type of FU issued +system.cpu3.iq.rate 0.739685 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 626046 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.015167 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 137559508 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 49974445 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 40123728 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 8395 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 4805 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 3602 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 41898968 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 4561 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 173439 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 1195264 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 1195 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 28361 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 579365 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 1192109 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 1191 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 28578 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 580828 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 104459 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 43794 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.rescheduledLoads 104405 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 43387 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 701676 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 2636383 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 282446 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 43936154 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 66826 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 7978184 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 6284983 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 267113 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 25993 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 250282 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 28361 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 127792 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 130048 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 257840 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 40954158 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 7560730 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 285711 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewSquashCycles 701473 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 2634873 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 283425 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 43928502 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 66531 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 7971579 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 6293429 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 268536 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 25934 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 251471 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 28578 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 127058 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 130735 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 257793 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 40956248 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 7556430 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 286903 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 62582 # number of nop insts executed -system.cpu3.iew.exec_refs 13496719 # number of memory reference insts executed -system.cpu3.iew.exec_branches 7548230 # Number of branches executed -system.cpu3.iew.exec_stores 5935989 # Number of stores executed -system.cpu3.iew.exec_rate 0.733912 # Inst execution rate -system.cpu3.iew.wb_sent 40661575 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 40124251 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 21126058 # num instructions producing a value -system.cpu3.iew.wb_consumers 37308798 # num instructions consuming a value -system.cpu3.iew.wb_rate 0.719039 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.566249 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 6107928 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 463664 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 213549 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 53039462 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.713065 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.610172 # Number of insts commited each cycle +system.cpu3.iew.exec_nop 60342 # number of nop insts executed +system.cpu3.iew.exec_refs 13498971 # number of memory reference insts executed +system.cpu3.iew.exec_branches 7544495 # Number of branches executed +system.cpu3.iew.exec_stores 5942541 # Number of stores executed +system.cpu3.iew.exec_rate 0.733928 # Inst execution rate +system.cpu3.iew.wb_sent 40664526 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 40127330 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 21123316 # num instructions producing a value +system.cpu3.iew.wb_consumers 37320445 # num instructions consuming a value +system.cpu3.iew.wb_rate 0.719074 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.565999 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 6097313 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 465472 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 213597 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 53033650 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.713199 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.610019 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 38622110 72.82% 72.82% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 6314877 11.91% 84.72% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 3213776 6.06% 90.78% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 1409463 2.66% 93.44% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 790260 1.49% 94.93% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 551904 1.04% 95.97% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 961415 1.81% 97.78% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 244563 0.46% 98.24% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 931094 1.76% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 38610990 72.80% 72.80% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 6319361 11.92% 84.72% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 3213493 6.06% 90.78% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 1410131 2.66% 93.44% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 792140 1.49% 94.93% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 553402 1.04% 95.98% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 958153 1.81% 97.78% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 245496 0.46% 98.25% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 930484 1.75% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 53039462 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 31045718 # Number of instructions committed -system.cpu3.commit.committedOps 37820561 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 53033650 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 31044800 # Number of instructions committed +system.cpu3.commit.committedOps 37823572 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 12488538 # Number of memory references committed -system.cpu3.commit.loads 6782920 # Number of loads committed -system.cpu3.commit.membars 181312 # Number of memory barriers committed -system.cpu3.commit.branches 7134012 # Number of branches committed -system.cpu3.commit.fp_insts 3283 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 32975843 # Number of committed integer instructions. -system.cpu3.commit.function_calls 1245781 # Number of function calls committed. +system.cpu3.commit.refs 12492071 # Number of memory references committed +system.cpu3.commit.loads 6779470 # Number of loads committed +system.cpu3.commit.membars 181779 # Number of memory barriers committed +system.cpu3.commit.branches 7130164 # Number of branches committed +system.cpu3.commit.fp_insts 3347 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 32983556 # Number of committed integer instructions. +system.cpu3.commit.function_calls 1245135 # Number of function calls committed. system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 25299473 66.89% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 30222 0.08% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 25299125 66.89% 66.89% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 30044 0.08% 66.97% # Class of committed instruction system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.97% # Class of committed instruction system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.97% # Class of committed instruction system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.97% # Class of committed instruction @@ -2138,36 +2132,36 @@ system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.97% # system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.97% # Class of committed instruction system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.97% # Class of committed instruction system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 2328 0.01% 66.98% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.98% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.98% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.98% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 6782920 17.93% 84.91% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 5705618 15.09% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 2332 0.01% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.97% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 6779470 17.92% 84.90% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 5712601 15.10% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 37820561 # Class of committed instruction -system.cpu3.commit.bw_lim_events 931094 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 90431014 # The number of ROB reads -system.cpu3.rob.rob_writes 89155949 # The number of ROB writes -system.cpu3.timesIdled 227288 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1464060 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 5161848397 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 31005981 # Number of Instructions Simulated -system.cpu3.committedOps 37780824 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.799736 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.799736 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.555637 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.555637 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 44884059 # number of integer regfile reads -system.cpu3.int_regfile_writes 25155589 # number of integer regfile writes -system.cpu3.fp_regfile_reads 14375 # number of floating regfile reads -system.cpu3.fp_regfile_writes 12072 # number of floating regfile writes -system.cpu3.cc_regfile_reads 144434496 # number of cc regfile reads -system.cpu3.cc_regfile_writes 15958517 # number of cc regfile writes -system.cpu3.misc_regfile_reads 98379107 # number of misc regfile reads -system.cpu3.misc_regfile_writes 343145 # number of misc regfile writes -system.iobus.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.cpu3.commit.op_class_0::total 37823572 # Class of committed instruction +system.cpu3.commit.bw_lim_events 930484 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 90425378 # The number of ROB reads +system.cpu3.rob.rob_writes 89139493 # The number of ROB writes +system.cpu3.timesIdled 227716 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1472719 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 5161848513 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 31006304 # Number of Instructions Simulated +system.cpu3.committedOps 37785076 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.799770 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.799770 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.555627 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.555627 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 44890181 # number of integer regfile reads +system.cpu3.int_regfile_writes 25156907 # number of integer regfile writes +system.cpu3.fp_regfile_reads 14457 # number of floating regfile reads +system.cpu3.fp_regfile_writes 12074 # number of floating regfile writes +system.cpu3.cc_regfile_reads 144431120 # number of cc regfile reads +system.cpu3.cc_regfile_writes 15956854 # number of cc regfile writes +system.cpu3.misc_regfile_reads 98347677 # number of misc regfile reads +system.cpu3.misc_regfile_writes 344757 # number of misc regfile writes +system.iobus.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30152 # Transaction distribution system.iobus.trans_dist::ReadResp 30152 # Transaction distribution system.iobus.trans_dist::WriteReq 59010 # Transaction distribution @@ -2218,15 +2212,15 @@ system.iobus.pkt_size_system.bridge.master::total 159093 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480085 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 29851500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 29764500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 228500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 229000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 19500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 20500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 4500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2236,32 +2230,32 @@ system.iobus.reqLayer19.occupancy 3000 # La system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 4026500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 3967500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 23286500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 23290000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 72958030 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 72552043 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 50254000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 50146000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 14338000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 14254000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 1.002565 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.002362 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 248718527509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.002565 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062660 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062660 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 248718607009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.002362 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062648 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062648 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 327996 # Number of tag accesses system.iocache.tags.data_accesses 327996 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses system.iocache.ReadReq_misses::total 220 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -2270,14 +2264,14 @@ system.iocache.demand_misses::realview.ide 36444 # system.iocache.demand_misses::total 36444 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36444 # number of overall misses system.iocache.overall_misses::total 36444 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 16295912 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 16295912 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 1689414118 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 1689414118 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 1705710030 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1705710030 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 1705710030 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1705710030 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 16061914 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 16061914 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 1680216129 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 1680216129 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 1696278043 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1696278043 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 1696278043 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1696278043 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2294,14 +2288,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 74072.327273 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 74072.327273 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 46637.978081 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 46637.978081 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 46803.589891 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 46803.589891 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 46803.589891 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 46803.589891 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 73008.700000 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 73008.700000 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 46384.058331 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 46384.058331 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 46544.782214 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 46544.782214 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 46544.782214 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 46544.782214 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2310,744 +2304,744 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 137 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 137 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 14064 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 14064 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 14201 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 14201 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 14201 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 14201 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 9445912 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 9445912 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 985358547 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 985358547 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 994804459 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 994804459 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 994804459 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 994804459 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.622727 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.622727 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.388251 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.388251 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.389666 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.389666 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.389666 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.389666 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68948.262774 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68948.262774 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70062.467790 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70062.467790 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 70051.718823 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70051.718823 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 70051.718823 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70051.718823 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 100866 # number of replacements -system.l2c.tags.tagsinuse 65104.734410 # Cycle average of tags in use -system.l2c.tags.total_refs 5134220 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 166034 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 30.922703 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 79359149000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 49022.002356 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.902695 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.002960 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4655.957926 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1835.969861 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000002 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 774.839390 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 858.475569 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 20.852845 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2233.809872 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 830.848364 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.dtb.walker 56.245543 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.itb.walker 0.001828 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2978.546484 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 1834.278716 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.748016 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000044 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.071044 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.028015 # Average percentage of cache occupancy +system.iocache.ReadReq_mshr_misses::realview.ide 135 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 135 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 13984 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 13984 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 14119 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 14119 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 14119 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 14119 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 9311914 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 9311914 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 980165529 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 980165529 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 989477443 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 989477443 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 989477443 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 989477443 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.613636 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.613636 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.386042 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.386042 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.387416 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.387416 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.387416 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.387416 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68977.140741 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68977.140741 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70091.928561 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70091.928561 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70081.269424 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70081.269424 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70081.269424 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70081.269424 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 100900 # number of replacements +system.l2c.tags.tagsinuse 65188.817028 # Cycle average of tags in use +system.l2c.tags.total_refs 5432391 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 166232 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 32.679574 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 76153677500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 0.990870 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.930107 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.003315 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4645.223340 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 20148.450289 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.003029 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 771.166553 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 6124.303836 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 20.124161 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2252.228504 # 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Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 59 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5926 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 59314 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000992 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.995895 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 45033905 # Number of tag accesses +system.l2c.tags.data_accesses 45033905 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.l2c.ReadReq_hits::cpu0.dtb.walker 3242 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1702 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 74714.285714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73170.660925 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67688.234733 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 82479.729730 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 73542.493221 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 73326.451368 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 71525.703753 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71495.521602 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70636.405335 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 75839.285714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72638.557585 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 68129.274155 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 83859.154930 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 74000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 73361.171563 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 72762.226913 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 71025.605108 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162942.157147 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 197019.980301 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202519.134132 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 192933.313315 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 89331.982197 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 113866.878100 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 112348.177269 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 108476.870894 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 349065 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 146440 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 73542.493221 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 73326.451368 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 71525.703753 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163168.516355 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 196949.240720 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202471.572555 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 192958.659371 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 89361.644274 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 113841.271131 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 112356.768966 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 108495.461818 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 344722 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 142063 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 474 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 40114 # Transaction distribution -system.membus.trans_dist::ReadResp 75665 # Transaction distribution +system.membus.trans_dist::ReadResp 75706 # Transaction distribution system.membus.trans_dist::WriteReq 27565 # Transaction distribution system.membus.trans_dist::WriteResp 27565 # Transaction distribution -system.membus.trans_dist::WritebackDirty 128699 # Transaction distribution -system.membus.trans_dist::CleanEvict 8576 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4535 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1836 # Transaction distribution -system.membus.trans_dist::ReadExReq 135474 # Transaction distribution -system.membus.trans_dist::ReadExResp 135474 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 35551 # Transaction distribution +system.membus.trans_dist::WritebackDirty 128718 # Transaction distribution +system.membus.trans_dist::CleanEvict 8591 # Transaction distribution +system.membus.trans_dist::UpgradeReq 126 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 40 # Transaction distribution +system.membus.trans_dist::ReadExReq 135468 # Transaction distribution +system.membus.trans_dist::ReadExResp 135468 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 35592 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 22160 # Transaction distribution +system.membus.trans_dist::InvalidateResp 22240 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105436 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2006 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 476553 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 584005 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95097 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 95097 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 679102 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 470452 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 577904 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95179 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 95179 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 673083 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159093 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16895100 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17058225 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2321472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2321472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19379697 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 340 # Total snoops (count) -system.membus.snoopTraffic 21632 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 342782 # Request fanout histogram -system.membus.snoop_fanout::mean 0.015424 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.123231 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16898684 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17061809 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2321600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2321600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19383409 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 336 # Total snoops (count) +system.membus.snoopTraffic 21376 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 338143 # Request fanout histogram +system.membus.snoop_fanout::mean 0.015650 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.124118 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 337495 98.46% 98.46% # Request fanout histogram -system.membus.snoop_fanout::1 5287 1.54% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 332851 98.43% 98.43% # Request fanout histogram +system.membus.snoop_fanout::1 5292 1.57% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 342782 # Request fanout histogram -system.membus.reqLayer0.occupancy 57572000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 338143 # Request fanout histogram +system.membus.reqLayer0.occupancy 57431500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 694499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 684999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 502472051 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 500677543 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 647767750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 649758250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 729588 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 720586 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3079,85 +3073,85 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5637070 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2833088 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 44773 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 304 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 304 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 5637023 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2833220 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 44733 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 306 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 306 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2823750824500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 110855 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2618591 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 111093 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2618641 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27565 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 746435 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1969655 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 146584 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2802 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 21 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2823 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296389 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296389 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1970201 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 537545 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4503 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5927985 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2623938 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 25305 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 99572 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8676800 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 252179448 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97825081 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41104 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 175440 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 350221073 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 122763 # Total snoops (count) -system.toL2Bus.snoopTraffic 6010036 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 4133801 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.021872 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.146266 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 747081 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1969505 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 146278 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2801 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2829 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296396 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296396 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1970061 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 537497 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4488 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5927533 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2623831 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24350 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 98043 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8673757 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 252159480 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97841913 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37624 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 168032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 350207049 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 125784 # Total snoops (count) +system.toL2Bus.snoopTraffic 6024500 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 4134386 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021942 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.146494 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4043386 97.81% 97.81% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 90415 2.19% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4043670 97.81% 97.81% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 90716 2.19% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4133801 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3409727455 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4134386 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3408827455 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 234412 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 230414 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1840405228 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1839308788 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 767451664 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 767442228 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10602473 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10535976 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 47179732 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 47560224 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu3.kern.inst.arm 0 # number of arm instructions executed system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 0ff6fe40b..21f94071a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.804565 # Number of seconds simulated -sim_ticks 2804565276000 # Number of ticks simulated -final_tick 2804565276000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.804492 # Number of seconds simulated +sim_ticks 2804492191000 # Number of ticks simulated +final_tick 2804492191000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 107399 # Simulator instruction rate (inst/s) -host_op_rate 130353 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2576386262 # Simulator tick rate (ticks/s) -host_mem_usage 586748 # Number of bytes of host memory used -host_seconds 1088.57 # Real time elapsed on the host -sim_insts 116911386 # Number of instructions simulated -sim_ops 141898031 # Number of ops (including micro ops) simulated +host_inst_rate 104736 # Simulator instruction rate (inst/s) +host_op_rate 127120 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2512420654 # Simulator tick rate (ticks/s) +host_mem_usage 592468 # Number of bytes of host memory used +host_seconds 1116.25 # Real time elapsed on the host +sim_insts 116911529 # Number of instructions simulated +sim_ops 141898255 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 4032 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 684608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5013536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 4544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 686976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4780808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 689856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4962016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 4288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 685888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4855432 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11175528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 684608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 686976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1371584 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8423424 # Number of bytes written to this memory +system.physmem.bytes_read::total 11202536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 689856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 685888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1375744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8427008 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8440948 # Number of bytes written to this memory +system.physmem.bytes_written::total 8444532 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 63 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10697 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 78855 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 71 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 10734 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 74702 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10779 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 78050 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 67 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10717 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 75868 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 175138 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131616 # Number of write requests responded to by this memory +system.physmem.num_reads::total 175560 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131672 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135997 # Number of write requests responded to by this memory +system.physmem.num_writes::total 136053 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 1438 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 244105 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1787634 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 244949 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1704652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 245982 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1769310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1529 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 244568 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1731305 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3984763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 244105 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 244949 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 489054 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3003469 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3994497 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 245982 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 244568 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 490550 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3004825 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6246 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3009717 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3003469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3011073 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3004825 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 1438 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 244105 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1793879 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 244949 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1704655 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 245982 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1775556 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 244568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1731308 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 342 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6994480 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 175139 # Number of read requests accepted -system.physmem.writeReqs 135997 # Number of write requests accepted -system.physmem.readBursts 175139 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 135997 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11199488 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue -system.physmem.bytesWritten 8453504 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11175592 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8440948 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 7005571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 175561 # Number of read requests accepted +system.physmem.writeReqs 136053 # Number of write requests accepted +system.physmem.readBursts 175561 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 136053 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11226560 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue +system.physmem.bytesWritten 8456704 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11202600 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8444532 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11119 # Per bank write bursts -system.physmem.perBankRdBursts::1 11081 # Per bank write bursts -system.physmem.perBankRdBursts::2 11640 # Per bank write bursts -system.physmem.perBankRdBursts::3 11194 # Per bank write bursts -system.physmem.perBankRdBursts::4 11361 # Per bank write bursts -system.physmem.perBankRdBursts::5 11364 # Per bank write bursts -system.physmem.perBankRdBursts::6 11912 # Per bank write bursts -system.physmem.perBankRdBursts::7 11778 # Per bank write bursts -system.physmem.perBankRdBursts::8 10214 # Per bank write bursts -system.physmem.perBankRdBursts::9 10385 # Per bank write bursts -system.physmem.perBankRdBursts::10 10562 # Per bank write bursts -system.physmem.perBankRdBursts::11 9757 # Per bank write bursts -system.physmem.perBankRdBursts::12 10332 # Per bank write bursts -system.physmem.perBankRdBursts::13 11401 # Per bank write bursts -system.physmem.perBankRdBursts::14 10617 # Per bank write bursts -system.physmem.perBankRdBursts::15 10275 # Per bank write bursts -system.physmem.perBankWrBursts::0 8313 # Per bank write bursts -system.physmem.perBankWrBursts::1 8440 # Per bank write bursts -system.physmem.perBankWrBursts::2 9041 # Per bank write bursts -system.physmem.perBankWrBursts::3 8539 # Per bank write bursts -system.physmem.perBankWrBursts::4 8335 # Per bank write bursts -system.physmem.perBankWrBursts::5 8538 # Per bank write bursts -system.physmem.perBankWrBursts::6 8956 # Per bank write bursts -system.physmem.perBankWrBursts::7 8814 # Per bank write bursts -system.physmem.perBankWrBursts::8 7742 # Per bank write bursts -system.physmem.perBankWrBursts::9 7782 # Per bank write bursts -system.physmem.perBankWrBursts::10 7931 # Per bank write bursts -system.physmem.perBankWrBursts::11 7392 # Per bank write bursts -system.physmem.perBankWrBursts::12 7874 # Per bank write bursts -system.physmem.perBankWrBursts::13 8749 # Per bank write bursts -system.physmem.perBankWrBursts::14 8038 # Per bank write bursts -system.physmem.perBankWrBursts::15 7602 # Per bank write bursts +system.physmem.perBankRdBursts::0 11215 # Per bank write bursts +system.physmem.perBankRdBursts::1 11147 # Per bank write bursts +system.physmem.perBankRdBursts::2 11273 # Per bank write bursts +system.physmem.perBankRdBursts::3 10737 # Per bank write bursts +system.physmem.perBankRdBursts::4 11860 # Per bank write bursts +system.physmem.perBankRdBursts::5 11441 # Per bank write bursts +system.physmem.perBankRdBursts::6 12346 # Per bank write bursts +system.physmem.perBankRdBursts::7 11875 # Per bank write bursts +system.physmem.perBankRdBursts::8 10047 # Per bank write bursts +system.physmem.perBankRdBursts::9 10348 # Per bank write bursts +system.physmem.perBankRdBursts::10 10556 # Per bank write bursts +system.physmem.perBankRdBursts::11 9541 # Per bank write bursts +system.physmem.perBankRdBursts::12 10610 # Per bank write bursts +system.physmem.perBankRdBursts::13 11371 # Per bank write bursts +system.physmem.perBankRdBursts::14 10552 # Per bank write bursts +system.physmem.perBankRdBursts::15 10496 # Per bank write bursts +system.physmem.perBankWrBursts::0 8375 # Per bank write bursts +system.physmem.perBankWrBursts::1 8461 # Per bank write bursts +system.physmem.perBankWrBursts::2 8703 # Per bank write bursts +system.physmem.perBankWrBursts::3 8182 # Per bank write bursts +system.physmem.perBankWrBursts::4 8713 # Per bank write bursts +system.physmem.perBankWrBursts::5 8565 # Per bank write bursts +system.physmem.perBankWrBursts::6 9253 # Per bank write bursts +system.physmem.perBankWrBursts::7 8873 # Per bank write bursts +system.physmem.perBankWrBursts::8 7587 # Per bank write bursts +system.physmem.perBankWrBursts::9 7750 # Per bank write bursts +system.physmem.perBankWrBursts::10 7865 # Per bank write bursts +system.physmem.perBankWrBursts::11 7197 # Per bank write bursts +system.physmem.perBankWrBursts::12 8117 # Per bank write bursts +system.physmem.perBankWrBursts::13 8726 # Per bank write bursts +system.physmem.perBankWrBursts::14 7969 # Per bank write bursts +system.physmem.perBankWrBursts::15 7800 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 2804565097500 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 2804492012500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 174583 # Read request sizes (log2) +system.physmem.readPktSize::6 175005 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 131616 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 103547 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8418 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1715 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see +system.physmem.writePktSize::6 131672 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 103754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8374 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1717 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -164,180 +164,182 @@ system.physmem.rdQLenPdf::30 0 # Wh system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 104 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 89 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 87 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 25 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64824 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 303.173639 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.438923 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.896368 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24325 37.52% 37.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16003 24.69% 62.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6580 10.15% 72.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3580 5.52% 77.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2814 4.34% 82.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1563 2.41% 84.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1120 1.73% 86.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1064 1.64% 88.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7775 11.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64824 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6666 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.249925 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 478.560077 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6664 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-8191 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::36864-38911 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6666 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6666 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.814881 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.232650 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.394597 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 11 0.17% 0.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 7 0.11% 0.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 4 0.06% 0.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 12 0.18% 0.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5751 86.27% 86.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 132 1.98% 88.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 86 1.29% 90.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 46 0.69% 90.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 272 4.08% 94.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 61 0.92% 95.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 24 0.36% 96.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 14 0.21% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 13 0.20% 96.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.12% 96.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.09% 96.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 6 0.09% 96.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 155 2.33% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.08% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.02% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.05% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 9 0.14% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.05% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 6 0.09% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 8 0.12% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.17% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6666 # Writes before turning the bus around for reads -system.physmem.totQLat 2635898000 # Total ticks spent queuing -system.physmem.totMemAccLat 5916998000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 874960000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15062.96 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::9 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7629 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64611 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 304.641624 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.481113 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 327.031220 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24202 37.46% 37.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15601 24.15% 61.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6722 10.40% 72.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3765 5.83% 77.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2815 4.36% 82.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1576 2.44% 84.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1095 1.69% 86.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1044 1.62% 87.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7791 12.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64611 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6681 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.254154 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 478.043046 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6679 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-8191 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::36864-38911 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6681 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6681 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.777878 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.220598 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.301236 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 12 0.18% 0.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 6 0.09% 0.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 6 0.09% 0.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 5 0.07% 0.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5747 86.02% 86.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 151 2.26% 88.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 95 1.42% 90.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 50 0.75% 90.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 278 4.16% 95.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 50 0.75% 95.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 23 0.34% 96.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 15 0.22% 96.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 16 0.24% 96.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 5 0.07% 96.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.01% 96.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 9 0.13% 96.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 158 2.36% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.09% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 1 0.01% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.04% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.06% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 4 0.06% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.01% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.04% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 8 0.12% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 10 0.15% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.04% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6681 # Writes before turning the bus around for reads +system.physmem.totQLat 2656456250 # Total ticks spent queuing +system.physmem.totMemAccLat 5945487500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 877075000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15143.84 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33812.96 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.99 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.01 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.98 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 33893.84 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.99 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.01 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.88 # Average write queue length when enqueuing -system.physmem.readRowHits 144615 # Number of row buffer hits during reads -system.physmem.writeRowHits 97638 # Number of row buffer hits during writes +system.physmem.avgWrQLen 11.27 # Average write queue length when enqueuing +system.physmem.readRowHits 144956 # Number of row buffer hits during reads +system.physmem.writeRowHits 97983 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.64 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.91 # Row buffer hit rate for writes -system.physmem.avgGap 9013952.41 # Average gap between requests -system.physmem.pageHitRate 78.88 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 258899760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 141264750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 713294400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 446964480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 183180260640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 77917696695 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1614387610500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1877045991225 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.283406 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2685583279000 # Time in different power states -system.physmem_0.memoryStateTime::REF 93650440000 # Time in different power states +system.physmem.writeRowHitRate 74.14 # Row buffer hit rate for writes +system.physmem.avgGap 8999890.93 # Average gap between requests +system.physmem.pageHitRate 78.98 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 256646880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 140035500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 716765400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 447930000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 183175683600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 77871232575 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1614386322750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1876994616705 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.281811 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2685576144250 # Time in different power states +system.physmem_0.memoryStateTime::REF 93648100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 25331546500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 25267936250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 231169680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 126134250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 651635400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 408952800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 183180260640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 76668612660 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1615483298250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1876750063680 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.177890 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2687409308250 # Time in different power states -system.physmem_1.memoryStateTime::REF 93650440000 # Time in different power states +system.physmem_1.actEnergy 231812280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 126484875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 651463800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 408311280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 183175683600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 76860878220 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1615272598500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1876727232555 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.186470 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2687058026250 # Time in different power states +system.physmem_1.memoryStateTime::REF 93648100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23501044250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23784590000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 768 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 768 # Number of instructions bytes read from this memory @@ -350,30 +352,30 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 274 system.realview.nvmem.bw_inst_read::total 274 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 274 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 274 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 26568186 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13757380 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 498035 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 15521852 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 8027077 # Number of BTB hits +system.cpu0.branchPred.lookups 26597024 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13781156 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 500525 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 15548162 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 8034631 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 51.714686 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 6610878 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28698 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4514253 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 4401271 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 112982 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 32075 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 51.675761 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 6612410 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28559 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 4512781 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 4401242 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 111539 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 32310 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -403,95 +405,95 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 58842 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 58842 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17810 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 14845 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 26187 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 32655 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 632.200276 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 3881.293866 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-16383 32316 98.96% 98.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-32767 258 0.79% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-49151 49 0.15% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::49152-65535 18 0.06% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-81919 10 0.03% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::81920-98303 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::98304-114687 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::114688-131071 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::147456-163839 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 32655 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 12803 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12389.596188 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 10179.754175 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7970.003099 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-8191 4327 33.80% 33.80% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::8192-16383 5843 45.64% 79.43% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-24575 2208 17.25% 96.68% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::24576-32767 213 1.66% 98.34% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-40959 113 0.88% 99.23% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::40960-49151 69 0.54% 99.77% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-57343 10 0.08% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::57344-65535 2 0.02% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-73727 2 0.02% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 58420 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 58420 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17812 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 14989 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 25619 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 32801 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 529.800921 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 3188.709692 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-8191 31978 97.49% 97.49% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-16383 569 1.73% 99.23% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-24575 144 0.44% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-32767 64 0.20% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-40959 17 0.05% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::40960-49151 11 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::49152-57343 8 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::57344-65535 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-73727 7 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 32801 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 12297 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 10850.939253 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9044.162625 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7100.469115 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-8191 4812 39.13% 39.13% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::8192-16383 6113 49.71% 88.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-24575 1067 8.68% 97.52% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::24576-32767 142 1.15% 98.67% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-40959 98 0.80% 99.47% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::40960-49151 40 0.33% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-57343 6 0.05% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::57344-65535 3 0.02% 99.87% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::73728-81919 1 0.01% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-90111 7 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::90112-98303 4 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-106495 4 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 12803 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 80889831836 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.654695 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.499418 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 80811540336 99.90% 99.90% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 53922000 0.07% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 11918500 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 4370000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 2811000 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 1565500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 964000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 1576000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 313500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 197500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-21 119500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::22-23 36500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-25 186500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::26-27 25500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-29 24000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::30-31 261500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 80889831836 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3539 69.42% 69.42% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1559 30.58% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5098 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 58842 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::81920-90111 7 0.06% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::90112-98303 3 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-106495 4 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::106496-114687 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 12297 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 80893915836 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.682843 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.485602 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 80818881836 99.91% 99.91% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 52303000 0.06% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 11277500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 4307500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 2702500 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 1677000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 813500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 1083500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 273500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 145500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-21 137500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::22-23 22500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-25 149000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::26-27 15000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-29 8000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::30-31 118500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 80893915836 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3573 69.87% 69.87% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1541 30.13% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5114 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 58420 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 58842 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5098 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 58420 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5114 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5098 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 63940 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5114 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 63534 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 13766353 # DTB read hits -system.cpu0.dtb.read_misses 49364 # DTB read misses -system.cpu0.dtb.write_hits 10259633 # DTB write hits -system.cpu0.dtb.write_misses 9478 # DTB write misses -system.cpu0.dtb.flush_tlb 182 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 441 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 13811519 # DTB read hits +system.cpu0.dtb.read_misses 49680 # DTB read misses +system.cpu0.dtb.write_hits 10255920 # DTB write hits +system.cpu0.dtb.write_misses 8740 # DTB write misses +system.cpu0.dtb.flush_tlb 180 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3387 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 892 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1297 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3407 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 831 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1345 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 658 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 13815717 # DTB read accesses -system.cpu0.dtb.write_accesses 10269111 # DTB write accesses +system.cpu0.dtb.perms_faults 681 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 13861199 # DTB read accesses +system.cpu0.dtb.write_accesses 10264660 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 24025986 # DTB hits -system.cpu0.dtb.misses 58842 # DTB misses -system.cpu0.dtb.accesses 24084828 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 24067439 # DTB hits +system.cpu0.dtb.misses 58420 # DTB misses +system.cpu0.dtb.accesses 24125859 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -521,817 +523,813 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 7885 # Table walker walks requested -system.cpu0.itb.walker.walksShort 7885 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2420 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 4556 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 909 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 6976 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1209.934060 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 4914.790808 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-8191 6588 94.44% 94.44% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-16383 240 3.44% 97.88% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-24575 86 1.23% 99.11% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-32767 32 0.46% 99.57% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-40959 14 0.20% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::40960-49151 8 0.11% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::49152-57343 3 0.04% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-73727 1 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::73728-81919 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::81920-90111 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 7709 # Table walker walks requested +system.cpu0.itb.walker.walksShort 7709 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2350 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 4518 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 841 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 6868 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1028.028538 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 4446.105505 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-8191 6539 95.21% 95.21% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-16383 228 3.32% 98.53% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-24575 54 0.79% 99.32% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-32767 25 0.36% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-40959 8 0.12% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::40960-49151 8 0.12% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::57344-65535 3 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::73728-81919 2 0.03% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::98304-106495 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 6976 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 3232 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 11727.877475 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 9548.081517 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 7530.941401 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 1404 43.44% 43.44% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1169 36.17% 79.61% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 601 18.60% 98.21% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 35 1.08% 99.29% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 11 0.34% 99.63% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 7 0.22% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-57343 3 0.09% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkWaitTime::total 6868 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 3155 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 10383.835182 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 8379.659125 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 7218.357480 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 1697 53.79% 53.79% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 897 28.43% 82.22% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 526 16.67% 98.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 22 0.70% 99.59% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 6 0.19% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 4 0.13% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 2 0.06% 99.97% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 3232 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 33645212080 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.830268 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.375687 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 5713730428 16.98% 16.98% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 27928860152 83.01% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 2282500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 253000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 59500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 26500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 33645212080 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1739 74.86% 74.86% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 584 25.14% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2323 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 3155 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 33631218080 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.664997 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.472178 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 11268855428 33.51% 33.51% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 22360574652 66.49% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 1449000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 215000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 92500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 31500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 33631218080 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1735 74.98% 74.98% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 579 25.02% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2314 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 7885 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 7885 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 7709 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 7709 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2323 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2323 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 10208 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 19916742 # ITB inst hits -system.cpu0.itb.inst_misses 7885 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2314 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2314 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 10023 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 19932883 # ITB inst hits +system.cpu0.itb.inst_misses 7709 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 182 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 441 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 180 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2222 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2198 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1235 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1360 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 19924627 # ITB inst accesses -system.cpu0.itb.hits 19916742 # DTB hits -system.cpu0.itb.misses 7885 # DTB misses -system.cpu0.itb.accesses 19924627 # DTB accesses -system.cpu0.numPwrStateTransitions 3162 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1581 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 934903714.786211 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 18749967267.112076 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1545 97.72% 97.72% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 33 2.09% 99.81% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 19940592 # ITB inst accesses +system.cpu0.itb.hits 19932883 # DTB hits +system.cpu0.itb.misses 7709 # DTB misses +system.cpu0.itb.accesses 19940592 # DTB accesses +system.cpu0.numPwrStateTransitions 3142 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1571 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 940850098.166136 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 18809432155.510696 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1535 97.71% 97.71% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 33 2.10% 99.81% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.06% 99.87% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.13% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499976755656 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1581 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 1326482502923 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1478082773077 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 106412241 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 499976941836 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1571 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 1326416686781 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 1478075504219 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 106432025 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 39807667 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 102389396 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 26568186 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 19039226 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 62026637 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3110102 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 107465 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 3850 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 421 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 155531 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 127911 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 368 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 19914927 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 350256 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3998 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 103784864 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.186876 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.290419 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 39943206 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 102521046 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 26597024 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 19048283 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 61908935 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3115038 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 100477 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 4639 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 343 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 145025 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 124692 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 417 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 19931005 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 352594 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3944 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 103785216 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.188198 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.291827 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 75488274 72.74% 72.74% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 3815041 3.68% 76.41% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 2353974 2.27% 78.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 7979190 7.69% 86.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1587719 1.53% 87.90% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 994623 0.96% 88.86% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 6057014 5.84% 94.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1019102 0.98% 95.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4489927 4.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 75467525 72.72% 72.72% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 3816070 3.68% 76.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 2355731 2.27% 78.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 7980688 7.69% 86.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1585704 1.53% 87.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 994797 0.96% 88.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 6063354 5.84% 94.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1019951 0.98% 95.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4501396 4.34% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 103784864 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.249672 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.962196 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 27473759 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 58173812 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 15291505 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1432841 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1412652 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1823499 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 144249 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 84520525 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 475248 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1412652 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 28280194 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 6736942 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 43934801 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 15910349 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 7509629 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 80887884 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 3905 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1038108 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 267593 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 5492226 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 83297539 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 373007231 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 90195870 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 6961 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 70398676 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 12898863 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1526830 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1432825 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8315442 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 14569662 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 11312381 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1968850 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2730392 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 77926980 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1058477 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 74778360 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 90763 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10627433 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 23204178 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 112737 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 103784864 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.720513 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.414461 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 103785216 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.249897 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.963254 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 27593672 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 58026004 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 15320051 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1430610 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1414570 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1827863 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 144800 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 84662278 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 478152 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1414570 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 28401012 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 6705964 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 43841646 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 15935208 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 7486513 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 81019638 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 3792 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1047421 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 274733 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 5461326 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 83455149 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 373514562 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 90323598 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 7046 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 70490289 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 12964860 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1525331 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1431631 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 8308638 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 14616199 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 11309054 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1973588 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2673938 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 78051120 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1056498 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 74882378 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 90977 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10675596 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 23316802 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 112757 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 103785216 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.721513 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.414764 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 73826337 71.13% 71.13% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10059193 9.69% 80.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 7635969 7.36% 88.18% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 6342907 6.11% 94.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2283033 2.20% 96.50% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1456613 1.40% 97.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 1481922 1.43% 99.33% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 479341 0.46% 99.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 219549 0.21% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 73772912 71.08% 71.08% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10078271 9.71% 80.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 7660438 7.38% 88.17% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 6348835 6.12% 94.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2285768 2.20% 96.49% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1455335 1.40% 97.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 1487712 1.43% 99.33% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 476853 0.46% 99.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 219092 0.21% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 103784864 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 103785216 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 96825 8.81% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 525523 47.82% 56.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 476662 43.37% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 97071 8.87% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 526414 48.10% 56.97% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 471010 43.03% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2194 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 49752146 66.53% 66.54% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57180 0.08% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 4372 0.01% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.62% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 14148422 18.92% 85.54% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 10814044 14.46% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2186 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 49813565 66.52% 66.53% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57268 0.08% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 4356 0.01% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.61% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 14194612 18.96% 85.56% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 10810388 14.44% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 74778360 # Type of FU issued -system.cpu0.iq.rate 0.702723 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1099011 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.014697 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 254516336 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 89657321 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 72555337 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 15022 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 8945 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 6550 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 75867097 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 8080 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 352646 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 74882378 # Type of FU issued +system.cpu0.iq.rate 0.703570 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1094496 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.014616 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 254720610 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 89827638 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 72651171 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 14835 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 9007 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 6569 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 75966729 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 7959 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 355417 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2054023 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2148 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2067343 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2157 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 54598 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1028244 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedStores 1028774 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 203435 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 82087 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 204196 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 85944 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1412652 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 5873643 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 655367 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 79110277 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 106917 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 14569662 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 11312381 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 551702 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 44436 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 599579 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1414570 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 5871401 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 626694 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 79236238 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 107112 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 14616199 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 11309054 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 550325 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 44645 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 570692 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 54598 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 206066 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 219140 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 425206 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 74227613 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 13928296 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 492013 # Number of squashed instructions skipped in execute +system.cpu0.iew.predictedTakenIncorrect 206831 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 220981 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 427812 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 74329730 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 13972872 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 494338 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 124820 # number of nop insts executed -system.cpu0.iew.exec_refs 24646290 # number of memory reference insts executed -system.cpu0.iew.exec_branches 14030699 # Number of branches executed -system.cpu0.iew.exec_stores 10717994 # Number of stores executed -system.cpu0.iew.exec_rate 0.697548 # Inst execution rate -system.cpu0.iew.wb_sent 73714298 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 72561887 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 37730883 # num instructions producing a value -system.cpu0.iew.wb_consumers 65693607 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.681894 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.574346 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 10582820 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 945740 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 355599 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 101354368 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.675249 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.564531 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 128620 # number of nop insts executed +system.cpu0.iew.exec_refs 24687619 # number of memory reference insts executed +system.cpu0.iew.exec_branches 14050828 # Number of branches executed +system.cpu0.iew.exec_stores 10714747 # Number of stores executed +system.cpu0.iew.exec_rate 0.698377 # Inst execution rate +system.cpu0.iew.wb_sent 73810336 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 72657740 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 37782988 # num instructions producing a value +system.cpu0.iew.wb_consumers 65726436 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.682668 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.574852 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 10630509 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 943741 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 357539 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 101347140 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.676054 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.564689 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 74626886 73.63% 73.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 12088537 11.93% 85.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 6044710 5.96% 91.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2569505 2.54% 94.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1279385 1.26% 95.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 839259 0.83% 96.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1807050 1.78% 97.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 395487 0.39% 98.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1703549 1.68% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 74567913 73.58% 73.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 12119278 11.96% 85.53% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 6061489 5.98% 91.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2574374 2.54% 94.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1279376 1.26% 95.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 838406 0.83% 96.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1806795 1.78% 97.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 395599 0.39% 98.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1703910 1.68% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 101354368 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 56197107 # Number of instructions committed -system.cpu0.commit.committedOps 68439408 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 101347140 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 56273825 # Number of instructions committed +system.cpu0.commit.committedOps 68516155 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 22799776 # Number of memory references committed -system.cpu0.commit.loads 12515639 # Number of loads committed -system.cpu0.commit.membars 380661 # Number of memory barriers committed -system.cpu0.commit.branches 13306067 # Number of branches committed -system.cpu0.commit.fp_insts 6109 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 59926267 # Number of committed integer instructions. -system.cpu0.commit.function_calls 2612600 # Number of function calls committed. +system.cpu0.commit.refs 22829136 # Number of memory references committed +system.cpu0.commit.loads 12548856 # Number of loads committed +system.cpu0.commit.membars 380096 # Number of memory barriers committed +system.cpu0.commit.branches 13320608 # Number of branches committed +system.cpu0.commit.fp_insts 6081 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 59986977 # Number of committed integer instructions. +system.cpu0.commit.function_calls 2613752 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 45579664 66.60% 66.60% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55599 0.08% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 4369 0.01% 66.69% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.69% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.69% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.69% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 12515639 18.29% 84.97% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 10284137 15.03% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 45626966 66.59% 66.59% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55700 0.08% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 4353 0.01% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.68% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 12548856 18.32% 85.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 10280280 15.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 68439408 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1703549 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 166286675 # The number of ROB reads -system.cpu0.rob.rob_writes 160474100 # The number of ROB writes -system.cpu0.timesIdled 401346 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 2627377 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2956165518 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 56115723 # Number of Instructions Simulated -system.cpu0.committedOps 68358024 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.896300 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.896300 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.527343 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.527343 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 80796649 # number of integer regfile reads -system.cpu0.int_regfile_writes 46187734 # number of integer regfile writes -system.cpu0.fp_regfile_reads 17075 # number of floating regfile reads -system.cpu0.fp_regfile_writes 13292 # number of floating regfile writes -system.cpu0.cc_regfile_reads 262559417 # number of cc regfile reads -system.cpu0.cc_regfile_writes 27235047 # number of cc regfile writes -system.cpu0.misc_regfile_reads 188679333 # number of misc regfile reads -system.cpu0.misc_regfile_writes 725405 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 851456 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.984383 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 42342080 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 851968 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 49.699144 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 68516155 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1703910 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 166404387 # The number of ROB reads +system.cpu0.rob.rob_writes 160730663 # The number of ROB writes +system.cpu0.timesIdled 403591 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 2646809 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2956150979 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 56189692 # Number of Instructions Simulated +system.cpu0.committedOps 68432022 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.894156 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.894156 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.527940 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.527940 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 80895945 # number of integer regfile reads +system.cpu0.int_regfile_writes 46256017 # number of integer regfile writes +system.cpu0.fp_regfile_reads 17128 # number of floating regfile reads +system.cpu0.fp_regfile_writes 13236 # number of floating regfile writes +system.cpu0.cc_regfile_reads 262969083 # number of cc regfile reads +system.cpu0.cc_regfile_writes 27284448 # number of cc regfile writes +system.cpu0.misc_regfile_reads 188741772 # number of misc regfile reads +system.cpu0.misc_regfile_writes 723817 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 851102 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.984391 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 42341917 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 851614 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 49.719611 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 92671500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 183.852002 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 328.132381 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.359086 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.640884 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999969 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.368893 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 327.615499 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.360095 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.639874 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 189174693 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 189174693 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 12241825 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 12926435 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25168260 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 7660735 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 8240746 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15901481 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 177973 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 185251 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 363224 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 210012 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 236500 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 446512 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 216376 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 242998 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 459374 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 19902560 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 21167181 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41069741 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20080533 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21352432 # number of overall hits -system.cpu0.dcache.overall_hits::total 41432965 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 399594 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 432990 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 832584 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1948359 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1749519 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 3697878 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 78958 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 104644 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 183602 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13682 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 13994 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 27676 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 42 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 43 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 85 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2347953 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 2182509 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4530462 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2426911 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 2287153 # number of overall misses -system.cpu0.dcache.overall_misses::total 4714064 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5954800500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6571091500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 12525892000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 86724909183 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 78793160939 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 165518070122 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 180271000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 207675500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 387946500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 854000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 810000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 1664000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 92679709683 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 85364252439 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 178043962122 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 92679709683 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 85364252439 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 178043962122 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 12641419 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 13359425 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 26000844 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 9609094 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 9990265 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 19599359 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 256931 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 289895 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 546826 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 223694 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 250494 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 474188 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 216418 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 243041 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 459459 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 22250513 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 23349690 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 45600203 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 22507444 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 23639585 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 46147029 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031610 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.032411 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.032021 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.202762 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.175122 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.188673 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.307312 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.360972 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.335759 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.061164 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.055866 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058365 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000194 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000177 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000185 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.105524 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.093471 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.099352 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.107827 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.096751 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.102153 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14902.126909 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15176.081434 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15044.598503 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44511.770769 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45037.042146 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44760.284174 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13175.778395 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14840.324425 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14017.433878 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20333.333333 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 18837.209302 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 19576.470588 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39472.557450 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 39112.898246 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 39299.294889 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 38188.342994 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 37323.367715 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 37768.677329 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1136536 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 185396 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 52540 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 2932 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.631823 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 63.231924 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 702421 # number of writebacks -system.cpu0.dcache.writebacks::total 702421 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 189399 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 219838 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 409237 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1792246 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1606080 # 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number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 213152 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 423347 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 156113 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 143439 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 299552 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 54836 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 68047 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 122883 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4173 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4897 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9070 # 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number of ReadReq MSHR uncacheable +system.cpu0.dcache.tags.tag_accesses 189170266 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 189170266 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 12276993 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 12891400 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 25168393 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 7660658 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 8240277 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15900935 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 178519 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 185010 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 363529 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 209836 # 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miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.096912 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.102136 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14958.823705 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15213.882272 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15090.748624 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44168.470186 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45490.267402 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44795.353956 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13082.389064 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14782.521346 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13940.396871 # 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number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 183848 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 53098 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 2861 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.620212 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 64.260049 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 702238 # number of writebacks +system.cpu0.dcache.writebacks::total 702238 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 190024 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 217945 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 407969 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1788584 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1610518 # 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number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 54425000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82975500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137400500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 812000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 767000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1579000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10256910369 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9775526443 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 20032436812 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11025750369 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10744583443 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 21770333812 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3299950500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3004338000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6304288500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3299950500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3004338000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6304288500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016627 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015955 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016282 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016246 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014358 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015284 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.213427 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.234730 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224720 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018655 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019549 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019127 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000194 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000177 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000185 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016463 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015272 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015853 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018711 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017963 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018328 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14231.737196 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14430.873274 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14332.000699 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46539.816473 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46706.662365 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46619.709807 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14020.716318 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14240.995194 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14142.696712 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13042.175893 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16944.149479 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15148.897464 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19333.333333 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 17837.209302 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18576.470588 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28000.781771 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27413.833897 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27711.252626 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26180.475963 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25302.924945 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25739.887834 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 202116.157285 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 202995.810811 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202534.407428 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 102333.565913 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 113525.468561 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 107378.319225 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1933722 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.561114 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 38706921 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1934234 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 20.011499 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 9780443500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 229.301603 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 282.259511 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.447855 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.551288 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999143 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3008616500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 3065906000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6074522500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7160903385 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6753725936 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13914629321 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 778587000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 955209000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1733796000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 53300000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84160500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137460500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 566500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 463000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1029500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10169519885 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9819631936 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 19989151821 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10948106885 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10774840936 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 21722947821 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3301571000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3002627500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6304198500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3301571000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3002627500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6304198500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016659 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015909 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016275 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016226 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014365 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015277 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.215686 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.232170 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224381 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018415 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020151 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019333 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000180 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000127 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000152 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016472 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015247 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.015846 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018757 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017899 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018318 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14245.208379 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14466.802248 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14356.195156 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45945.932983 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47042.328223 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46471.633083 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13963.682342 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14257.063538 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14123.805567 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12949.465500 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16662.146110 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14995.145631 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14525.641026 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14935.483871 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14707.142857 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27705.560403 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27622.496965 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27664.693317 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25893.373899 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25503.004632 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25698.263616 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 202165.880840 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 202935.083806 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202531.516047 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 102342.560446 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 113516.596726 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 107376.786292 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1935798 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.566475 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 38706343 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1936310 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 19.989745 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 9778864500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 232.011267 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 279.555207 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.453147 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.546006 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999153 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 227 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 151 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 153 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 42723428 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 42723428 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 18879325 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 19827596 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 38706921 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 18879325 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 19827596 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 38706921 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 18879325 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 19827596 # number of overall hits -system.cpu0.icache.overall_hits::total 38706921 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1034931 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 1047206 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 2082137 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1034931 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 1047206 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 2082137 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1034931 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 1047206 # number of overall misses -system.cpu0.icache.overall_misses::total 2082137 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14029669987 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14232269988 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 28261939975 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14029669987 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 14232269988 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 28261939975 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14029669987 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 14232269988 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 28261939975 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 19914256 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 20874802 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 40789058 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 19914256 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 20874802 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 40789058 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 19914256 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 20874802 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 40789058 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051969 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.050166 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.051046 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051969 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.050166 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.051046 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051969 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.050166 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.051046 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13556.140445 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13590.707070 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13573.525649 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13556.140445 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13590.707070 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13573.525649 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13556.140445 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13590.707070 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13573.525649 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 12122 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 42727106 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 42727106 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 18888703 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 19817640 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 38706343 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 18888703 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 19817640 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 38706343 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 18888703 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 19817640 # number of overall hits +system.cpu0.icache.overall_hits::total 38706343 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1041631 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 1042707 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 2084338 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1041631 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 1042707 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 2084338 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1041631 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 1042707 # number of overall misses +system.cpu0.icache.overall_misses::total 2084338 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14123286486 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14169720487 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 28293006973 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14123286486 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 14169720487 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 28293006973 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14123286486 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 14169720487 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 28293006973 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 19930334 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 20860347 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 40790681 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 19930334 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 20860347 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 40790681 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 19930334 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 20860347 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 40790681 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.052264 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.049985 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.051098 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.052264 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.049985 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.051098 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.052264 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.049985 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.051098 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13558.819281 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13589.359702 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13574.097374 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13558.819281 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13589.359702 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13574.097374 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13558.819281 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13589.359702 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13574.097374 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 11799 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 623 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 615 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.457464 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.185366 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1933722 # number of writebacks -system.cpu0.icache.writebacks::total 1933722 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 71718 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 76048 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 147766 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 71718 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 76048 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 147766 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 71718 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 76048 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 147766 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 963213 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 971158 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1934371 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 963213 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 971158 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1934371 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 963213 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 971158 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1934371 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1935798 # number of writebacks +system.cpu0.icache.writebacks::total 1935798 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 72135 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 75777 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 147912 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 72135 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 75777 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 147912 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 72135 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 75777 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 147912 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 969496 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 966930 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1936426 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 969496 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 966930 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1936426 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 969496 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 966930 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1936426 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 667 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 667 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 667 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 667 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12408483492 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 12567838491 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 24976321983 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12408483492 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 12567838491 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 24976321983 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12408483492 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 12567838491 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 24976321983 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12493413990 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 12512123492 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 25005537482 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12493413990 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 12512123492 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 25005537482 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12493413990 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 12512123492 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 25005537482 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 53482500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 53482500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 53482500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 53482500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.048368 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.046523 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047424 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.048368 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.046523 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.047424 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.048368 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.046523 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.047424 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12882.387896 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12941.085272 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12911.857127 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12882.387896 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12941.085272 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12911.857127 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12882.387896 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12941.085272 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12911.857127 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.048644 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.046353 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047472 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.048644 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.046353 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.047472 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.048644 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.046353 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.047472 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12886.503905 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12940.050978 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12913.241963 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12886.503905 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12940.050978 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12913.241963 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12886.503905 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12940.050978 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12913.241963 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80183.658171 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 80183.658171 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80183.658171 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 80183.658171 # average overall mshr uncacheable latency -system.cpu1.branchPred.lookups 27798204 # Number of BP lookups -system.cpu1.branchPred.condPredicted 14470719 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 518667 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 17368333 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 8539564 # Number of BTB hits +system.cpu1.branchPred.lookups 27768467 # Number of BP lookups +system.cpu1.branchPred.condPredicted 14444745 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 516645 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 16732156 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 8530484 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 49.167436 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 6849209 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 29775 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 4616738 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 4505967 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 110771 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 32761 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 50.982575 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 6847641 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 29585 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 4618056 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 4506231 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 111825 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 32588 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1361,91 +1359,91 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 58826 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 58826 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18872 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 14273 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 25681 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 33145 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 585.865138 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3677.608561 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-16383 32788 98.92% 98.92% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-32767 287 0.87% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-49151 48 0.14% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::49152-65535 12 0.04% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-81919 7 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::98304-114687 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::114688-131071 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-147455 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 33145 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 13049 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12961.567936 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10723.007113 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7830.239554 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 3942 30.21% 30.21% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 6071 46.52% 76.73% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 2547 19.52% 96.25% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 256 1.96% 98.21% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 106 0.81% 99.03% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 110 0.84% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 9 0.07% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-73727 2 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::81920-90111 4 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 13049 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 90145173428 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.714972 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.473357 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 90067700428 99.91% 99.91% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 53747000 0.06% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 11656000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 4441500 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 2654000 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 1196000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 758000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 1848500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 266500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 153500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-21 119500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::22-23 164000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-25 321500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::26-27 35000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-29 7500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::30-31 104500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 90145173428 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3714 69.38% 69.38% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1639 30.62% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5353 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 58826 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 59138 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 59138 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19056 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 14153 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 25929 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 33209 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 492.833268 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3043.837220 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-8191 32423 97.63% 97.63% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::8192-16383 540 1.63% 99.26% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-24575 149 0.45% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-32767 52 0.16% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-40959 16 0.05% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::40960-49151 18 0.05% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::49152-57343 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::57344-65535 2 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-73727 5 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 33209 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 12964 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 10951.828139 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9214.622989 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6533.603209 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 4889 37.71% 37.71% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 6655 51.33% 89.05% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 1022 7.88% 96.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 238 1.84% 98.77% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 117 0.90% 99.67% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 38 0.29% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-73727 1 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-90111 2 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 12964 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 90072330428 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.721128 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.470247 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 89999642928 99.92% 99.92% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 51122000 0.06% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 10756000 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 3956500 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 2349000 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 1202000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 700500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 1277500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 267000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 187000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-21 117000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::22-23 117500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-25 238000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::26-27 36000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-29 19500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::30-31 342000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 90072330428 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3730 69.60% 69.60% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1629 30.40% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5359 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 59138 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 58826 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5353 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 59138 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5359 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5353 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 64179 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5359 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 64497 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 14560023 # DTB read hits -system.cpu1.dtb.read_misses 50490 # DTB read misses -system.cpu1.dtb.write_hits 10636581 # DTB write hits -system.cpu1.dtb.write_misses 8336 # DTB write misses -system.cpu1.dtb.flush_tlb 176 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 476 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 14518023 # DTB read hits +system.cpu1.dtb.read_misses 50239 # DTB read misses +system.cpu1.dtb.write_hits 10641437 # DTB write hits +system.cpu1.dtb.write_misses 8899 # DTB write misses +system.cpu1.dtb.flush_tlb 178 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 475 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3352 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 784 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1139 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 3373 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 787 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 1128 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 621 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 14610513 # DTB read accesses -system.cpu1.dtb.write_accesses 10644917 # DTB write accesses +system.cpu1.dtb.perms_faults 610 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 14568262 # DTB read accesses +system.cpu1.dtb.write_accesses 10650336 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 25196604 # DTB hits -system.cpu1.dtb.misses 58826 # DTB misses -system.cpu1.dtb.accesses 25255430 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 25159460 # DTB hits +system.cpu1.dtb.misses 59138 # DTB misses +system.cpu1.dtb.accesses 25218598 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1475,338 +1473,344 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 7718 # Table walker walks requested -system.cpu1.itb.walker.walksShort 7718 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2370 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 4511 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 837 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 6881 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1585.234704 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 6902.284757 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-16383 6686 97.17% 97.17% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-32767 129 1.87% 99.04% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-49151 34 0.49% 99.53% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::49152-65535 16 0.23% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-81919 8 0.12% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::81920-98303 3 0.04% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-114687 3 0.04% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::114688-131071 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-147455 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 6881 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 3170 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12167.034700 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 9891.169611 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 8057.359944 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-16383 2478 78.17% 78.17% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-32767 663 20.91% 99.09% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-49151 24 0.76% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-65535 4 0.13% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::147456-163839 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 3170 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 34310573580 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.816220 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.387901 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 6310834876 18.39% 18.39% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 27996313204 81.60% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 2293000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 658500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 333500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 91000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::6 49500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 34310573580 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1756 75.27% 75.27% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 577 24.73% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2333 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 7663 # Table walker walks requested +system.cpu1.itb.walker.walksShort 7663 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2322 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 4510 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 831 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 6832 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 994.072014 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 4194.954654 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-8191 6528 95.55% 95.55% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-16383 212 3.10% 98.65% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-24575 44 0.64% 99.30% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-32767 27 0.40% 99.69% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-40959 9 0.13% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::40960-49151 4 0.06% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::49152-57343 5 0.07% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-73727 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::73728-81919 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 6832 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 3180 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 10355.188679 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 8393.071987 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 7092.645451 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 28 0.88% 0.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 1663 52.30% 53.18% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 542 17.04% 70.22% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 404 12.70% 82.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 34 1.07% 83.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 470 14.78% 98.77% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 15 0.47% 99.25% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 7 0.22% 99.47% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 6 0.19% 99.65% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.09% 99.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 5 0.16% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 3 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 3180 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 25646768488 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.764516 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.424553 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 6041654948 23.56% 23.56% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 19603312040 76.44% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 1413500 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 335000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 53000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 25646768488 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1773 75.48% 75.48% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 576 24.52% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2349 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7718 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7718 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7663 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7663 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2333 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2333 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 10051 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 20877340 # ITB inst hits -system.cpu1.itb.inst_misses 7718 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2349 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2349 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 10012 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 20862819 # ITB inst hits +system.cpu1.itb.inst_misses 7663 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 176 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 476 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 178 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 475 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2200 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2217 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1355 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1301 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 20885058 # ITB inst accesses -system.cpu1.itb.hits 20877340 # DTB hits -system.cpu1.itb.misses 7718 # DTB misses -system.cpu1.itb.accesses 20885058 # DTB accesses -system.cpu1.numPwrStateTransitions 2914 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 1457 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 836230234.840082 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 15860875866.076208 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1422 97.60% 97.60% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 32 2.20% 99.79% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 20870482 # ITB inst accesses +system.cpu1.itb.hits 20862819 # DTB hits +system.cpu1.itb.misses 7663 # DTB misses +system.cpu1.itb.accesses 20870482 # DTB accesses +system.cpu1.numPwrStateTransitions 2936 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 1468 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 829956972.596730 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 15801466276.187872 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1432 97.55% 97.55% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 33 2.25% 99.80% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.07% 99.86% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11 1 0.07% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.07% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::max_value 499953982692 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 1457 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 1586177823838 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1218387452162 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 109746430 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::total 1468 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 1586115355228 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1218376835772 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 109612747 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 40895986 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 108462285 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 27798204 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 19894740 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 64228270 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3210503 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 105636 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 7306 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 364 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 136679 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 127439 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 259 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 20874803 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 362169 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3960 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 107107154 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.215557 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.316339 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 40790032 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 108316651 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 27768467 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 19884356 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 64224291 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3206570 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 101756 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 7200 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 365 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 143510 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 122842 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 226 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 20860348 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 361284 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3826 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 106993471 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.215539 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.315939 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 77373213 72.24% 72.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 3963895 3.70% 75.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 2490638 2.33% 78.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 8243801 7.70% 85.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1611366 1.50% 87.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 1186347 1.11% 88.57% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 6289453 5.87% 94.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 1183134 1.10% 95.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4765307 4.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 77281815 72.23% 72.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 3963095 3.70% 75.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 2488318 2.33% 78.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 8243119 7.70% 85.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1612889 1.51% 87.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 1184021 1.11% 88.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 6282411 5.87% 94.45% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1182908 1.11% 95.56% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4754895 4.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 107107154 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.253295 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.988299 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 27921866 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 60067662 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 15890093 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1767595 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1459620 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1999442 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 147513 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 90274906 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 488786 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1459620 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 28874792 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 5214847 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 47170555 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 16697712 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 7689265 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 86435062 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 2196 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 1738246 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 216044 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 4936698 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 89654559 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 397922384 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 96312255 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6119 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 76275352 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13379191 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1604332 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1503289 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 10206476 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 15384658 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 11766815 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 2187303 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 2806337 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 83309557 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1151208 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 79998202 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 91456 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10920754 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 24595973 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 103002 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 107107154 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.746899 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.431011 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 106993471 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.253332 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.988176 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 27827531 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 60076040 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 15861302 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1770624 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1457723 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1995842 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 147467 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 90138607 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 489536 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1457723 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 28780463 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 5201978 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 47127740 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 16672085 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 7753197 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 86299553 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 2624 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 1735423 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 210199 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 5005527 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 89489706 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 397397955 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 96183965 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6079 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 76183985 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13305705 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1606232 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1504962 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 10217330 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 15336831 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 11768795 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 2172366 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 2803589 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 83184481 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1153102 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 79902588 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 90974 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10871346 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 24449389 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 102910 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 106993471 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.746799 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.430875 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 75017466 70.04% 70.04% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 10766554 10.05% 80.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 8172110 7.63% 87.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 6817962 6.37% 94.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2501926 2.34% 96.42% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1553712 1.45% 97.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1535084 1.43% 99.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 491946 0.46% 99.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 250394 0.23% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 74936839 70.04% 70.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 10763085 10.06% 80.10% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 8157485 7.62% 87.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 6811202 6.37% 94.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 2499268 2.34% 96.42% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1551620 1.45% 97.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1531718 1.43% 99.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 492585 0.46% 99.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 249669 0.23% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 107107154 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 106993471 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 114052 9.86% 9.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 7 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 527984 45.67% 55.53% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 514092 44.47% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 113986 9.89% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 7 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 526393 45.65% 55.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 512676 44.46% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 143 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 53728973 67.16% 67.16% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59111 0.07% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 3 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 4201 0.01% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.24% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 14948674 18.69% 85.93% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 11257095 14.07% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 151 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 53671519 67.17% 67.17% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59014 0.07% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 3 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 4219 0.01% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.25% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 14905160 18.65% 85.90% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 11262520 14.10% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 79998202 # Type of FU issued -system.cpu1.iq.rate 0.728937 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 1156135 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.014452 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 268337940 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 95424057 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 77696965 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 13209 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 7523 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5720 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 81147055 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7139 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 351994 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 79902588 # Type of FU issued +system.cpu1.iq.rate 0.728953 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 1153062 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.014431 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 268029337 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 95251361 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 77606677 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 13346 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 7483 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5728 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 81048267 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7232 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 350880 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2099522 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2035 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 51133 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1012143 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2084815 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2040 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 50958 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1010162 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 193136 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 112329 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 192812 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 110845 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1459620 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 4216196 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 746434 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 84577573 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 108382 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 15384658 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 11766815 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 582249 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 44240 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 689439 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 51133 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 222163 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 226496 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 448659 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 79436293 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 14722883 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 503246 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1457723 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 4213427 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 739361 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 84450588 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 107924 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 15336831 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 11768795 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 583687 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 43916 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 682784 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 50958 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 221001 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 225315 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 446316 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 79342272 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 14681206 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 501344 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 116808 # number of nop insts executed -system.cpu1.iew.exec_refs 25882990 # number of memory reference insts executed -system.cpu1.iew.exec_branches 14805311 # Number of branches executed -system.cpu1.iew.exec_stores 11160107 # Number of stores executed -system.cpu1.iew.exec_rate 0.723817 # Inst execution rate -system.cpu1.iew.wb_sent 78872387 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 77702685 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 41015418 # num instructions producing a value -system.cpu1.iew.wb_consumers 71702227 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.708020 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.572024 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 10950045 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 1048206 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 372999 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 104597545 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.703779 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.594224 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 113005 # number of nop insts executed +system.cpu1.iew.exec_refs 25846099 # number of memory reference insts executed +system.cpu1.iew.exec_branches 14786732 # Number of branches executed +system.cpu1.iew.exec_stores 11164893 # Number of stores executed +system.cpu1.iew.exec_rate 0.723842 # Inst execution rate +system.cpu1.iew.wb_sent 78781509 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 77612405 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 40957824 # num instructions producing a value +system.cpu1.iew.wb_consumers 71653116 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.708060 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.571613 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 10899776 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 1050192 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 371047 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 104491444 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.703761 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.593714 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 76066046 72.72% 72.72% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 12690674 12.13% 84.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6559681 6.27% 91.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 2745344 2.62% 93.75% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1426512 1.36% 95.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 937004 0.90% 96.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1881396 1.80% 97.81% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 439088 0.42% 98.23% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1851800 1.77% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 75982461 72.72% 72.72% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 12681627 12.14% 84.85% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6552474 6.27% 91.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 2740841 2.62% 93.75% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1432894 1.37% 95.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 937550 0.90% 96.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1880638 1.80% 97.82% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 438919 0.42% 98.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1844040 1.76% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 104597545 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 60869184 # Number of instructions committed -system.cpu1.commit.committedOps 73613528 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 104491444 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 60792609 # Number of instructions committed +system.cpu1.commit.committedOps 73537005 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 24039808 # Number of memory references committed -system.cpu1.commit.loads 13285136 # Number of loads committed -system.cpu1.commit.membars 433641 # Number of memory barriers committed -system.cpu1.commit.branches 14069734 # Number of branches committed -system.cpu1.commit.fp_insts 5319 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 64506591 # Number of committed integer instructions. -system.cpu1.commit.function_calls 2723384 # Number of function calls committed. +system.cpu1.commit.refs 24010649 # Number of memory references committed +system.cpu1.commit.loads 13252016 # Number of loads committed +system.cpu1.commit.membars 434207 # Number of memory barriers committed +system.cpu1.commit.branches 14055285 # Number of branches committed +system.cpu1.commit.fp_insts 5347 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 64446138 # Number of committed integer instructions. +system.cpu1.commit.function_calls 2722289 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 49512063 67.26% 67.26% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 57459 0.08% 67.34% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 49464791 67.27% 67.27% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 57349 0.08% 67.34% # Class of committed instruction system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.34% # Class of committed instruction system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.34% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.34% # Class of committed instruction @@ -1830,36 +1834,36 @@ system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.34% # system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.34% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.34% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 4198 0.01% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 13285136 18.05% 85.39% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 10754672 14.61% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 4216 0.01% 67.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.35% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 13252016 18.02% 85.37% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 10758633 14.63% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 73613528 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1851800 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 174575850 # The number of ROB reads -system.cpu1.rob.rob_writes 171636243 # The number of ROB writes -system.cpu1.timesIdled 396046 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2639276 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2436774880 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 60795663 # Number of Instructions Simulated -system.cpu1.committedOps 73540007 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.805169 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.805169 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.553965 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.553965 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 86363747 # number of integer regfile reads -system.cpu1.int_regfile_writes 49530768 # number of integer regfile writes -system.cpu1.fp_regfile_reads 16607 # number of floating regfile reads -system.cpu1.fp_regfile_writes 12960 # number of floating regfile writes -system.cpu1.cc_regfile_reads 280533576 # number of cc regfile reads -system.cpu1.cc_regfile_writes 29711691 # number of cc regfile writes -system.cpu1.misc_regfile_reads 196904196 # number of misc regfile reads -system.cpu1.misc_regfile_writes 794253 # number of misc regfile writes -system.iobus.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.cpu1.commit.op_class_0::total 73537005 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1844040 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 174349530 # The number of ROB reads +system.cpu1.rob.rob_writes 171375071 # The number of ROB writes +system.cpu1.timesIdled 393969 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2619276 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2436753643 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 60721837 # Number of Instructions Simulated +system.cpu1.committedOps 73466233 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.805162 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.805162 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.553967 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.553967 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 86273419 # number of integer regfile reads +system.cpu1.int_regfile_writes 49465455 # number of integer regfile writes +system.cpu1.fp_regfile_reads 16586 # number of floating regfile reads +system.cpu1.fp_regfile_writes 13020 # number of floating regfile writes +system.cpu1.cc_regfile_reads 280148251 # number of cc regfile reads +system.cpu1.cc_regfile_writes 29662918 # number of cc regfile writes +system.cpu1.misc_regfile_reads 196736132 # number of misc regfile reads +system.cpu1.misc_regfile_writes 795813 # number of misc regfile writes +system.iobus.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30198 # Transaction distribution system.iobus.trans_dist::ReadResp 30198 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1910,23 +1914,23 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480349 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 49485500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 49487000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 338000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 335000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 29000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 13000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 12500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 87500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 623500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 619500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 19500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) @@ -1936,40 +1940,40 @@ system.iobus.reqLayer16.occupancy 49000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6415000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6425500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38220500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38207500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187814925 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187822672 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36770000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36409 # number of replacements -system.iocache.tags.tagsinuse 0.981737 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.981311 # Cycle average of tags in use system.iocache.tags.total_refs 30 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 234297107000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.981737 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.061359 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.061359 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 234301648000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.981311 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.061332 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.061332 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328227 # Number of tag accesses system.iocache.tags.data_accesses 328227 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states system.iocache.WriteLineReq_hits::realview.ide 29 # number of WriteLineReq hits system.iocache.WriteLineReq_hits::total 29 # number of WriteLineReq hits system.iocache.demand_hits::realview.ide 29 # number of demand (read+write) hits @@ -1984,14 +1988,14 @@ system.iocache.demand_misses::realview.ide 36444 # system.iocache.demand_misses::total 36444 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36444 # number of overall misses system.iocache.overall_misses::total 36444 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31227677 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31227677 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4282542248 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4282542248 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4313769925 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4313769925 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4313769925 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4313769925 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 31226877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31226877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4279492795 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4279492795 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4310719672 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4310719672 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4310719672 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4310719672 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2008,19 +2012,19 @@ system.iocache.demand_miss_rate::realview.ide 0.999205 system.iocache.demand_miss_rate::total 0.999205 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 0.999205 # miss rate for overall accesses system.iocache.overall_miss_rate::total 0.999205 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 125412.357430 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125412.357430 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118318.614394 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118318.614394 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118367.081687 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118367.081687 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118367.081687 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118367.081687 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 191 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 125409.144578 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125409.144578 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118234.363724 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118234.363724 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 118283.384700 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118283.384700 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 118283.384700 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118283.384700 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 95.500000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36160 # number of writebacks system.iocache.writebacks::total 36160 # number of writebacks @@ -2032,14 +2036,14 @@ system.iocache.demand_mshr_misses::realview.ide 36444 system.iocache.demand_mshr_misses::total 36444 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36444 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36444 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18777677 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18777677 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2470659836 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2470659836 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2489437513 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2489437513 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2489437513 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2489437513 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18776877 # 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Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.088989 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.052277 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993761 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 66 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65180 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 66 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 372 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3219 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8979 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52594 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.001007 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994568 # 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number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 36104 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6670 # number of overall hits -system.l2c.overall_hits::cpu1.inst 960231 # number of overall hits -system.l2c.overall_hits::cpu1.data 352306 # number of overall hits -system.l2c.overall_hits::total 2694166 # number of overall hits +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75409.144578 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75409.144578 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68175.552645 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68175.552645 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68224.975442 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68224.975442 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68224.975442 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68224.975442 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 104452 # number of replacements +system.l2c.tags.tagsinuse 65213.501449 # Cycle average of tags in use +system.l2c.tags.total_refs 5432730 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169859 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 31.983763 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 79304011000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::cpu0.dtb.walker 47.675626 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999974 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4819.813719 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 29687.680351 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 45.444052 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 5864.770891 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 24747.116836 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000727 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073545 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.452998 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000693 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.089489 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.377611 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995079 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 81 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65326 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 81 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7443 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 57733 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.001236 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.996796 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 45059004 # Number of tag accesses +system.l2c.tags.data_accesses 45059004 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.l2c.ReadReq_hits::cpu0.dtb.walker 34072 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 5784 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 34667 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5734 # number of ReadReq hits +system.l2c.ReadReq_hits::total 80257 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 702238 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 702238 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 1896138 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 1896138 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 1486 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 1347 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2833 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 38 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 83730 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 74268 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 157998 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 959179 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 956058 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1915237 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 263950 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 275779 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 539729 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 34072 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 5784 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 959179 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 347680 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 34667 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5734 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 956058 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 350047 # number of demand (read+write) hits +system.l2c.demand_hits::total 2693221 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 34072 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 5784 # number of overall hits +system.l2c.overall_hits::cpu0.inst 959179 # number of overall hits +system.l2c.overall_hits::cpu0.data 347680 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 34667 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5734 # number of overall hits +system.l2c.overall_hits::cpu1.inst 956058 # number of overall hits +system.l2c.overall_hits::cpu1.data 350047 # number of overall hits +system.l2c.overall_hits::total 2693221 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 63 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 71 # number of ReadReq misses -system.l2c.ReadReq_misses::total 135 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1443 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1292 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2735 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 12 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 9 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 21 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 72336 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 67790 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140126 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 10050 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 10740 # 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number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3095805000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2819282000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5958190498 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001797 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000154 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001963 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.001600 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.953734 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.957037 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.955292 # 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average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 187399.839529 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189662.053763 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 190431.603136 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 187397.008807 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64622.935532 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96002.883989 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 106532.723700 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 100343.401563 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 355735 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 149872 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 505 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96012.740236 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 106522.475521 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 100341.885850 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 352067 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 145781 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 504 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 31794 # Transaction distribution -system.membus.trans_dist::ReadResp 68005 # Transaction distribution +system.membus.trans_dist::ReadResp 68171 # Transaction distribution system.membus.trans_dist::WriteReq 27584 # Transaction distribution system.membus.trans_dist::WriteResp 27584 # Transaction distribution -system.membus.trans_dist::WritebackDirty 131616 # Transaction distribution -system.membus.trans_dist::CleanEvict 8821 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4625 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 21 # Transaction distribution +system.membus.trans_dist::WritebackDirty 131672 # Transaction distribution +system.membus.trans_dist::CleanEvict 9189 # Transaction distribution +system.membus.trans_dist::UpgradeReq 129 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 138237 # Transaction distribution -system.membus.trans_dist::ReadExResp 138237 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 36212 # Transaction distribution +system.membus.trans_dist::ReadExReq 138492 # Transaction distribution +system.membus.trans_dist::ReadExResp 138492 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 36378 # Transaction distribution system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 24 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 467969 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 575541 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 464721 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 572293 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72868 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72868 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 648409 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 645161 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 768 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17301276 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17465309 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17331868 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17495901 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2315200 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2315200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19780509 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 523 # Total snoops (count) -system.membus.snoopTraffic 33344 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 274669 # Request fanout histogram -system.membus.snoop_fanout::mean 0.019252 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.137411 # Request fanout histogram +system.membus.pkt_size::total 19811101 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 522 # Total snoops (count) +system.membus.snoopTraffic 33280 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 270575 # Request fanout histogram +system.membus.snoop_fanout::mean 0.019532 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.138387 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 269381 98.07% 98.07% # Request fanout histogram -system.membus.snoop_fanout::1 5288 1.93% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 265290 98.05% 98.05% # Request fanout histogram +system.membus.snoop_fanout::1 5285 1.95% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 274669 # Request fanout histogram -system.membus.reqLayer0.occupancy 95445000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 270575 # Request fanout histogram +system.membus.reqLayer0.occupancy 95437500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 18156 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1705498 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1702998 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 921900685 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 917027178 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1007122750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1009264500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1322824 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1323623 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -2615,88 +2616,88 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5612083 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2825755 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 47584 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 189 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 189 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 5615366 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2827339 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 47526 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 188 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 188 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2804565276000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 149636 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2639439 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 149674 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2641289 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 797877 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1933722 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 157607 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2864 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 85 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2948 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296722 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296722 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1934371 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 555503 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4762 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5803440 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2678918 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 36089 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 166154 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8684601 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 247577728 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99675933 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 52660 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 284944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 347591265 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 142991 # Total snoops (count) -system.toL2Bus.snoopTraffic 6276420 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 3079674 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.027770 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.164315 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 797750 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1935798 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 157804 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2842 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 70 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2911 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296610 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296610 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1936426 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 555260 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4760 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5809649 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2677780 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 34247 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 164021 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8685697 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 247843584 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99641501 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 46076 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 275476 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 347806637 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 147441 # Total snoops (count) +system.toL2Bus.snoopTraffic 6294736 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 3081797 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.027693 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.164091 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2994150 97.22% 97.22% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 85524 2.78% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2996454 97.23% 97.23% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 85343 2.77% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3079674 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 5529901884 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3081797 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5533506883 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 310676 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 309877 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2904308481 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2907318131 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1324888971 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1324202245 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 22963918 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 22762929 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 95377065 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 95604083 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3038 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 3039 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 864e3d209..539176c94 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,170 +1,170 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.445489 # Number of seconds simulated -sim_ticks 47445489241000 # Number of ticks simulated -final_tick 47445489241000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.276773 # Number of seconds simulated +sim_ticks 47276772827000 # Number of ticks simulated +final_tick 47276772827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 208966 # Simulator instruction rate (inst/s) -host_op_rate 245756 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10881126125 # Simulator tick rate (ticks/s) -host_mem_usage 759660 # Number of bytes of host memory used -host_seconds 4360.35 # Real time elapsed on the host -sim_insts 911162440 # Number of instructions simulated -sim_ops 1071583187 # Number of ops (including micro ops) simulated +host_inst_rate 146674 # Simulator instruction rate (inst/s) +host_op_rate 172507 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7728246229 # Simulator tick rate (ticks/s) +host_mem_usage 772984 # Number of bytes of host memory used +host_seconds 6117.40 # Real time elapsed on the host +sim_insts 897262562 # Number of instructions simulated +sim_ops 1055295890 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 163648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 157696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 8375360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 16685256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 18550592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 100224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 74048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2844864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 7994832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 10895744 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory -system.physmem.bytes_read::total 66279064 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 8375360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2844864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11220224 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 78621824 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 117376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 90560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 7953664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 13400200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 16005120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 165760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 157376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3942400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 13075216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 14708224 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 454784 # Number of bytes read from this memory +system.physmem.bytes_read::total 70070680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 7953664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3942400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 11896064 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 81443392 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 78642408 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2557 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2464 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 130865 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 260720 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 289853 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1566 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1157 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 44451 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 124932 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 170246 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1035636 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1228466 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 81463976 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1834 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1415 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 124276 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 209391 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 250080 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2590 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2459 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 61600 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 204313 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 229816 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 7106 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1094880 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1272553 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1231040 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3449 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 3324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 176526 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 351672 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 390987 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2112 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1561 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 59961 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 168506 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 229648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1396952 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 176526 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 59961 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 236487 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1657098 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1275127 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1916 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 168236 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 283442 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 338541 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3329 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 83390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 276567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 311109 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1482138 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 168236 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 83390 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 251626 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1722694 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1657532 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1657098 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 3324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 176526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 352106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 390987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2112 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1561 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 59961 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 168506 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 229648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3054484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1035636 # Number of read requests accepted -system.physmem.writeReqs 1231040 # Number of write requests accepted -system.physmem.readBursts 1035636 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1231040 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 66252160 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 28544 # Total number of bytes read from write queue -system.physmem.bytesWritten 78640192 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 66279064 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 78642408 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 446 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2268 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1723129 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1722694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1916 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 168236 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 283877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 338541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3506 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3329 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 83390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 276568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 311109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3205266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1094880 # Number of read requests accepted +system.physmem.writeReqs 1275127 # Number of write requests accepted +system.physmem.readBursts 1094880 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1275127 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 70042240 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 30080 # Total number of bytes read from write queue +system.physmem.bytesWritten 81461504 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 70070680 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 81463976 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 470 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2260 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 59521 # Per bank write bursts -system.physmem.perBankRdBursts::1 66808 # Per bank write bursts -system.physmem.perBankRdBursts::2 62154 # Per bank write bursts -system.physmem.perBankRdBursts::3 70128 # Per bank write bursts -system.physmem.perBankRdBursts::4 60732 # Per bank write bursts -system.physmem.perBankRdBursts::5 72109 # Per bank write bursts -system.physmem.perBankRdBursts::6 58717 # Per bank write bursts -system.physmem.perBankRdBursts::7 62140 # Per bank write bursts -system.physmem.perBankRdBursts::8 50595 # Per bank write bursts -system.physmem.perBankRdBursts::9 107916 # Per bank write bursts -system.physmem.perBankRdBursts::10 54809 # Per bank write bursts -system.physmem.perBankRdBursts::11 63010 # Per bank write bursts -system.physmem.perBankRdBursts::12 57730 # Per bank write bursts -system.physmem.perBankRdBursts::13 64314 # Per bank write bursts -system.physmem.perBankRdBursts::14 61474 # Per bank write bursts -system.physmem.perBankRdBursts::15 63033 # Per bank write bursts -system.physmem.perBankWrBursts::0 75175 # Per bank write bursts -system.physmem.perBankWrBursts::1 80913 # Per bank write bursts -system.physmem.perBankWrBursts::2 75568 # Per bank write bursts -system.physmem.perBankWrBursts::3 82272 # Per bank write bursts -system.physmem.perBankWrBursts::4 75546 # Per bank write bursts -system.physmem.perBankWrBursts::5 83102 # Per bank write bursts -system.physmem.perBankWrBursts::6 75765 # Per bank write bursts -system.physmem.perBankWrBursts::7 76740 # Per bank write bursts -system.physmem.perBankWrBursts::8 69114 # Per bank write bursts -system.physmem.perBankWrBursts::9 73138 # Per bank write bursts -system.physmem.perBankWrBursts::10 71733 # Per bank write bursts -system.physmem.perBankWrBursts::11 77960 # Per bank write bursts -system.physmem.perBankWrBursts::12 74616 # Per bank write bursts -system.physmem.perBankWrBursts::13 78881 # Per bank write bursts -system.physmem.perBankWrBursts::14 78631 # Per bank write bursts -system.physmem.perBankWrBursts::15 79599 # Per bank write bursts +system.physmem.perBankRdBursts::0 60604 # Per bank write bursts +system.physmem.perBankRdBursts::1 71691 # Per bank write bursts +system.physmem.perBankRdBursts::2 59265 # Per bank write bursts +system.physmem.perBankRdBursts::3 66946 # Per bank write bursts +system.physmem.perBankRdBursts::4 67906 # Per bank write bursts +system.physmem.perBankRdBursts::5 80109 # Per bank write bursts +system.physmem.perBankRdBursts::6 61949 # Per bank write bursts +system.physmem.perBankRdBursts::7 69447 # Per bank write bursts +system.physmem.perBankRdBursts::8 60494 # Per bank write bursts +system.physmem.perBankRdBursts::9 115448 # Per bank write bursts +system.physmem.perBankRdBursts::10 56514 # Per bank write bursts +system.physmem.perBankRdBursts::11 69665 # Per bank write bursts +system.physmem.perBankRdBursts::12 63387 # Per bank write bursts +system.physmem.perBankRdBursts::13 66346 # Per bank write bursts +system.physmem.perBankRdBursts::14 64421 # Per bank write bursts +system.physmem.perBankRdBursts::15 60218 # Per bank write bursts +system.physmem.perBankWrBursts::0 77101 # Per bank write bursts +system.physmem.perBankWrBursts::1 84577 # Per bank write bursts +system.physmem.perBankWrBursts::2 74746 # Per bank write bursts +system.physmem.perBankWrBursts::3 81276 # Per bank write bursts +system.physmem.perBankWrBursts::4 79990 # Per bank write bursts +system.physmem.perBankWrBursts::5 87328 # Per bank write bursts +system.physmem.perBankWrBursts::6 77464 # Per bank write bursts +system.physmem.perBankWrBursts::7 81707 # Per bank write bursts +system.physmem.perBankWrBursts::8 78209 # Per bank write bursts +system.physmem.perBankWrBursts::9 81569 # Per bank write bursts +system.physmem.perBankWrBursts::10 73819 # Per bank write bursts +system.physmem.perBankWrBursts::11 80687 # Per bank write bursts +system.physmem.perBankWrBursts::12 78674 # Per bank write bursts +system.physmem.perBankWrBursts::13 80970 # Per bank write bursts +system.physmem.perBankWrBursts::14 77560 # Per bank write bursts +system.physmem.perBankWrBursts::15 77159 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 48 # Number of times write queue was full causing retry -system.physmem.totGap 47445487151500 # Total gap between requests +system.physmem.numWrRetry 62 # Number of times write queue was full causing retry +system.physmem.totGap 47276770796500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1035606 # Read request sizes (log2) +system.physmem.readPktSize::6 1094850 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1228466 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 692790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 121307 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 45775 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 35632 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 30940 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 28399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 26620 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 23199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 20889 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3694 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1663 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 944 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 702 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 419 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 350 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 273 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 228 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1272553 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 725931 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 132585 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 49587 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 38066 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 32959 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 30077 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 28140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 24582 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 22148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1854 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1222 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 970 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -189,174 +189,172 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 27376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 51705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 59824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 65779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 68512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 70877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 72860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 75714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 75511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 79365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 82384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 78677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 77306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 82372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 73265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 67472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 64363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 423 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 144 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1012110 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 143.157878 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 97.072288 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 192.644368 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 686114 67.79% 67.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 195882 19.35% 87.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 47037 4.65% 91.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20980 2.07% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15295 1.51% 95.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9865 0.97% 96.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6724 0.66% 97.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5499 0.54% 97.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24714 2.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1012110 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60277 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 17.173764 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 160.670576 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60274 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 26459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 34937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 52906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 61188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 67814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 70802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 73289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 75619 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 78304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 78281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 81577 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 85157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 81436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 80619 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 87129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 77597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 71470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 67901 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 212 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1013795 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 149.441747 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 100.507639 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 197.056675 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 662057 65.30% 65.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 208347 20.55% 85.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52181 5.15% 91.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 23884 2.36% 93.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 17639 1.74% 95.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11113 1.10% 96.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7357 0.73% 96.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6249 0.62% 97.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24968 2.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1013795 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 63452 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 17.247415 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 156.483425 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 63450 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60277 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60277 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.385105 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.691366 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.394945 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 52026 86.31% 86.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 2335 3.87% 90.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 778 1.29% 91.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 614 1.02% 92.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 994 1.65% 94.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 490 0.81% 94.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 334 0.55% 95.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 282 0.47% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 206 0.34% 96.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 170 0.28% 96.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 135 0.22% 96.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 158 0.26% 97.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 477 0.79% 97.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 137 0.23% 98.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 123 0.20% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 110 0.18% 98.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 87 0.14% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 84 0.14% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 91 0.15% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 102 0.17% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 72 0.12% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 71 0.12% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 64 0.11% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 59 0.10% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 43 0.07% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 45 0.07% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 41 0.07% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 40 0.07% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 47 0.08% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 20 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 11 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 5 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 4 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 8 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60277 # Writes before turning the bus around for reads -system.physmem.totQLat 35377622933 # Total ticks spent queuing -system.physmem.totMemAccLat 54787435433 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5175950000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34175.00 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 63452 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 63452 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.059825 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.482738 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.878895 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 55385 87.29% 87.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 2264 3.57% 90.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 727 1.15% 92.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 608 0.96% 92.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 1019 1.61% 94.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 457 0.72% 95.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 338 0.53% 95.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 295 0.46% 96.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 198 0.31% 96.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 179 0.28% 96.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 127 0.20% 97.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 154 0.24% 97.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 464 0.73% 98.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 118 0.19% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 142 0.22% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 119 0.19% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 89 0.14% 98.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 71 0.11% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 72 0.11% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 80 0.13% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 103 0.16% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 73 0.12% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 46 0.07% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 54 0.09% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 48 0.08% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 39 0.06% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 53 0.08% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 25 0.04% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 49 0.08% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 20 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 13 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 6 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 63452 # Writes before turning the bus around for reads +system.physmem.totQLat 38795138463 # Total ticks spent queuing +system.physmem.totMemAccLat 59315325963 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5472050000 # Total ticks spent in databus transfers +system.physmem.avgQLat 35448.45 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 52925.00 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.40 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.66 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.40 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.66 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 54198.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.48 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.72 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.48 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.72 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.61 # Average write queue length when enqueuing -system.physmem.readRowHits 780044 # Number of row buffer hits during reads -system.physmem.writeRowHits 471783 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.35 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 38.39 # Row buffer hit rate for writes -system.physmem.avgGap 20931746.38 # Average gap between requests -system.physmem.pageHitRate 55.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3937837680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2148621750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3995955600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4050479520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3098908325760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1191842451045 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27421814259750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31726697931105 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.697958 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45618359398995 # Time in different power states -system.physmem_0.memoryStateTime::REF 1584308960000 # Time in different power states +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.57 # Average write queue length when enqueuing +system.physmem.readRowHits 817920 # Number of row buffer hits during reads +system.physmem.writeRowHits 535530 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.74 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 42.07 # Row buffer hit rate for writes +system.physmem.avgGap 19947945.64 # Average gap between requests +system.physmem.pageHitRate 57.17 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3880003680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2117065500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4195752600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4174344720 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3087888847680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1190314271070 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27321927289500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31614497574750 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.711016 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45452122728628 # Time in different power states +system.physmem_0.memoryStateTime::REF 1578675280000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 242820245005 # Time in different power states +system.physmem_0.memoryStateTime::ACT 245973030122 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3713615640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2026278375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4078440600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3911723280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3098908325760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1186342158240 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27426639078000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31725619619895 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.675231 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45626361005854 # Time in different power states -system.physmem_1.memoryStateTime::REF 1584308960000 # Time in different power states +system.physmem_1.actEnergy 3784278960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2064834750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4340583000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4073632560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3087888847680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1186461286245 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27325307092500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31613920555695 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.698811 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45457733356018 # Time in different power states +system.physmem_1.memoryStateTime::REF 1578675280000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 234814164146 # Time in different power states +system.physmem_1.memoryStateTime::ACT 240362584982 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory @@ -372,41 +370,41 @@ system.realview.nvmem.num_reads::cpu1.data 1 # system.realview.nvmem.num_reads::total 27 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 13 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 14 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 29 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 13 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 14 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 28 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 13 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 14 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 29 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1674 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 160314756 # Number of BP lookups -system.cpu0.branchPred.condPredicted 112651620 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 7238532 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 119384108 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 83018284 # Number of BTB hits +system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1670 # Number of DMA write transactions. +system.cpu0.branchPred.lookups 132137665 # Number of BP lookups +system.cpu0.branchPred.condPredicted 93617551 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5999845 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 98810350 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 69427031 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 69.538807 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 19042266 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1248322 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4272460 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2939923 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 1332537 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 468796 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 70.262914 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15260285 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1044115 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 3387017 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2259695 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 1127322 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 409659 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -436,63 +434,64 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 329365 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 329365 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11619 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 95372 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 329365 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 329365 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 329365 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 106991 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 23090.091690 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 21491.120734 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 15706.739319 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 105441 98.55% 98.55% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1327 1.24% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 42 0.04% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 76 0.07% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 69 0.06% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 15 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 14 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 271762 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 271762 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10351 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 74846 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 271762 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 271762 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 271762 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 85197 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 23819.195512 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 22123.263295 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 14060.055266 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 84296 98.94% 98.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 776 0.91% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 35 0.04% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 41 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 35 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 106991 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 85197 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 734573704 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 734573704 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 734573704 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 95372 89.14% 89.14% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 11619 10.86% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 106991 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 329365 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 74846 87.85% 87.85% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10351 12.15% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 85197 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 271762 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 329365 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106991 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 271762 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85197 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106991 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 436356 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85197 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 356959 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 103710651 # DTB read hits -system.cpu0.dtb.read_misses 276993 # DTB read misses -system.cpu0.dtb.write_hits 90811723 # DTB write hits -system.cpu0.dtb.write_misses 52372 # DTB write misses +system.cpu0.dtb.read_hits 82756248 # DTB read hits +system.cpu0.dtb.read_misses 224730 # DTB read misses +system.cpu0.dtb.write_hits 74117187 # DTB write hits +system.cpu0.dtb.write_misses 47032 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 43240 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1075 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 42132 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 2205 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 11314 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 42591 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 34573 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 2108 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9506 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 11590 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 103987644 # DTB read accesses -system.cpu0.dtb.write_accesses 90864095 # DTB write accesses +system.cpu0.dtb.perms_faults 11030 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 82980978 # DTB read accesses +system.cpu0.dtb.write_accesses 74164219 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 194522374 # DTB hits -system.cpu0.dtb.misses 329365 # DTB misses -system.cpu0.dtb.accesses 194851739 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 156873435 # DTB hits +system.cpu0.dtb.misses 271762 # DTB misses +system.cpu0.dtb.accesses 157145197 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -522,912 +521,906 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 72209 # Table walker walks requested -system.cpu0.itb.walker.walksLong 72209 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 611 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59557 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 72209 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 72209 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 72209 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 60168 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 25971.338585 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23756.230706 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 17963.019846 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 55134 91.63% 91.63% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 3439 5.72% 97.35% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 6 0.01% 97.36% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 1442 2.40% 99.76% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 23 0.04% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 16 0.03% 99.82% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 52 0.09% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 23 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 12 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 4 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 60168 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 60398 # Table walker walks requested +system.cpu0.itb.walker.walksLong 60398 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 589 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51882 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 60398 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 60398 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 60398 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 52471 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 25793.819443 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 24019.609428 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 15089.787613 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 46836 89.26% 89.26% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 4750 9.05% 98.31% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 22 0.04% 98.36% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 772 1.47% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 22 0.04% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 15 0.03% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 26 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 9 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 9 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 52471 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 733851204 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 733851204 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 733851204 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 59557 98.98% 98.98% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 611 1.02% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 60168 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 51882 98.88% 98.88% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 589 1.12% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 52471 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 72209 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 72209 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60398 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60398 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60168 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60168 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 132377 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 285203366 # ITB inst hits -system.cpu0.itb.inst_misses 72209 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52471 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52471 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 112869 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 234456044 # ITB inst hits +system.cpu0.itb.inst_misses 60398 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 43240 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1075 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 30424 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 42591 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 24118 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 190431 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 160109 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 285275575 # ITB inst accesses -system.cpu0.itb.hits 285203366 # DTB hits -system.cpu0.itb.misses 72209 # DTB misses -system.cpu0.itb.accesses 285275575 # DTB accesses -system.cpu0.numPwrStateTransitions 26302 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 13151 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 3564690271.200593 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 65409151988.663887 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3759 28.58% 28.58% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 9361 71.18% 99.76% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.77% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.78% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 4 0.03% 99.81% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.82% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 2 0.02% 99.84% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 18 0.14% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 234516442 # ITB inst accesses +system.cpu0.itb.hits 234456044 # DTB hits +system.cpu0.itb.misses 60398 # DTB misses +system.cpu0.itb.accesses 234516442 # DTB accesses +system.cpu0.numPwrStateTransitions 8178 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 4089 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 11447226771.455124 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 162386644618.467285 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 2836 69.36% 69.36% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 1230 30.08% 99.44% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.46% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.05% 99.51% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.05% 99.56% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.58% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.61% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.63% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.66% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 14 0.34% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 1988779311380 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 13151 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 566247484441 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46879241756559 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 1132534446 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 7470355608744 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 4089 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 469062558520 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46807710268480 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 938130839 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 532076805 # Number of instructions committed -system.cpu0.committedOps 624758290 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 52154793 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 4664 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93759282538 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.128517 # CPI: cycles per instruction -system.cpu0.ipc 0.469811 # IPC: instructions per cycle -system.cpu0.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.op_class_0::IntAlu 432780145 69.27% 69.27% # Class of committed instruction -system.cpu0.op_class_0::IntMult 1412970 0.23% 69.50% # Class of committed instruction -system.cpu0.op_class_0::IntDiv 69899 0.01% 69.51% # Class of committed instruction -system.cpu0.op_class_0::FloatAdd 0 0.00% 69.51% # Class of committed instruction -system.cpu0.op_class_0::FloatCmp 0 0.00% 69.51% # Class of committed instruction -system.cpu0.op_class_0::FloatCvt 0 0.00% 69.51% # Class of committed instruction -system.cpu0.op_class_0::FloatMult 0 0.00% 69.51% # Class of committed instruction -system.cpu0.op_class_0::FloatDiv 0 0.00% 69.51% # Class of committed instruction -system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.51% # Class of committed instruction -system.cpu0.op_class_0::SimdAdd 0 0.00% 69.51% # Class of committed instruction -system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.51% # Class of committed instruction -system.cpu0.op_class_0::SimdAlu 0 0.00% 69.51% # Class of committed instruction -system.cpu0.op_class_0::SimdCmp 0 0.00% 69.51% # Class of committed instruction -system.cpu0.op_class_0::SimdCvt 0 0.00% 69.51% # Class of committed instruction -system.cpu0.op_class_0::SimdMisc 0 0.00% 69.51% # Class of committed instruction -system.cpu0.op_class_0::SimdMult 0 0.00% 69.51% # Class of committed instruction -system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.51% # Class of committed instruction -system.cpu0.op_class_0::SimdShift 0 0.00% 69.51% # Class of committed instruction -system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.51% # Class of committed instruction -system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.51% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.51% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.51% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.51% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.51% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.51% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMisc 79522 0.01% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu0.op_class_0::MemRead 99981749 16.00% 85.52% # Class of committed instruction -system.cpu0.op_class_0::MemWrite 90434005 14.48% 100.00% # Class of committed instruction +system.cpu0.committedInsts 430200528 # Number of instructions committed +system.cpu0.committedOps 505771410 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 45690974 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 3904 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93616054941 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.180683 # CPI: cycles per instruction +system.cpu0.ipc 0.458572 # IPC: instructions per cycle +system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction +system.cpu0.op_class_0::IntAlu 351125189 69.42% 69.42% # Class of committed instruction +system.cpu0.op_class_0::IntMult 1073769 0.21% 69.64% # Class of committed instruction +system.cpu0.op_class_0::IntDiv 52983 0.01% 69.65% # Class of committed instruction +system.cpu0.op_class_0::FloatAdd 0 0.00% 69.65% # Class of committed instruction +system.cpu0.op_class_0::FloatCmp 0 0.00% 69.65% # Class of committed instruction +system.cpu0.op_class_0::FloatCvt 0 0.00% 69.65% # Class of committed instruction +system.cpu0.op_class_0::FloatMult 0 0.00% 69.65% # Class of committed instruction +system.cpu0.op_class_0::FloatDiv 0 0.00% 69.65% # Class of committed instruction +system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.65% # Class of committed instruction +system.cpu0.op_class_0::SimdAdd 0 0.00% 69.65% # Class of committed instruction +system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.65% # Class of committed instruction +system.cpu0.op_class_0::SimdAlu 0 0.00% 69.65% # Class of committed instruction +system.cpu0.op_class_0::SimdCmp 0 0.00% 69.65% # Class of committed instruction +system.cpu0.op_class_0::SimdCvt 0 0.00% 69.65% # Class of committed instruction +system.cpu0.op_class_0::SimdMisc 0 0.00% 69.65% # Class of committed instruction +system.cpu0.op_class_0::SimdMult 0 0.00% 69.65% # Class of committed instruction +system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.65% # Class of committed instruction +system.cpu0.op_class_0::SimdShift 0 0.00% 69.65% # Class of committed instruction +system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.65% # Class of committed instruction +system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.65% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAdd 8 0.00% 69.65% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.65% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCmp 13 0.00% 69.65% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCvt 21 0.00% 69.65% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.65% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMisc 68782 0.01% 69.66% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.66% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.66% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.66% # Class of committed instruction +system.cpu0.op_class_0::MemRead 79655364 15.75% 85.41% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 73795280 14.59% 100.00% # Class of committed instruction system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.op_class_0::total 624758290 # Class of committed instruction +system.cpu0.op_class_0::total 505771410 # Class of committed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13151 # number of quiesce instructions executed -system.cpu0.tickCycles 847175236 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 285359210 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 6574289 # number of replacements -system.cpu0.dcache.tags.tagsinuse 508.066535 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 184992173 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6574801 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.136543 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 4089 # number of quiesce instructions executed +system.cpu0.tickCycles 697846091 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 240284748 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 5497391 # number of replacements +system.cpu0.dcache.tags.tagsinuse 500.377946 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 148839422 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5497903 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.072035 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 5039429000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.066535 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992317 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.992317 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.377946 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977301 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.977301 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 383 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 392594755 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 392594755 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 95401287 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 95401287 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 84287466 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 84287466 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 321965 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 321965 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 280846 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 280846 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2060188 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 2060188 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2061125 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 2061125 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 179969599 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 179969599 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 180291564 # number of overall hits -system.cpu0.dcache.overall_hits::total 180291564 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3840217 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3840217 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2718306 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2718306 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 733729 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 733729 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 858022 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 858022 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 199658 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 199658 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 197397 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 197397 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 7416545 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 7416545 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 8150274 # number of overall misses -system.cpu0.dcache.overall_misses::total 8150274 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 59779296000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 59779296000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 54754909500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 54754909500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 28457275000 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 28457275000 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2995014000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2995014000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4953933500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4953933500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3818500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3818500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 142991480500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 142991480500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 142991480500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 142991480500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 99241504 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 99241504 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 87005772 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 87005772 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1055694 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1055694 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1138868 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1138868 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2259846 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2259846 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2258522 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2258522 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 187386144 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 187386144 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 188441838 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 188441838 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038696 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.038696 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031243 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.031243 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.695021 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.695021 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.753399 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.753399 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088350 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088350 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.087401 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.087401 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.039579 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.039579 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.043251 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.043251 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15566.645322 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15566.645322 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20143.026392 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20143.026392 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33166.136766 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33166.136766 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15000.721233 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15000.721233 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25096.295790 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25096.295790 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 316768421 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 316768421 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 75978032 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 75978032 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 68482955 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 68482955 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 264842 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 264842 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 244065 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 244065 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1687572 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1687572 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1654235 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1654235 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 144705052 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 144705052 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 144969894 # number of overall hits +system.cpu0.dcache.overall_hits::total 144969894 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3066734 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3066734 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2419958 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2419958 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 670609 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 670609 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 786129 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 786129 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 148878 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 148878 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 181031 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 181031 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 6272821 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 6272821 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 6943430 # number of overall misses +system.cpu0.dcache.overall_misses::total 6943430 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 47243422000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 47243422000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 49248110500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 49248110500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 26231986000 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 26231986000 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2187373500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2187373500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4323764500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4323764500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2754000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2754000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 122723518500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 122723518500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 122723518500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 122723518500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 79044766 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 79044766 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 70902913 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 70902913 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 935451 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 935451 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1030194 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1030194 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1836450 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1836450 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1835266 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1835266 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 150977873 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 150977873 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 151913324 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 151913324 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038797 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.038797 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.034131 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.034131 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.716883 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.716883 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.763088 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.763088 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.081068 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.081068 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098640 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098640 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.041548 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.041548 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.045707 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.045707 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15405.125453 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15405.125453 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20350.812080 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20350.812080 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33368.551472 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33368.551472 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14692.389070 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14692.389070 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23884.111009 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23884.111009 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19280.066460 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19280.066460 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17544.377097 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17544.377097 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19564.326561 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19564.326561 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17674.768594 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17674.768594 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 6574291 # number of writebacks -system.cpu0.dcache.writebacks::total 6574291 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 237792 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 237792 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1117306 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1117306 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 90 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 90 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 48445 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 48445 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 60 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 60 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1355188 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1355188 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1355188 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1355188 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3602425 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3602425 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1601000 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1601000 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 732137 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 732137 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 857932 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 857932 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 151213 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 151213 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 197337 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 197337 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 6061357 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 6061357 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 6793494 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 6793494 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29793 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29793 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 29400 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 29400 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 59193 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 59193 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 50925119500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50925119500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 31536308500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 31536308500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16544300500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16544300500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 27594364000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 27594364000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1964885000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1964885000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4754516500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4754516500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3441500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3441500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 110055792000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 110055792000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 126600092500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 126600092500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5675765000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5675765000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5675765000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5675765000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036300 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036300 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018401 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018401 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.693513 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.693513 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.753320 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.753320 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.066913 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.066913 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.087374 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.087374 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032347 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032347 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036051 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.036051 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14136.344129 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14136.344129 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19697.881636 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19697.881636 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22597.274144 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22597.274144 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32163.812517 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32163.812517 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12994.153942 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12994.153942 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24093.385934 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24093.385934 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5497393 # number of writebacks +system.cpu0.dcache.writebacks::total 5497393 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 200047 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 200047 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1012976 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1012976 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 94 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 94 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 39271 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 39271 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 90 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 90 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1213117 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1213117 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1213117 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1213117 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2866687 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2866687 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1406982 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1406982 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 668415 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 668415 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 786035 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 786035 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 109607 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 109607 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 180941 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 180941 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5059704 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5059704 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5728119 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5728119 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20634 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20634 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 22275 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 22275 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 42909 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 42909 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 39457015000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 39457015000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27671793000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27671793000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15966528000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15966528000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 25439405000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 25439405000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1452927000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1452927000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4140525000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4140525000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2476500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2476500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 92568213000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 92568213000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 108534741000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 108534741000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4015086500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4015086500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4015086500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4015086500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036267 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036267 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019844 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019844 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.714538 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.714538 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.762997 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.762997 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059684 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059684 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098591 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098591 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033513 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033513 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037706 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.037706 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13763.977372 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13763.977372 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19667.481887 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19667.481887 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23887.147954 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23887.147954 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32364.214062 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32364.214062 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13255.786583 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13255.786583 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22883.287923 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22883.287923 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18156.955942 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18156.955942 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18635.490441 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18635.490441 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190506.662639 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190506.662639 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95885.746625 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95885.746625 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 10998491 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.932591 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 274007938 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 10999003 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 24.912070 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 22037323000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932591 # Average occupied blocks per requestor +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18295.183473 # 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number of replacements +system.cpu0.icache.tags.tagsinuse 511.932285 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 225009210 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 9281120 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 24.243756 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 22204306000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932285 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999868 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999868 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 207 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 79 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 581012885 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 581012885 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 274007938 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 274007938 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 274007938 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 274007938 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 274007938 # number of overall hits -system.cpu0.icache.overall_hits::total 274007938 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 10999003 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 10999003 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 10999003 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 10999003 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 10999003 # number of overall misses -system.cpu0.icache.overall_misses::total 10999003 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 111429437000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 111429437000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 111429437000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 111429437000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 111429437000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 111429437000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 285006941 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 285006941 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 285006941 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 285006941 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 285006941 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 285006941 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038592 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.038592 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038592 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.038592 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038592 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.038592 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10130.867043 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10130.867043 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10130.867043 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10130.867043 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10130.867043 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10130.867043 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 477861809 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 477861809 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 225009210 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 225009210 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 225009210 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 225009210 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 225009210 # number of overall hits +system.cpu0.icache.overall_hits::total 225009210 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 9281130 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 9281130 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 9281130 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 9281130 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 9281130 # number of overall misses +system.cpu0.icache.overall_misses::total 9281130 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 94226606500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 94226606500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 94226606500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 94226606500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 94226606500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 94226606500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 234290340 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 234290340 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 234290340 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 234290340 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 234290340 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 234290340 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039614 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.039614 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039614 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.039614 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039614 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.039614 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10152.492908 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10152.492908 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10152.492908 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10152.492908 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10152.492908 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10152.492908 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 10998491 # number of writebacks -system.cpu0.icache.writebacks::total 10998491 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 10999003 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 10999003 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 10999003 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 10999003 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 10999003 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 10999003 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 9280608 # number of writebacks +system.cpu0.icache.writebacks::total 9280608 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9281130 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 9281130 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 9281130 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 9281130 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 9281130 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 9281130 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52300 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 52300 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52300 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 52300 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 105929935500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 105929935500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 105929935500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 105929935500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 105929935500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 105929935500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 89586042000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 89586042000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 89586042000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 89586042000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 89586042000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 89586042000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4836784500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4836784500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4836784500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 4836784500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038592 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038592 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038592 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.038592 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038592 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.038592 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9630.867043 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9630.867043 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9630.867043 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9630.867043 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9630.867043 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9630.867043 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039614 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039614 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039614 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.039614 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039614 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.039614 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9652.492962 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9652.492962 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9652.492962 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9652.492962 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9652.492962 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9652.492962 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92481.539197 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92481.539197 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92481.539197 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92481.539197 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 8833822 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8835143 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 1166 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7507862 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7509065 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 1069 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1192777 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 3147716 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16192.217188 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 27546589 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 3163437 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 8.707804 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 942183 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 2584098 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15590.889787 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 13248667 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2600019 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 5.095604 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 5661168000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15379.701531 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 70.199902 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 67.449935 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 674.865820 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.938702 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004285 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004117 # 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mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.038304 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.057948 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.073593 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.253885 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.130924 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.038304 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.057948 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.073593 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.253885 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.177578 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31964.749945 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36773.233810 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33942.280254 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48247.921077 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48247.921077 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20579.127566 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20579.127566 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16567.541334 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16567.541334 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 588999.800000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 588999.800000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41547.435606 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41547.435606 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 27916.187063 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27916.187063 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30232.016808 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30232.016808 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33273.354564 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33273.354564 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31964.749945 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36773.233810 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 27916.187063 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32548.114608 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30864.262300 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31964.749945 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36773.233810 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 27916.187063 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32548.114608 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48247.921077 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35770.124238 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.183830 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25044.765562 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28622.126588 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26207.203520 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49101.672698 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49101.672698 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18404.407019 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18404.407019 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15359.648034 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15359.648034 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 672666.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 672666.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40319.771067 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40319.771067 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28744.946005 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28744.946005 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29230.500946 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29230.500946 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33177.583784 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33177.583784 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25044.765562 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28622.126588 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28744.946005 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31672.597112 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30556.137615 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25044.765562 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28622.126588 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28744.946005 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31672.597112 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49101.672698 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35893.492134 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84481.539197 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182497.298023 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 120053.189675 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186571.047785 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 113364.020896 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84481.539197 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91854.476036 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 88395.921717 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 36072564 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 18399437 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3515 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 2427957 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2427386 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 571 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 1003133 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 16585926 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 29400 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 29400 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 6083435 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 13283967 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 3350152 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1133444 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 490495 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 347636 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 543136 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1366077 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1342549 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 10999003 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5499511 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 903440 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 855584 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 33101096 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21166131 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 412052 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1345098 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 56024377 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1411186752 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 800229141 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1569912 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5118984 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 2218104789 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 7999072 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 122429440 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 26916994 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.103450 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.304616 # Request fanout histogram +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89717.937962 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 86841.490825 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 30377137 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 15497883 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2826 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 666100 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 666086 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 14 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 826394 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 13852976 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 22275 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 22275 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5277668 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 11102490 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1369040 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 998456 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 452524 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 330100 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 496609 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1203701 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1179860 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9281130 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4723846 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 838465 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 784086 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 27947466 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17813968 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 344869 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1089699 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 47196002 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1191298304 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 667170422 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1315256 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4133624 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1863917606 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 5747559 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 110232304 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 21648150 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.044453 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.206103 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 24132997 89.66% 89.66% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2783426 10.34% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 571 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 20685836 95.55% 95.55% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 962300 4.45% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 14 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 26916994 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 35963769502 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 21648150 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 30255355989 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 196401052 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 202143120 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 16580139110 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 14002739292 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 9441182874 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7861824025 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 215851922 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 180564794 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 705346257 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 573087816 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 118915951 # Number of BP lookups -system.cpu1.branchPred.condPredicted 85033049 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5367569 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 89750040 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 63411692 # Number of BTB hits +system.cpu1.branchPred.lookups 142890193 # Number of BP lookups +system.cpu1.branchPred.condPredicted 101173603 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6378415 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 107083119 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 74895456 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 70.653664 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 13468810 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 887929 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 3084567 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 1998882 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1085685 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 396796 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 69.941422 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16732142 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 1061167 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 3812146 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2601182 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1210964 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 435637 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1457,69 +1450,63 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 246313 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 246313 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8582 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 75463 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 246313 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 246313 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 246313 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 84045 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 22346.070557 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21064.042846 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 12361.258067 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 79296 94.35% 94.35% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 4004 4.76% 99.11% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 175 0.21% 99.32% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 458 0.54% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 22 0.03% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 12 0.01% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 27 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 10 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 13 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 13 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 84045 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -766256056 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -766256056 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -766256056 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 75463 89.79% 89.79% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 8582 10.21% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 84045 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 246313 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 301450 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 301450 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 14052 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94528 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 301450 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 301450 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 301450 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 108580 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23842.945294 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21967.326975 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 15932.247293 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 107036 98.58% 98.58% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1312 1.21% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 57 0.05% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 69 0.06% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 74 0.07% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 19 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 9 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 108580 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -588118056 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -588118056 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -588118056 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 94528 87.06% 87.06% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 14052 12.94% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 108580 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 301450 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 246313 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84045 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 301450 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 108580 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84045 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 330358 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 108580 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 410030 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 74020776 # DTB read hits -system.cpu1.dtb.read_misses 200548 # DTB read misses -system.cpu1.dtb.write_hits 65603987 # DTB write hits -system.cpu1.dtb.write_misses 45765 # DTB write misses +system.cpu1.dtb.read_hits 92214946 # DTB read hits +system.cpu1.dtb.read_misses 251350 # DTB read misses +system.cpu1.dtb.write_hits 79863458 # DTB write hits +system.cpu1.dtb.write_misses 50100 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 43240 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1075 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 34845 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 889 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 6796 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 42591 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 41485 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1017 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 8355 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11277 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 74221324 # DTB read accesses -system.cpu1.dtb.write_accesses 65649752 # DTB write accesses +system.cpu1.dtb.perms_faults 11459 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 92466296 # DTB read accesses +system.cpu1.dtb.write_accesses 79913558 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 139624763 # DTB hits -system.cpu1.dtb.misses 246313 # DTB misses -system.cpu1.dtb.accesses 139871076 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 172078404 # DTB hits +system.cpu1.dtb.misses 301450 # DTB misses +system.cpu1.dtb.accesses 172379854 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1549,899 +1536,892 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 60327 # Table walker walks requested -system.cpu1.itb.walker.walksLong 60327 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 545 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 52409 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 60327 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 60327 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 60327 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 52954 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 24879.980738 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 23402.458623 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 13318.614145 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 48523 91.63% 91.63% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 3764 7.11% 98.74% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 13 0.02% 98.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 577 1.09% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 18 0.03% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 8 0.02% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 20 0.04% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 20 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 68405 # Table walker walks requested +system.cpu1.itb.walker.walksLong 68405 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 536 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57692 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 68405 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 68405 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 68405 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 58228 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 26184.473106 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23792.146832 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18243.083639 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 52664 90.44% 90.44% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 3935 6.76% 97.20% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 14 0.02% 97.23% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 1454 2.50% 99.72% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 38 0.07% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 17 0.03% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 63 0.11% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 12 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 10 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 10 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 3 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 52954 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -766782556 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -766782556 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -766782556 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 52409 98.97% 98.97% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 545 1.03% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 52954 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 58228 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -588816556 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -588816556 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -588816556 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 57692 99.08% 99.08% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 536 0.92% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 58228 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60327 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60327 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 68405 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 68405 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 52954 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 52954 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 113281 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 210682225 # ITB inst hits -system.cpu1.itb.inst_misses 60327 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58228 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58228 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 126633 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 253981708 # ITB inst hits +system.cpu1.itb.inst_misses 68405 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 43240 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1075 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 24520 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 42591 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 29878 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 163777 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 186858 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 210742552 # ITB inst accesses -system.cpu1.itb.hits 210682225 # DTB hits -system.cpu1.itb.misses 60327 # DTB misses -system.cpu1.itb.accesses 210742552 # DTB accesses -system.cpu1.numPwrStateTransitions 10392 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 5196 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 9053828227.255966 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 188730440437.234528 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3531 67.96% 67.96% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1645 31.66% 99.62% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 9 0.17% 99.79% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.81% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.83% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.02% 99.85% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.02% 99.87% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 7 0.13% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 254050113 # ITB inst accesses +system.cpu1.itb.hits 253981708 # DTB hits +system.cpu1.itb.misses 68405 # DTB misses +system.cpu1.itb.accesses 254050113 # DTB accesses +system.cpu1.numPwrStateTransitions 29008 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 14504 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 3226000342.121070 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 122202778079.734619 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 4515 31.13% 31.13% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 9966 68.71% 99.84% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 7 0.05% 99.89% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.91% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.92% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.92% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.93% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 10 0.07% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 7351146453012 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 5196 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 401797772178 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 47043691468822 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 803603609 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 11813587669000 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 14504 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 486863864876 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 46789908962124 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 973770006 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 379085635 # Number of instructions committed -system.cpu1.committedOps 446824897 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 44295367 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 4823 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 94088042190 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.119847 # CPI: cycles per instruction -system.cpu1.ipc 0.471732 # IPC: instructions per cycle -system.cpu1.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction -system.cpu1.op_class_0::IntAlu 309274392 69.22% 69.22% # Class of committed instruction -system.cpu1.op_class_0::IntMult 866353 0.19% 69.41% # Class of committed instruction -system.cpu1.op_class_0::IntDiv 49212 0.01% 69.42% # Class of committed instruction -system.cpu1.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction -system.cpu1.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction -system.cpu1.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction -system.cpu1.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction -system.cpu1.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction -system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction -system.cpu1.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction -system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction -system.cpu1.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction -system.cpu1.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction -system.cpu1.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction -system.cpu1.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction -system.cpu1.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction -system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction -system.cpu1.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction -system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction -system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAdd 8 0.00% 69.42% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCmp 13 0.00% 69.42% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCvt 21 0.00% 69.42% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMisc 34424 0.01% 69.43% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction -system.cpu1.op_class_0::MemRead 71272038 15.95% 85.38% # Class of committed instruction -system.cpu1.op_class_0::MemWrite 65328435 14.62% 100.00% # Class of committed instruction +system.cpu1.committedInsts 467062034 # Number of instructions committed +system.cpu1.committedOps 549524480 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 49354477 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 5829 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 93580668477 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.084884 # CPI: cycles per instruction +system.cpu1.ipc 0.479643 # IPC: instructions per cycle +system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu1.op_class_0::IntAlu 379758717 69.11% 69.11% # Class of committed instruction +system.cpu1.op_class_0::IntMult 1174710 0.21% 69.32% # Class of committed instruction +system.cpu1.op_class_0::IntDiv 62873 0.01% 69.33% # Class of committed instruction +system.cpu1.op_class_0::FloatAdd 0 0.00% 69.33% # Class of committed instruction +system.cpu1.op_class_0::FloatCmp 0 0.00% 69.33% # Class of committed instruction +system.cpu1.op_class_0::FloatCvt 0 0.00% 69.33% # Class of committed instruction +system.cpu1.op_class_0::FloatMult 0 0.00% 69.33% # Class of committed instruction +system.cpu1.op_class_0::FloatDiv 0 0.00% 69.33% # Class of committed instruction +system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.33% # Class of committed instruction +system.cpu1.op_class_0::SimdAdd 0 0.00% 69.33% # Class of committed instruction +system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.33% # Class of committed instruction +system.cpu1.op_class_0::SimdAlu 0 0.00% 69.33% # Class of committed instruction +system.cpu1.op_class_0::SimdCmp 0 0.00% 69.33% # Class of committed instruction +system.cpu1.op_class_0::SimdCvt 0 0.00% 69.33% # Class of committed instruction +system.cpu1.op_class_0::SimdMisc 0 0.00% 69.33% # Class of committed instruction +system.cpu1.op_class_0::SimdMult 0 0.00% 69.33% # Class of committed instruction +system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.33% # Class of committed instruction +system.cpu1.op_class_0::SimdShift 0 0.00% 69.33% # Class of committed instruction +system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.33% # Class of committed instruction +system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.33% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 69.33% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.33% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 69.33% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 69.33% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.33% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMisc 42788 0.01% 69.34% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.34% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.34% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.34% # Class of committed instruction +system.cpu1.op_class_0::MemRead 88942339 16.19% 85.53% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 79543053 14.47% 100.00% # Class of committed instruction system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.op_class_0::total 446824897 # Class of committed instruction +system.cpu1.op_class_0::total 549524480 # Class of committed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5196 # number of quiesce instructions executed -system.cpu1.tickCycles 627540865 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 176062744 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 4660684 # number of replacements -system.cpu1.dcache.tags.tagsinuse 434.489996 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 132775101 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 4661196 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.485200 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8377585211000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 434.489996 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.848613 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.848613 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 281793929 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 281793929 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 67965873 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 67965873 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 61015488 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 61015488 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 190971 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 190971 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 44349 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 44349 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1561438 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1561438 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1518539 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1518539 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 129025710 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 129025710 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 129216681 # number of overall hits -system.cpu1.dcache.overall_hits::total 129216681 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2729495 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2729495 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2149690 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2149690 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 616052 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 616052 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 399927 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 399927 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 143085 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 143085 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 184951 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 184951 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5279112 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5279112 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5895164 # number of overall misses -system.cpu1.dcache.overall_misses::total 5895164 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 39717227000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 39717227000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 40094025500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 40094025500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 9755721000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 9755721000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2101168500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2101168500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4571201000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4571201000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4144500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4144500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 89566973500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 89566973500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 89566973500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 89566973500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 70695368 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 70695368 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 63165178 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 63165178 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 807023 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 807023 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 444276 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 444276 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1704523 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1704523 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1703490 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1703490 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 134304822 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 134304822 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 135111845 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 135111845 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038609 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.038609 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034033 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.034033 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.763364 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.763364 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.900177 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.900177 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.083944 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.083944 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108572 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108572 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.039307 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.039307 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043632 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.043632 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14551.126490 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14551.126490 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18651.073178 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18651.073178 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24393.754360 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24393.754360 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14684.757312 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14684.757312 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24715.740926 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24715.740926 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 14504 # number of quiesce instructions executed +system.cpu1.tickCycles 754340504 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 219429502 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 5584308 # number of replacements +system.cpu1.dcache.tags.tagsinuse 440.375822 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 163963779 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5584818 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.358840 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8377741807000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 440.375822 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.860109 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.860109 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 234 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 347150058 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 347150058 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 84821089 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 84821089 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 74565342 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 74565342 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 240493 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 240493 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 73857 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 73857 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1888770 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1888770 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1879546 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1879546 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 159460288 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 159460288 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 159700781 # number of overall hits +system.cpu1.dcache.overall_hits::total 159700781 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3413550 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3413550 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2348662 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2348662 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 664960 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 664960 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 462804 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 462804 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 186013 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 186013 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193851 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 193851 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 6225016 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 6225016 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 6889976 # number of overall misses +system.cpu1.dcache.overall_misses::total 6889976 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 52244752500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 52244752500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 43500498500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 43500498500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11517052000 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 11517052000 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2853085500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2853085500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4630433000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4630433000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2585500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2585500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 107262303000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 107262303000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 107262303000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 107262303000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 88234639 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 88234639 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 76914004 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 76914004 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 905453 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 905453 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 536661 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 536661 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2074783 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 2074783 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2073397 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 2073397 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 165685304 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 165685304 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 166590757 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 166590757 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038687 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.038687 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030536 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030536 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.734395 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.734395 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.862377 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.862377 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089654 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089654 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.093494 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.093494 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.037571 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.037571 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041359 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.041359 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15305.108318 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15305.108318 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18521.395799 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18521.395799 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24885.376963 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24885.376963 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15338.097337 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15338.097337 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23886.557201 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23886.557201 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16966.295373 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16966.295373 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15193.296319 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15193.296319 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17230.847760 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17230.847760 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15567.877595 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15567.877595 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 4660691 # number of writebacks -system.cpu1.dcache.writebacks::total 4660691 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 132278 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 132278 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 894898 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 894898 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 69 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 69 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 37558 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 37558 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 59 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 59 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1027245 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1027245 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1027245 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1027245 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2597217 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2597217 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1254792 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1254792 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 615702 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 615702 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 399858 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 399858 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 105527 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 105527 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 184892 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 184892 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4251867 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4251867 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4867569 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4867569 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8793 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 8793 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 9091 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 9091 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 17884 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 17884 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 34245614000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 34245614000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22880344500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22880344500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13431113500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13431113500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9350661500 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9350661500 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1405417000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1405417000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4384302500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4384302500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3898500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3898500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 66476620000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 66476620000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 79907733500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 79907733500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1305175500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1305175500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1305175500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1305175500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036738 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036738 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019865 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019865 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.762930 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.762930 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.900022 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.900022 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.061910 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.061910 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108537 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108537 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031658 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031658 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.036026 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.036026 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13185.503560 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13185.503560 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18234.372310 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18234.372310 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21814.308708 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21814.308708 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23384.955409 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23384.955409 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13318.079733 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13318.079733 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23712.775566 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23712.775566 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 5584335 # number of writebacks +system.cpu1.dcache.writebacks::total 5584335 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 169267 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 169267 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 957224 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 957224 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 58 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44866 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44866 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 87 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 87 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1126549 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1126549 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1126549 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1126549 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3244283 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3244283 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1391438 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1391438 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 664681 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 664681 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 462746 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 462746 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 141147 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 141147 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193764 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 193764 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 5098467 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 5098467 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5763148 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5763148 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17608 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17608 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 15853 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 15853 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 33461 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 33461 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 45298654500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 45298654500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 25106196000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 25106196000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14639124500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14639124500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 11050641000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 11050641000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1898988000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1898988000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4434665000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4434665000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2119500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2119500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 81455491500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 81455491500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 96094616000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 96094616000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2936127500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2936127500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2936127500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2936127500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036769 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036769 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018091 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018091 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.734087 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.734087 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.862269 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.862269 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068030 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068030 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.093452 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.093452 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030772 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030772 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034595 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034595 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13962.608841 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13962.608841 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18043.345086 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18043.345086 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22024.286086 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22024.286086 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23880.575953 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23880.575953 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13453.973517 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13453.973517 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22886.939782 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22886.939782 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15634.689420 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15634.689420 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16416.353523 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16416.353523 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148433.469806 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 148433.469806 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 72980.065981 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 72980.065981 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 8014386 # number of replacements -system.cpu1.icache.tags.tagsinuse 507.062567 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 202497896 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 8014898 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 25.265187 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8368004575000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.062567 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990357 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.990357 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15976.467338 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15976.467338 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16673.980262 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16673.980262 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166749.630850 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 166749.630850 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 87747.751113 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 87747.751113 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 9521452 # number of replacements +system.cpu1.icache.tags.tagsinuse 507.043038 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 244267020 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 9521964 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 25.653008 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8368158607000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.043038 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990318 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.990318 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 273 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 429040515 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 429040515 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 202497896 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 202497896 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 202497896 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 202497896 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 202497896 # number of overall hits -system.cpu1.icache.overall_hits::total 202497896 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 8014908 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 8014908 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 8014908 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 8014908 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 8014908 # number of overall misses -system.cpu1.icache.overall_misses::total 8014908 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 81330977500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 81330977500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 81330977500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 81330977500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 81330977500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 81330977500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 210512804 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 210512804 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 210512804 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 210512804 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 210512804 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 210512804 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038073 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.038073 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038073 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.038073 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038073 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.038073 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10147.462391 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10147.462391 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10147.462391 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10147.462391 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10147.462391 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10147.462391 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 517099934 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 517099934 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 244267020 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 244267020 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 244267020 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 244267020 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 244267020 # number of overall hits +system.cpu1.icache.overall_hits::total 244267020 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 9521965 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 9521965 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 9521965 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 9521965 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 9521965 # number of overall misses +system.cpu1.icache.overall_misses::total 9521965 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 96688620500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 96688620500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 96688620500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 96688620500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 96688620500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 96688620500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 253788985 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 253788985 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 253788985 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 253788985 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 253788985 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 253788985 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037519 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.037519 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037519 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.037519 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037519 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.037519 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10154.271781 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10154.271781 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10154.271781 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10154.271781 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10154.271781 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10154.271781 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 8014386 # number of writebacks -system.cpu1.icache.writebacks::total 8014386 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8014908 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 8014908 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 8014908 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 8014908 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 8014908 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 8014908 # 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number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038073 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038073 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038073 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.038073 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038073 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.038073 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9647.462454 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9647.462454 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9647.462454 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9647.462454 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9647.462454 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9647.462454 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92278.947368 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92278.947368 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92278.947368 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92278.947368 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6532358 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6532555 # 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average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9654.271834 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9654.271834 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9654.271834 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95478.947368 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95478.947368 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95478.947368 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95478.947368 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7586302 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7586460 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 136 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 799581 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 2133098 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13038.197584 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 20019506 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2148887 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 9.316221 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9619713453000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 11987.780509 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 23.994022 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 12.035388 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1014.387665 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.731676 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001464 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000735 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.061913 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.795788 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 829 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 65 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14895 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 152 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 567 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 82 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 55 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1161 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5545 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7510 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 574 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.050598 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003967 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.909119 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 428778233 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 428778233 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # 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number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 7365861 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3198465 # number of overall hits -system.cpu1.l2cache.overall_hits::total 11192773 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11255 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7950 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 19205 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 218866 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 218866 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 184883 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 184883 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 9 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 254182 # 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number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1381240500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3788499 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3788499 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10033557499 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 10033557499 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 20842529000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 20842529000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 28170928990 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 28170928990 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 350412000 # 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Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 402 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 743 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6180 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6756 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 775 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.016541 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004822 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.906738 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 519862521 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 519862521 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # 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number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 74961772378 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8006500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1234720500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1242727000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8006500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1234720500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1242727000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023233 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048663 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.029644 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 33461 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 33556 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 591166500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 369748000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 960914500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 34084097769 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 34084097769 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4320296500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4320296500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2976407492 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2976407492 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1712499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1712499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8961948498 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8961948498 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 20179405000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 20179405000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 29636625496 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 29636625496 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 7368901000 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 7368901000 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 591166500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 369748000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 20179405000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 38598573994 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 59738893494 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 591166500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 369748000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20179405000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 38598573994 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 34084097769 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 93822991263 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8310500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2795199500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2803510000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8310500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2795199500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2803510000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.037574 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.059771 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.042758 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998117 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998117 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.239653 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.239653 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.080980 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.080980 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.272149 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.272149 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.584803 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.584803 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023233 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048663 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.080980 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.264406 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.139801 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023233 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048663 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.080980 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.264406 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.216988 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.216988 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.077743 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.077743 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.253348 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.253348 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.584169 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.584169 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.037574 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.059771 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.077743 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.245244 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.132230 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.037574 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.059771 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.077743 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.245244 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.192823 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28796.827795 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 28624.732536 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28725.610709 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38948.299055 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 38948.299055 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20841.626813 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20841.626813 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16189.657767 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16189.657767 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 372944.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 372944.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31574.707002 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31574.707002 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26112.486981 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26112.486981 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25163.535220 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25163.535220 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26480.228622 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26480.228622 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28796.827795 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 28624.732536 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26112.486981 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26548.026857 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26415.677887 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28796.827795 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 28624.732536 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26112.486981 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26548.026857 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38948.299055 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29861.857270 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84278.947368 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 140420.846128 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139820.769577 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84278.947368 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 69040.511071 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 69121.030091 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 26150144 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 13381244 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1981 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 1969364 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1969026 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 338 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 732517 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 12156991 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 9091 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 9091 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4007359 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 9735300 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2694691 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 886167 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 430328 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 337223 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 468486 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1067899 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1044213 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8014908 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4433895 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 458319 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 398059 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 24044391 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15175224 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 343569 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1027712 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 40590896 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1025880832 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 583383788 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1306120 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3875096 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1614445836 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 6456023 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 75189768 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 20132697 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.112928 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.316558 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.182494 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26192.578644 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33797.806216 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28675.455088 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43700.698728 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43700.698728 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18593.996531 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18593.996531 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15361.231063 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15361.231063 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 570833 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 570833 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 35561.735393 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 35561.735393 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 27259.704295 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27259.704295 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28885.430978 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28885.430978 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27367.029139 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27367.029139 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26192.578644 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33797.806216 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27259.704295 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 30201.925322 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29115.472472 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26192.578644 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33797.806216 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27259.704295 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 30201.925322 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43700.698728 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33132.675950 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87478.947368 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158745.996138 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158363.554200 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87478.947368 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 83536.041959 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 83547.204673 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 31064178 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15870221 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1958 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 609547 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 609525 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 22 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 891069 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 14544906 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 15853 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 15853 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4703319 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 11641461 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 1517999 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 982833 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 435735 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 338791 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 485404 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1187635 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1166992 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9521965 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5021918 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 508584 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 460932 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 28565571 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17994817 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 387517 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1269560 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 48217465 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1218784704 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 696648341 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1464248 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4805440 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1921702733 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5371031 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 85625912 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 21661443 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.043843 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.204751 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 17859482 88.71% 88.71% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2272877 11.29% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 338 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 20711756 95.62% 95.62% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 949665 4.38% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 22 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 20132697 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 25974578977 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 21661443 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 30930175985 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 179053447 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 161428122 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 12025219550 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 14285968218 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 6952751265 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 8290126100 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 180351405 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 204584802 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 543399850 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 668995768 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40387 # Transaction distribution -system.iobus.trans_dist::ReadResp 40387 # Transaction distribution -system.iobus.trans_dist::WriteReq 136979 # Transaction distribution -system.iobus.trans_dist::WriteResp 136979 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47808 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40347 # Transaction distribution +system.iobus.trans_dist::ReadResp 40347 # Transaction distribution +system.iobus.trans_dist::WriteReq 136610 # Transaction distribution +system.iobus.trans_dist::WriteResp 136610 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47638 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2452,15 +2432,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122950 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231702 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231702 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122572 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231262 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354732 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47828 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47658 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2471,105 +2451,105 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155965 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7355160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155679 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7339064 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7513211 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42458502 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496829 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 41998503 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 311001 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 312000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 15000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 26063002 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25719009 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 34444001 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 34474500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 570734934 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569697884 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92958000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92693000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148142000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147958000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115832 # number of replacements -system.iocache.tags.tagsinuse 11.305903 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115612 # number of replacements +system.iocache.tags.tagsinuse 11.289058 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115848 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115628 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9127528857000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.833923 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.471980 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239620 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.466999 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706619 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9127814531000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.847615 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.441443 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240476 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.465090 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705566 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1043016 # Number of tag accesses -system.iocache.tags.data_accesses 1043016 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1041036 # Number of tag accesses +system.iocache.tags.data_accesses 1041036 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8867 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8904 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8903 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8940 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # 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number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5198500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1683130463 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1688328963 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12886794903 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12886794903 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14534068934 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14539635934 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5567000 # 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number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8867 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8904 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8903 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8940 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115851 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115891 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115631 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115671 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115851 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115891 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115631 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115671 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2583,53 +2563,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 185775.801398 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 185587.604560 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140500 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 189052.056947 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 188851.114430 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120455.347557 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120455.347557 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125454.842289 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125459.577827 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125454.842289 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125459.577827 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32243 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120501.451550 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120501.451550 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139187.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125779.500169 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125784.136767 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139187.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125779.500169 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125784.136767 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 33720 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3515 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3566 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.172973 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.455973 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106950 # number of writebacks -system.iocache.writebacks::total 106950 # number of writebacks +system.iocache.writebacks::writebacks 106694 # number of writebacks +system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8867 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8904 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8903 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8940 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115851 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115891 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115631 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115671 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115851 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115891 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1203924031 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1207272031 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115631 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115671 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1237980463 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1241328963 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7528956843 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7528956843 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 8732880874 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8736447874 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 8732880874 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8736447874 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7515783412 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7515783412 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3567500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8753763875 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8757331375 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3567500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8753763875 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8757331375 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2643,660 +2623,661 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135775.801398 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 135587.604560 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90500 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139052.056947 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 138851.114430 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70374.605950 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70374.605950 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75380.280481 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75385.041755 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75380.280481 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75385.041755 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1436798 # number of replacements -system.l2c.tags.tagsinuse 63641.257392 # Cycle average of tags in use -system.l2c.tags.total_refs 6808742 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1497176 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.547723 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8050623000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 20256.980304 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 307.265586 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 477.600666 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 6075.269789 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 12531.509900 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 19419.437449 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.305032 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 4.128844 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2389.320183 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1436.582929 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 731.856711 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.309097 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.004689 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.007288 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.092701 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.191216 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.296317 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000173 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000063 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.036458 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.021921 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.011167 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.971089 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10768 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 197 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 49413 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 162 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 3598 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 6999 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 179 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2209 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 15374 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 31482 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.164307 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003006 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.753983 # 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Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 10181 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 246 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1499 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4720 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 44382 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.161819 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003876 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.774124 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 80901066 # 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mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.263538 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.457750 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.189222 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.193640 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.068356 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.170778 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.357669 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.225148 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.266299 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.360234 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.095263 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.263538 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.457750 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.189222 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.193640 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.068356 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.170778 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.357669 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.225148 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21504.428630 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21588.308809 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21544.753533 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24597.736546 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24607.311801 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24602.095240 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 78922.059614 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72763.810098 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 76751.364510 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 78712.358623 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 78882.508929 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75186.249850 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79262.094163 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116268.528234 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82711.049170 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82989.197926 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74551.369900 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 83037.216747 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115710.968135 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 98969.705542 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20911.097724 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20861.825980 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20902.941631 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78712.358623 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78882.508929 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75186.249850 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79150.090720 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116268.528234 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82711.049170 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82989.197926 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74551.369900 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 79246.180478 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115710.968135 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 95938.382922 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78712.358623 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78882.508929 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75186.249850 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79150.090720 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116268.528234 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82711.049170 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82989.197926 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74551.369900 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 79246.180478 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115710.968135 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 95938.382922 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.093219 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.134678 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.112579 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.010320 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.011003 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.010686 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.572702 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.527134 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.551760 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.126474 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.200994 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.105395 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.184563 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.460976 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.171217 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.339172 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.083119 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.192553 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.426901 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.223735 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.769896 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.489397 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.682634 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.126474 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.200994 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.105395 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.245282 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.460976 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.171217 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.339172 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.083119 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.236577 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.426901 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.242775 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.126474 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.200994 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.105395 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.245282 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.460976 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.171217 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.339172 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.083119 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.236577 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.426901 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.242775 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20324.905081 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20303.646459 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20313.029194 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 23768.339768 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23863.207547 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 23820.623917 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 81312.890475 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 77267.336603 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 79536.682552 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 82350.600872 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80699.647350 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75514.802228 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 82256.965971 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 122293.381948 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79260.811197 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 77929.646604 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76272.038697 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80061.794451 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114455.846723 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 100288.348496 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20885.125643 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20211.825556 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20734.958685 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 82350.600872 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80699.647350 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75514.802228 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 81912.133550 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 122293.381948 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79260.811197 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77929.646604 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76272.038697 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 79242.515396 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114455.846723 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 97550.886770 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 82350.600872 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80699.647350 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75514.802228 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 81912.133550 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 122293.381948 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79260.811197 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77929.646604 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76272.038697 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 79242.515396 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114455.846723 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 97550.886770 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63481.529637 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164491.491592 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63273.684211 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122437.265840 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102255.861386 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168555.103615 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 66442.105263 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 140758.775417 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102416.958217 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63481.529637 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82791.799858 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63273.684211 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 60191.589531 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 71855.534201 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 3914348 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2362357 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 2871 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 81054.464285 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 66442.105263 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 74066.738396 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 72090.282208 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3909047 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2292243 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 2625 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 90979 # Transaction distribution -system.membus.trans_dist::ReadResp 948459 # Transaction distribution -system.membus.trans_dist::WriteReq 38491 # Transaction distribution -system.membus.trans_dist::WriteResp 38491 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1228466 # Transaction distribution -system.membus.trans_dist::CleanEvict 265252 # Transaction distribution -system.membus.trans_dist::UpgradeReq 443986 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 298688 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 90635 # Transaction distribution +system.membus.trans_dist::ReadResp 999620 # Transaction distribution +system.membus.trans_dist::WriteReq 38128 # Transaction distribution +system.membus.trans_dist::WriteResp 38128 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1272553 # Transaction distribution +system.membus.trans_dist::CleanEvict 289712 # Transaction distribution +system.membus.trans_dist::UpgradeReq 348270 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 267748 # Transaction distribution system.membus.trans_dist::UpgradeResp 23 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 145286 # Transaction distribution -system.membus.trans_dist::ReadExResp 128554 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 857480 # Transaction distribution -system.membus.trans_dist::InvalidateReq 675140 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122950 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 152656 # Transaction distribution +system.membus.trans_dist::ReadExResp 136047 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 908985 # Transaction distribution +system.membus.trans_dist::InvalidateReq 669058 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122572 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 54 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25980 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4768940 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4917924 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238548 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238548 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5156472 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155965 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24944 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4823028 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4970598 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238389 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238389 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5208987 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155679 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1388 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 137639872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 137849185 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7281600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7281600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 145130785 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 603530 # Total snoops (count) -system.membus.snoopTraffic 179328 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2550056 # Request fanout histogram -system.membus.snoop_fanout::mean 0.011955 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.108685 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49888 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 144251456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 144458411 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7283200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7283200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 151741611 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 583612 # Total snoops (count) +system.membus.snoopTraffic 163584 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2475487 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012229 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.109905 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2519569 98.80% 98.80% # Request fanout histogram -system.membus.snoop_fanout::1 30487 1.20% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2445215 98.78% 98.78% # Request fanout histogram +system.membus.snoop_fanout::1 30272 1.22% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2550056 # Request fanout histogram -system.membus.reqLayer0.occupancy 103375494 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2475487 # Request fanout histogram +system.membus.reqLayer0.occupancy 102607988 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 34812 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21768496 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20962995 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8632891321 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8793410200 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5537724663 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5849158337 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45395946 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45598905 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3339,78 +3320,78 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 12809826 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6934559 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2124865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 137043 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 124917 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 12126 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47445489241000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 90981 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4987806 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38491 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38491 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3972958 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 3104635 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 749262 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 382090 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1131352 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 138 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 306540 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 306540 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4897318 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 863164 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 835591 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 11082342 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7735233 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 18817575 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 276628165 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 188875292 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 465503457 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2889580 # Total snoops (count) -system.toL2Bus.snoopTraffic 125478224 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 8764836 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.360858 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.483121 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 12529275 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6783970 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2045593 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 207524 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 190768 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 16756 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47276772827000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 90637 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4878287 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38128 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38128 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3994832 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 3079472 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 721673 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 374590 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1096263 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 115 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 301835 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 301835 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4787847 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 854297 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 826693 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9608901 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8808719 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 18417620 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 240252134 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 217815813 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 458067947 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2968837 # Total snoops (count) +system.toL2Bus.snoopTraffic 127024720 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 8725155 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.358566 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.483567 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5614105 64.05% 64.05% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3138605 35.81% 99.86% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 12126 0.14% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5613365 64.34% 64.34% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3095034 35.47% 99.81% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 16756 0.19% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8764836 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9763497454 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8725155 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9593262018 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2559907 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2632911 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 5082599079 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4411209152 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3859782501 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4336941336 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index d21e89078..c77078f22 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.660717 # Number of seconds simulated -sim_ticks 51660717372000 # Number of ticks simulated -final_tick 51660717372000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.687765 # Number of seconds simulated +sim_ticks 51687764518000 # Number of ticks simulated +final_tick 51687764518000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 187164 # Simulator instruction rate (inst/s) -host_op_rate 219920 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10422609624 # Simulator tick rate (ticks/s) -host_mem_usage 677216 # Number of bytes of host memory used -host_seconds 4956.60 # Real time elapsed on the host -sim_insts 927696922 # Number of instructions simulated -sim_ops 1090057089 # Number of ops (including micro ops) simulated +host_inst_rate 151884 # Simulator instruction rate (inst/s) +host_op_rate 178474 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8204277049 # Simulator tick rate (ticks/s) +host_mem_usage 687220 # Number of bytes of host memory used +host_seconds 6300.10 # Real time elapsed on the host +sim_insts 956884636 # Number of instructions simulated +sim_ops 1124405089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 368128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 311744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10118784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 60722568 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 418176 # Number of bytes read from this memory -system.physmem.bytes_read::total 71939400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10118784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10118784 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 88730048 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 423488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 359680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10197440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 68348040 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 416768 # Number of bytes read from this memory +system.physmem.bytes_read::total 79745416 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10197440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10197440 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 96812416 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 88750628 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 5752 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 4871 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 158106 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 948803 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6534 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1124066 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1386407 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 96832996 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 6617 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5620 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 159335 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1067951 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6512 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1246035 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1512694 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1388980 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 7126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 6034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 195870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1175411 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1392536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 195870 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 195870 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1717554 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1515267 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 8193 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 6959 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 197289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1322325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1542830 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 197289 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197289 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1873024 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1717952 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1717554 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 7126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 6034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 195870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1175809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3110488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1124066 # Number of read requests accepted -system.physmem.writeReqs 1388980 # Number of write requests accepted -system.physmem.readBursts 1124066 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1388980 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 71890560 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 49664 # Total number of bytes read from write queue -system.physmem.bytesWritten 88748928 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 71939400 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 88750628 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 776 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2249 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1873422 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1873024 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 8193 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 6959 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1322723 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8063 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3416252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1246035 # Number of read requests accepted +system.physmem.writeReqs 1515267 # Number of write requests accepted +system.physmem.readBursts 1246035 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1515267 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 79703040 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 43200 # Total number of bytes read from write queue +system.physmem.bytesWritten 96830656 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 79745416 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 96832996 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 675 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2258 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 65344 # Per bank write bursts -system.physmem.perBankRdBursts::1 73127 # Per bank write bursts -system.physmem.perBankRdBursts::2 68334 # Per bank write bursts -system.physmem.perBankRdBursts::3 62589 # Per bank write bursts -system.physmem.perBankRdBursts::4 65747 # Per bank write bursts -system.physmem.perBankRdBursts::5 73971 # Per bank write bursts -system.physmem.perBankRdBursts::6 66723 # Per bank write bursts -system.physmem.perBankRdBursts::7 65172 # Per bank write bursts -system.physmem.perBankRdBursts::8 63356 # Per bank write bursts -system.physmem.perBankRdBursts::9 122297 # Per bank write bursts -system.physmem.perBankRdBursts::10 70526 # Per bank write bursts -system.physmem.perBankRdBursts::11 71466 # Per bank write bursts -system.physmem.perBankRdBursts::12 64199 # Per bank write bursts -system.physmem.perBankRdBursts::13 65172 # Per bank write bursts -system.physmem.perBankRdBursts::14 60121 # Per bank write bursts -system.physmem.perBankRdBursts::15 65146 # Per bank write bursts -system.physmem.perBankWrBursts::0 84316 # Per bank write bursts -system.physmem.perBankWrBursts::1 87030 # Per bank write bursts -system.physmem.perBankWrBursts::2 86821 # Per bank write bursts -system.physmem.perBankWrBursts::3 84154 # Per bank write bursts -system.physmem.perBankWrBursts::4 87756 # Per bank write bursts -system.physmem.perBankWrBursts::5 92254 # Per bank write bursts -system.physmem.perBankWrBursts::6 85357 # Per bank write bursts -system.physmem.perBankWrBursts::7 85828 # Per bank write bursts -system.physmem.perBankWrBursts::8 86266 # Per bank write bursts -system.physmem.perBankWrBursts::9 90537 # Per bank write bursts -system.physmem.perBankWrBursts::10 89139 # Per bank write bursts -system.physmem.perBankWrBursts::11 90914 # Per bank write bursts -system.physmem.perBankWrBursts::12 83868 # Per bank write bursts -system.physmem.perBankWrBursts::13 84845 # Per bank write bursts -system.physmem.perBankWrBursts::14 82305 # Per bank write bursts -system.physmem.perBankWrBursts::15 85312 # Per bank write bursts +system.physmem.perBankRdBursts::0 74796 # Per bank write bursts +system.physmem.perBankRdBursts::1 76131 # Per bank write bursts +system.physmem.perBankRdBursts::2 70862 # Per bank write bursts +system.physmem.perBankRdBursts::3 68837 # Per bank write bursts +system.physmem.perBankRdBursts::4 72123 # Per bank write bursts +system.physmem.perBankRdBursts::5 84628 # Per bank write bursts +system.physmem.perBankRdBursts::6 78694 # Per bank write bursts +system.physmem.perBankRdBursts::7 74893 # Per bank write bursts +system.physmem.perBankRdBursts::8 72007 # Per bank write bursts +system.physmem.perBankRdBursts::9 129561 # Per bank write bursts +system.physmem.perBankRdBursts::10 74825 # Per bank write bursts +system.physmem.perBankRdBursts::11 74032 # Per bank write bursts +system.physmem.perBankRdBursts::12 72055 # Per bank write bursts +system.physmem.perBankRdBursts::13 77727 # Per bank write bursts +system.physmem.perBankRdBursts::14 71057 # Per bank write bursts +system.physmem.perBankRdBursts::15 73132 # Per bank write bursts +system.physmem.perBankWrBursts::0 93267 # Per bank write bursts +system.physmem.perBankWrBursts::1 94026 # Per bank write bursts +system.physmem.perBankWrBursts::2 93600 # Per bank write bursts +system.physmem.perBankWrBursts::3 92665 # Per bank write bursts +system.physmem.perBankWrBursts::4 94539 # Per bank write bursts +system.physmem.perBankWrBursts::5 102396 # Per bank write bursts +system.physmem.perBankWrBursts::6 95600 # Per bank write bursts +system.physmem.perBankWrBursts::7 94740 # Per bank write bursts +system.physmem.perBankWrBursts::8 92115 # Per bank write bursts +system.physmem.perBankWrBursts::9 99710 # Per bank write bursts +system.physmem.perBankWrBursts::10 92671 # Per bank write bursts +system.physmem.perBankWrBursts::11 94633 # Per bank write bursts +system.physmem.perBankWrBursts::12 92127 # Per bank write bursts +system.physmem.perBankWrBursts::13 95527 # Per bank write bursts +system.physmem.perBankWrBursts::14 92160 # Per bank write bursts +system.physmem.perBankWrBursts::15 93203 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 29 # Number of times write queue was full causing retry -system.physmem.totGap 51660715485000 # Total gap between requests +system.physmem.numWrRetry 30 # Number of times write queue was full causing retry +system.physmem.totGap 51687762664000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1124051 # Read request sizes (log2) +system.physmem.readPktSize::6 1246020 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1386407 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1060868 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 56201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 631 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 541 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 751 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 177 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 132 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1512694 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1180646 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 58552 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 634 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 329 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 497 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 483 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 610 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 505 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 179 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 133 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 79 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 54 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -160,164 +160,173 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 33876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 39158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 77727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 79574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 81890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 80157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 81104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 84995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 84344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 80623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 81914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 84683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 81947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 82184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 83786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 79897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 78990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 78233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 82 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 638647 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 251.530251 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 152.310832 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 286.508507 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 275744 43.18% 43.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 164283 25.72% 68.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 60231 9.43% 78.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 32872 5.15% 83.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22951 3.59% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 16028 2.51% 89.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 11191 1.75% 91.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9395 1.47% 92.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 45952 7.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 638647 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 75991 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.781369 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 142.935713 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 75988 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 31478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 39945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 83104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 89526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 91633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 87574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 93055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 92225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 93220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 90182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 92806 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 106 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 686907 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 256.997398 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 154.492038 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 292.459663 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 294027 42.80% 42.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 175466 25.54% 68.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 64376 9.37% 77.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35669 5.19% 82.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 24767 3.61% 86.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 16380 2.38% 88.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 12324 1.79% 90.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 10264 1.49% 92.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 53634 7.81% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 686907 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 80666 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.437595 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 138.740748 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 80664 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 75991 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 75991 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.248240 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.695683 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.085121 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 64109 84.36% 84.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 9386 12.35% 96.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 485 0.64% 97.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 369 0.49% 97.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 63 0.08% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 114 0.15% 98.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 258 0.34% 98.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 31 0.04% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 303 0.40% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 66 0.09% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 30 0.04% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 60 0.08% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 313 0.41% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 41 0.05% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 27 0.04% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 117 0.15% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 162 0.21% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 21 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 12 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 75991 # Writes before turning the bus around for reads -system.physmem.totQLat 16312474093 # Total ticks spent queuing -system.physmem.totMemAccLat 37374161593 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5616450000 # Total ticks spent in databus transfers -system.physmem.avgQLat 14522.05 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 80666 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 80666 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.756093 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.057108 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.363487 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 67894 84.17% 84.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 3915 4.85% 89.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 3350 4.15% 93.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 2485 3.08% 96.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 1103 1.37% 97.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 521 0.65% 98.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 244 0.30% 98.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 153 0.19% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 79 0.10% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 83 0.10% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 83 0.10% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 89 0.11% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 450 0.56% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 43 0.05% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 41 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 30 0.04% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 23 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 5 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 4 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 6 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 9 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 18 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 7 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 80666 # Writes before turning the bus around for reads +system.physmem.totQLat 17151209707 # Total ticks spent queuing +system.physmem.totMemAccLat 40501709707 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6226800000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13772.09 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33272.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.39 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.72 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.39 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.72 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 32522.09 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.54 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.54 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.87 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.67 # Average write queue length when enqueuing -system.physmem.readRowHits 859362 # Number of row buffer hits during reads -system.physmem.writeRowHits 1011981 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.98 # Row buffer hit rate for writes -system.physmem.avgGap 20557011.49 # Average gap between requests -system.physmem.pageHitRate 74.55 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2420719560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1320829125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4219854600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4493983680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3374226435840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1315006290315 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29842911750000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34544599863120 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.682250 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49645601262378 # Time in different power states -system.physmem_0.memoryStateTime::REF 1725064640000 # Time in different power states +system.physmem.avgWrQLen 25.30 # Average write queue length when enqueuing +system.physmem.readRowHits 964137 # Number of row buffer hits during reads +system.physmem.writeRowHits 1107294 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.42 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.18 # Row buffer hit rate for writes +system.physmem.avgGap 18718619.94 # Average gap between requests +system.physmem.pageHitRate 75.10 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2629783800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1434901875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4687519200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4930197840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3375993173280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1305935149860 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29867098550250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34562709276105 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.682675 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49685845654409 # Time in different power states +system.physmem_0.memoryStateTime::REF 1725967880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 290044177622 # Time in different power states +system.physmem_0.memoryStateTime::ACT 275945978091 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2407451760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1313589750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4541752800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4491845280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3374226435840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1315022855940 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29842897218750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34544901150120 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.688082 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49645554021211 # Time in different power states -system.physmem_1.memoryStateTime::REF 1725064640000 # Time in different power states +system.physmem_1.actEnergy 2563233120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1398589500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5026242000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4873906080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3375993173280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1305717731910 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29867289276000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34562862151890 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.685632 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49686132095770 # Time in different power states +system.physmem_1.memoryStateTime::REF 1725967880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 290092863289 # Time in different power states +system.physmem_1.memoryStateTime::ACT 275664064230 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory @@ -334,30 +343,30 @@ system.realview.nvmem.bw_inst_read::total 14 # I system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 256052360 # Number of BP lookups -system.cpu.branchPred.condPredicted 178125867 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12215850 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 188334497 # Number of BTB lookups -system.cpu.branchPred.BTBHits 126943208 # Number of BTB hits +system.cpu.branchPred.lookups 264432116 # Number of BP lookups +system.cpu.branchPred.condPredicted 184777930 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12360480 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 195121872 # Number of BTB lookups +system.cpu.branchPred.BTBHits 131792442 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 67.403057 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31309548 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2129742 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 7077002 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 5011250 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2065752 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 841782 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 67.543654 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 32005520 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2166164 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 7202634 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 5156312 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2046322 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 848562 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,65 +396,70 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 558947 # Table walker walks requested -system.cpu.dtb.walker.walksLong 558947 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 19870 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 181727 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 558947 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 558947 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 558947 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 201597 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 27104.207900 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 22942.325413 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 21051.309840 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 199234 98.83% 98.83% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 98.83% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 2010 1.00% 99.83% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 57 0.03% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 120 0.06% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 59 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 92 0.05% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 13 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 201597 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples -1569310592 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 -1569310592 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total -1569310592 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 181728 90.14% 90.14% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 19870 9.86% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 201598 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 558947 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 584775 # Table walker walks requested +system.cpu.dtb.walker.walksLong 584775 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 23234 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 194431 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 584775 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 584775 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 584775 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 217665 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 25428.727632 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 21638.505013 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 16299.176879 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 136227 62.59% 62.59% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-65535 78767 36.19% 98.77% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-98303 1401 0.64% 99.42% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-131071 854 0.39% 99.81% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 27 0.01% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::163840-196607 133 0.06% 99.88% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-229375 57 0.03% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::229376-262143 75 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-294911 47 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::294912-327679 26 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-360447 20 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::360448-393215 15 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-425983 8 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 217665 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -10206296 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 -10206296 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -10206296 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 194432 89.33% 89.33% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 23234 10.67% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 217666 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 584775 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 558947 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 201598 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 584775 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 217666 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 201598 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 760545 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 217666 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 802441 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 179275780 # DTB read hits -system.cpu.dtb.read_misses 461379 # DTB read misses -system.cpu.dtb.write_hits 158920483 # DTB write hits -system.cpu.dtb.write_misses 97568 # DTB write misses +system.cpu.dtb.read_hits 184602893 # DTB read hits +system.cpu.dtb.read_misses 481054 # DTB read misses +system.cpu.dtb.write_hits 163948315 # DTB write hits +system.cpu.dtb.write_misses 103721 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 45647 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1093 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 78530 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1411 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 14509 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 47766 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1117 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 80755 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1436 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 15519 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 22879 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 179737159 # DTB read accesses -system.cpu.dtb.write_accesses 159018051 # DTB write accesses +system.cpu.dtb.perms_faults 23435 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 185083947 # DTB read accesses +system.cpu.dtb.write_accesses 164052036 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 338196263 # DTB hits -system.cpu.dtb.misses 558947 # DTB misses -system.cpu.dtb.accesses 338755210 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 348551208 # DTB hits +system.cpu.dtb.misses 584775 # DTB misses +system.cpu.dtb.accesses 349135983 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -475,634 +489,639 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 134834 # Table walker walks requested -system.cpu.itb.walker.walksLong 134834 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1067 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 117333 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 134834 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 134834 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 134834 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 118400 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 30431.579392 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 25904.631312 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 24094.406061 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 115676 97.70% 97.70% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 5 0.00% 97.70% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 2464 2.08% 99.78% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 78 0.07% 99.85% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 124 0.10% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 31 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 17 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 118400 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples -1570341092 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 -1570341092 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total -1570341092 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 117333 99.10% 99.10% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1067 0.90% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 118400 # Table walker page sizes translated +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 136740 # Table walker walks requested +system.cpu.itb.walker.walksLong 136740 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1077 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 118526 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 136740 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 136740 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 136740 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 119603 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 27883.393393 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 23898.853743 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 18564.311346 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-32767 67731 56.63% 56.63% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-65535 48774 40.78% 97.41% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-98303 1154 0.96% 98.37% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::98304-131071 1639 1.37% 99.74% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-163839 37 0.03% 99.78% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::163840-196607 137 0.11% 99.89% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-229375 43 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::229376-262143 18 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-294911 21 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::294912-327679 20 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-360447 18 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::360448-393215 9 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 119603 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples -10844796 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 -10844796 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total -10844796 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 118526 99.10% 99.10% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1077 0.90% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 119603 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 134834 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 134834 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136740 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 136740 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118400 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 118400 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 253234 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 442741882 # ITB inst hits -system.cpu.itb.inst_misses 134834 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 119603 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 119603 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 256343 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 457894474 # ITB inst hits +system.cpu.itb.inst_misses 136740 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 45647 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1093 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 56540 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 47766 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1117 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 57885 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 318606 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 331252 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 442876716 # ITB inst accesses -system.cpu.itb.hits 442741882 # DTB hits -system.cpu.itb.misses 134834 # DTB misses -system.cpu.itb.accesses 442876716 # DTB accesses -system.cpu.numPwrStateTransitions 33004 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 16502 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3052827188.483881 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 59796953066.006256 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 7205 43.66% 43.66% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9262 56.13% 99.79% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 458031214 # ITB inst accesses +system.cpu.itb.hits 457894474 # DTB hits +system.cpu.itb.misses 136740 # DTB misses +system.cpu.itb.accesses 458031214 # DTB accesses +system.cpu.numPwrStateTransitions 33262 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16631 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3032078673.597498 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 59558384510.943253 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7336 44.11% 44.11% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9260 55.68% 99.79% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 1988777699120 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 16502 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 1282963107639 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50377754264361 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2565980290 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 1988777698120 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 16631 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 1261264097400 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50426500420600 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2522582223 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 927696922 # Number of instructions committed -system.cpu.committedOps 1090057089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 94830796 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 7642 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 100756547271 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.765968 # CPI: cycles per instruction -system.cpu.ipc 0.361537 # IPC: instructions per cycle +system.cpu.committedInsts 956884636 # Number of instructions committed +system.cpu.committedOps 1124405089 # Number of ops (including micro ops) committed +system.cpu.discardedOps 99545013 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7771 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100854059486 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.636245 # CPI: cycles per instruction +system.cpu.ipc 0.379327 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction -system.cpu.op_class_0::IntAlu 755349201 69.29% 69.29% # Class of committed instruction -system.cpu.op_class_0::IntMult 2273269 0.21% 69.50% # Class of committed instruction -system.cpu.op_class_0::IntDiv 98990 0.01% 69.51% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 8 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 13 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 21 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 69.51% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 109509 0.01% 69.52% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu.op_class_0::MemRead 173855507 15.95% 85.47% # Class of committed instruction -system.cpu.op_class_0::MemWrite 158370570 14.53% 100.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 779381648 69.32% 69.32% # Class of committed instruction +system.cpu.op_class_0::IntMult 2317785 0.21% 69.52% # Class of committed instruction +system.cpu.op_class_0::IntDiv 99593 0.01% 69.53% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 8 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 13 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 21 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 69.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 108729 0.01% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction +system.cpu.op_class_0::MemRead 179105650 15.93% 85.47% # Class of committed instruction +system.cpu.op_class_0::MemWrite 163391641 14.53% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 1090057089 # Class of committed instruction +system.cpu.op_class_0::total 1124405089 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16502 # number of quiesce instructions executed -system.cpu.tickCycles 1756726391 # Number of cycles that the object actually ticked -system.cpu.idleCycles 809253899 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 10800470 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.930063 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 322845784 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 10800982 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.890410 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 7088310500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.930063 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 16631 # number of quiesce instructions executed +system.cpu.tickCycles 1810679239 # Number of cycles that the object actually ticked +system.cpu.idleCycles 711902984 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 11237287 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.957340 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 332608189 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11237799 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.597272 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4326295500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.957340 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999917 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999917 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1354272764 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1354272764 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 165477998 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 165477998 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148389977 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148389977 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 514152 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 514152 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 336855 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 336855 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3884412 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3884412 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4194010 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4194010 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 314204830 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 314204830 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 314718982 # number of overall hits -system.cpu.dcache.overall_hits::total 314718982 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 5939711 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 5939711 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4167073 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4167073 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1413293 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1413293 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1239143 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1239143 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 311310 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 311310 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1395920077 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1395920077 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 170244902 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 170244902 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 153016106 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 153016106 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 525044 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 525044 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 336678 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 336678 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4066137 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4066137 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4385244 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4385244 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 323597686 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 323597686 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 324122730 # number of overall hits +system.cpu.dcache.overall_hits::total 324122730 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6163054 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6163054 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4362358 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4362358 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1504058 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1504058 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1246141 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1246141 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 320841 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 320841 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 11345927 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 11345927 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 12759220 # number of overall misses -system.cpu.dcache.overall_misses::total 12759220 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 110013337000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 110013337000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 204497661000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 204497661000 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 53262030500 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 53262030500 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5161319000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5161319000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # 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number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3424677000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 82000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 82000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 197537687000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 197537687000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 221752800000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 221752800000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6231251500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6231251500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6231251500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6231251500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033149 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033149 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.737534 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.737534 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787195 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787195 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056967 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056967 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028266 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028266 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032392 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032392 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17115.819039 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17115.819039 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46509.168472 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46509.168472 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18995.493708 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18995.493708 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41982.291942 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41982.291942 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14507.908157 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14507.908157 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27908.292969 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27908.292969 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26727.106386 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26727.106386 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183932.976229 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183932.976229 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91954.208270 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91954.208270 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 24348068 # number of replacements -system.cpu.icache.tags.tagsinuse 511.885312 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 418063563 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24348580 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.169936 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 32786837500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.885312 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999776 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999776 # Average percentage of cache occupancy +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028403 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028403 # 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average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13703.531643 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13703.531643 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20737.885034 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20737.885034 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20119.141922 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20119.141922 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184914.579500 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184914.579500 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92444.944737 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92444.944737 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 24740790 # number of replacements +system.cpu.icache.tags.tagsinuse 511.930482 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 432810859 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24741302 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.493455 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 20587192500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.930482 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999864 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999864 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 466760742 # Number of tag accesses -system.cpu.icache.tags.data_accesses 466760742 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 418063563 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 418063563 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 418063563 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 418063563 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 418063563 # number of overall hits -system.cpu.icache.overall_hits::total 418063563 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 24348590 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 24348590 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 24348590 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 24348590 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 24348590 # number of overall misses -system.cpu.icache.overall_misses::total 24348590 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 329659145500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 329659145500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 329659145500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 329659145500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 329659145500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 329659145500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 442412153 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 442412153 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 442412153 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 442412153 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 442412153 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 442412153 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.055036 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.055036 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.055036 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.055036 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.055036 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.055036 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13539.147257 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13539.147257 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13539.147257 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13539.147257 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13539.147257 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13539.147257 # average overall miss latency +system.cpu.icache.tags.tag_accesses 482293482 # Number of tag accesses +system.cpu.icache.tags.data_accesses 482293482 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 432810859 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 432810859 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 432810859 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 432810859 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 432810859 # number of overall hits +system.cpu.icache.overall_hits::total 432810859 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 24741312 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 24741312 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 24741312 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 24741312 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 24741312 # number of overall misses +system.cpu.icache.overall_misses::total 24741312 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 329592002500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 329592002500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 329592002500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 329592002500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 329592002500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 329592002500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 457552171 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 457552171 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 457552171 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 457552171 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 457552171 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 457552171 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054073 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.054073 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.054073 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.054073 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.054073 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.054073 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13321.524845 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13321.524845 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13321.524845 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13321.524845 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13321.524845 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13321.524845 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 24348068 # number of writebacks -system.cpu.icache.writebacks::total 24348068 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24348590 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 24348590 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 24348590 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 24348590 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 24348590 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 24348590 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable -system.cpu.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable -system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 305310556500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 305310556500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 305310556500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 305310556500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 305310556500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 305310556500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6746653000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6746653000 # 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average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12539.147298 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12539.147298 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12539.147298 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12539.147298 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128976.906460 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128976.906460 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128976.906460 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128976.906460 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51660717372000 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.564379 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004995 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006269 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.122755 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.298762 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997160 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 289 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 63079 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 289 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 541 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2400 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5595 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54498 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004410 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962509 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 577006805 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 577006805 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 916908 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 278918 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1195826 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 8297164 # 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average overall mshr uncacheable latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 1647378 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65415.989966 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 70152651 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1710758 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 41.006765 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 5897369000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 9082.397486 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 468.031396 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 465.228429 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8079.882193 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 47320.450462 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.138586 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.007142 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007099 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123289 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.722053 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998169 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 304 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 63076 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 301 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 861 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5993 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55903 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004639 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962463 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 587932179 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 587932179 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 928594 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 259345 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78867184023 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 87607182024 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 516791000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 440365500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7782841501 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78867184023 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 87607182024 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 3276571500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5809931000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 9086502500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3276571500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5809931000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9086502500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007075 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.021210 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010196 # mshr miss rate for ReadReq accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782369 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782369 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.118132 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.118132 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.278818 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.278818 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004346 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004346 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043089 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043089 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.431195 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.431195 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006234 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.017164 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004346 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.099357 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.030370 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006234 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.017164 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004346 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.099357 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.030370 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126606.310848 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127272.839253 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 126911.936364 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67985.168034 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67985.168034 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122812.641665 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122812.641665 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122437.282746 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122437.282746 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124905.908758 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124905.908758 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69672.880744 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69672.880744 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126606.310848 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127272.839253 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122437.282746 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123503.756561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123431.883604 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126606.310848 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127272.839253 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122437.282746 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123503.756561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123431.883604 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113476.772640 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171430.275692 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136182.853522 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113476.772640 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85703.692714 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 97839.335238 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 71038022 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 35888421 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4192 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2302 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2302 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.305219 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.305219 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004327 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004327 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.044412 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.044412 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.439635 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.439635 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007075 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.021210 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004327 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.107001 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.033073 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007075 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.021210 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004327 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.107001 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.033073 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78100.498715 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 78356.850534 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 78218.231593 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19083.602484 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19083.602484 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72944.879406 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72944.879406 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72690.640537 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72690.640537 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75552.119164 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75552.119164 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20639.713938 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20639.713938 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78100.498715 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 78356.850534 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72690.640537 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73767.351916 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73716.178974 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78100.498715 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 78356.850534 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72690.640537 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73767.351916 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73716.178974 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62657.937009 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172411.745504 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 105668.064100 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62657.937009 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86194.362436 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 75911.899113 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 72719983 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 36740859 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1912 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1912 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1730261 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 33359239 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 9683600 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 24348068 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2741013 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 48305 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1798088 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 34134170 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 10025859 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 24740790 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2858806 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 34075 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 48306 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2282432 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2282432 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 24348590 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7288491 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1345648 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1238984 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73149864 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32634714 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 686896 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2163808 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 108635282 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3119933760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1143229458 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2270312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7381280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 4272814810 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2178284 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 92284400 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 38701577 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018037 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.133086 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 34076 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2397848 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2397848 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 24741312 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7596551 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1271756 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1245987 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 74327998 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 33916673 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 673778 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2238495 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 111156944 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3170201152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1191384986 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2119720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7481688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 4371187546 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2188425 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 94133704 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 39520716 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018595 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.135091 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 38003503 98.20% 98.20% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 698074 1.80% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 38785811 98.14% 98.14% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 734905 1.86% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 38701577 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 68717300491 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 39520716 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 70288980496 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1477390 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1482392 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 36605927318 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 37194713363 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 15037927648 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 15679329987 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 403140932 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 408839447 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1241184926 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1303303960 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40331 # Transaction distribution -system.iobus.trans_dist::ReadResp 40331 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40309 # Transaction distribution +system.iobus.trans_dist::ReadResp 40309 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1314,11 +1333,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231020 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231020 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230976 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230976 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353804 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353760 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1333,16 +1352,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334512 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334336 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334336 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492432 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 37711500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 37793000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 336000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 335000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1352,7 +1371,7 @@ system.iobus.reqLayer10.occupancy 9000 # La system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) @@ -1360,75 +1379,75 @@ system.iobus.reqLayer16.occupancy 16000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25249000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25128500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36460500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36456000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 567164602 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569339894 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147780000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147736000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115492 # number of replacements -system.iocache.tags.tagsinuse 10.441393 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115470 # number of replacements +system.iocache.tags.tagsinuse 10.448409 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115508 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115486 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13153371816000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.521310 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.920084 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.220082 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.432505 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.652587 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13140724969000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.519445 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.928964 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219965 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.433060 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653026 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039947 # Number of tag accesses -system.iocache.tags.data_accesses 1039947 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039749 # Number of tag accesses +system.iocache.tags.data_accesses 1039749 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8846 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8883 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8824 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8861 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115510 # number of demand (read+write) misses -system.iocache.demand_misses::total 115550 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115488 # number of demand (read+write) misses +system.iocache.demand_misses::total 115528 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115510 # number of overall misses -system.iocache.overall_misses::total 115550 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1687962584 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1693032584 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115488 # number of overall misses +system.iocache.overall_misses::total 115528 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1631024611 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1636110611 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13411761018 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13411761018 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15099723602 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15105144602 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15099723602 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15105144602 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12739251283 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12739251283 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14370275894 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14375712894 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14370275894 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14375712894 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8846 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8883 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8824 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8861 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115510 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115550 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115488 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115528 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115510 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115550 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115488 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115528 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1442,53 +1461,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 190816.480217 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 190592.433187 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 184839.597801 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 184641.757251 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125738.403004 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125738.403004 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 130722.219739 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 130723.882319 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 130722.219739 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 130723.882319 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 34055 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119433.466615 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 119433.466615 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124430.900994 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124434.880670 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124430.900994 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124434.880670 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31942 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3409 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3389 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.989733 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.425199 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8846 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8883 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8824 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8861 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115510 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115550 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115488 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115528 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115510 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115550 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1245662584 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1248882584 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115488 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115528 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1189824611 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1193060611 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8073418582 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8073418582 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9319081166 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9322502166 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9319081166 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9322502166 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7399114026 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7399114026 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8588938637 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8592375637 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8588938637 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8592375637 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1502,89 +1521,95 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140816.480217 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 140592.433187 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134839.597801 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 134641.757251 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75690.191461 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75690.191461 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 80677.700338 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 80679.378330 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 80677.700338 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 80679.378330 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 86006 # Transaction distribution -system.membus.trans_dist::ReadResp 525005 # Transaction distribution -system.membus.trans_dist::WriteReq 33706 # Transaction distribution -system.membus.trans_dist::WriteResp 33706 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1386407 # Transaction distribution -system.membus.trans_dist::CleanEvict 236604 # Transaction distribution -system.membus.trans_dist::UpgradeReq 38552 # Transaction distribution +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69368.428204 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69368.428204 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 74370.831922 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 74374.832396 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74370.831922 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74374.832396 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 3617552 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1792214 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3206 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 85991 # Transaction distribution +system.membus.trans_dist::ReadResp 551423 # Transaction distribution +system.membus.trans_dist::WriteReq 33707 # Transaction distribution +system.membus.trans_dist::WriteResp 33707 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1512694 # Transaction distribution +system.membus.trans_dist::CleanEvict 249055 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4641 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 7 # Transaction distribution -system.membus.trans_dist::ReadExReq 635760 # Transaction distribution -system.membus.trans_dist::ReadExResp 635760 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 438999 # Transaction distribution -system.membus.trans_dist::InvalidateReq 640771 # Transaction distribution +system.membus.trans_dist::ReadExReq 731311 # Transaction distribution +system.membus.trans_dist::ReadExResp 731311 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 465432 # Transaction distribution +system.membus.trans_dist::InvalidateReq 654388 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4321043 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4450695 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237576 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237576 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4688271 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6920 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4683490 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4813146 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237510 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237510 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5050656 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 153447468 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 153617874 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7242560 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7242560 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 160860434 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3013 # Total snoops (count) -system.membus.snoopTraffic 192384 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3496836 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 169337260 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 169507674 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7241152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7241152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 176748826 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3012 # Total snoops (count) +system.membus.snoopTraffic 192320 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1975472 # Request fanout histogram +system.membus.snoop_fanout::mean 0.014689 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.120303 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3496836 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1946455 98.53% 98.53% # Request fanout histogram +system.membus.snoop_fanout::1 29017 1.47% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3496836 # Request fanout histogram -system.membus.reqLayer0.occupancy 99852500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1975472 # Request fanout histogram +system.membus.reqLayer0.occupancy 99807500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 18828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5614500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5588000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9224879373 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9976212567 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6035081327 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6680987810 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44925690 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44817130 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1627,28 +1652,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51660717372000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51687764518000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt index 0a085b4b5..12a2f6bdf 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.327143 # Number of seconds simulated -sim_ticks 51327142820000 # Number of ticks simulated -final_tick 51327142820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.558015 # Number of seconds simulated +sim_ticks 51558014828000 # Number of ticks simulated +final_tick 51558014828000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124063 # Simulator instruction rate (inst/s) -host_op_rate 145776 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7507150065 # Simulator tick rate (ticks/s) -host_mem_usage 681576 # Number of bytes of host memory used -host_seconds 6837.10 # Real time elapsed on the host -sim_insts 848230502 # Number of instructions simulated -sim_ops 996685945 # Number of ops (including micro ops) simulated +host_inst_rate 110619 # Simulator instruction rate (inst/s) +host_op_rate 130023 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5152408080 # Simulator tick rate (ticks/s) +host_mem_usage 695916 # Number of bytes of host memory used +host_seconds 10006.59 # Real time elapsed on the host +sim_insts 1106923026 # Number of instructions simulated +sim_ops 1301083589 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 227712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 212864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5673056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 41642312 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 444928 # Number of bytes read from this memory -system.physmem.bytes_read::total 48200872 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5673056 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5673056 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 68445056 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 667968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 559488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 6546400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112650248 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 429376 # Number of bytes read from this memory +system.physmem.bytes_read::total 120853480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 6546400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6546400 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 140957120 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 68465636 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 3558 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3326 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 104594 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 650674 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6952 # Number of read requests responded to by this memory -system.physmem.num_reads::total 769104 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1069454 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 140977700 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 10437 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 8742 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 118240 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1760173 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6709 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1904301 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2202455 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1072027 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 4436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 4147 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 110527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 811312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8668 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 939091 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 110527 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 110527 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1333506 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1333907 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1333506 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 4436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 4147 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 110527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 811713 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8668 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2272998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 769104 # Number of read requests accepted -system.physmem.writeReqs 1072027 # Number of write requests accepted -system.physmem.readBursts 769104 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1072027 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 49176064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 46592 # Total number of bytes read from write queue -system.physmem.bytesWritten 68464384 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 48200872 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 68465636 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 728 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one +system.physmem.num_writes::total 2205028 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 12956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 10852 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 126972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2184922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8328 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2344029 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 126972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 126972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2733952 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2734351 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2733952 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 12956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 10852 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 126972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2185321 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5078380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1904301 # Number of read requests accepted +system.physmem.writeReqs 2205028 # Number of write requests accepted +system.physmem.readBursts 1904301 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2205028 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 121838144 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 37120 # Total number of bytes read from write queue +system.physmem.bytesWritten 140976896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 120853480 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 140977700 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 580 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 44564 # Per bank write bursts -system.physmem.perBankRdBursts::1 52315 # Per bank write bursts -system.physmem.perBankRdBursts::2 47721 # Per bank write bursts -system.physmem.perBankRdBursts::3 44538 # Per bank write bursts -system.physmem.perBankRdBursts::4 44659 # Per bank write bursts -system.physmem.perBankRdBursts::5 50872 # Per bank write bursts -system.physmem.perBankRdBursts::6 46439 # Per bank write bursts -system.physmem.perBankRdBursts::7 47959 # Per bank write bursts -system.physmem.perBankRdBursts::8 44018 # Per bank write bursts -system.physmem.perBankRdBursts::9 71274 # Per bank write bursts -system.physmem.perBankRdBursts::10 43972 # Per bank write bursts -system.physmem.perBankRdBursts::11 51692 # Per bank write bursts -system.physmem.perBankRdBursts::12 45026 # Per bank write bursts -system.physmem.perBankRdBursts::13 46672 # Per bank write bursts -system.physmem.perBankRdBursts::14 42515 # Per bank write bursts -system.physmem.perBankRdBursts::15 44140 # Per bank write bursts -system.physmem.perBankWrBursts::0 64758 # Per bank write bursts -system.physmem.perBankWrBursts::1 69412 # Per bank write bursts -system.physmem.perBankWrBursts::2 67623 # Per bank write bursts -system.physmem.perBankWrBursts::3 66442 # Per bank write bursts -system.physmem.perBankWrBursts::4 66817 # Per bank write bursts -system.physmem.perBankWrBursts::5 69740 # Per bank write bursts -system.physmem.perBankWrBursts::6 65132 # Per bank write bursts -system.physmem.perBankWrBursts::7 69008 # Per bank write bursts -system.physmem.perBankWrBursts::8 65482 # Per bank write bursts -system.physmem.perBankWrBursts::9 70623 # Per bank write bursts -system.physmem.perBankWrBursts::10 64235 # Per bank write bursts -system.physmem.perBankWrBursts::11 70444 # Per bank write bursts -system.physmem.perBankWrBursts::12 64965 # Per bank write bursts -system.physmem.perBankWrBursts::13 66804 # Per bank write bursts -system.physmem.perBankWrBursts::14 64273 # Per bank write bursts -system.physmem.perBankWrBursts::15 63998 # Per bank write bursts +system.physmem.perBankRdBursts::0 114327 # Per bank write bursts +system.physmem.perBankRdBursts::1 123692 # Per bank write bursts +system.physmem.perBankRdBursts::2 118245 # Per bank write bursts +system.physmem.perBankRdBursts::3 117057 # Per bank write bursts +system.physmem.perBankRdBursts::4 115229 # Per bank write bursts +system.physmem.perBankRdBursts::5 125268 # Per bank write bursts +system.physmem.perBankRdBursts::6 115683 # Per bank write bursts +system.physmem.perBankRdBursts::7 119593 # Per bank write bursts +system.physmem.perBankRdBursts::8 115543 # Per bank write bursts +system.physmem.perBankRdBursts::9 144676 # Per bank write bursts +system.physmem.perBankRdBursts::10 112600 # Per bank write bursts +system.physmem.perBankRdBursts::11 120122 # Per bank write bursts +system.physmem.perBankRdBursts::12 113965 # Per bank write bursts +system.physmem.perBankRdBursts::13 118266 # Per bank write bursts +system.physmem.perBankRdBursts::14 113146 # Per bank write bursts +system.physmem.perBankRdBursts::15 116309 # Per bank write bursts +system.physmem.perBankWrBursts::0 135142 # Per bank write bursts +system.physmem.perBankWrBursts::1 141643 # Per bank write bursts +system.physmem.perBankWrBursts::2 136917 # Per bank write bursts +system.physmem.perBankWrBursts::3 137997 # Per bank write bursts +system.physmem.perBankWrBursts::4 135684 # Per bank write bursts +system.physmem.perBankWrBursts::5 143871 # Per bank write bursts +system.physmem.perBankWrBursts::6 135153 # Per bank write bursts +system.physmem.perBankWrBursts::7 138864 # Per bank write bursts +system.physmem.perBankWrBursts::8 135935 # Per bank write bursts +system.physmem.perBankWrBursts::9 142790 # Per bank write bursts +system.physmem.perBankWrBursts::10 134947 # Per bank write bursts +system.physmem.perBankWrBursts::11 140191 # Per bank write bursts +system.physmem.perBankWrBursts::12 134987 # Per bank write bursts +system.physmem.perBankWrBursts::13 137976 # Per bank write bursts +system.physmem.perBankWrBursts::14 134592 # Per bank write bursts +system.physmem.perBankWrBursts::15 136075 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 34 # Number of times write queue was full causing retry -system.physmem.totGap 51327141408500 # Total gap between requests +system.physmem.numWrRetry 125 # Number of times write queue was full causing retry +system.physmem.totGap 51558013451500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 747819 # Read request sizes (log2) +system.physmem.readPktSize::6 1883016 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1069454 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 515353 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 203905 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30484 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12938 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 553 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 806 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2202455 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1140639 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 689076 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 48103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 20384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 609 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 498 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1348 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -160,171 +160,170 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 26806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 32475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 54613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 60437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 62183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 62151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 69842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 64006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 76985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62423 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 65026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 68511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 60500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 57192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 74 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 471870 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 249.306089 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 149.569568 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 290.567780 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 207742 44.03% 44.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 122462 25.95% 69.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 42886 9.09% 79.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 22733 4.82% 83.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14982 3.18% 87.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9606 2.04% 89.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7566 1.60% 90.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6003 1.27% 91.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 37890 8.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 471870 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 54238 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.166341 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 76.651597 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 54233 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 30482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 38490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 83702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 117171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 125843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 130438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 133004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 138248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 140822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 137539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 142466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 143357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 133954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 146358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 136372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 127299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 130102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 120942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 1055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 365 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 933198 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 281.628105 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 167.352526 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 309.404332 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 371108 39.77% 39.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 233427 25.01% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 88383 9.47% 74.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 51664 5.54% 79.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 37413 4.01% 83.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 26389 2.83% 86.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 21045 2.26% 88.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 17945 1.92% 90.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 85824 9.20% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 933198 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 116229 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.379053 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 52.340079 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 116223 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 4 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 54238 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 54238 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.723367 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.775784 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.950161 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 40620 74.89% 74.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 4585 8.45% 83.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 5200 9.59% 92.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1381 2.55% 95.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 413 0.76% 96.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 235 0.43% 96.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 311 0.57% 97.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 127 0.23% 97.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 390 0.72% 98.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 127 0.23% 98.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 50 0.09% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 65 0.12% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 327 0.60% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 36 0.07% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 29 0.05% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 111 0.20% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 166 0.31% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 5 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 17 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 12 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 54238 # Writes before turning the bus around for reads -system.physmem.totQLat 15209667379 # Total ticks spent queuing -system.physmem.totMemAccLat 29616717379 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3841880000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19794.56 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 116229 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 116228 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.951965 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.478061 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 17.079115 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 111884 96.26% 96.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 1770 1.52% 97.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 397 0.34% 98.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 626 0.54% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 488 0.42% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 246 0.21% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 362 0.31% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 120 0.10% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 64 0.06% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 59 0.05% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 51 0.04% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 11 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 17 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 10 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 37 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 24 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 14 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 6 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 5 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 4 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-623 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::624-639 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::752-767 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::768-783 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::976-991 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 116228 # Writes before turning the bus around for reads +system.physmem.totQLat 42075497859 # Total ticks spent queuing +system.physmem.totMemAccLat 77770266609 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9518605000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22101.71 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38544.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.96 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.33 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.94 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.33 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 40851.71 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.36 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.34 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.73 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.49 # Average write queue length when enqueuing -system.physmem.readRowHits 580662 # Number of row buffer hits during reads -system.physmem.writeRowHits 785598 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.57 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.44 # Row buffer hit rate for writes -system.physmem.avgGap 27878049.64 # Average gap between requests -system.physmem.pageHitRate 74.33 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1803657240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 984138375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2956722600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3492279360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1235640856320 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29712388110000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34309704980775 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.451533 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49429181288166 # Time in different power states -system.physmem_0.memoryStateTime::REF 1713925980000 # Time in different power states +system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.62 # Average write queue length when enqueuing +system.physmem.readRowHits 1533744 # Number of row buffer hits during reads +system.physmem.writeRowHits 1639539 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.43 # Row buffer hit rate for writes +system.physmem.avgGap 12546577.18 # Average gap between requests +system.physmem.pageHitRate 77.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3530119320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1926156375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7402894200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 7162084800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3367518529440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1313077918185 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29782982922000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34483600624320 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.831109 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49545451951432 # Time in different power states +system.physmem_0.memoryStateTime::REF 1721635240000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 184032075584 # Time in different power states +system.physmem_0.memoryStateTime::ACT 290927248568 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1763679960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 962325375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3036563400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3439739520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1235034526230 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29712919978500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34309596029865 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.449411 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49430060847495 # Time in different power states -system.physmem_1.memoryStateTime::REF 1713925980000 # Time in different power states +system.physmem_1.actEnergy 3524804640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1923256500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7446082800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 7111728720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3367518529440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1314046606680 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29782133195250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34483704204030 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.833118 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49544014933949 # Time in different power states +system.physmem_1.memoryStateTime::REF 1721635240000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 183155359005 # Time in different power states +system.physmem_1.memoryStateTime::ACT 292364518051 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory @@ -341,30 +340,30 @@ system.realview.nvmem.bw_inst_read::total 7 # I system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 225047911 # Number of BP lookups -system.cpu.branchPred.condPredicted 149825196 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12305756 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 158986930 # Number of BTB lookups -system.cpu.branchPred.BTBHits 98148773 # Number of BTB hits +system.cpu.branchPred.lookups 290131106 # Number of BP lookups +system.cpu.branchPred.condPredicted 198353835 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 13679752 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 208494226 # Number of BTB lookups +system.cpu.branchPred.BTBHits 130534623 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.733863 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 30878370 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 343644 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6734089 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 4745857 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1988232 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 765703 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 62.608268 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 37597374 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 402079 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 8125236 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 6045082 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2080154 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 800698 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -394,47 +393,47 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.checker.dtb.walker.walks 197474 # Table walker walks requested -system.cpu.checker.dtb.walker.walksLong 197474 # Table walker walks initiated with long descriptors -system.cpu.checker.dtb.walker.walkWaitTime::samples 197474 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::0 197474 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::total 197474 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walksPending::samples -1584953796 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::0 -1584953796 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::total -1584953796 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walkPageSizes::4K 153977 91.65% 91.65% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::2M 14023 8.35% 100.00% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::total 168000 # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 197474 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.checker.dtb.walker.walks 345580 # Table walker walks requested +system.cpu.checker.dtb.walker.walksLong 345580 # Table walker walks initiated with long descriptors +system.cpu.checker.dtb.walker.walkWaitTime::samples 345580 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::0 345580 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::total 345580 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walksPending::samples 1638693500 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::0 1638693500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::total 1638693500 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walkPageSizes::4K 271194 90.38% 90.38% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::2M 28860 9.62% 100.00% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::total 300054 # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 345580 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 197474 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 168000 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 345580 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 300054 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 168000 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 365474 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 300054 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 645634 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 159568162 # DTB read hits -system.cpu.checker.dtb.read_misses 146947 # DTB read misses -system.cpu.checker.dtb.write_hits 144766301 # DTB write hits -system.cpu.checker.dtb.write_misses 50527 # DTB write misses -system.cpu.checker.dtb.flush_tlb 20 # Number of times complete TLB was flushed +system.cpu.checker.dtb.read_hits 205011929 # DTB read hits +system.cpu.checker.dtb.read_misses 252661 # DTB read misses +system.cpu.checker.dtb.write_hits 188856696 # DTB write hits +system.cpu.checker.dtb.write_misses 92919 # DTB write misses +system.cpu.checker.dtb.flush_tlb 22 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dtb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dtb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 71659 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_tlb_mva_asid 126550 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dtb.flush_tlb_asid 2406 # Number of times TLB was flushed by ASID +system.cpu.checker.dtb.flush_entries 84606 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 6990 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 10719 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dtb.perms_faults 19053 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 159715109 # DTB read accesses -system.cpu.checker.dtb.write_accesses 144816828 # DTB write accesses +system.cpu.checker.dtb.perms_faults 24551 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dtb.read_accesses 205264590 # DTB read accesses +system.cpu.checker.dtb.write_accesses 188949615 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 304334463 # DTB hits -system.cpu.checker.dtb.misses 197474 # DTB misses -system.cpu.checker.dtb.accesses 304531937 # DTB accesses -system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.checker.dtb.hits 393868625 # DTB hits +system.cpu.checker.dtb.misses 345580 # DTB misses +system.cpu.checker.dtb.accesses 394214205 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -464,51 +463,51 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.checker.itb.walker.walks 119817 # Table walker walks requested -system.cpu.checker.itb.walker.walksLong 119817 # Table walker walks initiated with long descriptors -system.cpu.checker.itb.walker.walkWaitTime::samples 119817 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::0 119817 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::total 119817 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walksPending::samples -1586149296 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::0 -1586149296 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::total -1586149296 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walkPageSizes::4K 107958 98.83% 98.83% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::2M 1280 1.17% 100.00% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::total 109238 # Table walker page sizes translated +system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.checker.itb.walker.walks 130718 # Table walker walks requested +system.cpu.checker.itb.walker.walksLong 130718 # Table walker walks initiated with long descriptors +system.cpu.checker.itb.walker.walkWaitTime::samples 130718 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::0 130718 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::total 130718 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walksPending::samples 1638085000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::0 1638085000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::total 1638085000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walkPageSizes::4K 116451 98.90% 98.90% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::2M 1296 1.10% 100.00% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::total 117747 # Table walker page sizes translated system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 119817 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 119817 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 130718 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 130718 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 109238 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 109238 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin::total 229055 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 848636866 # ITB inst hits -system.cpu.checker.itb.inst_misses 119817 # ITB inst misses +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 117747 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 117747 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin::total 248465 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.inst_hits 1107463254 # ITB inst hits +system.cpu.checker.itb.inst_misses 130718 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses system.cpu.checker.itb.write_hits 0 # DTB write hits system.cpu.checker.itb.write_misses 0 # DTB write misses -system.cpu.checker.itb.flush_tlb 20 # Number of times complete TLB was flushed +system.cpu.checker.itb.flush_tlb 22 # Number of times complete TLB was flushed system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.itb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.itb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 51647 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.flush_tlb_mva_asid 126550 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.itb.flush_tlb_asid 2406 # Number of times TLB was flushed by ASID +system.cpu.checker.itb.flush_entries 56882 # Number of entries that have been flushed from TLB system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 848756683 # ITB inst accesses -system.cpu.checker.itb.hits 848636866 # DTB hits -system.cpu.checker.itb.misses 119817 # DTB misses -system.cpu.checker.itb.accesses 848756683 # DTB accesses -system.cpu.checker.pwrStateResidencyTicks::ON 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.checker.numCycles 997255251 # number of cpu cycles simulated +system.cpu.checker.itb.inst_accesses 1107593972 # ITB inst accesses +system.cpu.checker.itb.hits 1107463254 # DTB hits +system.cpu.checker.itb.misses 130718 # DTB misses +system.cpu.checker.itb.accesses 1107593972 # DTB accesses +system.cpu.checker.pwrStateResidencyTicks::ON 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.checker.numCycles 1301797660 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -538,87 +537,88 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 948773 # Table walker walks requested -system.cpu.dtb.walker.walksLong 948773 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15596 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155468 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 437937 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 510836 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 2285.186439 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 14758.274331 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-65535 507265 99.30% 99.30% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-131071 2025 0.40% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-196607 1066 0.21% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-262143 211 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-327679 145 0.03% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-393215 26 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-458751 51 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::458752-524287 43 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 1423094 # Table walker walks requested +system.cpu.dtb.walker.walksLong 1423094 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 30587 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 273540 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 668841 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 754253 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2502.822660 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 16371.142747 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 747574 99.11% 99.11% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 4739 0.63% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 871 0.12% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 433 0.06% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 327 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 64 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 235 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 510836 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 488329 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 23221.803333 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 18175.804190 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 21042.780895 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 476828 97.64% 97.64% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 7891 1.62% 99.26% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 2533 0.52% 99.78% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 229 0.05% 99.83% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 568 0.12% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 131 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 114 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 26 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 488329 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 779668986876 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.725199 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.523523 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 777411937376 99.71% 99.71% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 1169683000 0.15% 99.86% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 513347500 0.07% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 208116000 0.03% 99.95% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 157188000 0.02% 99.97% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 121226500 0.02% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 32342000 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 52541000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 2605500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 779668986876 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 155469 90.88% 90.88% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 15596 9.12% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 171065 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 948773 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkWaitTime::655360-720895 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 754253 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 795185 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 25800.017606 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 21033.129871 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 18337.040091 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 776690 97.67% 97.67% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 15553 1.96% 99.63% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 1840 0.23% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 558 0.07% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 320 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 153 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 44 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 19 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 795185 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 1040609044948 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.747004 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.517062 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 1036648437448 99.62% 99.62% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 2501393000 0.24% 99.86% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 710900000 0.07% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 286069000 0.03% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 201203000 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 121106500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 48982500 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 87667500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 3189000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::18-19 41500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::20-21 55500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 1040609044948 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 273541 89.94% 89.94% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 30587 10.06% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 304128 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1423094 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 948773 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 171065 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1423094 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 304128 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 171065 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1119838 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 304128 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1727222 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 169411407 # DTB read hits -system.cpu.dtb.read_misses 675369 # DTB read misses -system.cpu.dtb.write_hits 147344334 # DTB write hits -system.cpu.dtb.write_misses 273404 # DTB write misses -system.cpu.dtb.flush_tlb 20 # Number of times complete TLB was flushed +system.cpu.dtb.read_hits 217549636 # DTB read hits +system.cpu.dtb.read_misses 1002675 # DTB read misses +system.cpu.dtb.write_hits 192429615 # DTB write hits +system.cpu.dtb.write_misses 420419 # DTB write misses +system.cpu.dtb.flush_tlb 22 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 71963 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 101 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 10047 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 126550 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 2406 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 84838 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 16158 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 69388 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 170086776 # DTB read accesses -system.cpu.dtb.write_accesses 147617738 # DTB write accesses +system.cpu.dtb.perms_faults 86326 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 218552311 # DTB read accesses +system.cpu.dtb.write_accesses 192850034 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 316755741 # DTB hits -system.cpu.dtb.misses 948773 # DTB misses -system.cpu.dtb.accesses 317704514 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 409979251 # DTB hits +system.cpu.dtb.misses 1423094 # DTB misses +system.cpu.dtb.accesses 411402345 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -648,1104 +648,1098 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 162181 # Table walker walks requested -system.cpu.itb.walker.walksLong 162181 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1496 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 120027 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 17971 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 144210 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1137.740101 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 9342.723838 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 143038 99.19% 99.19% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 619 0.43% 99.62% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 86 0.06% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 189 0.13% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 221 0.15% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::163840-196607 35 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 144210 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 139494 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 29066.088864 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24052.553358 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 24213.231696 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 136396 97.78% 97.78% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 707 0.51% 98.29% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 1985 1.42% 99.71% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 151 0.11% 99.82% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 171 0.12% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 34 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 34 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 9 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 139494 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 676589720772 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.947980 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.222341 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 35236838356 5.21% 5.21% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 641313182416 94.79% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 39010000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 686000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 4000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 676589720772 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 120027 98.77% 98.77% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1496 1.23% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 121523 # Table walker page sizes translated +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 177767 # Table walker walks requested +system.cpu.itb.walker.walksLong 177767 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1532 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 128663 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 19966 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 157801 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1393.783943 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 9971.559116 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 155663 98.65% 98.65% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 1042 0.66% 99.31% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 672 0.43% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 333 0.21% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 30 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::163840-196607 26 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::229376-262143 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::294912-327679 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::327680-360447 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 157801 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 150161 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 28501.914612 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 23015.105793 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 23459.229673 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 144112 95.97% 95.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 5152 3.43% 99.40% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 475 0.32% 99.72% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 255 0.17% 99.89% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 99 0.07% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 55 0.04% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 8 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 150161 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 911756921068 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.951043 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.216068 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 44693483152 4.90% 4.90% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 867007398416 95.09% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 55571500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 466000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 911756921068 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 128663 98.82% 98.82% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1532 1.18% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 130195 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 162181 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 162181 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 177767 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 177767 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 121523 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 121523 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 283704 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 357038073 # ITB inst hits -system.cpu.itb.inst_misses 162181 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 130195 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 130195 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 307962 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 462600046 # ITB inst hits +system.cpu.itb.inst_misses 177767 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 20 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb 22 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 78770 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 2038 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 52848 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 126550 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 2406 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 58185 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 357344 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 440221 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 357200254 # ITB inst accesses -system.cpu.itb.hits 357038073 # DTB hits -system.cpu.itb.misses 162181 # DTB misses -system.cpu.itb.accesses 357200254 # DTB accesses -system.cpu.numPwrStateTransitions 32228 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 16114 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3134631677.512784 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 60494120707.852806 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 6793 42.16% 42.16% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9285 57.62% 99.78% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.83% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 462777813 # ITB inst accesses +system.cpu.itb.hits 462600046 # DTB hits +system.cpu.itb.misses 177767 # DTB misses +system.cpu.itb.accesses 462777813 # DTB accesses +system.cpu.numPwrStateTransitions 34262 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 17131 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 2947433272.666569 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 58590018858.186401 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7811 45.60% 45.60% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9284 54.19% 99.79% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::9.5e+11-1e+12 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 16114 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 815687968559 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50511454851441 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1631385344 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::total 17131 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 1065535433949 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50492479394051 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2131080190 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 646877625 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1002761410 # Number of instructions fetch has processed -system.cpu.fetch.Branches 225047911 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 133773000 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 898188451 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26266186 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3841497 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 30548 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8722394 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1026877 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 1034 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 356664988 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6247416 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 47904 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 1571821519 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.747042 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.149310 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 789533395 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1294232501 # Number of instructions fetch has processed +system.cpu.fetch.Branches 290131106 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 174177079 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1253396684 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29442936 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 4521296 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 28032 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11449142 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1221670 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 685 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 462141962 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6901101 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 52491 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 2074872372 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.731015 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.142682 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1014113227 64.52% 64.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 214297646 13.63% 78.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 70312417 4.47% 82.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 273098229 17.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1354023092 65.26% 65.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 279633538 13.48% 78.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 86518146 4.17% 82.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 354697596 17.09% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1571821519 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.137949 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.614669 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 526332322 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 552246914 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 434136742 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 49729183 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9376358 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33563941 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 3814299 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1086052117 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29449193 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9376358 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 571289803 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 66024800 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 371545208 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 438989582 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 114595768 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1065754363 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6907795 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 5097238 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 334375 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 639506 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 63573833 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 20465 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1013430764 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1640279788 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1259572075 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1474026 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 947250209 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 66180552 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 26901106 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23243208 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 101784051 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 173837388 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 150829276 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9883117 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9014861 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1030729252 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27201158 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1045808358 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3377405 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 61244461 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 34071399 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 308913 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1571821519 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.665348 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.919634 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 2074872372 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.136143 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.607313 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 615922756 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 835719938 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 532432043 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 80077312 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10720323 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 41258933 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4059445 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1407827153 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 33008479 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10720323 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 679035070 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 79966926 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 552687037 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 549603762 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 202859254 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1383638167 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 8109162 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7348509 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 966276 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1094350 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 119568064 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 22725 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1333397174 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2200696007 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1641425227 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1433031 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1254726296 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 78670875 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 43643507 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 39180007 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 166278031 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 222554034 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 196867138 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12635283 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11114743 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1330840515 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 43953891 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1360477402 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4212137 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 73710813 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41934009 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 368799 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 2074872372 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.655692 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.916068 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 924230442 58.80% 58.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 334342298 21.27% 80.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234750151 14.93% 95.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 72048277 4.58% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6430828 0.41% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 19523 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 1226409345 59.11% 59.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 451307165 21.75% 80.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 291780533 14.06% 94.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 95920964 4.62% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9425546 0.45% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 28819 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1571821519 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 2074872372 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57691324 35.03% 35.03% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 100152 0.06% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26730 0.02% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 622 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44285841 26.89% 62.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 62576075 38.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 73561900 34.17% 34.17% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 90692 0.04% 34.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26794 0.01% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 484 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 57931960 26.91% 61.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 83660297 38.86% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 720343690 68.88% 68.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2530628 0.24% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 122776 0.01% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 375 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 119191 0.01% 69.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 173490543 16.59% 85.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 149201098 14.27% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 57 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 939889673 69.09% 69.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2936613 0.22% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 130878 0.01% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 372 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 112363 0.01% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 222587367 16.36% 85.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 194820033 14.32% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1045808358 # Type of FU issued -system.cpu.iq.rate 0.641055 # Inst issue rate -system.cpu.iq.fu_busy_cnt 164680744 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157467 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3829023509 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1118377930 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1027460456 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2472874 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 938610 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 909796 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1208933693 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1555398 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4274316 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1360477402 # Type of FU issued +system.cpu.iq.rate 0.638398 # Inst issue rate +system.cpu.iq.fu_busy_cnt 215272127 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.158233 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5012901497 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1447776434 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1338315649 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2409942 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 914537 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 885572 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1574233532 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1515940 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5717597 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14173969 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14495 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 142953 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6059351 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 17343387 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24124 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 187368 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7978529 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2526453 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1440750 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3596780 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1680866 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9376358 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 7004216 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6913167 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1058165202 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 10720323 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12040487 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4569260 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1375079942 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 173837388 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 150829276 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22819114 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 57849 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6781828 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 142953 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3462734 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5495013 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8957747 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1034296660 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 169399584 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10573772 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 222554034 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 196867138 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 38644291 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 177419 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4207009 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 187368 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4048268 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6103351 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10151619 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1346834094 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 217554512 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 12249639 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 234792 # number of nop insts executed -system.cpu.iew.exec_refs 316739180 # number of memory reference insts executed -system.cpu.iew.exec_branches 196198672 # Number of branches executed -system.cpu.iew.exec_stores 147339596 # Number of stores executed -system.cpu.iew.exec_rate 0.633999 # Inst execution rate -system.cpu.iew.wb_sent 1029187818 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1028370252 # cumulative count of insts written-back -system.cpu.iew.wb_producers 437853372 # num instructions producing a value -system.cpu.iew.wb_consumers 708400240 # num instructions consuming a value -system.cpu.iew.wb_rate 0.630366 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.618088 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 51884426 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 26892245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8549021 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1559762540 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.638999 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.273827 # Number of insts commited each cycle +system.cpu.iew.exec_nop 285536 # number of nop insts executed +system.cpu.iew.exec_refs 409993947 # number of memory reference insts executed +system.cpu.iew.exec_branches 255680172 # Number of branches executed +system.cpu.iew.exec_stores 192439435 # Number of stores executed +system.cpu.iew.exec_rate 0.631996 # Inst execution rate +system.cpu.iew.wb_sent 1340240150 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1339201221 # cumulative count of insts written-back +system.cpu.iew.wb_producers 574929948 # num instructions producing a value +system.cpu.iew.wb_consumers 943031378 # num instructions consuming a value +system.cpu.iew.wb_rate 0.628414 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.609662 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 62850702 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 43585092 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9678607 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 2060674246 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.631387 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.270689 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1047991029 67.19% 67.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288035307 18.47% 85.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 120100080 7.70% 93.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 36659789 2.35% 95.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28506606 1.83% 97.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13942789 0.89% 98.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8651847 0.55% 98.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4181084 0.27% 99.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11694009 0.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1383412740 67.13% 67.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 394991247 19.17% 86.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 150433823 7.30% 93.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 44582057 2.16% 95.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36156812 1.75% 97.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 18175173 0.88% 98.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10964042 0.53% 98.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5475656 0.27% 99.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 16482696 0.80% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1559762540 # Number of insts commited each cycle -system.cpu.commit.committedInsts 848230502 # Number of instructions committed -system.cpu.commit.committedOps 996685945 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 2060674246 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1106923026 # Number of instructions committed +system.cpu.commit.committedOps 1301083589 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 304433343 # Number of memory references committed -system.cpu.commit.loads 159663418 # Number of loads committed -system.cpu.commit.membars 6927415 # Number of memory barriers committed -system.cpu.commit.branches 189324067 # Number of branches committed -system.cpu.commit.fp_insts 898712 # Number of committed floating point instructions. -system.cpu.commit.int_insts 915721971 # Number of committed integer instructions. -system.cpu.commit.function_calls 25285288 # Number of function calls committed. +system.cpu.commit.refs 394099255 # Number of memory references committed +system.cpu.commit.loads 205210646 # Number of loads committed +system.cpu.commit.membars 9122435 # Number of memory barriers committed +system.cpu.commit.branches 247396089 # Number of branches committed +system.cpu.commit.fp_insts 873905 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1189215854 # Number of committed integer instructions. +system.cpu.commit.function_calls 30973786 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 689893101 69.22% 69.22% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2149376 0.22% 69.43% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 98151 0.01% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 111932 0.01% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 159663418 16.02% 85.47% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 144769925 14.53% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 904226715 69.50% 69.50% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2546778 0.20% 69.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 104952 0.01% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 105847 0.01% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 205210646 15.77% 85.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 188888609 14.52% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 996685945 # Class of committed instruction -system.cpu.commit.bw_lim_events 11694009 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2589097882 # The number of ROB reads -system.cpu.rob.rob_writes 2109106528 # The number of ROB writes -system.cpu.timesIdled 8171713 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59563825 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 101022900419 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 848230502 # Number of Instructions Simulated -system.cpu.committedOps 996685945 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.923281 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.923281 # CPI: Total CPI of All Threads -system.cpu.ipc 0.519945 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.519945 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1223820104 # number of integer regfile reads -system.cpu.int_regfile_writes 731394908 # number of integer regfile writes -system.cpu.fp_regfile_reads 1462803 # number of floating regfile reads -system.cpu.fp_regfile_writes 780644 # number of floating regfile writes -system.cpu.cc_regfile_reads 225050166 # number of cc regfile reads -system.cpu.cc_regfile_writes 225684828 # number of cc regfile writes -system.cpu.misc_regfile_reads 2570368432 # number of misc regfile reads -system.cpu.misc_regfile_writes 26931155 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9701158 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.972800 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 283187639 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9701670 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.189577 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 2743199500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.972800 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy +system.cpu.commit.op_class_0::total 1301083589 # Class of committed instruction +system.cpu.commit.bw_lim_events 16482696 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3398675710 # The number of ROB reads +system.cpu.rob.rob_writes 2741957858 # The number of ROB writes +system.cpu.timesIdled 9058128 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 56207818 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 100984949503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 1106923026 # Number of Instructions Simulated +system.cpu.committedOps 1301083589 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.925229 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.925229 # CPI: Total CPI of All Threads +system.cpu.ipc 0.519419 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.519419 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1599627417 # number of integer regfile reads +system.cpu.int_regfile_writes 942915982 # number of integer regfile writes +system.cpu.fp_regfile_reads 1421408 # number of floating regfile reads +system.cpu.fp_regfile_writes 762380 # number of floating regfile writes +system.cpu.cc_regfile_reads 312164706 # number of cc regfile reads +system.cpu.cc_regfile_writes 313034766 # number of cc regfile writes +system.cpu.misc_regfile_reads 3414318389 # number of misc regfile reads +system.cpu.misc_regfile_writes 44468731 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 13662519 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.983620 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 361203380 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 13663031 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 26.436548 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1659288500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.983620 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 395 # 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miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.756052 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.756052 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.792087 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.792087 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119373 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119373 # miss rate for LoadLockedReq accesses +system.cpu.dcache.tags.tag_accesses 1599492126 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1599492126 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 186946586 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 186946586 # 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average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32224409 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.085323 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.085323 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.090060 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.090060 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16095.314606 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16095.314606 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53809.325082 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53809.325082 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23587.956296 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23587.956296 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16291.062223 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16291.062223 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 33388.888889 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 33388.888889 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37889.669487 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37889.669487 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35663.668807 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35663.668807 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24419954 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1601607 # 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number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 7056 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 219268 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 219268 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 13714443 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 13714443 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 13714443 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 13714443 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5124316 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5124316 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2003239 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2003239 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1163648 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1163648 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1226583 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1226583 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 227441 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 227441 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 8 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 8354138 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 8354138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9517786 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9517786 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84959954500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 84959954500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77558080846 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77558080846 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23723735000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23723735000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 50708992789 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 50708992789 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3202218000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3202218000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 372500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 372500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213227028135 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 213227028135 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 236950763135 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 236950763135 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6192056000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6192056000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6192056000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6192056000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032685 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032685 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014359 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014359 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751649 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751649 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787557 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787557 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060778 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060778 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.writebacks::writebacks 10319802 # number of writebacks +system.cpu.dcache.writebacks::total 10319802 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5736139 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5736139 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15576096 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15576096 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6849 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 6849 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 265006 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 265006 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 21319084 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 21319084 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 21319084 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 21319084 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7051922 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7051922 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3072420 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3072420 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2034687 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2034687 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263657 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1263657 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 283363 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 283363 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 9 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 9 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 11387999 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 11387999 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 13422686 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 13422686 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 33692 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 67395 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 110827450000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 110827450000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 147154305213 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 147154305213 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 32559356000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 32559356000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 28426038502 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 28426038502 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4117736500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4117736500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 291500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 291500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 286407793715 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 286407793715 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 318967149715 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 318967149715 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6225596500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6225596500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6225596500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6225596500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035306 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035306 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016882 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016882 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.812301 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.812301 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787574 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787574 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.053048 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.053048 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028048 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028048 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031790 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031790 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16579.764890 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16579.764890 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38716.339311 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38716.339311 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20387.380892 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20387.380892 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41341.672589 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41341.672589 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14079.334860 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14079.334860 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 46562.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 46562.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25523.522371 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25523.522371 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24895.575834 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24895.575834 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183860.561791 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183860.561791 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.720308 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.720308 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 15134592 # number of replacements -system.cpu.icache.tags.tagsinuse 511.928988 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 340756209 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15135104 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22.514296 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 20447572500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.928988 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999861 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999861 # Average percentage of cache occupancy +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029708 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.029708 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034789 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034789 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15715.921135 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15715.921135 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47895.243884 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47895.243884 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16002.144802 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16002.144802 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22495.058787 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22495.058787 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14531.666096 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14531.666096 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 32388.888889 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 32388.888889 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25149.966532 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25149.966532 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23763.287744 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23763.287744 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184779.665796 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184779.665796 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92374.753320 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92374.753320 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 16891256 # number of replacements +system.cpu.icache.tags.tagsinuse 511.956016 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 444441322 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16891768 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26.311119 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 13164566500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.956016 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999914 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999914 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 112 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 371779021 # Number of tag accesses -system.cpu.icache.tags.data_accesses 371779021 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 340756209 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 340756209 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 340756209 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 340756209 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 340756209 # number of overall hits -system.cpu.icache.overall_hits::total 340756209 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15887482 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15887482 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15887482 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15887482 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15887482 # number of overall misses -system.cpu.icache.overall_misses::total 15887482 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 214918228873 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 214918228873 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 214918228873 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 214918228873 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 214918228873 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 214918228873 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 356643691 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 356643691 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 356643691 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 356643691 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 356643691 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 356643691 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044547 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.044547 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.044547 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.044547 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.044547 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.044547 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13527.519897 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13527.519897 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13527.519897 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13527.519897 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13527.519897 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13527.519897 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 24649 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 479012658 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 192625378387 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192625378387 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 192625378387 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 2684938500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 2684938500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 2684938500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 2684938500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.042438 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.042438 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.042438 # 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average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.968724 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.968724 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.968724 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1148622 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65301.900403 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 46289210 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1211379 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 38.211996 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 4512200500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37189.560843 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 293.778433 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 476.562000 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 7800.369043 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 19541.630085 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.567468 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004483 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007272 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.119024 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.298182 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996428 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 234 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62523 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 234 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 564 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2712 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5162 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54018 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003571 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.954025 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 410396361 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12472.863440 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75642.082277 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75642.082277 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75642.082277 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75642.082277 # average overall mshr uncacheable latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 2372905 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65457.290128 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 58959202 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2435994 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 24.203345 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2520974000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 9397.889077 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 196.572797 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 228.214718 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6628.882550 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 49005.730985 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.143400 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.002999 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.003482 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101149 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 153827177338 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1344547500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5804287500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7148835000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1344547500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5804287500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 7148835000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.008126 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.028090 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012019 # mshr miss rate for ReadReq accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.785050 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.785050 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.201159 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.201159 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005506 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005506 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.039465 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039465 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.407265 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.407265 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004498 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.011061 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005506 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.076921 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.030044 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004498 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.011061 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005506 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.076921 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.030044 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129027.059531 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128624.275131 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68019.072693 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68019.072693 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69375 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69375 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129347.114780 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129347.114780 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124865.765533 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124865.765533 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129442.828646 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129442.828646 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69894.144460 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69894.144460 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129027.059531 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124865.765533 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129384.846523 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128870.322998 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129027.059531 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124865.765533 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129384.846523 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128870.322998 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171356.256310 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148979.471367 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85655.237926 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 92363.643028 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 50407203 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 25570213 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3413 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2115 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2115 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.094837 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.094837 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.444444 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.444444 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437822 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437822 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005741 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.045756 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.045756 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.466977 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.466977 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008126 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.028090 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.142052 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060787 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008126 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.028090 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.142052 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060787 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 79519.552688 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19090.240314 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19090.240314 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45375 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45375 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82894.958867 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82894.958867 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75598.356935 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75598.356935 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80471.401186 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80471.401186 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20686.901693 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20686.901693 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75598.356935 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82306.041929 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81931.089559 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75598.356935 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82306.041929 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81931.089559 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63142.082277 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172274.946575 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 130011.912123 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63142.082277 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86123.414200 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 80605.655718 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 62084255 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 31529230 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3455 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2096 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2096 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1618708 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23266675 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8573574 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 15134592 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2391693 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43548 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43556 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1963232 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1963232 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15135331 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6520715 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1333247 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1226583 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45447628 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29327152 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 726647 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1928826 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 77430253 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1937602080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1022907422 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2405600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6328296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2969243398 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1852603 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 72285944 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 27912596 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.024958 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.155996 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 2242102 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 28488845 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33703 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33703 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 12415627 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 16891256 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 3619797 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43003 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 43012 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3045422 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3045422 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 16891994 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 9356331 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1295806 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1263657 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50717623 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41210208 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 777423 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3005376 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 95710630 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2162455328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1454268658 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2489712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10275752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 3629489450 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2999840 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 138927432 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 35281285 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.026592 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.160887 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 27215961 97.50% 97.50% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 696635 2.50% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 34343098 97.34% 97.34% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 938187 2.66% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 27912596 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 48339894491 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 35281285 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 58941748976 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1459384 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1470395 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22733591738 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 25369728010 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13401353655 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 19308156079 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 426266814 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 466604190 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1138134788 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1721722349 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40293 # Transaction distribution -system.iobus.trans_dist::ReadResp 40293 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40300 # Transaction distribution +system.iobus.trans_dist::ReadResp 40300 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1762,11 +1756,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230944 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230958 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353728 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353742 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1781,16 +1775,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334208 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334264 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334264 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492128 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 41884500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492184 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 41887500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 345000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 337000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1798,85 +1792,85 @@ system.iobus.reqLayer4.occupancy 9500 # La system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25117000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25106500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 36500500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 567323274 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 568968673 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147704000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147718000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115453 # number of replacements -system.iocache.tags.tagsinuse 10.423128 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115465 # number of replacements +system.iocache.tags.tagsinuse 10.450543 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115469 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115481 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13098782503000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544201 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.878927 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221513 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.429933 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651446 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13091229344000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 5.877255 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 4.573288 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.367328 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.285830 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653159 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039605 # Number of tag accesses -system.iocache.tags.data_accesses 1039605 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039668 # Number of tag accesses +system.iocache.tags.data_accesses 1039668 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8808 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8845 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8815 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8852 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115472 # number of demand (read+write) misses -system.iocache.demand_misses::total 115512 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115479 # number of demand (read+write) misses +system.iocache.demand_misses::total 115519 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115472 # number of overall misses -system.iocache.overall_misses::total 115512 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5076000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1670063987 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1675139987 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115479 # number of overall misses +system.iocache.overall_misses::total 115519 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1629675592 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1634761592 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13414774287 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13414774287 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5427000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15084838274 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15090265274 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5427000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15084838274 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15090265274 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12811525081 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12811525081 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14441200673 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14446637673 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14441200673 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14446637673 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8808 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8845 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8815 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8852 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115472 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115512 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115479 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115519 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115472 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115512 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115479 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115519 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1890,53 +1884,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137189.189189 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 189607.627952 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 189388.353533 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 184875.279864 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 184677.089019 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125766.653107 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125766.653107 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135675 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 130636.329794 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 130638.074607 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135675 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 130636.329794 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 130638.074607 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33964 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120111.050411 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120111.050411 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125054.777691 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125058.541651 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125054.777691 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125058.541651 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32070 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3510 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3415 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.676353 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.390922 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8808 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8845 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8815 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8852 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115472 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115512 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115479 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115519 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115472 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115512 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3226000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1229663987 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1232889987 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115479 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115519 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1188925592 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1192161592 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8076516803 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8076516803 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3427000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9306180790 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9309607790 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3427000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9306180790 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9309607790 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7471582182 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7471582182 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8660507774 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8663944774 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8660507774 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8663944774 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1950,89 +1944,95 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87189.189189 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139607.627952 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 139388.353533 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134875.279864 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 134677.089019 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75719.238009 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75719.238009 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85675 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 80592.531436 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 80594.291416 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85675 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 80592.531436 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 80594.291416 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 54972 # Transaction distribution -system.membus.trans_dist::ReadResp 411033 # Transaction distribution -system.membus.trans_dist::WriteReq 33696 # Transaction distribution -system.membus.trans_dist::WriteResp 33696 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1069454 # Transaction distribution -system.membus.trans_dist::CleanEvict 193565 # Transaction distribution -system.membus.trans_dist::UpgradeReq 34895 # Transaction distribution +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70047.834152 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70047.834152 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 74996.386997 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75000.171175 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74996.386997 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75000.171175 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 5074419 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2524015 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3002 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 54986 # Transaction distribution +system.membus.trans_dist::ReadResp 608005 # Transaction distribution +system.membus.trans_dist::WriteReq 33703 # Transaction distribution +system.membus.trans_dist::WriteResp 33703 # Transaction distribution +system.membus.trans_dist::WritebackDirty 2202455 # Transaction distribution +system.membus.trans_dist::CleanEvict 284620 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4643 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 394310 # Transaction distribution -system.membus.trans_dist::ReadExResp 394310 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 356061 # Transaction distribution -system.membus.trans_dist::InvalidateReq 606112 # Transaction distribution +system.membus.trans_dist::ReadExReq 1332798 # Transaction distribution +system.membus.trans_dist::ReadExResp 1332798 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 553019 # Transaction distribution +system.membus.trans_dist::InvalidateReq 696755 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3212019 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3341639 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237917 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237917 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3579556 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6767333 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 6896995 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237693 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237693 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7134688 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 109397260 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 109567230 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7269248 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7269248 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 116836478 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2560 # Total snoops (count) -system.membus.snoopTraffic 163328 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2743103 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 254577484 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 254747538 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7253696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 262001234 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2809 # Total snoops (count) +system.membus.snoopTraffic 179264 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2675908 # Request fanout histogram +system.membus.snoop_fanout::mean 0.013150 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.113918 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2743103 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2640719 98.68% 98.68% # Request fanout histogram +system.membus.snoop_fanout::1 35189 1.32% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2743103 # Request fanout histogram -system.membus.reqLayer0.occupancy 103939500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2675908 # Request fanout histogram +system.membus.reqLayer0.occupancy 103923000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5573000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5620000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7172212711 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 14223305475 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4075256665 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 10050154677 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44789891 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44814659 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -2042,11 +2042,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -2075,30 +2075,30 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16114 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 17131 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index df40a85e7..7c01d248f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,171 +1,171 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.384351 # Number of seconds simulated -sim_ticks 47384351300000 # Number of ticks simulated -final_tick 47384351300000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.383918 # Number of seconds simulated +sim_ticks 47383917710000 # Number of ticks simulated +final_tick 47383917710000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 183431 # Simulator instruction rate (inst/s) -host_op_rate 207694 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7126665146 # Simulator tick rate (ticks/s) -host_mem_usage 777076 # Number of bytes of host memory used -host_seconds 6648.88 # Real time elapsed on the host -sim_insts 1219610005 # Number of instructions simulated -sim_ops 1380933056 # Number of ops (including micro ops) simulated +host_inst_rate 126839 # Simulator instruction rate (inst/s) +host_op_rate 149150 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6559041658 # Simulator tick rate (ticks/s) +host_mem_usage 782584 # Number of bytes of host memory used +host_seconds 7224.21 # Real time elapsed on the host +sim_insts 916315151 # Number of instructions simulated +sim_ops 1077489368 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 205248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 202880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4270112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 16788488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 21729728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 123968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 83584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3109600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 10061712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 12393536 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 438400 # Number of bytes read from this memory -system.physmem.bytes_read::total 69407256 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4270112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3109600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7379712 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 85545984 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 217728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 211200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4242016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 16335944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 21100544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 95616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 61568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3171760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 9979472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 12170752 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 426688 # Number of bytes read from this memory +system.physmem.bytes_read::total 68013288 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4242016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3171760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7413776 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 84160640 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 85566568 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 3207 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3170 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 82673 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 262333 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 339527 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1937 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1306 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 48631 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 157227 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 193649 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6850 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1100510 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1336656 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 84181224 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3402 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3300 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 82234 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 255262 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 329696 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1494 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 962 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 49603 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 155942 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 190168 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6667 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1078730 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1315010 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1339230 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 4332 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 4282 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 90117 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 354304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 458584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2616 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1764 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 65625 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 212343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 261553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9252 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1464772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 90117 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 65625 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 155742 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1805364 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1317584 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 4595 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 4457 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 89524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 344757 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 445310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2018 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 66937 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 210609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 256854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1435366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 89524 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 66937 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 156462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1776144 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1805798 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1805364 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 4332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 4282 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 90117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 354739 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 458584 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2616 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1764 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 65625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 212343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 261553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9252 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3270570 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1100510 # Number of read requests accepted -system.physmem.writeReqs 1339230 # Number of write requests accepted -system.physmem.readBursts 1100510 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1339230 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 70408640 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 24000 # Total number of bytes read from write queue -system.physmem.bytesWritten 85564992 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 69407256 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 85566568 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 375 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2249 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1776578 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1776144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 4595 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 4457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 89524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 345191 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 445310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2018 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 66937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 210609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 256854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9005 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3211944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1078730 # Number of read requests accepted +system.physmem.writeReqs 1317584 # Number of write requests accepted +system.physmem.readBursts 1078730 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1317584 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 69010688 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 28032 # Total number of bytes read from write queue +system.physmem.bytesWritten 84179968 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 68013288 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 84181224 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 438 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 70416 # Per bank write bursts -system.physmem.perBankRdBursts::1 75191 # Per bank write bursts -system.physmem.perBankRdBursts::2 64063 # Per bank write bursts -system.physmem.perBankRdBursts::3 69912 # Per bank write bursts -system.physmem.perBankRdBursts::4 59812 # Per bank write bursts -system.physmem.perBankRdBursts::5 69643 # Per bank write bursts -system.physmem.perBankRdBursts::6 65430 # Per bank write bursts -system.physmem.perBankRdBursts::7 68144 # Per bank write bursts -system.physmem.perBankRdBursts::8 61950 # Per bank write bursts -system.physmem.perBankRdBursts::9 89644 # Per bank write bursts -system.physmem.perBankRdBursts::10 68037 # Per bank write bursts -system.physmem.perBankRdBursts::11 70586 # Per bank write bursts -system.physmem.perBankRdBursts::12 61163 # Per bank write bursts -system.physmem.perBankRdBursts::13 71056 # Per bank write bursts -system.physmem.perBankRdBursts::14 65094 # Per bank write bursts -system.physmem.perBankRdBursts::15 69994 # Per bank write bursts -system.physmem.perBankWrBursts::0 85481 # Per bank write bursts -system.physmem.perBankWrBursts::1 90029 # Per bank write bursts -system.physmem.perBankWrBursts::2 81966 # Per bank write bursts -system.physmem.perBankWrBursts::3 85433 # Per bank write bursts -system.physmem.perBankWrBursts::4 77921 # Per bank write bursts -system.physmem.perBankWrBursts::5 84076 # Per bank write bursts -system.physmem.perBankWrBursts::6 83054 # Per bank write bursts -system.physmem.perBankWrBursts::7 85039 # Per bank write bursts -system.physmem.perBankWrBursts::8 78873 # Per bank write bursts -system.physmem.perBankWrBursts::9 84297 # Per bank write bursts -system.physmem.perBankWrBursts::10 83224 # Per bank write bursts -system.physmem.perBankWrBursts::11 86586 # Per bank write bursts -system.physmem.perBankWrBursts::12 79852 # Per bank write bursts -system.physmem.perBankWrBursts::13 85124 # Per bank write bursts -system.physmem.perBankWrBursts::14 80745 # Per bank write bursts -system.physmem.perBankWrBursts::15 85253 # Per bank write bursts +system.physmem.perBankRdBursts::0 67696 # Per bank write bursts +system.physmem.perBankRdBursts::1 73149 # Per bank write bursts +system.physmem.perBankRdBursts::2 67549 # Per bank write bursts +system.physmem.perBankRdBursts::3 71981 # Per bank write bursts +system.physmem.perBankRdBursts::4 66956 # Per bank write bursts +system.physmem.perBankRdBursts::5 73789 # Per bank write bursts +system.physmem.perBankRdBursts::6 64889 # Per bank write bursts +system.physmem.perBankRdBursts::7 66635 # Per bank write bursts +system.physmem.perBankRdBursts::8 57075 # Per bank write bursts +system.physmem.perBankRdBursts::9 82656 # Per bank write bursts +system.physmem.perBankRdBursts::10 58467 # Per bank write bursts +system.physmem.perBankRdBursts::11 69413 # Per bank write bursts +system.physmem.perBankRdBursts::12 60741 # Per bank write bursts +system.physmem.perBankRdBursts::13 63810 # Per bank write bursts +system.physmem.perBankRdBursts::14 67156 # Per bank write bursts +system.physmem.perBankRdBursts::15 66330 # Per bank write bursts +system.physmem.perBankWrBursts::0 82175 # Per bank write bursts +system.physmem.perBankWrBursts::1 87404 # Per bank write bursts +system.physmem.perBankWrBursts::2 82364 # Per bank write bursts +system.physmem.perBankWrBursts::3 86039 # Per bank write bursts +system.physmem.perBankWrBursts::4 82832 # Per bank write bursts +system.physmem.perBankWrBursts::5 88693 # Per bank write bursts +system.physmem.perBankWrBursts::6 80795 # Per bank write bursts +system.physmem.perBankWrBursts::7 83065 # Per bank write bursts +system.physmem.perBankWrBursts::8 76149 # Per bank write bursts +system.physmem.perBankWrBursts::9 79916 # Per bank write bursts +system.physmem.perBankWrBursts::10 77037 # Per bank write bursts +system.physmem.perBankWrBursts::11 82986 # Per bank write bursts +system.physmem.perBankWrBursts::12 77147 # Per bank write bursts +system.physmem.perBankWrBursts::13 80171 # Per bank write bursts +system.physmem.perBankWrBursts::14 84038 # Per bank write bursts +system.physmem.perBankWrBursts::15 84501 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 51215 # Number of times write queue was full causing retry -system.physmem.totGap 47384349786500 # Total gap between requests +system.physmem.numWrRetry 50212 # Number of times write queue was full causing retry +system.physmem.totGap 47383916196500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) -system.physmem.readPktSize::4 21333 # Read request sizes (log2) +system.physmem.readPktSize::4 21334 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1079152 # Read request sizes (log2) +system.physmem.readPktSize::6 1057371 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1336656 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 480448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 272774 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 88894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 67384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 42690 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 36411 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 33268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27820 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 7595 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2606 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1628 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 684 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 590 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 501 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1315010 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 477824 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 264556 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 85571 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 63109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 41587 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 35911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 32865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 30424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27932 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 7543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 3912 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2354 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1437 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1085 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 609 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 445 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 357 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 93 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -189,136 +189,136 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 24574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 28512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 38198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 43791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 48248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 52275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 57744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 62191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 67593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 69901 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 75312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 79272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 77429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 80341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 90816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 80863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 73646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 69003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 2100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 2366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 2471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 2894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 3089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 3468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 6200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 24545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 120342 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1069816 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 145.794462 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 98.799028 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 192.755385 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 712470 66.60% 66.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 211048 19.73% 86.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 55044 5.15% 91.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23596 2.21% 93.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 18557 1.73% 95.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 10547 0.99% 96.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7452 0.70% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5550 0.52% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25552 2.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1069816 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 62458 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 17.613853 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 71.325725 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 62454 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 22527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 26520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 36837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 42274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 46464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 50322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 56496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 66561 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 68608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 74012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 78194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 76215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 79218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 90231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 80845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 75138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 70175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 2035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 2146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 2370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 2522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 2917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 2998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 2934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 3382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 4014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 5428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 24238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 118579 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1002120 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 152.866515 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.517170 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 198.697434 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 641919 64.06% 64.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 209293 20.89% 84.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 56817 5.67% 90.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24891 2.48% 93.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 19538 1.95% 95.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11144 1.11% 96.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7510 0.75% 96.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6154 0.61% 97.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24854 2.48% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1002120 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61846 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 17.434870 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 71.484606 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 61843 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 62458 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 62458 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.405633 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.660061 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 609.107080 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-4095 62456 100.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45056-49151 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 61846 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61846 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.267535 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.561626 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 606.950117 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-4095 61844 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40960-45055 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::143360-147455 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 62458 # Writes before turning the bus around for reads -system.physmem.totQLat 48895390505 # Total ticks spent queuing -system.physmem.totMemAccLat 69522921755 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5500675000 # Total ticks spent in databus transfers -system.physmem.avgQLat 44444.90 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 61846 # Writes before turning the bus around for reads +system.physmem.totQLat 51075620081 # Total ticks spent queuing +system.physmem.totMemAccLat 71293595081 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5391460000 # Total ticks spent in databus transfers +system.physmem.avgQLat 47367.15 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 63194.90 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.49 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.81 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.46 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.81 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 66117.15 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.46 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.78 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.44 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.78 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.21 # Average write queue length when enqueuing -system.physmem.readRowHits 830166 # Number of row buffer hits during reads -system.physmem.writeRowHits 537104 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.46 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.17 # Row buffer hit rate for writes -system.physmem.avgGap 19421885.03 # Average gap between requests -system.physmem.pageHitRate 56.10 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4087639080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2230358625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4232326800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4361033520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3094915112640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1166279241240 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27407555547000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31683661258905 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.652499 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45594888254330 # Time in different power states -system.physmem_0.memoryStateTime::REF 1582267440000 # Time in different power states +system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.55 # Average write queue length when enqueuing +system.physmem.readRowHits 810741 # Number of row buffer hits during reads +system.physmem.writeRowHits 580742 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.19 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 44.15 # Row buffer hit rate for writes +system.physmem.avgGap 19773667.47 # Average gap between requests +system.physmem.pageHitRate 58.13 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3929423400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2144030625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4310615400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4363418160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3094887141840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1164748800645 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27408641092500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31683024522570 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.645104 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45596671664426 # Time in different power states +system.physmem_0.memoryStateTime::REF 1582253140000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 207195159170 # Time in different power states +system.physmem_0.memoryStateTime::ACT 204992820574 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4000169880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2182632375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4348679400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4302421920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3094915112640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1168435080135 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27405664460250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31683848556600 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.656452 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45591701065782 # Time in different power states -system.physmem_1.memoryStateTime::REF 1582267440000 # Time in different power states +system.physmem_1.actEnergy 3646603800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1989714375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4100054400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4159803600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3094887141840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1159320938310 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27413402375250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31681506631575 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.613070 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45604605403923 # Time in different power states +system.physmem_1.memoryStateTime::REF 1582253140000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 210382633218 # Time in different power states +system.physmem_1.memoryStateTime::ACT 197059081077 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory @@ -345,30 +345,30 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 199183431 # Number of BP lookups -system.cpu0.branchPred.condPredicted 140489040 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 7036065 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 156342542 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 99990575 # Number of BTB hits +system.cpu0.branchPred.lookups 139955722 # Number of BP lookups +system.cpu0.branchPred.condPredicted 92576910 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6767718 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 98409045 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 61922323 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 63.956089 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 20013017 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 198399 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4618183 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2919648 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 1698535 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 412858 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 62.923406 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 19026711 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 185987 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 4326684 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2749366 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 1577318 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 397214 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -398,86 +398,86 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 607513 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 607513 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13877 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 97395 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 289192 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 318321 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2219.643065 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 12711.673990 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 315923 99.25% 99.25% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1786 0.56% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 409 0.13% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 127 0.04% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 41 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 31 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 318321 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 324666 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 20482.457356 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 17703.017560 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 16938.599592 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 320665 98.77% 98.77% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 2783 0.86% 99.62% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 369 0.11% 99.74% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 625 0.19% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 139 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 57 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 611788 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 611788 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13108 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 98298 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 292807 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 318981 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2428.828049 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 13543.109769 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 316274 99.15% 99.15% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 2036 0.64% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 442 0.14% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 138 0.04% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 53 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 29 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 318981 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 326187 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 22022.583671 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18838.451550 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 17664.426007 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 321608 98.60% 98.60% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 3320 1.02% 99.61% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 429 0.13% 99.75% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 611 0.19% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 146 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 45 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::393216-458751 21 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 324666 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 513372677252 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.571567 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.552695 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 512028975252 99.74% 99.74% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 726675000 0.14% 99.88% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 290458500 0.06% 99.94% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 129299000 0.03% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 102361000 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 55725500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 16517000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 21785000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 858500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 22500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 513372677252 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 97395 87.53% 87.53% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 13877 12.47% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 111272 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 607513 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 326187 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 530119453936 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.586335 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.554664 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 528635854936 99.72% 99.72% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 807711000 0.15% 99.87% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 321496500 0.06% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 138249500 0.03% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 109943500 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 58618500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 20610000 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 26013000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 940000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 17000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 530119453936 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 98298 88.23% 88.23% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 13108 11.77% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 111406 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 611788 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 607513 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 111272 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 611788 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 111406 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 111272 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 718785 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 111406 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 723194 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 141538315 # DTB read hits -system.cpu0.dtb.read_misses 437252 # DTB read misses -system.cpu0.dtb.write_hits 86796370 # DTB write hits -system.cpu0.dtb.write_misses 170261 # DTB write misses +system.cpu0.dtb.read_hits 102674478 # DTB read hits +system.cpu0.dtb.read_misses 445170 # DTB read misses +system.cpu0.dtb.write_hits 82832935 # DTB write hits +system.cpu0.dtb.write_misses 166618 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 44490 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 43183 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 271 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 6902 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 44145 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 42795 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 479 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 7037 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 42288 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 141975567 # DTB read accesses -system.cpu0.dtb.write_accesses 86966631 # DTB write accesses +system.cpu0.dtb.perms_faults 40072 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 103119648 # DTB read accesses +system.cpu0.dtb.write_accesses 82999553 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 228334685 # DTB hits -system.cpu0.dtb.misses 607513 # DTB misses -system.cpu0.dtb.accesses 228942198 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 185507413 # DTB hits +system.cpu0.dtb.misses 611788 # DTB misses +system.cpu0.dtb.accesses 186119201 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -507,1194 +507,1182 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 87943 # Table walker walks requested -system.cpu0.itb.walker.walksLong 87943 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1130 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 62851 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 10253 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 77690 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1458.353713 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 10159.922633 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 76707 98.73% 98.73% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 405 0.52% 99.26% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 337 0.43% 99.69% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 198 0.25% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 85546 # Table walker walks requested +system.cpu0.itb.walker.walksLong 85546 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1054 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59782 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 10366 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 75180 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1322.160149 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 9414.531253 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 74314 98.85% 98.85% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 448 0.60% 99.44% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 228 0.30% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 153 0.20% 99.95% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::131072-163839 9 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 14 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 9 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 10 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::294912-327679 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 77690 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 74234 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 26234.178409 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23080.051735 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 21732.027543 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 71871 96.82% 96.82% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1986 2.68% 99.49% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 153 0.21% 99.70% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 128 0.17% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 62 0.08% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 21 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 9 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 75180 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 71202 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 26797.709334 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23346.070270 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 22372.473032 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 68772 96.59% 96.59% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 2000 2.81% 99.40% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 197 0.28% 99.67% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 144 0.20% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 55 0.08% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 23 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 74234 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 410290287148 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.846605 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.360675 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 62979367364 15.35% 15.35% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 347270506784 84.64% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 38246000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 1931000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 236000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 410290287148 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 62851 98.23% 98.23% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 1130 1.77% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 63981 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 71202 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 422744199036 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.876427 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.329334 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 52271860780 12.36% 12.36% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 370441299256 87.63% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 29828500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 1210500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 422744199036 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 59782 98.27% 98.27% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 1054 1.73% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 60836 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 87943 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 87943 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 85546 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 85546 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 63981 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 63981 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 151924 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 282848559 # ITB inst hits -system.cpu0.itb.inst_misses 87943 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60836 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60836 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 146382 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 220474674 # ITB inst hits +system.cpu0.itb.inst_misses 85546 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 44490 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 30949 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 44145 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 31037 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 212727 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 205838 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 282936502 # ITB inst accesses -system.cpu0.itb.hits 282848559 # DTB hits -system.cpu0.itb.misses 87943 # DTB misses -system.cpu0.itb.accesses 282936502 # DTB accesses -system.cpu0.numPwrStateTransitions 28168 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 14084 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 3333377849.836978 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 92382687873.308472 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 4020 28.54% 28.54% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 10033 71.24% 99.78% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 12 0.09% 99.87% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 13 0.09% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 6914082605000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 14084 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 437057662896 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46947293637104 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 874125395 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 220560220 # ITB inst accesses +system.cpu0.itb.hits 220474674 # DTB hits +system.cpu0.itb.misses 85546 # DTB misses +system.cpu0.itb.accesses 220560220 # DTB accesses +system.cpu0.numPwrStateTransitions 10840 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 5420 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 8671662092.472324 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 149203914828.202179 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3833 70.72% 70.72% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 1557 28.73% 99.45% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 11 0.20% 99.65% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 3 0.06% 99.70% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.72% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.74% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.76% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 13 0.24% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 6993554617000 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 5420 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 383509168800 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 47000408541200 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 767019929 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 92275983 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 768900237 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 199183431 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 122923240 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 738928784 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 15190816 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2037144 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 294842 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 6072240 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 792344 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 839757 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 282635522 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1737700 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 28623 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 848836502 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.034930 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.208968 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 88196996 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 619911097 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 139955722 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 83698400 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 636708825 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 14589342 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2007819 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 289070 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 6017581 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 759490 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 830550 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 220269194 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1684756 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 27864 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 742105002 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.977120 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.219124 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 416377385 49.05% 49.05% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 176079063 20.74% 69.80% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 66732959 7.86% 77.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 189647095 22.34% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 394679215 53.18% 53.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 135211877 18.22% 71.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 46727804 6.30% 77.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 165486106 22.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 848836502 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.227866 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.879622 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 110330106 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 381856903 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 311429263 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 39757521 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5462709 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 29836532 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2173523 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 791623702 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 24444549 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5462709 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 147675961 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 53914284 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 258297798 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 313275075 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 70210675 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 773227105 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 6509157 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 10689754 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 377832 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 811571 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 32991272 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 11799 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 742885425 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1169549966 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 880889153 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 700737 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 682115784 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 60769635 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 16576266 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 14423738 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 79729853 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 141637487 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 90242008 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 9692958 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 8374311 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 749539213 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 16620515 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 754385019 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2849937 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 57154900 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 36998097 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 294454 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 848836502 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.888728 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.088535 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 742105002 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.182467 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.808207 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 106471358 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 362106065 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 229306920 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 38969186 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5251473 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19951761 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2082457 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 641630797 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 23347252 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5251473 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 142650653 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 53065481 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 241402745 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 231558396 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 68176254 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 624076980 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6229632 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 10704846 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 385160 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 931811 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 31501280 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 11804 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 596222700 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 963956032 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 736577059 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 695179 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 537389975 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 58832686 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 16140854 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 14103711 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 78118251 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 102816112 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 86124751 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 9533509 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 8142362 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 600960924 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 16329392 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 605893488 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2751703 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 55206879 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 35882934 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 285911 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 742105002 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.816453 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.065729 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 442949824 52.18% 52.18% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 161566736 19.03% 71.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 148384909 17.48% 88.70% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 87697049 10.33% 99.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 8232602 0.97% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 5382 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 411055814 55.39% 55.39% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 139198751 18.76% 74.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 116841261 15.74% 89.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 67029634 9.03% 98.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 7974397 1.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 5145 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 848836502 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 742105002 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 74538342 48.88% 48.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 62447 0.04% 48.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 15099 0.01% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 9 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 48.93% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 37581602 24.64% 73.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 40298347 26.43% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 62807824 45.43% 45.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 65216 0.05% 45.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 15839 0.01% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 32 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 36880846 26.68% 72.17% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 38467267 27.83% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 51 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 519755806 68.90% 68.90% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1543884 0.20% 69.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 77211 0.01% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 64 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 2 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 1 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 42719 0.01% 69.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.12% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 144854124 19.20% 88.32% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 88111156 11.68% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 25 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 414236377 68.37% 68.37% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1540158 0.25% 68.62% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 80647 0.01% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 9 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 1 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 41778 0.01% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 105913797 17.48% 86.12% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 84080696 13.88% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 754385019 # Type of FU issued -system.cpu0.iq.rate 0.863017 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 152495846 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.202146 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2511823586 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 823027375 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 736101219 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1128735 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 443604 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 415332 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 906176667 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 704147 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2868207 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 605893488 # Type of FU issued +system.cpu0.iq.rate 0.789932 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 138237024 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.228154 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2093764115 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 672208466 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 588253598 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1116590 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 439713 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 411739 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 743434871 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 695616 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2774549 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 13104832 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 17724 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 157642 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 5794849 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 12838296 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 17783 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 152412 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 5562268 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2875718 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4918474 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2788433 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4754457 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5462709 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 7926079 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1884320 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 766295642 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5251473 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 7932610 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1687524 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 617423509 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 141637487 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 90242008 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 14144816 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 61216 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1749510 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 157642 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2035907 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 3235941 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5271848 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 745963336 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 141529970 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7821454 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 102816112 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 86124751 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13854081 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 62183 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1552208 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 152412 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 1974984 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 3105212 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5080196 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 597824194 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 102668745 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7465093 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 135914 # number of nop insts executed -system.cpu0.iew.exec_refs 228324326 # number of memory reference insts executed -system.cpu0.iew.exec_branches 170531782 # Number of branches executed -system.cpu0.iew.exec_stores 86794356 # Number of stores executed -system.cpu0.iew.exec_rate 0.853383 # Inst execution rate -system.cpu0.iew.wb_sent 737330155 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 736516551 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 351214969 # num instructions producing a value -system.cpu0.iew.wb_consumers 595098705 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.842575 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.590179 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 49835507 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 16326061 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4903366 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 839368834 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.844688 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.533259 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 133193 # number of nop insts executed +system.cpu0.iew.exec_refs 185500111 # number of memory reference insts executed +system.cpu0.iew.exec_branches 112433305 # Number of branches executed +system.cpu0.iew.exec_stores 82831366 # Number of stores executed +system.cpu0.iew.exec_rate 0.779412 # Inst execution rate +system.cpu0.iew.wb_sent 589443856 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 588665337 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 287005457 # num instructions producing a value +system.cpu0.iew.wb_consumers 470602155 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.767471 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.609869 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 48230515 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 16043481 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4724520 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 732949405 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.766879 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.569816 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 512658006 61.08% 61.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 158759517 18.91% 79.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 92536082 11.02% 91.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 27862473 3.32% 94.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 13576189 1.62% 95.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 9358920 1.11% 97.07% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6289735 0.75% 97.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3875341 0.46% 98.28% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 14452571 1.72% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 487135616 66.46% 66.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 127506386 17.40% 83.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 54345658 7.41% 91.27% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 18167389 2.48% 93.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 13030534 1.78% 95.53% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 9013680 1.23% 96.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6080548 0.83% 97.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3647046 0.50% 98.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 14022548 1.91% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 839368834 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 622433451 # Number of instructions committed -system.cpu0.commit.committedOps 709004821 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 732949405 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 479057822 # Number of instructions committed +system.cpu0.commit.committedOps 562083399 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 212979813 # Number of memory references committed -system.cpu0.commit.loads 128532654 # Number of loads committed -system.cpu0.commit.membars 3921678 # Number of memory barriers committed -system.cpu0.commit.branches 164749224 # Number of branches committed -system.cpu0.commit.fp_insts 407380 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 634275437 # Number of committed integer instructions. -system.cpu0.commit.function_calls 14942203 # Number of function calls committed. +system.cpu0.commit.refs 170540284 # Number of memory references committed +system.cpu0.commit.loads 89977801 # Number of loads committed +system.cpu0.commit.membars 3918882 # Number of memory barriers committed +system.cpu0.commit.branches 106864519 # Number of branches committed +system.cpu0.commit.fp_insts 404083 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 515735338 # Number of committed integer instructions. +system.cpu0.commit.function_calls 14196925 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 494636379 69.76% 69.76% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1291078 0.18% 69.95% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 60530 0.01% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 37021 0.01% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.96% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 128532654 18.13% 88.09% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 84447159 11.91% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 390151246 69.41% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1292004 0.23% 69.64% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 63609 0.01% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.65% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 36256 0.01% 69.66% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.66% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.66% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.66% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 89977801 16.01% 85.67% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 80562483 14.33% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 709004821 # Class of committed instruction -system.cpu0.commit.bw_lim_events 14452571 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1579278211 # The number of ROB reads -system.cpu0.rob.rob_writes 1527109253 # The number of ROB writes -system.cpu0.timesIdled 1033857 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 25288893 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 93894577230 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 622433451 # Number of Instructions Simulated -system.cpu0.committedOps 709004821 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.404368 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.404368 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.712064 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.712064 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 848778973 # number of integer regfile reads -system.cpu0.int_regfile_writes 506977822 # number of integer regfile writes -system.cpu0.fp_regfile_reads 685984 # number of floating regfile reads -system.cpu0.fp_regfile_writes 317032 # number of floating regfile writes -system.cpu0.cc_regfile_reads 188384037 # number of cc regfile reads -system.cpu0.cc_regfile_writes 189031095 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1602344785 # number of misc regfile reads -system.cpu0.misc_regfile_writes 16401028 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 6409966 # number of replacements -system.cpu0.dcache.tags.tagsinuse 480.619482 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 199938758 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6410478 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 31.189368 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 562083399 # Class of committed instruction +system.cpu0.commit.bw_lim_events 14022548 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1325013729 # The number of ROB reads +system.cpu0.rob.rob_writes 1229746140 # The number of ROB writes +system.cpu0.timesIdled 998783 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 24914927 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 94000815527 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 479057822 # Number of Instructions Simulated +system.cpu0.committedOps 562083399 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.601101 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.601101 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.624570 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.624570 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 705670279 # number of integer regfile reads +system.cpu0.int_regfile_writes 419695299 # number of integer regfile writes +system.cpu0.fp_regfile_reads 680997 # number of floating regfile reads +system.cpu0.fp_regfile_writes 310212 # number of floating regfile writes +system.cpu0.cc_regfile_reads 130338984 # number of cc regfile reads +system.cpu0.cc_regfile_writes 131056521 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1328403158 # number of misc regfile reads +system.cpu0.misc_regfile_writes 16107336 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 6279329 # number of replacements +system.cpu0.dcache.tags.tagsinuse 481.718631 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 157880144 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6279840 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 25.140791 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1908955000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.619482 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938710 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.938710 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 439216738 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 439216738 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 121629785 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 121629785 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 73254039 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 73254039 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 225954 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 225954 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 195110 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 195110 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1865486 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1865486 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1919454 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1919454 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 195078934 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 195078934 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 195304888 # number of overall hits -system.cpu0.dcache.overall_hits::total 195304888 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 7140435 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7140435 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 8024708 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 8024708 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 776369 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 776369 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 838591 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 838591 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 289464 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 289464 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195968 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 195968 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 16003734 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 16003734 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 16780103 # number of overall misses -system.cpu0.dcache.overall_misses::total 16780103 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 108528058000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 108528058000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 153779451872 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 153779451872 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 31763636892 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 31763636892 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4317295000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4317295000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4927286000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4927286000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3123500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3123500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 294071146764 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 294071146764 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 294071146764 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 294071146764 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 128770220 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 128770220 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81278747 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 81278747 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1002323 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1002323 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1033701 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1033701 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2154950 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2154950 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2115422 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2115422 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 211082668 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 211082668 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 212084991 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 212084991 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.055451 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.055451 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.098731 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.098731 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.774570 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.774570 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.811251 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.811251 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.134325 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.134325 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.092638 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.092638 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.075817 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.075817 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.079120 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.079120 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15199.082129 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15199.082129 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19163.245799 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19163.245799 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 37877.388252 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 37877.388252 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14914.790786 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14914.790786 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25143.319317 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25143.319317 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.718631 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.940857 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.940857 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 218 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 354237308 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 354237308 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 83229187 # 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number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 153279748 # number of overall hits +system.cpu0.dcache.overall_hits::total 153279748 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 7047364 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7047364 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 7798246 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 7798246 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 750513 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 750513 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 796040 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 796040 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 285990 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 285990 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 189707 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 189707 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 15641650 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 15641650 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 16392163 # number of overall misses +system.cpu0.dcache.overall_misses::total 16392163 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 106587069500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 106587069500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 149276619912 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 149276619912 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 30060531759 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 30060531759 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4170219500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 4170219500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4536657500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4536657500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2221500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2221500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 285924221171 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 285924221171 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 285924221171 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 285924221171 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 90276551 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 90276551 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 77499003 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 77499003 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 952272 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 952272 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 944085 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 944085 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2149453 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2149453 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2112219 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2112219 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 168719639 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 168719639 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 169671911 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 169671911 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.078064 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.078064 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.100624 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.100624 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.788129 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788129 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.843187 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.843187 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.133052 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.133052 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.089814 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.089814 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092708 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092708 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096611 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.096611 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15124.388282 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15124.388282 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19142.332765 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 19142.332765 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 37762.589517 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 37762.589517 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14581.696912 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14581.696912 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23914.022677 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23914.022677 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 18375.158370 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 18375.158370 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17524.990566 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17524.990566 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9668545 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 23532840 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 779892 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 794197 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.397287 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 29.630986 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 6410042 # number of writebacks -system.cpu0.dcache.writebacks::total 6410042 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3690786 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3690786 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6446005 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 6446005 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4347 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 4347 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 149571 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 149571 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 10141138 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 10141138 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 10141138 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 10141138 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3449649 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3449649 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1578703 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1578703 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 769355 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 769355 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 834244 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 834244 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 139893 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 139893 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195965 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 195965 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5862596 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5862596 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 6631951 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 6631951 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31285 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31285 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 30958 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 30958 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62243 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62243 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 50416416500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50416416500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 33875543231 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33875543231 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17245260500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17245260500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 30759768392 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 30759768392 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1918237000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1918237000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4731380000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4731380000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3064500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3064500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 115051728123 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 115051728123 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 132296988623 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 132296988623 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6062914000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6062914000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6062914000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6062914000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.026789 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026789 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019423 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019423 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.767572 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.767572 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.807046 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.807046 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064917 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064917 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.092636 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.092636 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027774 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027774 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031270 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031270 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14614.940969 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14614.940969 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21457.831670 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21457.831670 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22415.218592 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22415.218592 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 36871.428973 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36871.428973 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13712.172875 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13712.172875 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24144.005307 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24144.005307 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 18279.671337 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 18279.671337 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17442.739019 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17442.739019 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9136124 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 22955799 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 744485 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 773832 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.271737 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 29.665094 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 6279393 # number of writebacks +system.cpu0.dcache.writebacks::total 6279393 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3627313 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3627313 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6268862 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 6268862 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4039 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 4039 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 145852 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 145852 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 9900214 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 9900214 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 9900214 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 9900214 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3420051 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3420051 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1529384 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1529384 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 743716 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 743716 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 792001 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 792001 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 140138 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 140138 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 189707 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 189707 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5741436 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5741436 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 6485152 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 6485152 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17085 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17085 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18834 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18834 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 35919 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 35919 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 49260241500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 49260241500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 32250000948 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 32250000948 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16897998500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16897998500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 29124405259 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 29124405259 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1866604500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1866604500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4347004500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4347004500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2167500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2167500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 110634647707 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 110634647707 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 127532646207 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 127532646207 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3215151000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3215151000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3215151000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3215151000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037884 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037884 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019734 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019734 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.780991 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.780991 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.838909 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.838909 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065197 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065197 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.089814 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.089814 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.034029 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.034029 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.038222 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.038222 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14403.364599 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14403.364599 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21086.921890 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21086.921890 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22721.036659 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22721.036659 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 36773.192533 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36773.192533 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13319.759808 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13319.759808 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22914.307327 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22914.307327 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19624.706891 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19624.706891 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19948.426733 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19948.426733 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193796.196260 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193796.196260 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97407.162251 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97407.162251 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 6234341 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.962382 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 276007197 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 6234853 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 44.268437 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 12884658000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.962382 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999927 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999927 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19269.508135 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19269.508135 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19665.328771 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19665.328771 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188185.601405 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188185.601405 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89511.150088 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 89511.150088 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 5960489 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.962298 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 213927686 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5961001 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 35.887880 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 13033031000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.962298 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999926 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999926 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 571449747 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 571449747 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 276007197 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 276007197 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 276007197 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 276007197 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 276007197 # number of overall hits -system.cpu0.icache.overall_hits::total 276007197 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6600102 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6600102 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6600102 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6600102 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6600102 # number of overall misses -system.cpu0.icache.overall_misses::total 6600102 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 71550800576 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 71550800576 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 71550800576 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 71550800576 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 71550800576 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 71550800576 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 282607299 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 282607299 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 282607299 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 282607299 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 282607299 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 282607299 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.023354 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.023354 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.023354 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.023354 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.023354 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.023354 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10840.862850 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10840.862850 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10840.862850 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10840.862850 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10840.862850 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10840.862850 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 10420482 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 1138 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 752268 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.852087 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 103.454545 # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 6234341 # number of writebacks -system.cpu0.icache.writebacks::total 6234341 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 364953 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 364953 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 364953 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 364953 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 364953 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 364953 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6235149 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 6235149 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 6235149 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 6235149 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 6235149 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 6235149 # number of overall MSHR misses +system.cpu0.icache.tags.tag_accesses 446443685 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 446443685 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 213927686 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 213927686 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 213927686 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 213927686 # 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number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 68941695345 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 68941695345 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 220241314 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 220241314 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 220241314 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 220241314 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 220241314 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 220241314 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028667 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.028667 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028667 # 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number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5961057 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 5961057 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 5961057 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 5961057 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 5961057 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 5961057 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 64720811973 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 64720811973 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 64720811973 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 64720811973 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 64720811973 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 64720811973 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 62354110053 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 62354110053 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 62354110053 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 62354110053 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 62354110053 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 62354110053 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1885677498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1885677498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1885677498 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 1885677498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.022063 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.022063 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.022063 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.022063 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.022063 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.022063 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10379.994443 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10379.994443 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10379.994443 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10379.994443 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10379.994443 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10379.994443 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027066 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027066 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027066 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.027066 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027066 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.027066 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10460.243888 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10460.243888 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10460.243888 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10460.243888 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10460.243888 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10460.243888 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88558.563753 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88558.563753 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 8818791 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8829534 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 9675 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8592940 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8600926 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 7220 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1134314 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2939155 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16147.226336 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 18219506 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2955258 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.165115 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2212473000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15244.220202 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.043386 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 62.165258 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000002 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 782.797489 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.930433 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003543 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003794 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.047778 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.985548 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1151 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 81 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14871 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 189 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 576 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 372 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 48 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 14 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1385 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6005 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4408 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2945 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.070251 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004944 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.907654 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 433411639 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 433411639 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 616680 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 198735 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 815415 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 4206029 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 4206029 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 8435953 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 8435953 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 888 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 888 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 1016467 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 1016467 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5621992 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 5621992 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3255070 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 3255070 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 189931 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 189931 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 616680 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 198735 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 5621992 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 4271537 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 10708944 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 616680 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 198735 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 5621992 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 4271537 # number of overall hits -system.cpu0.l2cache.overall_hits::total 10708944 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13303 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10046 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 23349 # number of ReadReq misses -system.cpu0.l2cache.WritebackDirty_misses::writebacks 5 # number of WritebackDirty misses -system.cpu0.l2cache.WritebackDirty_misses::total 5 # number of WritebackDirty misses -system.cpu0.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses -system.cpu0.l2cache.WritebackClean_misses::total 1 # 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mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.099943 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.235520 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230754 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36963.079931 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 41668.758717 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38987.144877 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56590.929630 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56590.929630 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20556.048168 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20556.048168 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16627.774157 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16627.774157 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 655374.750000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 655374.750000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 44819.023202 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 44819.023202 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28775.786737 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28775.786737 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31374.295958 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31374.295958 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36606.229223 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36606.229223 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36963.079931 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 41668.758717 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28775.786737 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34126.392569 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32554.736432 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36963.079931 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 41668.758717 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28775.786737 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34126.392569 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56590.929630 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 40136.035953 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.228959 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28922.853015 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 39048.012963 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 32290.152869 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59475.138338 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59475.138338 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18533.216598 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18533.216598 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15397.474383 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15397.474383 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 587500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 587500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45129.381880 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45129.381880 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29103.997241 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29103.997241 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31830.259628 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31830.259628 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36425.359014 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36425.359014 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28922.853015 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 39048.012963 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29103.997241 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34545.803791 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32838.272405 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28922.853015 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 39048.012963 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29103.997241 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34545.803791 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59475.138338 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41184.535280 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185781.620585 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 143370.934611 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180158.267486 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 125175.439054 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 93378.821715 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 90238.424152 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 26220064 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13479100 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2657 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 2182451 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2181920 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 531 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 979416 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 11666319 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 30958 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 30958 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 6060800 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 8438347 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2860883 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1184490 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 488552 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348527 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 533031 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 69 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 124 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1347603 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1325056 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6235149 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5307790 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 891051 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 832317 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18746760 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20650560 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 436622 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1328978 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 41162920 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 798358288 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 780155262 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1670248 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5039864 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1585223662 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 7567060 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 126041936 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 21529267 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.118569 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.323357 # Request fanout histogram +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 85692.920182 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 83968.101098 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 25397703 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13066663 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1795 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 671473 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 671468 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 963728 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 11315166 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 18834 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 18834 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5872564 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 8129050 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1348327 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1122615 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 22 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 466810 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 338240 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 510310 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1307620 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1285212 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5961057 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5219350 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 843100 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 790085 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 17925156 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20147173 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 419117 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1337980 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 39829426 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 763317520 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 765224037 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1592032 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5061960 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1535195549 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 5838031 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 119621704 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 19351504 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.054273 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.226556 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 18977100 88.15% 88.15% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2551636 11.85% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 531 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 18301249 94.57% 94.57% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 1050250 5.43% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 5 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 21529267 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 26091722433 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 19351504 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 25250991712 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 187623310 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 173970437 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 9380939070 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 8969219750 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 9216328089 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 9025116687 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 228203766 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 220608496 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 699632706 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 706093257 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 194671556 # Number of BP lookups -system.cpu1.branchPred.condPredicted 153305610 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6254288 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 157865267 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 88709282 # Number of BTB hits +system.cpu1.branchPred.lookups 128968222 # Number of BP lookups +system.cpu1.branchPred.condPredicted 85282466 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6518355 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 89675287 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 55364340 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 56.193033 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 16475486 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 172497 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 3896881 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 2381021 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1515860 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 389837 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 61.738682 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17439644 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 182879 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 4134289 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2557852 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1576437 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 401535 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1724,93 +1712,96 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 533309 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 533309 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10503 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 81680 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 248509 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 284800 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2470.932233 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 13518.648671 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-32767 279405 98.11% 98.11% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-65535 3083 1.08% 99.19% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-98303 908 0.32% 99.51% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::98304-131071 713 0.25% 99.76% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-163839 284 0.10% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::163840-196607 163 0.06% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-229375 124 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::229376-262143 32 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-294911 13 0.00% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::294912-327679 40 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-360447 32 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 531460 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 531460 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10155 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 82594 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 244261 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 287199 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2189.199823 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 12408.912934 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-32767 282304 98.30% 98.30% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-65535 2996 1.04% 99.34% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-98303 743 0.26% 99.60% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::98304-131071 602 0.21% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-163839 197 0.07% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::163840-196607 152 0.05% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-229375 103 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::229376-262143 33 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-294911 16 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::294912-327679 35 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-360447 11 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::425984-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 284800 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 268382 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 19517.668845 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 17136.373439 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 13227.910444 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 250971 93.51% 93.51% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 15361 5.72% 99.24% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 757 0.28% 99.52% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 835 0.31% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 87 0.03% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 116 0.04% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 116 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 51 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 29 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 31 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 7 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 15 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 287199 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 267684 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 20635.114538 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 18133.747768 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 11911.787641 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 239914 89.63% 89.63% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 26330 9.84% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 756 0.28% 99.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 476 0.18% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 73 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 24 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 55 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 22 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 9 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 8 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 3 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 5 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 268382 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 466126532996 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.617043 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.546089 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 464998520496 99.76% 99.76% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 569195000 0.12% 99.88% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 249472000 0.05% 99.93% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 122508000 0.03% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 91886000 0.02% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 55274500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 15901500 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 23390500 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 385000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 466126532996 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 81681 88.61% 88.61% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 10503 11.39% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 92184 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 533309 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 267684 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 465694213496 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.593113 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.550788 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 464589649996 99.76% 99.76% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 559093500 0.12% 99.88% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 239052500 0.05% 99.93% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 120378000 0.03% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 87009500 0.02% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 57335500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 14978500 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 26310000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 396500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 9500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 465694213496 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 82595 89.05% 89.05% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 10155 10.95% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 92750 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 531460 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 533309 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 92184 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 531460 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 92750 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 92184 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 625493 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 92750 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 624210 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 161844710 # DTB read hits -system.cpu1.dtb.read_misses 366883 # DTB read misses -system.cpu1.dtb.write_hits 74184112 # DTB write hits -system.cpu1.dtb.write_misses 166426 # DTB write misses +system.cpu1.dtb.read_hits 93944307 # DTB read hits +system.cpu1.dtb.read_misses 364370 # DTB read misses +system.cpu1.dtb.write_hits 78170381 # DTB write hits +system.cpu1.dtb.write_misses 167090 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 44490 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 34599 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 386 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 6272 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 44145 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 34720 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 381 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 5735 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 37354 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 162211593 # DTB read accesses -system.cpu1.dtb.write_accesses 74350538 # DTB write accesses +system.cpu1.dtb.perms_faults 39000 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 94308677 # DTB read accesses +system.cpu1.dtb.write_accesses 78337471 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 236028822 # DTB hits -system.cpu1.dtb.misses 533309 # DTB misses -system.cpu1.dtb.accesses 236562131 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 172114688 # DTB hits +system.cpu1.dtb.misses 531460 # DTB misses +system.cpu1.dtb.accesses 172646148 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1840,1178 +1831,1180 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 80718 # Table walker walks requested -system.cpu1.itb.walker.walksLong 80718 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 768 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57037 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 10137 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 70581 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 996.309205 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 6981.449622 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 70036 99.23% 99.23% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 380 0.54% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 60 0.09% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 83 0.12% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 82381 # Table walker walks requested +system.cpu1.itb.walker.walksLong 82381 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1018 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 59631 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 9853 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 72528 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 882.590172 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 6870.472006 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 72114 99.43% 99.43% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 279 0.38% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 39 0.05% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 75 0.10% 99.97% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::131072-163839 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 70581 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 67942 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 24162.219246 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 22142.693859 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 15015.121608 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 66991 98.60% 98.60% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 778 1.15% 99.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 100 0.15% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 45 0.07% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 20 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 67942 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 397380257260 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.877039 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.328570 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 48883602860 12.30% 12.30% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 348476867900 87.69% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 18158500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 1572000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 56000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 397380257260 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 57037 98.67% 98.67% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 768 1.33% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 57805 # Table walker page sizes translated +system.cpu1.itb.walker.walkWaitTime::163840-196607 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 72528 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 70502 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 24022.878784 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 22243.496704 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 12757.621468 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 63844 90.56% 90.56% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 6070 8.61% 99.17% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 93 0.13% 99.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 382 0.54% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 44 0.06% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 19 0.03% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 18 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 8 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 70502 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 379792000076 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.874646 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.331269 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 47625596788 12.54% 12.54% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 332150851288 87.46% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 14331500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 990000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 230500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 379792000076 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 59631 98.32% 98.32% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 1018 1.68% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 60649 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 80718 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 80718 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 82381 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 82381 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 57805 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 57805 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 138523 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 264777096 # ITB inst hits -system.cpu1.itb.inst_misses 80718 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 60649 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 60649 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 143030 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 201934152 # ITB inst hits +system.cpu1.itb.inst_misses 82381 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 44490 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 24684 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 44145 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 24569 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 195163 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 202631 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 264857814 # ITB inst accesses -system.cpu1.itb.hits 264777096 # DTB hits -system.cpu1.itb.misses 80718 # DTB misses -system.cpu1.itb.accesses 264857814 # DTB accesses -system.cpu1.numPwrStateTransitions 9670 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 4835 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 9724953244.725336 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 147881742434.863098 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3183 65.83% 65.83% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1626 33.63% 99.46% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.04% 99.50% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 5 0.10% 99.61% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 2 0.04% 99.65% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.67% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.69% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.02% 99.71% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 14 0.29% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 7390881470984 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 4835 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 364202361753 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 47020148938247 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 728406370 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 202016533 # ITB inst accesses +system.cpu1.itb.hits 201934152 # DTB hits +system.cpu1.itb.misses 82381 # DTB misses +system.cpu1.itb.accesses 202016533 # DTB accesses +system.cpu1.numPwrStateTransitions 26784 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 13392 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 3512583180.059961 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 88770415671.353104 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3351 25.02% 25.02% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 10014 74.78% 99.80% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.82% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 4 0.03% 99.85% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::3.5e+11-4e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 7430623145540 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 13392 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 343403762637 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 47040513947363 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 686817572 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 83192103 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 724269312 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 194671556 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 107565789 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 610871186 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13439122 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1719504 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 273339 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 5608482 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 704978 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 774415 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 264561727 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1602178 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 26700 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 709863568 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.153991 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.257090 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 87491536 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 569150585 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 128968222 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 75361836 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 564504137 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 14030828 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1743458 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 273069 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 5670150 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 713565 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 783781 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 201710843 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1678338 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 26867 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 668195110 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.000138 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.225435 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 331851103 46.75% 46.75% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 119648081 16.86% 63.60% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 75565351 10.65% 74.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 182799033 25.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 348421230 52.14% 52.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 124504424 18.63% 70.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 42025261 6.29% 77.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 153244195 22.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 709863568 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.267257 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.994320 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 98062054 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 297890044 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 275618841 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 33512378 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 4780251 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 17247911 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1977266 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 743961992 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 21656856 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 4780251 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 130238128 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 40363481 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 204147620 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 276602035 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 53732053 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 728176206 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 5626727 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 9082967 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 240191 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 268836 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 22296515 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 11543 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 630286495 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 1024905330 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 827525539 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 801877 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 577128327 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 53158158 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 14384532 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 12638476 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 67737488 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 162372694 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 77181222 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 8520193 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 7294637 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 707349171 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 14663402 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 711466322 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2509310 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 50084332 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 32217686 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 252969 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 709863568 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.002258 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.141899 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 668195110 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.187777 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.828678 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 102161242 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 311763510 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 215198558 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 34078749 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 4993051 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 18208977 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 2060516 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 590405276 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 22672761 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 4993051 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 135354794 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 41008219 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 216515907 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 215714387 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 54608752 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 573925738 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5865325 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 9111156 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 235226 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 246551 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 22706071 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 10845 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 544713354 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 881414288 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 677140554 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 799785 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 489645115 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 55068233 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 14685141 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 12835902 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 68922736 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 94552173 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 81340147 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8760661 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7542596 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 552653279 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 14818656 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 556478216 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2578197 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 52065959 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 33349277 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 259122 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 668195110 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.832808 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.070079 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 346424684 48.80% 48.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 123916139 17.46% 66.26% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 138092978 19.45% 85.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 94358537 13.29% 99.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7067534 1.00% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 3696 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 364178661 54.50% 54.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 127786531 19.12% 73.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 107346035 16.07% 89.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 61539810 9.21% 98.90% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7340180 1.10% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 3893 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 709863568 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 668195110 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 53419887 27.72% 27.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 53191 0.03% 27.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 19037 0.01% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 15 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.76% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 103986379 53.96% 81.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 35231745 18.28% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 55774345 44.07% 44.07% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 53478 0.04% 44.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 18362 0.01% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 15 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 33579431 26.53% 70.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 37124892 29.34% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 25 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 469996066 66.06% 66.06% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1210560 0.17% 66.23% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 70927 0.01% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.24% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 81598 0.01% 66.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.25% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 164776620 23.16% 89.41% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 75330478 10.59% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 35 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 378772554 68.07% 68.07% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1203453 0.22% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 69506 0.01% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 82169 0.01% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 96967073 17.43% 85.73% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 79383378 14.27% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 711466322 # Type of FU issued -system.cpu1.iq.rate 0.976744 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 192710254 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.270863 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 2326678945 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 771690256 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 695698465 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1336829 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 536159 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 497637 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 903350253 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 826298 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2394067 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 556478216 # Type of FU issued +system.cpu1.iq.rate 0.810227 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 126550523 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.227413 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1908944024 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 619142753 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 540109020 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1336236 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 533681 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 496559 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 682200972 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 827732 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2535076 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 11654320 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 15948 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 130447 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5130974 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 12050927 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 15964 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 139670 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5367770 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2399995 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 3738162 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2479862 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 3811174 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 4780251 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 5901245 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 1355404 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 722138785 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 4993051 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 6066595 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1484920 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 567600146 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 162372694 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 77181222 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 12419825 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 58724 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1239916 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 130447 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1767111 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2862185 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4629296 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 704121990 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 161840669 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6820718 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 94552173 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 81340147 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12593166 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 61012 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1366008 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 139670 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1864288 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2962654 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4826942 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 548760252 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 93936954 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 7198002 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 126212 # number of nop insts executed -system.cpu1.iew.exec_refs 236024480 # number of memory reference insts executed -system.cpu1.iew.exec_branches 169760384 # Number of branches executed -system.cpu1.iew.exec_stores 74183811 # Number of stores executed -system.cpu1.iew.exec_rate 0.966661 # Inst execution rate -system.cpu1.iew.wb_sent 696881354 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 696196102 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 357262878 # num instructions producing a value -system.cpu1.iew.wb_consumers 517340824 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.955780 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.690575 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 43732145 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 14410433 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4314978 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 701540457 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.957790 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.589997 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 128211 # number of nop insts executed +system.cpu1.iew.exec_refs 172107181 # number of memory reference insts executed +system.cpu1.iew.exec_branches 103045741 # Number of branches executed +system.cpu1.iew.exec_stores 78170227 # Number of stores executed +system.cpu1.iew.exec_rate 0.798990 # Inst execution rate +system.cpu1.iew.wb_sent 541337937 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 540605579 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 260784878 # num instructions producing a value +system.cpu1.iew.wb_consumers 427489689 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.787117 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.610038 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 45375845 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 14559534 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4495992 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 659550921 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.781450 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.574730 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 413092247 58.88% 58.88% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 113176092 16.13% 75.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 83530992 11.91% 86.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 51841229 7.39% 94.31% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 11508500 1.64% 95.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 7726725 1.10% 97.05% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5343630 0.76% 97.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3131269 0.45% 98.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 12189773 1.74% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 433210493 65.68% 65.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 117319741 17.79% 83.47% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 50366969 7.64% 91.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 16989740 2.58% 93.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 12025543 1.82% 95.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 8091474 1.23% 96.73% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5593324 0.85% 97.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3365512 0.51% 98.09% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 12588125 1.91% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 701540457 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 597176554 # Number of instructions committed -system.cpu1.commit.committedOps 671928235 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 659550921 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 437257329 # Number of instructions committed +system.cpu1.commit.committedOps 515405969 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 222768619 # Number of memory references committed -system.cpu1.commit.loads 150718371 # Number of loads committed -system.cpu1.commit.membars 39196572 # Number of memory barriers committed -system.cpu1.commit.branches 164739467 # Number of branches committed -system.cpu1.commit.fp_insts 488627 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 631392614 # Number of committed integer instructions. -system.cpu1.commit.function_calls 12167965 # Number of function calls committed. +system.cpu1.commit.refs 158473622 # Number of memory references committed +system.cpu1.commit.loads 82501245 # Number of loads committed +system.cpu1.commit.membars 3568741 # Number of memory barriers committed +system.cpu1.commit.branches 97797753 # Number of branches committed +system.cpu1.commit.fp_insts 487077 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 473223690 # Number of committed integer instructions. +system.cpu1.commit.function_calls 12865392 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 448043617 66.68% 66.68% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 985154 0.15% 66.83% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 56630 0.01% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 66.84% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 74173 0.01% 66.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 66.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.85% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.85% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 150718371 22.43% 89.28% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 72050248 10.72% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 355828768 69.04% 69.04% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 973462 0.19% 69.23% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 55201 0.01% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.24% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 74874 0.01% 69.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.25% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.25% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 82501245 16.01% 85.26% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 75972377 14.74% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 671928235 # Class of committed instruction -system.cpu1.commit.bw_lim_events 12189773 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1401264531 # The number of ROB reads -system.cpu1.rob.rob_writes 1439606443 # The number of ROB writes -system.cpu1.timesIdled 902579 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 18542802 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 94040296263 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 597176554 # Number of Instructions Simulated -system.cpu1.committedOps 671928235 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.219750 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.219750 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.819840 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.819840 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 799341399 # number of integer regfile reads -system.cpu1.int_regfile_writes 475575163 # number of integer regfile writes -system.cpu1.fp_regfile_reads 787030 # number of floating regfile reads -system.cpu1.fp_regfile_writes 454812 # number of floating regfile writes -system.cpu1.cc_regfile_reads 112918659 # number of cc regfile reads -system.cpu1.cc_regfile_writes 113685571 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1436513215 # number of misc regfile reads -system.cpu1.misc_regfile_writes 14489141 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 5047432 # number of replacements -system.cpu1.dcache.tags.tagsinuse 457.905792 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 212666270 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5047943 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 42.129293 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8477400492000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.905792 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.894347 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.894347 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 457080025 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 457080025 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 145190780 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 145190780 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 62993534 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 62993534 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 167629 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 167629 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 116242 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 116242 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1721505 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1721505 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1728884 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1728884 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 208300556 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 208300556 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 208468185 # number of overall hits -system.cpu1.dcache.overall_hits::total 208468185 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 5993321 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 5993321 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 6604202 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 6604202 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 607895 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 607895 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 421696 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 421696 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 237246 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 237246 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 187668 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 187668 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 13019219 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 13019219 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 13627114 # number of overall misses -system.cpu1.dcache.overall_misses::total 13627114 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 89379669000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 89379669000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 119695443135 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 119695443135 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10488678921 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 10488678921 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3322992000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 3322992000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4669078500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4669078500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3521000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3521000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 219563791056 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 219563791056 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 219563791056 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 219563791056 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 151184101 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 151184101 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 69597736 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 69597736 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 775524 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 775524 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 537938 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 537938 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1958751 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1958751 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1916552 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1916552 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 221319775 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 221319775 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 222095299 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 222095299 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039643 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.039643 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.094891 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.094891 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.783851 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.783851 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.783912 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.783912 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.121121 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.121121 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097920 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097920 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.058825 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.058825 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.061357 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.061357 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14913.212391 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14913.212391 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18124.134170 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18124.134170 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24872.607094 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24872.607094 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14006.524873 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14006.524873 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24879.460004 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24879.460004 # average StoreCondReq miss latency +system.cpu1.commit.op_class_0::total 515405969 # Class of committed instruction +system.cpu1.commit.bw_lim_events 12588125 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1203797977 # The number of ROB reads +system.cpu1.rob.rob_writes 1130170940 # The number of ROB writes +system.cpu1.timesIdled 922689 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 18622462 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 94081017888 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 437257329 # Number of Instructions Simulated +system.cpu1.committedOps 515405969 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.570740 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.570740 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.636643 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.636643 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 647634757 # number of integer regfile reads +system.cpu1.int_regfile_writes 384292228 # number of integer regfile writes +system.cpu1.fp_regfile_reads 785728 # number of floating regfile reads +system.cpu1.fp_regfile_writes 454696 # number of floating regfile writes +system.cpu1.cc_regfile_reads 117471222 # number of cc regfile reads +system.cpu1.cc_regfile_writes 118161265 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1199366647 # number of misc regfile reads +system.cpu1.misc_regfile_writes 14671382 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 5153619 # number of replacements +system.cpu1.dcache.tags.tagsinuse 456.044406 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 148207895 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5154131 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 28.755166 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8517415326000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 456.044406 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890712 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.890712 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 328622817 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 328622817 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 76967758 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 76967758 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 66682281 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 66682281 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 189501 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 189501 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 166829 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 166829 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1726427 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1726427 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1743769 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1743769 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 143816868 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 143816868 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 144006369 # number of overall hits +system.cpu1.dcache.overall_hits::total 144006369 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 5978399 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 5978399 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 6727643 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 6727643 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 625948 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 625948 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 458256 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 458256 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 242959 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 242959 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 183921 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 183921 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 13164298 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 13164298 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 13790246 # number of overall misses +system.cpu1.dcache.overall_misses::total 13790246 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 87383841500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 87383841500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 119886339095 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 119886339095 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11324190656 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 11324190656 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3328957500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 3328957500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4379371000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4379371000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2907500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2907500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 218594371251 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 218594371251 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 218594371251 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 218594371251 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 82946157 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 82946157 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 73409924 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 73409924 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 815449 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 815449 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 625085 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 625085 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1969386 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1969386 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1927690 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1927690 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 156981166 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 156981166 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 157796615 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 157796615 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.072076 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.072076 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.091645 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.091645 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.767611 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.767611 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.733110 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.733110 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.123368 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.123368 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095410 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095410 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.083859 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.083859 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.087393 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.087393 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14616.595764 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14616.595764 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17819.961478 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17819.961478 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24711.494571 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24711.494571 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13701.725394 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13701.725394 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23811.152614 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23811.152614 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16864.590038 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16864.590038 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16112.273740 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16112.273740 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 2706631 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 18960106 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 351175 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 660083 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.707357 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 28.723821 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 5047462 # number of writebacks -system.cpu1.dcache.writebacks::total 5047462 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3052290 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3052290 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5325465 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 5325465 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3276 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 3276 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 122610 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 122610 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 8381031 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 8381031 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 8381031 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 8381031 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2941031 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2941031 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1278737 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1278737 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 607807 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 607807 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 418420 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 418420 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 114636 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 114636 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 187667 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 187667 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4638188 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4638188 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5245995 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5245995 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7218 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7218 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7480 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7480 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14698 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14698 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39704145500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39704145500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24666220214 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24666220214 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14600377000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14600377000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9957787421 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9957787421 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1521960000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1521960000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4481476500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4481476500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3456000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3456000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 74328153135 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 74328153135 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 88928530135 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 88928530135 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 880126000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 880126000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 880126000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 880126000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.019453 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.019453 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018373 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018373 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.783737 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.783737 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.777822 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.777822 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058525 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058525 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097919 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097919 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.020957 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.020957 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.023620 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.023620 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13500.077184 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13500.077184 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19289.517871 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19289.517871 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24021.403176 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24021.403176 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23798.545531 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23798.545531 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13276.457657 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13276.457657 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23879.938934 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23879.938934 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16605.091381 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16605.091381 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15851.375766 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15851.375766 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 2917967 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 18895353 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 374678 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 668758 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.787933 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 28.254395 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 5153631 # number of writebacks +system.cpu1.dcache.writebacks::total 5153631 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3023211 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3023211 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5427179 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 5427179 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3743 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 3743 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 127495 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 127495 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 8454133 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 8454133 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 8454133 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 8454133 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2955188 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2955188 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1300464 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1300464 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 625861 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 625861 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 454513 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 454513 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 115464 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 115464 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 183920 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 183920 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4710165 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4710165 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5336026 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5336026 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 21232 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 21232 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 19410 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 19410 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 40642 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 40642 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40128990000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40128990000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24368462066 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24368462066 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13718666000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13718666000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10741056156 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10741056156 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1514532000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1514532000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4195522000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4195522000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2836500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2836500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 75238508222 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 75238508222 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 88957174222 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 88957174222 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3718611500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3718611500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3718611500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3718611500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035628 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035628 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017715 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017715 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.767505 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.767505 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.727122 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.727122 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058629 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058629 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095410 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095410 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030005 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030005 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033816 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033816 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13579.166537 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13579.166537 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18738.282694 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18738.282694 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21919.669064 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21919.669064 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23632.010869 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23632.010869 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13116.919559 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13116.919559 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22811.668117 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22811.668117 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16025.256659 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16025.256659 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16951.699370 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16951.699370 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 121934.885010 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 121934.885010 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 59880.664036 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 59880.664036 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 5706197 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.707809 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 258521982 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5706709 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 45.301413 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8517122288000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.707809 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979898 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.979898 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15973.645981 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15973.645981 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16671.053369 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16671.053369 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175141.837792 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 175141.837792 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91496.764431 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91496.764431 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 6014648 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.532915 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 195349774 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 6015160 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 32.476239 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8517720712000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.532915 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979556 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.979556 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 307 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 341 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 534817167 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 534817167 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 258521982 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 258521982 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 258521982 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 258521982 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 258521982 # number of overall hits -system.cpu1.icache.overall_hits::total 258521982 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 6033199 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 6033199 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 6033199 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 6033199 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 6033199 # number of overall misses -system.cpu1.icache.overall_misses::total 6033199 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 64071626251 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 64071626251 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 64071626251 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 64071626251 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 64071626251 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 64071626251 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 264555181 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 264555181 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 264555181 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 264555181 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 264555181 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 264555181 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022805 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.022805 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022805 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.022805 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022805 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.022805 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10619.843014 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10619.843014 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10619.843014 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10619.843014 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10619.843014 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10619.843014 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 9429094 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 244 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 708482 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 409423979 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 409423979 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 195349774 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 195349774 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 195349774 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 195349774 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 195349774 # number of overall hits +system.cpu1.icache.overall_hits::total 195349774 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 6354622 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 6354622 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 6354622 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 6354622 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 6354622 # number of overall misses +system.cpu1.icache.overall_misses::total 6354622 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 66668444908 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 66668444908 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 66668444908 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 66668444908 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 66668444908 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 66668444908 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 201704396 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 201704396 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 201704396 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 201704396 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 201704396 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 201704396 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.031505 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.031505 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.031505 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.031505 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.031505 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.031505 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10491.331335 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10491.331335 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10491.331335 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10491.331335 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10491.331335 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10491.331335 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 9555681 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 472 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 727552 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.308869 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 61 # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 5706197 # number of writebacks -system.cpu1.icache.writebacks::total 5706197 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 326394 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 326394 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 326394 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 326394 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 326394 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 326394 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5706805 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5706805 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5706805 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5706805 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5706805 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5706805 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable -system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable -system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses -system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 58058775330 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 58058775330 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 58058775330 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 58058775330 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 58058775330 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 58058775330 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6679498 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6679498 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6679498 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 6679498 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021571 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.021571 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021571 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.021571 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021571 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.021571 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10173.604202 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10173.604202 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10173.604202 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10173.604202 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10173.604202 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10173.604202 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 99694 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 99694 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 99694 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 99694 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6901811 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6907587 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 5314 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.134018 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 118 # average number of cycles each access was blocked +system.cpu1.icache.writebacks::writebacks 6014648 # number of writebacks +system.cpu1.icache.writebacks::total 6014648 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 339435 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 339435 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 339435 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 339435 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 339435 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 339435 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 6015187 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 6015187 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 6015187 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 6015187 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 6015187 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 6015187 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 68 # number of ReadReq MSHR uncacheable +system.cpu1.icache.ReadReq_mshr_uncacheable::total 68 # number of ReadReq MSHR uncacheable +system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 68 # number of overall MSHR uncacheable misses +system.cpu1.icache.overall_mshr_uncacheable_misses::total 68 # number of overall MSHR uncacheable misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 60428904539 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 60428904539 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 60428904539 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 60428904539 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 60428904539 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 60428904539 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6183499 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6183499 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6183499 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 6183499 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.029822 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.029822 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.029822 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.029822 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.029822 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.029822 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10046.055848 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10046.055848 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10046.055848 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10046.055848 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10046.055848 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10046.055848 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90933.808824 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90933.808824 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90933.808824 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90933.808824 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6826847 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 6833838 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 6347 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 821749 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 2026075 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13356.542127 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 16274118 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2041771 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 7.970589 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9992426830500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12440.422172 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 43.172118 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 33.879322 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 0.000015 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 839.068499 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.759303 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002635 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.002068 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.000000 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.051213 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.815219 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1386 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 96 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14214 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 75 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 230 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 627 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 454 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 79 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 797 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4633 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4798 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3775 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.084595 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005859 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.867554 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 369100514 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 369100514 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 546957 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 179929 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 726886 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 3170558 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 3170558 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 7581614 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 7581614 # number of WritebackClean hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 544 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 544 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 2 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 815108 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 815108 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5173102 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 5173102 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2742764 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 2742764 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 184198 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 184198 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 546957 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 179929 # 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mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.236871 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.216738 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31072.697285 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30150.086720 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30698.366424 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44779.098624 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44779.098624 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21123.913810 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21123.913810 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16366.066612 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16366.066612 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 247208.166667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 247208.166667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33772.345856 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33772.345856 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28015.333267 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28015.333267 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28790.171126 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28790.171126 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26887.644192 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26887.644192 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31072.697285 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30150.086720 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28015.333267 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29817.820889 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29263.608095 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31072.697285 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30150.086720 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28015.333267 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29817.820889 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44779.098624 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33864.848983 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92179.104478 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 113906.275977 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 113706.451613 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92179.104478 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 55937.916723 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 56102.370471 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 22350657 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11505244 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1543 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 1883368 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1883027 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 341 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 842183 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10302833 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 7480 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 7480 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4215889 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 7583095 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2514473 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 909607 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 430035 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 341692 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 476439 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 71 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 124 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1090279 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1068076 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5706805 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4656106 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 474602 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 416607 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17119850 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16343111 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 395526 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1186164 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 35044651 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 730427376 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 631688689 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1504072 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4470264 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1368090401 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 6163170 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 73999248 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 18018661 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.123449 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.329009 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.206422 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24239.749338 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 26356.473345 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24907.731273 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 47104.456602 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 47104.456602 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18790.618769 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18790.618769 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15296.842015 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15296.842015 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 574874.750000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 574874.750000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33451.032223 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33451.032223 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28270.219367 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28270.219367 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28485.685373 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28485.685373 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26859.329809 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26859.329809 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24239.749338 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 26356.473345 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28270.219367 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29527.346947 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29059.233508 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24239.749338 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 26356.473345 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28270.219367 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29527.346947 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 47104.456602 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34310.488986 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83426.470588 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 167132.912585 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166865.680751 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83426.470588 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87312.779883 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87306.288381 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 23161545 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11911126 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1586 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 559932 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 559928 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 4 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 858463 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10650090 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 19410 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 19410 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4372034 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 7887876 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 1202832 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 877539 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 29 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 412195 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 333118 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 458356 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1116808 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1095312 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 6015187 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4685876 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 509592 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 452179 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18045125 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16655613 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 406321 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1179507 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 36286566 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 769908416 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 641765745 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1546392 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4442928 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1417663481 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4824103 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 76247568 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 17122714 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.052642 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.223318 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 15794619 87.66% 87.66% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2223701 12.34% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 341 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 16221347 94.74% 94.74% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 901363 5.26% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 4 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 18018661 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 22188055468 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 17122714 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 23027796506 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 182014003 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 160947650 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8566090793 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 9028759604 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7517136176 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7641863842 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 207825380 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 213393747 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 628033176 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 624968323 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40328 # Transaction distribution -system.iobus.trans_dist::ReadResp 40328 # Transaction distribution -system.iobus.trans_dist::WriteReq 136631 # Transaction distribution -system.iobus.trans_dist::WriteResp 136631 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47646 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40315 # Transaction distribution +system.iobus.trans_dist::ReadResp 40315 # Transaction distribution +system.iobus.trans_dist::WriteReq 136630 # Transaction distribution +system.iobus.trans_dist::WriteResp 136630 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47698 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -3022,15 +3015,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122580 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231258 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231230 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231230 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353918 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47666 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353890 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47718 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -3041,19 +3034,19 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155687 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339048 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7339048 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155710 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338936 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338936 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496821 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36938002 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496732 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36996503 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 332000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 325000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -3061,85 +3054,85 @@ system.iobus.reqLayer4.occupancy 10500 # La system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 13500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 24205503 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 24232502 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36443500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36410001 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569408550 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 568919799 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92680000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92681000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147954000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147926000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115626 # number of replacements -system.iocache.tags.tagsinuse 11.305309 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115610 # number of replacements +system.iocache.tags.tagsinuse 11.211324 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115642 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115626 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9115830406000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.413187 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.892123 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463324 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.243258 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706582 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9155814843000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.413268 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.798056 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463329 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.237379 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.700708 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1041018 # Number of tag accesses -system.iocache.tags.data_accesses 1041018 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1040892 # Number of tag accesses +system.iocache.tags.data_accesses 1040892 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8901 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8938 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8887 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8924 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115629 # number of demand (read+write) misses -system.iocache.demand_misses::total 115669 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115615 # number of demand (read+write) misses +system.iocache.demand_misses::total 115655 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115629 # number of overall misses -system.iocache.overall_misses::total 115669 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5198500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1667264523 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1672463023 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115615 # number of overall misses +system.iocache.overall_misses::total 115655 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5200000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1677259553 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1682459553 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12925157527 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12925157527 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5567500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14592422050 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14597989550 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5567500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14592422050 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14597989550 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12947566246 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12947566246 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5569000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14624825799 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14630394799 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5569000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14624825799 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14630394799 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8901 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8938 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8887 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8924 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115629 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115669 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115615 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115655 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115629 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115669 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115615 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115655 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -3153,53 +3146,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140500 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 187312.046175 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 187118.261692 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140540.540541 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 188731.805221 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 188531.998319 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121103.717178 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 121103.717178 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139187.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 126200.365393 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126204.856530 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139187.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 126200.365393 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126204.856530 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33241 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121313.678191 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 121313.678191 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139225 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 126495.920071 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126500.322502 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139225 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 126495.920071 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126500.322502 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 33395 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3524 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3494 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.432747 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.557813 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106695 # number of writebacks -system.iocache.writebacks::total 106695 # number of writebacks +system.iocache.writebacks::writebacks 106693 # number of writebacks +system.iocache.writebacks::total 106693 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8901 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8938 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8887 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8924 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115629 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115669 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115615 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115655 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115629 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115669 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1222214523 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1225563023 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115615 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115655 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3350000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1232909553 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1236259553 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7580015931 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7580015931 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3567500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 8802230454 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8805797954 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3567500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 8802230454 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8805797954 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7602399187 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7602399187 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3569000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8835308740 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8838877740 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3569000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8835308740 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8838877740 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -3213,664 +3206,665 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90500 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137312.046175 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 137118.261692 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90540.540541 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138731.805221 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 138531.998319 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71021.811811 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71021.811811 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89187.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 76124.765016 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76129.282297 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89187.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 76124.765016 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76129.282297 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1557710 # number of replacements -system.l2c.tags.tagsinuse 63573.891854 # Cycle average of tags in use -system.l2c.tags.total_refs 6243665 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1617388 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.860338 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 3022937500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 21119.731437 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 317.083055 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 501.157048 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4189.705266 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 12756.928607 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 18825.078792 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 29.382680 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 33.853586 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2676.679680 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1884.367858 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1239.923843 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.322262 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.004838 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.007647 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.063930 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.194655 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.287248 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000448 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000517 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.040843 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.028753 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.018920 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.970061 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 11464 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 277 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 47937 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 1377 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 337 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9749 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 272 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 349 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3074 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5518 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 38948 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.174927 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.004227 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.731461 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 79574133 # Number of tag accesses -system.l2c.tags.data_accesses 79574133 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2888931 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2888931 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 180891 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 129539 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 310430 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 43976 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 36797 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 80773 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 55787 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 50048 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 105835 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6797 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4576 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 551177 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 671308 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 325157 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6401 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4256 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 484948 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 535287 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 285618 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2875525 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 132882 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 123273 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 256155 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6797 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4576 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 551177 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 727095 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 325157 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6401 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4256 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 484948 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 585335 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 285618 # number of demand (read+write) hits -system.l2c.demand_hits::total 2981360 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6797 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4576 # number of overall hits -system.l2c.overall_hits::cpu0.inst 551177 # number of overall hits -system.l2c.overall_hits::cpu0.data 727095 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 325157 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6401 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4256 # number of overall hits -system.l2c.overall_hits::cpu1.inst 484948 # number of overall hits -system.l2c.overall_hits::cpu1.data 585335 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 285618 # number of overall hits -system.l2c.overall_hits::total 2981360 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 62870 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 65353 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 128223 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 13472 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 11956 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 25428 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 91907 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 48160 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140067 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3207 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3170 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 61507 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 173115 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 339604 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1937 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1306 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 48662 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 111561 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 193805 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 937874 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 497642 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 96113 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 593755 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 3207 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 3170 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 61507 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 265022 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 339604 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1937 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1306 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 48662 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 159721 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 193805 # number of demand (read+write) misses -system.l2c.demand_misses::total 1077941 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 3207 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 3170 # number of overall misses -system.l2c.overall_misses::cpu0.inst 61507 # number of overall misses -system.l2c.overall_misses::cpu0.data 265022 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 339604 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1937 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1306 # number of overall misses -system.l2c.overall_misses::cpu1.inst 48662 # number of overall misses -system.l2c.overall_misses::cpu1.data 159721 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 193805 # number of overall misses -system.l2c.overall_misses::total 1077941 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 420802000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 429972500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 850774500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 88078000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 80352500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 168430500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 8572942990 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4240159498 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 12813102488 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 292674000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 283861500 # 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number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 612684 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 992117 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 664761 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 8338 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 5562 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 533610 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 745056 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 479423 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 4059301 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.257917 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.335329 # 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average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6537.856295 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6720.684175 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 6623.820198 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 93278.455286 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 88043.178945 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 91478.381689 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 91260.991581 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 89546.214511 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 88518.965305 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 95859.103735 # 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average overall miss latency -system.l2c.blocked_cycles::no_mshrs 7857 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71231.534246 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71231.534246 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76420.090300 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76424.518957 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76420.090300 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76424.518957 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1575605 # number of replacements +system.l2c.tags.tagsinuse 65208.311267 # Cycle average of tags in use +system.l2c.tags.total_refs 6750580 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1636875 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.124066 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 3024712500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 9648.504654 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 430.210636 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 509.722466 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4113.935017 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 22579.924066 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 21373.967512 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 14.667516 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 13.437669 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2580.265558 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2788.873436 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1154.802739 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.147224 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.006564 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.007778 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.062774 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.344542 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.326141 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000224 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000205 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.039372 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.042555 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.017621 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995000 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 10940 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 249 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 50081 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 103 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 404 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 10423 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 244 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2182 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 3614 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 44004 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.166931 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003799 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.764175 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 76956529 # Number of tag accesses +system.l2c.tags.data_accesses 76956529 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 2841841 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 2841841 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 3 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 3 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 208782 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 171973 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 380755 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 54097 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 47819 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 101916 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 54890 # 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number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 134880 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 130480 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 265360 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 12794 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 5104 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 534660 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 683464 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 294599 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 11629 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5041 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 480238 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 596154 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 283154 # 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mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.401912 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.265748 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20007.215133 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20922.435798 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20480.106273 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24467.990066 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24337.044534 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24399.682682 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 85540.175428 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 80775.672510 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 83866.595921 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 81466.490300 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80108.939394 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 79397.611466 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 87340.145476 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133615.676277 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 84530.456493 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 86464.137214 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 78311.895891 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 87513.582380 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134729.425703 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 112772.350532 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24895.958354 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20717.471769 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 24117.700412 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 81466.490300 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80108.939394 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 79397.611466 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 86722.561889 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133615.676277 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 84530.456493 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 86464.137214 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 78311.895891 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 85469.251788 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134729.425703 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 109056.054139 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 81466.490300 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80108.939394 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 79397.611466 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 86722.561889 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133615.676277 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 84530.456493 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 86464.137214 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 78311.895891 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 85469.251788 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134729.425703 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 109056.054139 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167775.627329 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 74164.179104 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 95912.972007 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 121759.442826 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 162146.824876 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 65389.705882 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 149138.789590 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 122053.187311 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84328.526919 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 74164.179104 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 47094.992243 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 74147.671970 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 4190264 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2528993 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3019 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 77125.713494 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 65389.705882 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 77908.870645 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 74383.639767 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3980803 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2353726 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3243 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 59861 # Transaction distribution -system.membus.trans_dist::ReadResp 1006452 # Transaction distribution -system.membus.trans_dist::WriteReq 38438 # Transaction distribution -system.membus.trans_dist::WriteResp 38438 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1336656 # Transaction distribution -system.membus.trans_dist::CleanEvict 266935 # Transaction distribution -system.membus.trans_dist::UpgradeReq 438975 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 302731 # Transaction distribution -system.membus.trans_dist::UpgradeResp 22 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 150471 # Transaction distribution -system.membus.trans_dist::ReadExResp 135365 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 946591 # Transaction distribution -system.membus.trans_dist::InvalidateReq 696687 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 59676 # Transaction distribution +system.membus.trans_dist::ReadResp 985495 # Transaction distribution +system.membus.trans_dist::WriteReq 38244 # Transaction distribution +system.membus.trans_dist::WriteResp 38244 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1315010 # Transaction distribution +system.membus.trans_dist::CleanEvict 256715 # Transaction distribution +system.membus.trans_dist::UpgradeReq 339680 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 271581 # Transaction distribution +system.membus.trans_dist::UpgradeResp 24 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 147332 # Transaction distribution +system.membus.trans_dist::ReadExResp 134542 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 925819 # Transaction distribution +system.membus.trans_dist::InvalidateReq 674453 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122580 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26078 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5027920 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5176654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238145 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238145 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5414799 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155687 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25318 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4797896 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4945870 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237932 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237932 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5183802 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155710 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52156 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 147706944 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 147915343 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7266880 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7266880 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 155182223 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 597489 # Total snoops (count) -system.membus.snoopTraffic 179456 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2633759 # Request fanout histogram -system.membus.snoop_fanout::mean 0.013061 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.113535 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50636 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 144939472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 145146374 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7255040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7255040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 152401414 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 572055 # Total snoops (count) +system.membus.snoopTraffic 191360 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2456788 # Request fanout histogram +system.membus.snoop_fanout::mean 0.015156 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.122173 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2599360 98.69% 98.69% # Request fanout histogram -system.membus.snoop_fanout::1 34399 1.31% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2419553 98.48% 98.48% # Request fanout histogram +system.membus.snoop_fanout::1 37235 1.52% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2633759 # Request fanout histogram -system.membus.reqLayer0.occupancy 98019495 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2456788 # Request fanout histogram +system.membus.reqLayer0.occupancy 98064494 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21931994 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21142497 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9377704107 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9055699898 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5794716587 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5680392120 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45616715 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45554532 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3913,83 +3907,83 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 12205642 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6628070 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1941255 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 157740 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 142803 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 14937 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384351300000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 59863 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4654836 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38438 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38438 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 4118892 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2762121 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 740907 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 383504 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1124411 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 124 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 124 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298356 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298356 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4595571 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 881263 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 849910 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10458732 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7383011 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17841743 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 265418110 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 179948433 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 445366543 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3005080 # Total snoops (count) -system.toL2Bus.snoopTraffic 132103248 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 8556754 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.351410 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.481053 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 11893981 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6468498 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1904661 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 211231 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 193743 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 17488 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 59678 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4527289 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38244 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38244 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 4050158 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2718586 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 717362 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 373497 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1090859 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 125 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 293033 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 293033 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4468431 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 869390 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 835427 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9945746 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7459601 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17405347 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 252717925 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 183230753 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 435948678 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2969827 # Total snoops (count) +system.toL2Bus.snoopTraffic 128627856 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 8396274 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.355668 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.483046 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5564766 65.03% 65.03% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 2977051 34.79% 99.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 14937 0.17% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5427479 64.64% 64.64% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2951307 35.15% 99.79% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 17488 0.21% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8556754 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9506782087 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8396274 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9289434840 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2628899 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2606647 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4728944566 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4518737086 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3692981173 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3678115853 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 14084 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 5420 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 4835 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 13392 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index 7e1388539..7623e0029 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.327143 # Number of seconds simulated -sim_ticks 51327142820000 # Number of ticks simulated -final_tick 51327142820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.558015 # Number of seconds simulated +sim_ticks 51558014828000 # Number of ticks simulated +final_tick 51558014828000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 161850 # Simulator instruction rate (inst/s) -host_op_rate 190176 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9793667461 # Simulator tick rate (ticks/s) -host_mem_usage 681320 # Number of bytes of host memory used -host_seconds 5240.85 # Real time elapsed on the host -sim_insts 848230502 # Number of instructions simulated -sim_ops 996685945 # Number of ops (including micro ops) simulated +host_inst_rate 133865 # Simulator instruction rate (inst/s) +host_op_rate 157345 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6235119796 # Simulator tick rate (ticks/s) +host_mem_usage 696436 # Number of bytes of host memory used +host_seconds 8268.97 # Real time elapsed on the host +sim_insts 1106923026 # Number of instructions simulated +sim_ops 1301083589 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 227712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 212864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5673056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 41642312 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 444928 # Number of bytes read from this memory -system.physmem.bytes_read::total 48200872 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5673056 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5673056 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 68445056 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 667968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 559488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 6546400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112650248 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 429376 # Number of bytes read from this memory +system.physmem.bytes_read::total 120853480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 6546400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6546400 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 140957120 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 68465636 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 3558 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3326 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 104594 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 650674 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6952 # Number of read requests responded to by this memory -system.physmem.num_reads::total 769104 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1069454 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 140977700 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 10437 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 8742 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 118240 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1760173 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6709 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1904301 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2202455 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1072027 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 4436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 4147 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 110527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 811312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8668 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 939091 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 110527 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 110527 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1333506 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1333907 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1333506 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 4436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 4147 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 110527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 811713 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8668 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2272998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 769104 # Number of read requests accepted -system.physmem.writeReqs 1072027 # Number of write requests accepted -system.physmem.readBursts 769104 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1072027 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 49176064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 46592 # Total number of bytes read from write queue -system.physmem.bytesWritten 68464384 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 48200872 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 68465636 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 728 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one +system.physmem.num_writes::total 2205028 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 12956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 10852 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 126972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2184922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8328 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2344029 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 126972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 126972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2733952 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2734351 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2733952 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 12956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 10852 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 126972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2185321 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5078380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1904301 # Number of read requests accepted +system.physmem.writeReqs 2205028 # Number of write requests accepted +system.physmem.readBursts 1904301 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2205028 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 121838144 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 37120 # Total number of bytes read from write queue +system.physmem.bytesWritten 140976896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 120853480 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 140977700 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 580 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 44564 # Per bank write bursts -system.physmem.perBankRdBursts::1 52315 # Per bank write bursts -system.physmem.perBankRdBursts::2 47721 # Per bank write bursts -system.physmem.perBankRdBursts::3 44538 # Per bank write bursts -system.physmem.perBankRdBursts::4 44659 # Per bank write bursts -system.physmem.perBankRdBursts::5 50872 # Per bank write bursts -system.physmem.perBankRdBursts::6 46439 # Per bank write bursts -system.physmem.perBankRdBursts::7 47959 # Per bank write bursts -system.physmem.perBankRdBursts::8 44018 # Per bank write bursts -system.physmem.perBankRdBursts::9 71274 # Per bank write bursts -system.physmem.perBankRdBursts::10 43972 # Per bank write bursts -system.physmem.perBankRdBursts::11 51692 # Per bank write bursts -system.physmem.perBankRdBursts::12 45026 # Per bank write bursts -system.physmem.perBankRdBursts::13 46672 # Per bank write bursts -system.physmem.perBankRdBursts::14 42515 # Per bank write bursts -system.physmem.perBankRdBursts::15 44140 # Per bank write bursts -system.physmem.perBankWrBursts::0 64758 # Per bank write bursts -system.physmem.perBankWrBursts::1 69412 # Per bank write bursts -system.physmem.perBankWrBursts::2 67623 # Per bank write bursts -system.physmem.perBankWrBursts::3 66442 # Per bank write bursts -system.physmem.perBankWrBursts::4 66817 # Per bank write bursts -system.physmem.perBankWrBursts::5 69740 # Per bank write bursts -system.physmem.perBankWrBursts::6 65132 # Per bank write bursts -system.physmem.perBankWrBursts::7 69008 # Per bank write bursts -system.physmem.perBankWrBursts::8 65482 # Per bank write bursts -system.physmem.perBankWrBursts::9 70623 # Per bank write bursts -system.physmem.perBankWrBursts::10 64235 # Per bank write bursts -system.physmem.perBankWrBursts::11 70444 # Per bank write bursts -system.physmem.perBankWrBursts::12 64965 # Per bank write bursts -system.physmem.perBankWrBursts::13 66804 # Per bank write bursts -system.physmem.perBankWrBursts::14 64273 # Per bank write bursts -system.physmem.perBankWrBursts::15 63998 # Per bank write bursts +system.physmem.perBankRdBursts::0 114327 # Per bank write bursts +system.physmem.perBankRdBursts::1 123692 # Per bank write bursts +system.physmem.perBankRdBursts::2 118245 # Per bank write bursts +system.physmem.perBankRdBursts::3 117057 # Per bank write bursts +system.physmem.perBankRdBursts::4 115229 # Per bank write bursts +system.physmem.perBankRdBursts::5 125268 # Per bank write bursts +system.physmem.perBankRdBursts::6 115683 # Per bank write bursts +system.physmem.perBankRdBursts::7 119593 # Per bank write bursts +system.physmem.perBankRdBursts::8 115543 # Per bank write bursts +system.physmem.perBankRdBursts::9 144676 # Per bank write bursts +system.physmem.perBankRdBursts::10 112600 # Per bank write bursts +system.physmem.perBankRdBursts::11 120122 # Per bank write bursts +system.physmem.perBankRdBursts::12 113965 # Per bank write bursts +system.physmem.perBankRdBursts::13 118266 # Per bank write bursts +system.physmem.perBankRdBursts::14 113146 # Per bank write bursts +system.physmem.perBankRdBursts::15 116309 # Per bank write bursts +system.physmem.perBankWrBursts::0 135142 # Per bank write bursts +system.physmem.perBankWrBursts::1 141643 # Per bank write bursts +system.physmem.perBankWrBursts::2 136917 # Per bank write bursts +system.physmem.perBankWrBursts::3 137997 # Per bank write bursts +system.physmem.perBankWrBursts::4 135684 # Per bank write bursts +system.physmem.perBankWrBursts::5 143871 # Per bank write bursts +system.physmem.perBankWrBursts::6 135153 # Per bank write bursts +system.physmem.perBankWrBursts::7 138864 # Per bank write bursts +system.physmem.perBankWrBursts::8 135935 # Per bank write bursts +system.physmem.perBankWrBursts::9 142790 # Per bank write bursts +system.physmem.perBankWrBursts::10 134947 # Per bank write bursts +system.physmem.perBankWrBursts::11 140191 # Per bank write bursts +system.physmem.perBankWrBursts::12 134987 # Per bank write bursts +system.physmem.perBankWrBursts::13 137976 # Per bank write bursts +system.physmem.perBankWrBursts::14 134592 # Per bank write bursts +system.physmem.perBankWrBursts::15 136075 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 34 # Number of times write queue was full causing retry -system.physmem.totGap 51327141408500 # Total gap between requests +system.physmem.numWrRetry 125 # Number of times write queue was full causing retry +system.physmem.totGap 51558013451500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 747819 # Read request sizes (log2) +system.physmem.readPktSize::6 1883016 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1069454 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 515353 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 203905 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30484 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12938 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 553 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 806 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2202455 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1140639 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 689076 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 48103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 20384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 609 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 498 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1348 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -160,171 +160,170 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 26806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 32475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 54613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 60437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 62183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 62151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 69842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 64006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 76985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62423 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 65026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 68511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 60500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 57192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 74 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 471870 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 249.306089 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 149.569568 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 290.567780 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 207742 44.03% 44.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 122462 25.95% 69.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 42886 9.09% 79.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 22733 4.82% 83.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14982 3.18% 87.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9606 2.04% 89.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7566 1.60% 90.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6003 1.27% 91.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 37890 8.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 471870 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 54238 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.166341 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 76.651597 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 54233 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 30482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 38490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 83702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 117171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 125843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 130438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 133004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 138248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 140822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 137539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 142466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 143357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 133954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 146358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 136372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 127299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 130102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 120942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 1055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 365 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 933198 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 281.628105 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 167.352526 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 309.404332 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 371108 39.77% 39.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 233427 25.01% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 88383 9.47% 74.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 51664 5.54% 79.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 37413 4.01% 83.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 26389 2.83% 86.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 21045 2.26% 88.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 17945 1.92% 90.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 85824 9.20% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 933198 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 116229 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.379053 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 52.340079 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 116223 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 4 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 54238 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 54238 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.723367 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.775784 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.950161 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 40620 74.89% 74.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 4585 8.45% 83.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 5200 9.59% 92.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1381 2.55% 95.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 413 0.76% 96.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 235 0.43% 96.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 311 0.57% 97.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 127 0.23% 97.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 390 0.72% 98.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 127 0.23% 98.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 50 0.09% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 65 0.12% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 327 0.60% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 36 0.07% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 29 0.05% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 111 0.20% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 166 0.31% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 5 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 17 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 12 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 54238 # Writes before turning the bus around for reads -system.physmem.totQLat 15209667379 # Total ticks spent queuing -system.physmem.totMemAccLat 29616717379 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3841880000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19794.56 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 116229 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 116228 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.951965 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.478061 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 17.079115 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 111884 96.26% 96.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 1770 1.52% 97.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 397 0.34% 98.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 626 0.54% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 488 0.42% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 246 0.21% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 362 0.31% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 120 0.10% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 64 0.06% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 59 0.05% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 51 0.04% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 11 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 17 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 10 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 37 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 24 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 14 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 6 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 5 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 4 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-623 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::624-639 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::752-767 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::768-783 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::976-991 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 116228 # Writes before turning the bus around for reads +system.physmem.totQLat 42075497859 # Total ticks spent queuing +system.physmem.totMemAccLat 77770266609 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9518605000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22101.71 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38544.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.96 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.33 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.94 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.33 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 40851.71 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.36 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.34 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.73 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.49 # Average write queue length when enqueuing -system.physmem.readRowHits 580662 # Number of row buffer hits during reads -system.physmem.writeRowHits 785598 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.57 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.44 # Row buffer hit rate for writes -system.physmem.avgGap 27878049.64 # Average gap between requests -system.physmem.pageHitRate 74.33 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1803657240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 984138375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2956722600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3492279360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1235640856320 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29712388110000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34309704980775 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.451533 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49429181288166 # Time in different power states -system.physmem_0.memoryStateTime::REF 1713925980000 # Time in different power states +system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.62 # Average write queue length when enqueuing +system.physmem.readRowHits 1533744 # Number of row buffer hits during reads +system.physmem.writeRowHits 1639539 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.43 # Row buffer hit rate for writes +system.physmem.avgGap 12546577.18 # Average gap between requests +system.physmem.pageHitRate 77.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3530119320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1926156375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7402894200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 7162084800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3367518529440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1313077918185 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29782982922000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34483600624320 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.831109 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49545451951432 # Time in different power states +system.physmem_0.memoryStateTime::REF 1721635240000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 184032075584 # Time in different power states +system.physmem_0.memoryStateTime::ACT 290927248568 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1763679960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 962325375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3036563400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3439739520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3352439216880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1235034526230 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29712919978500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34309596029865 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.449411 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49430060847495 # Time in different power states -system.physmem_1.memoryStateTime::REF 1713925980000 # Time in different power states +system.physmem_1.actEnergy 3524804640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1923256500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7446082800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 7111728720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3367518529440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1314046606680 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29782133195250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34483704204030 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.833118 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49544014933949 # Time in different power states +system.physmem_1.memoryStateTime::REF 1721635240000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 183155359005 # Time in different power states +system.physmem_1.memoryStateTime::ACT 292364518051 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory @@ -341,30 +340,30 @@ system.realview.nvmem.bw_inst_read::total 7 # I system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 225047911 # Number of BP lookups -system.cpu.branchPred.condPredicted 149825196 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12305756 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 158986930 # Number of BTB lookups -system.cpu.branchPred.BTBHits 98148773 # Number of BTB hits +system.cpu.branchPred.lookups 290131106 # Number of BP lookups +system.cpu.branchPred.condPredicted 198353835 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 13679752 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 208494226 # Number of BTB lookups +system.cpu.branchPred.BTBHits 130534623 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.733863 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 30878370 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 343644 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6734089 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 4745857 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1988232 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 765703 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 62.608268 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 37597374 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 402079 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 8125236 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 6045082 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2080154 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 800698 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -394,87 +393,88 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 948773 # Table walker walks requested -system.cpu.dtb.walker.walksLong 948773 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15596 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155468 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 437937 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 510836 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 2285.186439 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 14758.274331 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-65535 507265 99.30% 99.30% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-131071 2025 0.40% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-196607 1066 0.21% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-262143 211 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-327679 145 0.03% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-393215 26 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-458751 51 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::458752-524287 43 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 1423094 # Table walker walks requested +system.cpu.dtb.walker.walksLong 1423094 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 30587 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 273540 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 668841 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 754253 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2502.822660 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 16371.142747 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 747574 99.11% 99.11% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 4739 0.63% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 871 0.12% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 433 0.06% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 327 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 64 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 235 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 510836 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 488329 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 23221.803333 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 18175.804190 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 21042.780895 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 476828 97.64% 97.64% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 7891 1.62% 99.26% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 2533 0.52% 99.78% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 229 0.05% 99.83% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 568 0.12% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 131 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 114 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 26 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 488329 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 779668986876 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.725199 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.523523 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 777411937376 99.71% 99.71% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 1169683000 0.15% 99.86% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 513347500 0.07% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 208116000 0.03% 99.95% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 157188000 0.02% 99.97% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 121226500 0.02% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 32342000 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 52541000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 2605500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 779668986876 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 155469 90.88% 90.88% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 15596 9.12% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 171065 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 948773 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkWaitTime::655360-720895 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 754253 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 795185 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 25800.017606 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 21033.129871 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 18337.040091 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 776690 97.67% 97.67% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 15553 1.96% 99.63% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 1840 0.23% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 558 0.07% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 320 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 153 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 44 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 19 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 795185 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 1040609044948 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.747004 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.517062 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 1036648437448 99.62% 99.62% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 2501393000 0.24% 99.86% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 710900000 0.07% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 286069000 0.03% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 201203000 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 121106500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 48982500 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 87667500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 3189000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::18-19 41500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::20-21 55500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 1040609044948 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 273541 89.94% 89.94% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 30587 10.06% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 304128 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1423094 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 948773 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 171065 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1423094 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 304128 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 171065 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1119838 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 304128 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1727222 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 169411407 # DTB read hits -system.cpu.dtb.read_misses 675369 # DTB read misses -system.cpu.dtb.write_hits 147344334 # DTB write hits -system.cpu.dtb.write_misses 273404 # DTB write misses -system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed +system.cpu.dtb.read_hits 217549636 # DTB read hits +system.cpu.dtb.read_misses 1002675 # DTB read misses +system.cpu.dtb.write_hits 192429615 # DTB write hits +system.cpu.dtb.write_misses 420419 # DTB write misses +system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 71963 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 101 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 10047 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 63275 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 84838 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 16158 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 69388 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 170086776 # DTB read accesses -system.cpu.dtb.write_accesses 147617738 # DTB write accesses +system.cpu.dtb.perms_faults 86326 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 218552311 # DTB read accesses +system.cpu.dtb.write_accesses 192850034 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 316755741 # DTB hits -system.cpu.dtb.misses 948773 # DTB misses -system.cpu.dtb.accesses 317704514 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 409979251 # DTB hits +system.cpu.dtb.misses 1423094 # DTB misses +system.cpu.dtb.accesses 411402345 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -504,1104 +504,1098 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 162181 # Table walker walks requested -system.cpu.itb.walker.walksLong 162181 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1496 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 120027 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 17971 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 144210 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1137.740101 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 9342.723838 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 143038 99.19% 99.19% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 619 0.43% 99.62% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 86 0.06% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 189 0.13% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 221 0.15% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::163840-196607 35 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 144210 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 139494 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 29066.088864 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24052.553358 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 24213.231696 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 136396 97.78% 97.78% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 707 0.51% 98.29% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 1985 1.42% 99.71% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 151 0.11% 99.82% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 171 0.12% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 34 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 34 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 9 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 139494 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 676589720772 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.947980 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.222341 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 35236838356 5.21% 5.21% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 641313182416 94.79% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 39010000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 686000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 4000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 676589720772 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 120027 98.77% 98.77% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1496 1.23% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 121523 # Table walker page sizes translated +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 177767 # Table walker walks requested +system.cpu.itb.walker.walksLong 177767 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1532 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 128663 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 19966 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 157801 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1393.783943 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 9971.559116 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 155663 98.65% 98.65% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 1042 0.66% 99.31% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 672 0.43% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 333 0.21% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 30 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::163840-196607 26 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::229376-262143 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::294912-327679 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::327680-360447 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 157801 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 150161 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 28501.914612 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 23015.105793 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 23459.229673 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 144112 95.97% 95.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 5152 3.43% 99.40% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 475 0.32% 99.72% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 255 0.17% 99.89% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 99 0.07% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 55 0.04% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 8 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 150161 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 911756921068 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.951043 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.216068 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 44693483152 4.90% 4.90% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 867007398416 95.09% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 55571500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 466000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 911756921068 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 128663 98.82% 98.82% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1532 1.18% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 130195 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 162181 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 162181 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 177767 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 177767 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 121523 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 121523 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 283704 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 357038073 # ITB inst hits -system.cpu.itb.inst_misses 162181 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 130195 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 130195 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 307962 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 462600046 # ITB inst hits +system.cpu.itb.inst_misses 177767 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 39385 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1019 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 52848 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 63275 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 58185 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 357344 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 440221 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 357200254 # ITB inst accesses -system.cpu.itb.hits 357038073 # DTB hits -system.cpu.itb.misses 162181 # DTB misses -system.cpu.itb.accesses 357200254 # DTB accesses -system.cpu.numPwrStateTransitions 32228 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 16114 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3134631677.512784 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 60494120707.852806 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 6793 42.16% 42.16% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9285 57.62% 99.78% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.83% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 462777813 # ITB inst accesses +system.cpu.itb.hits 462600046 # DTB hits +system.cpu.itb.misses 177767 # DTB misses +system.cpu.itb.accesses 462777813 # DTB accesses +system.cpu.numPwrStateTransitions 34262 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 17131 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 2947433272.666569 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 58590018858.186401 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7811 45.60% 45.60% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9284 54.19% 99.79% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::9.5e+11-1e+12 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 16114 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 815687968559 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50511454851441 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1631385344 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::total 17131 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 1065535433949 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50492479394051 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2131080190 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 646877625 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1002761410 # Number of instructions fetch has processed -system.cpu.fetch.Branches 225047911 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 133773000 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 898188451 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26266186 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3841497 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 30548 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8722394 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1026877 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 1034 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 356664988 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6247416 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 47904 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 1571821519 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.747042 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.149310 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 789533395 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1294232501 # Number of instructions fetch has processed +system.cpu.fetch.Branches 290131106 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 174177079 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1253396684 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29442936 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 4521296 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 28032 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11449142 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1221670 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 685 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 462141962 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6901101 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 52491 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 2074872372 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.731015 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.142682 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1014113227 64.52% 64.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 214297646 13.63% 78.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 70312417 4.47% 82.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 273098229 17.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1354023092 65.26% 65.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 279633538 13.48% 78.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 86518146 4.17% 82.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 354697596 17.09% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1571821519 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.137949 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.614669 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 526332322 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 552246914 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 434136742 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 49729183 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9376358 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33563941 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 3814299 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1086052117 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29449193 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9376358 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 571289803 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 66024800 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 371545208 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 438989582 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 114595768 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1065754363 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6907795 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 5097238 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 334375 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 639506 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 63573833 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 20465 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1013430764 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1640279788 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1259572075 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1474026 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 947250209 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 66180552 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 26901106 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23243208 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 101784051 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 173837388 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 150829276 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9883117 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9014861 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1030729252 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27201158 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1045808358 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3377405 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 61244461 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 34071399 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 308913 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1571821519 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.665348 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.919634 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 2074872372 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.136143 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.607313 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 615922756 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 835719938 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 532432043 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 80077312 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10720323 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 41258933 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4059445 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1407827153 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 33008479 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10720323 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 679035070 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 79966926 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 552687037 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 549603762 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 202859254 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1383638167 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 8109162 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7348509 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 966276 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1094350 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 119568064 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 22725 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1333397174 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2200696007 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1641425227 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1433031 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1254726296 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 78670875 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 43643507 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 39180007 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 166278031 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 222554034 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 196867138 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12635283 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11114743 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1330840515 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 43953891 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1360477402 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4212137 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 73710813 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41934009 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 368799 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 2074872372 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.655692 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.916068 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 924230442 58.80% 58.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 334342298 21.27% 80.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234750151 14.93% 95.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 72048277 4.58% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6430828 0.41% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 19523 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 1226409345 59.11% 59.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 451307165 21.75% 80.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 291780533 14.06% 94.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 95920964 4.62% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9425546 0.45% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 28819 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1571821519 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 2074872372 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57691324 35.03% 35.03% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 100152 0.06% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26730 0.02% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 622 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44285841 26.89% 62.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 62576075 38.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 73561900 34.17% 34.17% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 90692 0.04% 34.21% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26794 0.01% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 484 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 57931960 26.91% 61.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 83660297 38.86% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 720343690 68.88% 68.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2530628 0.24% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 122776 0.01% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 375 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 119191 0.01% 69.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 173490543 16.59% 85.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 149201098 14.27% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 57 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 939889673 69.09% 69.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2936613 0.22% 69.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 130878 0.01% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 372 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 112363 0.01% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 222587367 16.36% 85.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 194820033 14.32% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1045808358 # Type of FU issued -system.cpu.iq.rate 0.641055 # Inst issue rate -system.cpu.iq.fu_busy_cnt 164680744 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157467 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3829023509 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1118377930 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1027460456 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2472874 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 938610 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 909796 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1208933693 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1555398 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4274316 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1360477402 # Type of FU issued +system.cpu.iq.rate 0.638398 # Inst issue rate +system.cpu.iq.fu_busy_cnt 215272127 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.158233 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5012901497 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1447776434 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1338315649 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2409942 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 914537 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 885572 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1574233532 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1515940 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5717597 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14173969 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14495 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 142953 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6059351 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 17343387 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24124 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 187368 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7978529 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2526453 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1440750 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3596780 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1680866 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9376358 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 7004216 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6913167 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1058165202 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 10720323 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12040487 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4569260 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1375079942 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 173837388 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 150829276 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22819114 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 57849 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6781828 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 142953 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3462734 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5495013 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8957747 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1034296660 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 169399584 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10573772 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 222554034 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 196867138 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 38644291 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 177419 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4207009 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 187368 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4048268 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6103351 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10151619 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1346834094 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 217554512 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 12249639 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 234792 # number of nop insts executed -system.cpu.iew.exec_refs 316739180 # number of memory reference insts executed -system.cpu.iew.exec_branches 196198672 # Number of branches executed -system.cpu.iew.exec_stores 147339596 # Number of stores executed -system.cpu.iew.exec_rate 0.633999 # Inst execution rate -system.cpu.iew.wb_sent 1029187818 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1028370252 # cumulative count of insts written-back -system.cpu.iew.wb_producers 437853372 # num instructions producing a value -system.cpu.iew.wb_consumers 708400240 # num instructions consuming a value -system.cpu.iew.wb_rate 0.630366 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.618088 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 51884426 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 26892245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8549021 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1559762540 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.638999 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.273827 # Number of insts commited each cycle +system.cpu.iew.exec_nop 285536 # number of nop insts executed +system.cpu.iew.exec_refs 409993947 # number of memory reference insts executed +system.cpu.iew.exec_branches 255680172 # Number of branches executed +system.cpu.iew.exec_stores 192439435 # Number of stores executed +system.cpu.iew.exec_rate 0.631996 # Inst execution rate +system.cpu.iew.wb_sent 1340240150 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1339201221 # cumulative count of insts written-back +system.cpu.iew.wb_producers 574929948 # num instructions producing a value +system.cpu.iew.wb_consumers 943031378 # num instructions consuming a value +system.cpu.iew.wb_rate 0.628414 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.609662 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 62850702 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 43585092 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9678607 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 2060674246 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.631387 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.270689 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1047991029 67.19% 67.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288035307 18.47% 85.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 120100080 7.70% 93.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 36659789 2.35% 95.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28506606 1.83% 97.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13942789 0.89% 98.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8651847 0.55% 98.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4181084 0.27% 99.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11694009 0.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1383412740 67.13% 67.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 394991247 19.17% 86.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 150433823 7.30% 93.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 44582057 2.16% 95.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36156812 1.75% 97.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 18175173 0.88% 98.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10964042 0.53% 98.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5475656 0.27% 99.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 16482696 0.80% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1559762540 # Number of insts commited each cycle -system.cpu.commit.committedInsts 848230502 # Number of instructions committed -system.cpu.commit.committedOps 996685945 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 2060674246 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1106923026 # Number of instructions committed +system.cpu.commit.committedOps 1301083589 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 304433343 # Number of memory references committed -system.cpu.commit.loads 159663418 # Number of loads committed -system.cpu.commit.membars 6927415 # Number of memory barriers committed -system.cpu.commit.branches 189324067 # Number of branches committed -system.cpu.commit.fp_insts 898712 # Number of committed floating point instructions. -system.cpu.commit.int_insts 915721971 # Number of committed integer instructions. -system.cpu.commit.function_calls 25285288 # Number of function calls committed. +system.cpu.commit.refs 394099255 # Number of memory references committed +system.cpu.commit.loads 205210646 # Number of loads committed +system.cpu.commit.membars 9122435 # Number of memory barriers committed +system.cpu.commit.branches 247396089 # Number of branches committed +system.cpu.commit.fp_insts 873905 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1189215854 # Number of committed integer instructions. +system.cpu.commit.function_calls 30973786 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 689893101 69.22% 69.22% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2149376 0.22% 69.43% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 98151 0.01% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 111932 0.01% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 159663418 16.02% 85.47% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 144769925 14.53% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 904226715 69.50% 69.50% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2546778 0.20% 69.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 104952 0.01% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 105847 0.01% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 205210646 15.77% 85.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 188888609 14.52% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 996685945 # Class of committed instruction -system.cpu.commit.bw_lim_events 11694009 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2589097882 # The number of ROB reads -system.cpu.rob.rob_writes 2109106528 # The number of ROB writes -system.cpu.timesIdled 8171713 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59563825 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 101022900419 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 848230502 # Number of Instructions Simulated -system.cpu.committedOps 996685945 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.923281 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.923281 # CPI: Total CPI of All Threads -system.cpu.ipc 0.519945 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.519945 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1223820104 # number of integer regfile reads -system.cpu.int_regfile_writes 731394790 # number of integer regfile writes -system.cpu.fp_regfile_reads 1462803 # number of floating regfile reads -system.cpu.fp_regfile_writes 780644 # number of floating regfile writes -system.cpu.cc_regfile_reads 225050166 # number of cc regfile reads -system.cpu.cc_regfile_writes 225684828 # number of cc regfile writes -system.cpu.misc_regfile_reads 2570368432 # number of misc regfile reads -system.cpu.misc_regfile_writes 26931155 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9701158 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.972800 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 283187639 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9701670 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.189577 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 2743199500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.972800 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy +system.cpu.commit.op_class_0::total 1301083589 # Class of committed instruction +system.cpu.commit.bw_lim_events 16482696 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3398675710 # The number of ROB reads +system.cpu.rob.rob_writes 2741957858 # The number of ROB writes +system.cpu.timesIdled 9058128 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 56207818 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 100984949503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 1106923026 # Number of Instructions Simulated +system.cpu.committedOps 1301083589 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.925229 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.925229 # CPI: Total CPI of All Threads +system.cpu.ipc 0.519419 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.519419 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1599627417 # number of integer regfile reads +system.cpu.int_regfile_writes 942915680 # number of integer regfile writes +system.cpu.fp_regfile_reads 1421408 # number of floating regfile reads +system.cpu.fp_regfile_writes 762380 # number of floating regfile writes +system.cpu.cc_regfile_reads 312164706 # number of cc regfile reads +system.cpu.cc_regfile_writes 313034766 # number of cc regfile writes +system.cpu.misc_regfile_reads 3414318389 # number of misc regfile reads +system.cpu.misc_regfile_writes 44468731 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 13662519 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.983620 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 361203380 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 13663031 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 26.436548 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1659288500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.983620 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1237018765 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1237018765 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 147199934 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 147199934 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128255410 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128255410 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 377663 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 377663 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 323814 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 323814 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3295431 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3295431 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3691256 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3691256 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 275779158 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 275779158 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 276156821 # number of overall hits -system.cpu.dcache.overall_hits::total 276156821 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9580915 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9580915 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 11254027 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 11254027 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1170464 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1170464 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1233639 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1233639 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 446709 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 446709 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 8 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 22068581 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 22068581 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 23239045 # number of overall misses -system.cpu.dcache.overall_misses::total 23239045 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 168767240000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 168767240000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 444298934810 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 444298934810 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 52375248289 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 52375248289 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6883962000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 6883962000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 380500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 380500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 665441423099 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 665441423099 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 665441423099 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 665441423099 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 156780849 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 156780849 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 139509437 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 139509437 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1548127 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1548127 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1557453 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1557453 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3742140 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3742140 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3691264 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3691264 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 297847739 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 297847739 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 299395866 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 299395866 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061110 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.061110 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080669 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080669 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.756052 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.756052 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.792087 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.792087 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119373 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119373 # miss rate for LoadLockedReq accesses +system.cpu.dcache.tags.tag_accesses 1599492126 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1599492126 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 186946586 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 186946586 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 163344159 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 163344159 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 463383 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 463383 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 333988 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 333988 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4793284 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4793284 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5278947 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5278947 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 350624733 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 350624733 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 351088116 # number of overall hits +system.cpu.dcache.overall_hits::total 351088116 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12788061 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12788061 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 18648516 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 18648516 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 2041461 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2041461 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1270506 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1270506 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 548369 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 548369 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 9 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 32707083 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 32707083 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 34748544 # number of overall misses +system.cpu.dcache.overall_misses::total 34748544 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 205827865000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 205827865000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1003464059741 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1003464059741 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 29968640002 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 29968640002 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 8933513500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 8933513500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 300500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 300500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1239260564743 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1239260564743 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1239260564743 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1239260564743 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 199734647 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 199734647 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 181992675 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 181992675 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2504844 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2504844 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1604494 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1604494 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5341653 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5341653 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5278956 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5278956 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 383331816 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 383331816 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 385836660 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 385836660 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064025 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.064025 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.102468 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.102468 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.815005 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.815005 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791842 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.791842 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102659 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102659 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074093 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074093 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.077620 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.077620 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17614.939700 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17614.939700 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39479.106884 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39479.106884 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 42455.895354 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 42455.895354 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15410.394686 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15410.394686 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 47562.500000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 47562.500000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30153.339859 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30153.339859 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28634.628622 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28634.628622 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32224409 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.085323 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.085323 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.090060 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.090060 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16095.314606 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16095.314606 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53809.325082 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53809.325082 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23587.956296 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23587.956296 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16291.062223 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16291.062223 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 33388.888889 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 33388.888889 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37889.669487 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37889.669487 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35663.668807 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35663.668807 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24419954 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1601607 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2093623 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.120048 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.663969 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 7504086 # number of writebacks -system.cpu.dcache.writebacks::total 7504086 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4456599 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4456599 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9250788 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9250788 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7056 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 7056 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 219268 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 219268 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 13714443 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 13714443 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 13714443 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 13714443 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5124316 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5124316 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2003239 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2003239 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1163648 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1163648 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1226583 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1226583 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 227441 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 227441 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 8 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 8354138 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 8354138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9517786 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9517786 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84959954500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 84959954500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77558080846 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77558080846 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23723735000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23723735000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 50708992789 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 50708992789 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3202218000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3202218000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 372500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 372500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213227028135 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 213227028135 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 236950763135 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 236950763135 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6192056000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6192056000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6192056000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6192056000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032685 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032685 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014359 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014359 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751649 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751649 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787557 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787557 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060778 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060778 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.writebacks::writebacks 10319802 # number of writebacks +system.cpu.dcache.writebacks::total 10319802 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5736139 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5736139 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15576096 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15576096 # number of WriteReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6849 # number of WriteLineReq MSHR hits +system.cpu.dcache.WriteLineReq_mshr_hits::total 6849 # number of WriteLineReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 265006 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 265006 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 21319084 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 21319084 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 21319084 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 21319084 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7051922 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7051922 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3072420 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3072420 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2034687 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 2034687 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263657 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1263657 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 283363 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 283363 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 9 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 9 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 11387999 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 11387999 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 13422686 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 13422686 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 33692 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 67395 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 110827450000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 110827450000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 147154305213 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 147154305213 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 32559356000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 32559356000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 28426038502 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 28426038502 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4117736500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4117736500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 291500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 291500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 286407793715 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 286407793715 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 318967149715 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 318967149715 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6225596500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6225596500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6225596500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6225596500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035306 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035306 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016882 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016882 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.812301 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.812301 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787574 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787574 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.053048 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.053048 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028048 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028048 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031790 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031790 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16579.764890 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16579.764890 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38716.339311 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38716.339311 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20387.380892 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20387.380892 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 41341.672589 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 41341.672589 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14079.334860 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14079.334860 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 46562.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 46562.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25523.522371 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25523.522371 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24895.575834 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24895.575834 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183860.561791 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183860.561791 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.720308 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.720308 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 15134592 # number of replacements -system.cpu.icache.tags.tagsinuse 511.928988 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 340756209 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15135104 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22.514296 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 20447572500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.928988 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999861 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999861 # Average percentage of cache occupancy +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029708 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.029708 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034789 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034789 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15715.921135 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15715.921135 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47895.243884 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47895.243884 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16002.144802 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16002.144802 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22495.058787 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22495.058787 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14531.666096 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14531.666096 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 32388.888889 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 32388.888889 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25149.966532 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25149.966532 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23763.287744 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23763.287744 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184779.665796 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184779.665796 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92374.753320 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92374.753320 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 16891256 # number of replacements +system.cpu.icache.tags.tagsinuse 511.956016 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 444441322 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16891768 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26.311119 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 13164566500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.956016 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999914 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999914 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 112 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 371779021 # Number of tag accesses -system.cpu.icache.tags.data_accesses 371779021 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 340756209 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 340756209 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 340756209 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 340756209 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 340756209 # number of overall hits -system.cpu.icache.overall_hits::total 340756209 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15887482 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15887482 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15887482 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15887482 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15887482 # number of overall misses -system.cpu.icache.overall_misses::total 15887482 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 214918228873 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 214918228873 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 214918228873 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 214918228873 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 214918228873 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 214918228873 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 356643691 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 356643691 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 356643691 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 356643691 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 356643691 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 356643691 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044547 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.044547 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.044547 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.044547 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.044547 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.044547 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13527.519897 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13527.519897 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13527.519897 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13527.519897 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13527.519897 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13527.519897 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 24649 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 479012658 # Number of tag accesses +system.cpu.icache.tags.data_accesses 479012658 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 444441322 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 444441322 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 444441322 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 444441322 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 444441322 # number of overall hits +system.cpu.icache.overall_hits::total 444441322 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17679342 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17679342 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17679342 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17679342 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17679342 # number of overall misses +system.cpu.icache.overall_misses::total 17679342 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 234300237389 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 234300237389 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 234300237389 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 234300237389 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 234300237389 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 234300237389 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 462120664 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 462120664 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 462120664 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 462120664 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 462120664 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 462120664 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038257 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.038257 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.038257 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.038257 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.038257 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.038257 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13252.769101 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13252.769101 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13252.769101 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13252.769101 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13252.769101 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13252.769101 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 16371 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1517 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1212 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 16.248517 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 13.507426 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 15134592 # number of writebacks -system.cpu.icache.writebacks::total 15134592 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 752151 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 752151 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 752151 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 752151 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 752151 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 752151 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15135331 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15135331 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15135331 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15135331 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15135331 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15135331 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 16891256 # number of writebacks +system.cpu.icache.writebacks::total 16891256 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 787348 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 787348 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 787348 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 787348 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 787348 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 787348 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16891994 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 16891994 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 16891994 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 16891994 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 16891994 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 16891994 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192625378387 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 192625378387 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192625378387 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 192625378387 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192625378387 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 192625378387 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 2684938500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 2684938500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 2684938500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 2684938500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.042438 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.042438 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.042438 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.042438 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.042438 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.042438 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12726.869230 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12726.869230 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12726.869230 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12726.869230 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12726.869230 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12726.869230 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.968724 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.968724 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.968724 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.968724 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1148622 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65301.900403 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 46289210 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1211379 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 38.211996 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 4512200500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37189.560843 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 293.778433 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 476.562000 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 7800.369043 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 19541.630085 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.567468 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004483 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007272 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.119024 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.298182 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996428 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 234 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62523 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 234 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 564 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2712 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5162 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54018 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003571 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.954025 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 410396361 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 410396361 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 787478 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 297374 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1084852 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 7504086 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 7504086 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 15131991 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 15131991 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 9360 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 9360 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 4 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 210691534398 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 210691534398 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 210691534398 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 210691534398 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 210691534398 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1610722500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1610722500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1610722500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 1610722500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036553 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036553 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036553 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.036553 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036553 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.036553 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12472.863440 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12472.863440 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12472.863440 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12472.863440 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12472.863440 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12472.863440 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75642.082277 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75642.082277 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75642.082277 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75642.082277 # average overall mshr uncacheable latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 2372905 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65457.290128 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 58959202 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2435994 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 24.203345 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2520974000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 9397.889077 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 196.572797 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 228.214718 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6628.882550 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 49005.730985 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.143400 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.002999 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.003482 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101149 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.747768 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998799 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 222 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 62867 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 222 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 376 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1017 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5588 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55850 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003387 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.959274 # 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number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 8 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 8 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1963232 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1963232 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15135118 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 15135118 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6511870 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 6511870 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1226583 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::total 1226583 # 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miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.011061 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.006306 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.785050 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.785050 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.201159 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.201159 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005506 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005506 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.039469 # 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number of InvalidateReq MSHR miss cycles -system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 34915200500 # number of InvalidateReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 456305510 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 429144000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10406063168 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 84347922221 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 95639434899 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 456305510 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 429144000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10406063168 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 84347922221 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 95639434899 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2418763500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5770936000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8189699500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2418763500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5770936000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 8189699500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004498 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.011061 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.006306 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88689 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 832356501 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 692749000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1525105501 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 77850000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 77850000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 181500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 181500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 110528159195 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 110528159195 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 7331831049 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 7331831049 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 34442081593 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 34442081593 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 12207320002 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 12207320002 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 832356501 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 692749000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7331831049 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 144970240788 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 153827177338 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 832356501 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 692749000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7331831049 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 144970240788 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 153827177338 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1344547500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5804287500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7148835000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1344547500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5804287500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 7148835000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.008126 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.028090 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012019 # mshr miss rate for ReadReq accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.785050 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.785050 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.201159 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.201159 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005506 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005506 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.039465 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039465 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.407265 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.407265 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004498 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.011061 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005506 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.076921 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.030044 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004498 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.011061 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005506 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.076921 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.030044 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129027.059531 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128624.275131 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68019.072693 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68019.072693 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69375 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69375 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129347.114780 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129347.114780 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124865.765533 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124865.765533 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129442.828646 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129442.828646 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 69894.144460 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69894.144460 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129027.059531 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124865.765533 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129384.846523 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128870.322998 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128247.754356 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129027.059531 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124865.765533 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129384.846523 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128870.322998 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171356.256310 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148979.471367 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.968724 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85655.237926 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 92363.643028 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 50407203 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 25570213 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3413 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2115 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2115 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.094837 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.094837 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.444444 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.444444 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437822 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437822 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005741 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.045756 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.045756 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.466977 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.466977 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008126 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.028090 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.142052 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060787 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008126 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.028090 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.142052 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.060787 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 79519.552688 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19090.240314 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19090.240314 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45375 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45375 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82894.958867 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82894.958867 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75598.356935 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75598.356935 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80471.401186 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80471.401186 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20686.901693 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20686.901693 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75598.356935 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82306.041929 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81931.089559 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75598.356935 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82306.041929 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81931.089559 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63142.082277 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172274.946575 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 130011.912123 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63142.082277 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86123.414200 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 80605.655718 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 62084255 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 31529230 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3455 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2096 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2096 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1618708 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23266675 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8573574 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 15134592 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2391693 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43548 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43556 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1963232 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1963232 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15135331 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6520715 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1333247 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1226583 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45447628 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29327152 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 726647 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1928826 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 77430253 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1937602080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1022907422 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2405600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6328296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2969243398 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1852603 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 72285944 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 27912596 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.024958 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.155996 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 2242102 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 28488845 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33703 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33703 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 12415627 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 16891256 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 3619797 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43003 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 43012 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3045422 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3045422 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 16891994 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 9356331 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1295806 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1263657 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50717623 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41210208 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 777423 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3005376 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 95710630 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2162455328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1454268658 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2489712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10275752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 3629489450 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2999840 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 138927432 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 35281285 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.026592 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.160887 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 27215961 97.50% 97.50% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 696635 2.50% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 34343098 97.34% 97.34% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 938187 2.66% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 27912596 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 48339894491 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 35281285 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 58941748976 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1459384 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1470395 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22733591738 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 25369728010 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13401353655 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 19308156079 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 426266814 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 466604190 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1138134788 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1721722349 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40293 # Transaction distribution -system.iobus.trans_dist::ReadResp 40293 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40300 # Transaction distribution +system.iobus.trans_dist::ReadResp 40300 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1618,11 +1612,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230944 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230958 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353728 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353742 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1637,16 +1631,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334208 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334264 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334264 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492128 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 41884500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492184 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 41887500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 345000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 337000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1654,85 +1648,85 @@ system.iobus.reqLayer4.occupancy 9500 # La system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25117000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25106500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 36500500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 567323274 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 568968673 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147704000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147718000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115453 # number of replacements -system.iocache.tags.tagsinuse 10.423128 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115465 # number of replacements +system.iocache.tags.tagsinuse 10.450543 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115469 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115481 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13098782503000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544201 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.878927 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221513 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.429933 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651446 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13091229344000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 5.877255 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 4.573288 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.367328 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.285830 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653159 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039605 # Number of tag accesses -system.iocache.tags.data_accesses 1039605 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039668 # Number of tag accesses +system.iocache.tags.data_accesses 1039668 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8808 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8845 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8815 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8852 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115472 # number of demand (read+write) misses -system.iocache.demand_misses::total 115512 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115479 # number of demand (read+write) misses +system.iocache.demand_misses::total 115519 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115472 # number of overall misses -system.iocache.overall_misses::total 115512 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5076000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1670063987 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1675139987 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115479 # number of overall misses +system.iocache.overall_misses::total 115519 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1629675592 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1634761592 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13414774287 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13414774287 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5427000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15084838274 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15090265274 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5427000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15084838274 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15090265274 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12811525081 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12811525081 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14441200673 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14446637673 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14441200673 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14446637673 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8808 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8845 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8815 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8852 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115472 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115512 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115479 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115519 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115472 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115512 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115479 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115519 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1746,53 +1740,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137189.189189 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 189607.627952 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 189388.353533 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 184875.279864 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 184677.089019 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125766.653107 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125766.653107 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135675 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 130636.329794 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 130638.074607 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135675 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 130636.329794 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 130638.074607 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33964 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120111.050411 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120111.050411 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125054.777691 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125058.541651 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125054.777691 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125058.541651 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32070 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3510 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3415 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.676353 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.390922 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8808 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8845 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8815 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8852 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115472 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115512 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115479 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115519 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115472 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115512 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3226000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1229663987 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1232889987 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115479 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115519 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1188925592 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1192161592 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8076516803 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8076516803 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3427000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9306180790 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9309607790 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3427000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9306180790 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9309607790 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7471582182 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7471582182 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8660507774 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8663944774 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8660507774 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8663944774 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1806,89 +1800,95 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87189.189189 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139607.627952 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 139388.353533 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134875.279864 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 134677.089019 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75719.238009 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75719.238009 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85675 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 80592.531436 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 80594.291416 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85675 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 80592.531436 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 80594.291416 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 54972 # Transaction distribution -system.membus.trans_dist::ReadResp 411033 # Transaction distribution -system.membus.trans_dist::WriteReq 33696 # Transaction distribution -system.membus.trans_dist::WriteResp 33696 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1069454 # Transaction distribution -system.membus.trans_dist::CleanEvict 193565 # Transaction distribution -system.membus.trans_dist::UpgradeReq 34895 # Transaction distribution +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70047.834152 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70047.834152 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 74996.386997 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75000.171175 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74996.386997 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75000.171175 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 5074419 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2524015 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3002 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 54986 # Transaction distribution +system.membus.trans_dist::ReadResp 608005 # Transaction distribution +system.membus.trans_dist::WriteReq 33703 # Transaction distribution +system.membus.trans_dist::WriteResp 33703 # Transaction distribution +system.membus.trans_dist::WritebackDirty 2202455 # Transaction distribution +system.membus.trans_dist::CleanEvict 284620 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4643 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 394310 # Transaction distribution -system.membus.trans_dist::ReadExResp 394310 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 356061 # Transaction distribution -system.membus.trans_dist::InvalidateReq 606112 # Transaction distribution +system.membus.trans_dist::ReadExReq 1332798 # Transaction distribution +system.membus.trans_dist::ReadExResp 1332798 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 553019 # Transaction distribution +system.membus.trans_dist::InvalidateReq 696755 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3212019 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3341639 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237917 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237917 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3579556 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6767333 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 6896995 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237693 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237693 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7134688 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 109397260 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 109567230 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7269248 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7269248 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 116836478 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2560 # Total snoops (count) -system.membus.snoopTraffic 163328 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2743103 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 254577484 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 254747538 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7253696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 262001234 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2809 # Total snoops (count) +system.membus.snoopTraffic 179264 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2675908 # Request fanout histogram +system.membus.snoop_fanout::mean 0.013150 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.113918 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2743103 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2640719 98.68% 98.68% # Request fanout histogram +system.membus.snoop_fanout::1 35189 1.32% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2743103 # Request fanout histogram -system.membus.reqLayer0.occupancy 103939500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2675908 # Request fanout histogram +system.membus.reqLayer0.occupancy 103923000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5573000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5620000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7172212711 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 14223305475 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4075256665 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 10050154677 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44789891 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44814659 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1898,11 +1898,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -1931,30 +1931,30 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51327142820000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16114 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 17131 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt index b33124edd..a22c43be0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt @@ -1,58 +1,58 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 51.111167 # Number of seconds simulated -sim_ticks 51111167192000 # Number of ticks simulated -final_tick 51111167192000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 51111167268500 # Number of ticks simulated +final_tick 51111167268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 942442 # Simulator instruction rate (inst/s) -host_op_rate 1107573 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49042304128 # Simulator tick rate (ticks/s) -host_mem_usage 674172 # Number of bytes of host memory used -host_seconds 1042.19 # Real time elapsed on the host -sim_insts 982198638 # Number of instructions simulated -sim_ops 1154296340 # Number of ops (including micro ops) simulated +host_inst_rate 926682 # Simulator instruction rate (inst/s) +host_op_rate 1089052 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48222226969 # Simulator tick rate (ticks/s) +host_mem_usage 681368 # Number of bytes of host memory used +host_seconds 1059.91 # Real time elapsed on the host +sim_insts 982198023 # Number of instructions simulated +sim_ops 1154295627 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5484148 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 74913608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5483444 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 74913992 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory -system.physmem.bytes_read::total 81622588 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5484148 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5484148 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103278016 # Number of bytes written to this memory +system.physmem.bytes_read::total 81622268 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5483444 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5483444 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103278528 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103298596 # Number of bytes written to this memory +system.physmem.bytes_written::total 103299108 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 6476 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5837 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 126097 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1170538 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 126086 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1170544 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1315773 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1613719 # Number of write requests responded to by this memory +system.physmem.num_reads::total 1315768 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1613727 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1616292 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1616300 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 8109 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 7309 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 107298 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1465699 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 107285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1465707 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1596962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 107298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 107298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2020655 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1596956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 107285 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107285 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2020665 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2021057 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2020655 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2021067 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2020665 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 8109 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 7309 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 107298 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1466102 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 107285 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1466110 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3618019 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.physmem.bw_total::total 3618023 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -69,9 +69,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -79,7 +79,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -109,30 +109,30 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 266586 # Table walker walks requested -system.cpu.dtb.walker.walksLong 266586 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walkWaitTime::samples 266586 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 266586 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 266586 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 266581 # Table walker walks requested +system.cpu.dtb.walker.walksLong 266581 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walkWaitTime::samples 266581 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 266581 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 266581 # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution system.cpu.dtb.walker.walkPageSizes::4K 204774 89.35% 89.35% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 24416 10.65% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 229190 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 266586 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::2M 24411 10.65% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 229185 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 266581 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 266586 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 229190 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 266581 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 229185 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 229190 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 495776 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 229185 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 495766 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 183544097 # DTB read hits -system.cpu.dtb.read_misses 195348 # DTB read misses -system.cpu.dtb.write_hits 167774773 # DTB write hits +system.cpu.dtb.read_hits 183543984 # DTB read hits +system.cpu.dtb.read_misses 195343 # DTB read misses +system.cpu.dtb.write_hits 167774645 # DTB write hits system.cpu.dtb.write_misses 71238 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -140,16 +140,16 @@ system.cpu.dtb.flush_tlb_mva_asid 49771 # Nu system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 82439 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 9079 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 9074 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 183739445 # DTB read accesses -system.cpu.dtb.write_accesses 167846011 # DTB write accesses +system.cpu.dtb.read_accesses 183739327 # DTB read accesses +system.cpu.dtb.write_accesses 167845883 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 351318870 # DTB hits -system.cpu.dtb.misses 266586 # DTB misses -system.cpu.dtb.accesses 351585456 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 351318629 # DTB hits +system.cpu.dtb.misses 266581 # DTB misses +system.cpu.dtb.accesses 351585210 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -179,7 +179,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 126834 # Table walker walks requested system.cpu.itb.walker.walksLong 126834 # Table walker walks initiated with long descriptors system.cpu.itb.walker.walkWaitTime::samples 126834 # Table walker wait (enqueue to first request) latency @@ -198,7 +198,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114696 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 114696 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 241530 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 982675484 # ITB inst hits +system.cpu.itb.inst_hits 982674869 # ITB inst hits system.cpu.itb.inst_misses 126834 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -215,14 +215,14 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 982802318 # ITB inst accesses -system.cpu.itb.hits 982675484 # DTB hits +system.cpu.itb.inst_accesses 982801703 # ITB inst accesses +system.cpu.itb.hits 982674869 # DTB hits system.cpu.itb.misses 126834 # DTB misses -system.cpu.itb.accesses 982802318 # DTB accesses +system.cpu.itb.accesses 982801703 # DTB accesses system.cpu.numPwrStateTransitions 33550 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 16775 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3012440883.104620 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 59942517995.825706 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3012440908.824083 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 59942517661.771744 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 7454 44.44% 44.44% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 9286 55.36% 99.79% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state @@ -235,40 +235,40 @@ system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.89% system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 1988782948204 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 1988782931704 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 16775 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 577471377920 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50533695814080 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 102222351160 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 577471022976 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50533696245524 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 102222351313 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed -system.cpu.committedInsts 982198638 # Number of instructions committed -system.cpu.committedOps 1154296340 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1057877800 # Number of integer alu accesses +system.cpu.committedInsts 982198023 # Number of instructions committed +system.cpu.committedOps 1154295627 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1057877135 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 881349 # Number of float alu accesses -system.cpu.num_func_calls 56833909 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 151622723 # number of instructions that are conditional controls -system.cpu.num_int_insts 1057877800 # number of integer instructions +system.cpu.num_func_calls 56833843 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 151622640 # number of instructions that are conditional controls +system.cpu.num_int_insts 1057877135 # number of integer instructions system.cpu.num_fp_insts 881349 # number of float instructions -system.cpu.num_int_register_reads 1560754548 # number of times the integer registers were read -system.cpu.num_int_register_writes 840513636 # number of times the integer registers were written +system.cpu.num_int_register_reads 1560753668 # number of times the integer registers were read +system.cpu.num_int_register_writes 840513151 # number of times the integer registers were written system.cpu.num_fp_register_reads 1419767 # number of times the floating registers were read system.cpu.num_fp_register_writes 748560 # number of times the floating registers were written -system.cpu.num_cc_register_reads 264017562 # number of times the CC registers were read -system.cpu.num_cc_register_writes 263439787 # number of times the CC registers were written -system.cpu.num_mem_refs 351538306 # number of memory refs -system.cpu.num_load_insts 183711405 # Number of load instructions -system.cpu.num_store_insts 167826901 # Number of store instructions -system.cpu.num_idle_cycles 101067408214.617065 # Number of idle cycles -system.cpu.num_busy_cycles 1154942945.382940 # Number of busy cycles +system.cpu.num_cc_register_reads 264017457 # number of times the CC registers were read +system.cpu.num_cc_register_writes 263439679 # number of times the CC registers were written +system.cpu.num_mem_refs 351538055 # number of memory refs +system.cpu.num_load_insts 183711282 # Number of load instructions +system.cpu.num_store_insts 167826773 # Number of store instructions +system.cpu.num_idle_cycles 101067409077.505173 # Number of idle cycles +system.cpu.num_busy_cycles 1154942235.494823 # Number of busy cycles system.cpu.not_idle_fraction 0.011298 # Percentage of non-idle cycles system.cpu.idle_fraction 0.988702 # Percentage of idle cycles -system.cpu.Branches 219532347 # Number of branches fetched +system.cpu.Branches 219532189 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 800829907 69.34% 69.34% # Class of executed instruction -system.cpu.op_class::IntMult 2354386 0.20% 69.54% # Class of executed instruction +system.cpu.op_class::IntAlu 800829443 69.34% 69.34% # Class of executed instruction +system.cpu.op_class::IntMult 2354388 0.20% 69.54% # Class of executed instruction system.cpu.op_class::IntDiv 100543 0.01% 69.55% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction @@ -296,17 +296,17 @@ system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.56% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::MemRead 183711405 15.91% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 167826901 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 183711282 15.91% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 167826773 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1154931007 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 11605970 # number of replacements +system.cpu.op_class::total 1154930294 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 11606056 # number of replacements system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 339855114 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11606482 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.281492 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 339854782 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11606568 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.281247 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy @@ -316,87 +316,87 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 199 system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1417452931 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1417452931 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 171110382 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 171110382 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 159073547 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 159073547 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 424481 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 424481 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 1417452033 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1417452033 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 171110167 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 171110167 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 159090000 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 159090000 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 424478 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 424478 # number of SoftPFReq hits system.cpu.dcache.WriteLineReq_hits::cpu.data 336283 # number of WriteLineReq hits system.cpu.dcache.WriteLineReq_hits::total 336283 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303643 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4303643 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4555646 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4555646 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 330520212 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 330520212 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 330944693 # number of overall hits -system.cpu.dcache.overall_hits::total 330944693 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6002738 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6002738 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2568126 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2568126 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1586184 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1586184 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303639 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4303639 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4555644 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4555644 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 330536450 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 330536450 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 330960928 # number of overall hits +system.cpu.dcache.overall_hits::total 330960928 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6002834 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6002834 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2551547 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2551547 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1586190 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1586190 # number of SoftPFReq misses system.cpu.dcache.WriteLineReq_misses::cpu.data 1246772 # number of WriteLineReq misses system.cpu.dcache.WriteLineReq_misses::total 1246772 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 253806 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 253806 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 253808 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 253808 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 9817636 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9817636 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 11403820 # number of overall misses -system.cpu.dcache.overall_misses::total 11403820 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 177113120 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 177113120 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 161641673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 161641673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010665 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2010665 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9801153 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9801153 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 11387343 # number of overall misses +system.cpu.dcache.overall_misses::total 11387343 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 177113001 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 177113001 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 161641547 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 161641547 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010668 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2010668 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583055 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_accesses::total 1583055 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557449 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4557449 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555647 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4555647 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 340337848 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 340337848 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 342348513 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 342348513 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033892 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.033892 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015888 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015888 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788885 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.788885 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557447 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4557447 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555645 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4555645 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 340337603 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 340337603 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 342348271 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 342348271 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033893 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.033893 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015785 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015785 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788887 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.788887 # miss rate for SoftPFReq accesses system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787573 # miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_miss_rate::total 0.787573 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055690 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055690 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055691 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055691 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.028847 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.028847 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.033311 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.033311 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.028798 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.028798 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.033262 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.033262 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 8916642 # number of writebacks -system.cpu.dcache.writebacks::total 8916642 # number of writebacks -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 14265273 # number of replacements +system.cpu.dcache.writebacks::writebacks 8918956 # number of writebacks +system.cpu.dcache.writebacks::total 8918956 # number of writebacks +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 14265255 # number of replacements system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 968524390 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 14265785 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.891419 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 968523793 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 14265767 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.891463 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 6061932500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy @@ -406,27 +406,27 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 184 system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 997055970 # Number of tag accesses -system.cpu.icache.tags.data_accesses 997055970 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 968524390 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 968524390 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 968524390 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 968524390 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 968524390 # number of overall hits -system.cpu.icache.overall_hits::total 968524390 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14265790 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14265790 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14265790 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14265790 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14265790 # number of overall misses -system.cpu.icache.overall_misses::total 14265790 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 982790180 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 982790180 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 982790180 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 982790180 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 982790180 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 982790180 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 997055337 # Number of tag accesses +system.cpu.icache.tags.data_accesses 997055337 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 968523793 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 968523793 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 968523793 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 968523793 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 968523793 # number of overall hits +system.cpu.icache.overall_hits::total 968523793 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14265772 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14265772 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14265772 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14265772 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14265772 # number of overall misses +system.cpu.icache.overall_misses::total 14265772 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 982789565 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 982789565 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 982789565 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 982789565 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 982789565 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 982789565 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014516 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.014516 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.014516 # miss rate for demand accesses @@ -439,200 +439,200 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 14265273 # number of writebacks -system.cpu.icache.writebacks::total 14265273 # number of writebacks -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.cpu.icache.writebacks::writebacks 14265255 # number of writebacks +system.cpu.icache.writebacks::total 14265255 # number of writebacks +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1725823 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65319.568119 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 46895862 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1788839 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 26.215809 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37200.621218 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 312.625793 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 449.901085 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6075.914096 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 21280.505928 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.567636 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004770 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006865 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.092711 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.324715 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996698 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 317 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62699 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 317 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 608 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2778 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4924 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54253 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004837 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956711 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 425623617 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 425623617 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 509088 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255953 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 765041 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 8916642 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 8916642 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 14263696 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 14263696 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 11204 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 11204 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1689386 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1689386 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14182781 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 14182781 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7498617 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 7498617 # number of ReadSharedReq hits -system.cpu.l2cache.InvalidateReq_hits::cpu.data 694560 # number of InvalidateReq hits -system.cpu.l2cache.InvalidateReq_hits::total 694560 # number of InvalidateReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 509088 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 255953 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 14182781 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 9188003 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 24135825 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 509088 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 255953 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 14182781 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 9188003 # number of overall hits -system.cpu.l2cache.overall_hits::total 24135825 # number of overall hits +system.cpu.l2cache.tags.tagsinuse 65403.901916 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 49389938 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1788899 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 27.609126 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 395496000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 9615.361386 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 436.090806 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 495.840367 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6075.388739 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48781.220619 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.146719 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006654 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007566 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.092703 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.744342 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997984 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 373 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 62703 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 373 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1444 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5122 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55698 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.005692 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956772 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 422564531 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 422564531 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 480106 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 237369 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 717475 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 8918956 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 8918956 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 14263678 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 14263678 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 30692 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 30692 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1689371 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1689371 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14182774 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 14182774 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7498712 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 7498712 # number of ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 694558 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 694558 # number of InvalidateReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 480106 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 237369 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 14182774 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 9188083 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 24088332 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 480106 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 237369 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 14182774 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 9188083 # number of overall hits +system.cpu.l2cache.overall_hits::total 24088332 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6476 # 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number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 344111 # number of ReadSharedReq misses -system.cpu.l2cache.InvalidateReq_misses::cpu.data 552212 # number of InvalidateReq misses -system.cpu.l2cache.InvalidateReq_misses::total 552212 # number of InvalidateReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 827606 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 827606 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 82998 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 82998 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344120 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 344120 # number of ReadSharedReq misses +system.cpu.l2cache.InvalidateReq_misses::cpu.data 552214 # number of InvalidateReq misses +system.cpu.l2cache.InvalidateReq_misses::total 552214 # number of InvalidateReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 6476 # 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number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 515564 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261790 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 777354 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 8916642 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 8916642 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 14263696 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 14263696 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51131 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 51131 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.inst 82998 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1171726 # number of overall misses +system.cpu.l2cache.overall_misses::total 1267037 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 486582 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 243206 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 729788 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 8918956 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 8918956 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 14263678 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 14263678 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 34570 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 34570 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2516995 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2516995 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14265790 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 14265790 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7842728 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7842728 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2516977 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2516977 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14265772 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 14265772 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7842832 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 7842832 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1246772 # number of InvalidateReq accesses(hits+misses) system.cpu.l2cache.InvalidateReq_accesses::total 1246772 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 515564 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 261790 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 14265790 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 10359723 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 25402867 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 515564 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 261790 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 14265790 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 10359723 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 25402867 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012561 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022296 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015840 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780877 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780877 # miss rate for UpgradeReq accesses +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 486582 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 243206 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 14265772 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 10359809 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 25355369 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 486582 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 243206 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 14265772 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 10359809 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 25355369 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.013309 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.024000 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016872 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.112178 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.112178 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328808 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.328808 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005819 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005819 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043876 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043876 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442913 # miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442913 # miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012561 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022296 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005819 # miss rate for demand accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328810 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.328810 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005818 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005818 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043877 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043877 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442915 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442915 # miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.013309 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.024000 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005818 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.113103 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.049878 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012561 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022296 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005819 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.049971 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.013309 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.024000 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005818 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.113103 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.049878 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.049971 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1507088 # number of writebacks -system.cpu.l2cache.writebacks::total 1507088 # number of writebacks -system.cpu.toL2Bus.snoop_filter.tot_requests 52384615 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 26512337 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.writebacks::writebacks 1507096 # number of writebacks +system.cpu.l2cache.writebacks::total 1507096 # number of writebacks +system.cpu.toL2Bus.snoop_filter.tot_requests 52368206 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 26495860 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2694 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2694 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1229989 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23338507 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1229979 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23338583 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8916642 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 14265273 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2689328 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 51131 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 8918956 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 14265255 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2687100 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 34570 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 51132 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2516995 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2516995 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 14265790 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7842728 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 34571 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2516977 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2516977 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 14265772 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7842832 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 1246772 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateResp 1246772 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42883103 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35055544 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42883049 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35022680 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758208 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548412 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 80245267 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1826160532 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1233877030 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548392 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 80212329 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1826158228 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234030630 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 3069264042 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1957594 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 103278016 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 55015054 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.010836 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103531 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 3069415258 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1762518 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 96494656 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 54803543 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.010878 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103729 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 54418911 98.92% 98.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 596143 1.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 54207383 98.91% 98.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 596160 1.09% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 55015054 # Request fanout histogram -system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.snoop_fanout::total 54803543 # Request fanout histogram +system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 40242 # Transaction distribution system.iobus.trans_dist::ReadResp 40242 # Transaction distribution system.iobus.trans_dist::WriteReq 136515 # Transaction distribution @@ -675,13 +675,13 @@ system.iobus.pkt_size_system.realview.ide.dma::total 7334248 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 115459 # number of replacements system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13082113306009 # Cycle when the warmup percentage was hit. +system.iocache.tags.warmup_cycle 13082113307009 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy @@ -692,7 +692,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1039650 # Number of tag accesses system.iocache.tags.data_accesses 1039650 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses @@ -740,65 +740,71 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks -system.membus.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 3778694 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1875355 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 2861 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 76679 # Transaction distribution -system.membus.trans_dist::ReadResp 524962 # Transaction distribution +system.membus.trans_dist::ReadResp 524960 # Transaction distribution system.membus.trans_dist::WriteReq 33606 # Transaction distribution system.membus.trans_dist::WriteResp 33606 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1613719 # Transaction distribution -system.membus.trans_dist::CleanEvict 226329 # Transaction distribution -system.membus.trans_dist::UpgradeReq 40494 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1613727 # Transaction distribution +system.membus.trans_dist::CleanEvict 226320 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4445 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 40495 # Transaction distribution -system.membus.trans_dist::ReadExReq 827052 # Transaction distribution -system.membus.trans_dist::ReadExResp 827052 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 448283 # Transaction distribution -system.membus.trans_dist::InvalidateReq 658869 # Transaction distribution -system.membus.trans_dist::InvalidateResp 658869 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4446 # Transaction distribution +system.membus.trans_dist::ReadExReq 827049 # Transaction distribution +system.membus.trans_dist::ReadExResp 827049 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 448281 # Transaction distribution +system.membus.trans_dist::InvalidateReq 658871 # Transaction distribution +system.membus.trans_dist::InvalidateResp 658871 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5534331 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5663523 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5462226 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5591418 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346493 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 346493 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6010016 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5937911 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 177701792 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 177870842 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 177701984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 177871034 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 185261626 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 185261818 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3925032 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::samples 3888979 # Request fanout histogram +system.membus.snoop_fanout::mean 0.009406 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.096529 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3925032 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3852398 99.06% 99.06% # Request fanout histogram +system.membus.snoop_fanout::1 36581 0.94% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3925032 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.membus.snoop_fanout::total 3888979 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -841,28 +847,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index 99716a632..6d4993075 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -4,75 +4,75 @@ sim_seconds 47.296282 # Nu sim_ticks 47296281748500 # Number of ticks simulated final_tick 47296281748500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 717114 # Simulator instruction rate (inst/s) -host_op_rate 843581 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34713303168 # Simulator tick rate (ticks/s) -host_mem_usage 688104 # Number of bytes of host memory used -host_seconds 1362.48 # Real time elapsed on the host +host_inst_rate 890958 # Simulator instruction rate (inst/s) +host_op_rate 1048084 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43128593002 # Simulator tick rate (ticks/s) +host_mem_usage 697472 # Number of bytes of host memory used +host_seconds 1096.63 # Real time elapsed on the host sim_insts 977055082 # Number of instructions simulated sim_ops 1149364510 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 151424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 124352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3875572 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 35081800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 222336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 221312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2647048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 38747248 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 401984 # Number of bytes read from this memory -system.physmem.bytes_read::total 81473076 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3875572 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2647048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6522620 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 101454976 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 154816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4238644 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 35981768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 224128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 222976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3009416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 39414640 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 402560 # Number of bytes read from this memory +system.physmem.bytes_read::total 83777076 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4238644 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3009416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7248060 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 102370496 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 101475560 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2366 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1943 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 100963 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 548166 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3474 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 3458 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 41467 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 605442 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6281 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1313560 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1585234 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 102391080 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2002 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 106636 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 562228 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3502 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 3484 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 47129 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 615870 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6290 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1349560 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1599539 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1587808 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3202 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2629 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 81942 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 741745 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4701 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 4679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 55967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 819245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1722611 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 81942 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 55967 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 137910 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2145094 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1602113 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3273 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2709 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 89619 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 760774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4739 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 4714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 63629 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 833356 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8511 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1771325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 89619 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 63629 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 153248 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2164451 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2145529 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2145094 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3202 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2629 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 81942 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 742181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4701 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 4679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 55967 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 819245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3868140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2164886 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2164451 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3273 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2709 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 89619 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 761209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4739 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 4714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 63629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 833356 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3936211 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -332,11 +332,11 @@ system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 584096590 # Class of executed instruction system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 6248912 # number of replacements +system.cpu0.dcache.tags.replacements 6248914 # number of replacements system.cpu0.dcache.tags.tagsinuse 501.980044 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 171607959 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6249424 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.459804 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 171607957 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6249426 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.459795 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.980044 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.980430 # Average percentage of cache occupancy @@ -346,41 +346,41 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 199 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 362271537 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 362271537 # Number of data accesses +system.cpu0.dcache.tags.tag_accesses 362271539 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 362271539 # Number of data accesses system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.cpu0.dcache.ReadReq_hits::cpu0.data 86024172 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 86024172 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 80672636 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 80672636 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 80674063 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 80674063 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 216269 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 216269 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 261023 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 261023 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2087977 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 2087977 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2051999 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 2051999 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 166957831 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 166957831 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 167174100 # number of overall hits -system.cpu0.dcache.overall_hits::total 167174100 # number of overall hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 261006 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 261006 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2087975 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 2087975 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2051823 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 2051823 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 166959241 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 166959241 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 167175510 # number of overall hits +system.cpu0.dcache.overall_hits::total 167175510 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 3298422 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 3298422 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1479208 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1479208 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1477781 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1477781 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 769563 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 769563 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 824176 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 824176 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119749 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 119749 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 154638 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 154638 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5601806 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5601806 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6371369 # number of overall misses -system.cpu0.dcache.overall_misses::total 6371369 # number of overall misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 824193 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 824193 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119751 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 119751 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 154814 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 154814 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 5600396 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 5600396 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 6369959 # number of overall misses +system.cpu0.dcache.overall_misses::total 6369959 # number of overall misses system.cpu0.dcache.ReadReq_accesses::cpu0.data 89322594 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 89322594 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 82151844 # number of WriteReq accesses(hits+misses) @@ -399,34 +399,34 @@ system.cpu0.dcache.overall_accesses::cpu0.data 173545469 system.cpu0.dcache.overall_accesses::total 173545469 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036927 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.036927 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018006 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018006 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017988 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.017988 # miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.780623 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::total 0.780623 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.759470 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.759470 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054241 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054241 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.070079 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.070079 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032463 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.032463 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036713 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.036713 # miss rate for overall accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.759486 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.759486 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054242 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054242 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.070158 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.070158 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032455 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.032455 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036705 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.036705 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 6248912 # number of writebacks -system.cpu0.dcache.writebacks::total 6248912 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 6248914 # number of writebacks +system.cpu0.dcache.writebacks::total 6248914 # number of writebacks system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 5509619 # number of replacements +system.cpu0.icache.tags.replacements 5509624 # number of replacements system.cpu0.icache.tags.tagsinuse 511.989024 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 491225335 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5510131 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 89.149484 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 491225330 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5510136 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 89.149402 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 5759898000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989024 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy @@ -437,21 +437,21 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 248 system.cpu0.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 998981078 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 998981078 # Number of data accesses +system.cpu0.icache.tags.tag_accesses 998981083 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 998981083 # Number of data accesses system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 491225335 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 491225335 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 491225335 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 491225335 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 491225335 # number of overall hits -system.cpu0.icache.overall_hits::total 491225335 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5510136 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 5510136 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 5510136 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 5510136 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 5510136 # number of overall misses -system.cpu0.icache.overall_misses::total 5510136 # number of overall misses +system.cpu0.icache.ReadReq_hits::cpu0.inst 491225330 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 491225330 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 491225330 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 491225330 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 491225330 # number of overall hits +system.cpu0.icache.overall_hits::total 491225330 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 5510141 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 5510141 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 5510141 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 5510141 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 5510141 # number of overall misses +system.cpu0.icache.overall_misses::total 5510141 # number of overall misses system.cpu0.icache.ReadReq_accesses::cpu0.inst 496735471 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 496735471 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 496735471 # number of demand (read+write) accesses @@ -470,8 +470,8 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 5509619 # number of writebacks -system.cpu0.icache.writebacks::total 5509619 # number of writebacks +system.cpu0.icache.writebacks::writebacks 5509624 # number of writebacks +system.cpu0.icache.writebacks::total 5509624 # number of writebacks system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified @@ -480,193 +480,192 @@ system.cpu0.l2cache.prefetcher.pfInCache 0 # nu system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2653803 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16139.372932 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 15525451 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2669765 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.815287 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 2567589 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15706.944975 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 9429067 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2583246 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 3.650085 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 16063.015838 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 35.657747 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 40.699347 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.980409 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002176 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002484 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.985069 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 53 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15909 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 39 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1444 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4368 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5335 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4524 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003235 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.971008 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 395826781 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 395826781 # Number of data accesses +system.cpu0.l2cache.tags.occ_blocks::writebacks 15656.940594 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 27.364617 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 22.639763 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.955624 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001670 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001382 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.958676 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 57 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15600 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 41 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 421 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2091 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5339 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5411 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2338 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003479 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.952148 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 401859473 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 401859473 # Number of data accesses system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 296735 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 157755 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 454490 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 4439476 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 4439476 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 7317657 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 7317657 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 746 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 746 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 639086 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 639086 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5010934 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 5010934 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2954772 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 2954772 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 221315 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 221315 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 296735 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 157755 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 5010934 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3593858 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 9059282 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 296735 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 157755 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 5010934 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3593858 # number of overall hits -system.cpu0.l2cache.overall_hits::total 9059282 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11441 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8530 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 19971 # 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number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 474461 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4439476 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 4439476 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 7317657 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 7317657 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 139245 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 139245 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 154638 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 154638 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 287369 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 155522 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 442891 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 4441046 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 4441046 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 7316094 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 7316094 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 640560 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 640560 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5011469 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 5011469 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2961462 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 2961462 # number of ReadSharedReq hits +system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 222733 # number of InvalidateReq hits +system.cpu0.l2cache.InvalidateReq_hits::total 222733 # number of InvalidateReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 287369 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 155522 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 5011469 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3602022 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 9056382 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 287369 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 155522 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 5011469 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3602022 # number of overall hits +system.cpu0.l2cache.overall_hits::total 9056382 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 20057 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9858 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 29915 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 137835 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 137835 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154814 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 154814 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 699738 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 699738 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 498672 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 498672 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1226274 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 1226274 # number of ReadSharedReq misses +system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 601108 # number of InvalidateReq misses +system.cpu0.l2cache.InvalidateReq_misses::total 601108 # number of InvalidateReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 20057 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9858 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 498672 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1926012 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 2454599 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 20057 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9858 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 498672 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1926012 # number of overall misses +system.cpu0.l2cache.overall_misses::total 2454599 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 307426 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 165380 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 472806 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4441046 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 4441046 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 7316094 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 7316094 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 137835 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 137835 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 154814 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 154814 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1340298 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::total 1340298 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5510136 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 5510136 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4187734 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 4187734 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5510141 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 5510141 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4187736 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 4187736 # number of ReadSharedReq accesses(hits+misses) system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 823841 # number of InvalidateReq accesses(hits+misses) system.cpu0.l2cache.InvalidateReq_accesses::total 823841 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 308176 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 166285 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 5510136 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5528032 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 11512629 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 308176 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 166285 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 5510136 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5528032 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 11512629 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037125 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.051297 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.042092 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994643 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994643 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 307426 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 165380 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 5510141 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 5528034 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 11510981 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 307426 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 165380 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 5510141 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 5528034 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 11510981 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.065242 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.059608 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.063271 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.523176 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.523176 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090597 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090597 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.294422 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.294422 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.731362 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.731362 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037125 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.051297 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090597 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.349885 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.213101 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037125 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.051297 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090597 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.349885 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.213101 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.522076 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.522076 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090501 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090501 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.292825 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.292825 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.729641 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.729641 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.065242 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.059608 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090501 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.348408 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.213240 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.065242 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.059608 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090501 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.348408 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.213240 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.writebacks::writebacks 1559963 # number of writebacks -system.cpu0.l2cache.writebacks::total 1559963 # number of writebacks -system.cpu0.toL2Bus.snoop_filter.tot_requests 24176858 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12314856 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.l2cache.writebacks::writebacks 1552940 # number of writebacks +system.cpu0.l2cache.writebacks::total 1552940 # number of writebacks +system.cpu0.toL2Bus.snoop_filter.tot_requests 24175638 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12313629 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1398 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 1775409 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1775098 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 311 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 303605 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 303605 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.cpu0.toL2Bus.trans_dist::ReadReq 622617 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 10320487 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 10320494 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 33234 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 33234 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 4439476 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 7319055 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 139245 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 154638 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 293883 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 4441046 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 7317492 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 137835 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 154814 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 292649 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExReq 1340298 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExResp 1340298 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5510136 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4187734 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5510141 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4187736 # Transaction distribution system.cpu0.toL2Bus.trans_dist::InvalidateReq 823841 # Transaction distribution system.cpu0.toL2Bus.trans_dist::InvalidateResp 823841 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16616141 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19673024 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16616156 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19670562 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 364916 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 727936 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 37382017 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 705436820 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 753922812 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 37379570 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 705437460 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 753923068 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1459664 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2911744 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1463731040 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 6082125 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 101619328 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 30471409 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.066979 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.250027 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 1463731936 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 4670427 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 101174852 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 29058250 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.019576 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.138538 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 28430762 93.30% 93.30% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2040336 6.70% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 311 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 28489407 98.04% 98.04% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 568843 1.96% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 30471409 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 29058250 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -888,11 +887,11 @@ system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 565908654 # Class of executed instruction system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 5970882 # number of replacements +system.cpu1.dcache.tags.replacements 5970884 # number of replacements system.cpu1.dcache.tags.tagsinuse 423.354804 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 166384450 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5971393 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 27.863591 # Average number of references to valid blocks. +system.cpu1.dcache.tags.total_refs 166384448 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5971395 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.863581 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 8470277781000 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 423.354804 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.826865 # Average percentage of cache occupancy @@ -902,41 +901,41 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::0 180 system.cpu1.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 350957209 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 350957209 # Number of data accesses +system.cpu1.dcache.tags.tag_accesses 350957211 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 350957211 # Number of data accesses system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 84198599 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 84198599 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 77532107 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 77532107 # number of WriteReq hits +system.cpu1.dcache.ReadReq_hits::cpu1.data 84198598 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 84198598 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 77531561 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 77531561 # number of WriteReq hits system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187263 # number of SoftPFReq hits system.cpu1.dcache.SoftPFReq_hits::total 187263 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 64879 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 64879 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2055501 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 2055501 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2044925 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 2044925 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 161795585 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 161795585 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 161982848 # number of overall hits -system.cpu1.dcache.overall_hits::total 161982848 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3367289 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3367289 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1465578 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1465578 # number of WriteReq misses +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 64886 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 64886 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2055500 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 2055500 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2044725 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 2044725 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 161795045 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 161795045 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 161982308 # number of overall hits +system.cpu1.dcache.overall_hits::total 161982308 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3367290 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3367290 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1466124 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1466124 # number of WriteReq misses system.cpu1.dcache.SoftPFReq_misses::cpu1.data 793623 # number of SoftPFReq misses system.cpu1.dcache.SoftPFReq_misses::total 793623 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 433878 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 433878 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 147104 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 147104 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 156474 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 156474 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5266745 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5266745 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6060368 # number of overall misses -system.cpu1.dcache.overall_misses::total 6060368 # number of overall misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 433871 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 433871 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 147105 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 147105 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 156674 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 156674 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5267285 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5267285 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 6060908 # number of overall misses +system.cpu1.dcache.overall_misses::total 6060908 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 87565888 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 87565888 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 78997685 # number of WriteReq accesses(hits+misses) @@ -955,28 +954,28 @@ system.cpu1.dcache.overall_accesses::cpu1.data 168043216 system.cpu1.dcache.overall_accesses::total 168043216 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038454 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.038454 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018552 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018552 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018559 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018559 # miss rate for WriteReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.809088 # miss rate for SoftPFReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::total 0.809088 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.869919 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.869919 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066786 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066786 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071079 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071079 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031526 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031526 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036064 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.036064 # miss rate for overall accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.869905 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.869905 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066787 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066787 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071170 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071170 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031529 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031529 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036068 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.036068 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 5970882 # number of writebacks -system.cpu1.dcache.writebacks::total 5970882 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 5970884 # number of writebacks +system.cpu1.dcache.writebacks::total 5970884 # number of writebacks system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.cpu1.icache.tags.replacements 4768482 # number of replacements system.cpu1.icache.tags.tagsinuse 496.452247 # Cycle average of tags in use @@ -1035,193 +1034,191 @@ system.cpu1.l2cache.prefetcher.pfInCache 0 # nu system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 2262891 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13357.261726 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 14305129 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2278874 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 6.277279 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9829187815500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 13247.067066 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 51.785938 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 58.408722 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.808537 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003161 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003565 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.815263 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 91 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15892 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 53 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id +system.cpu1.l2cache.tags.replacements 2174770 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13105.960937 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 8815603 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2190453 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 4.024557 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 13068.855777 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 21.863128 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 15.242032 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.797660 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001334 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000930 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.799924 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 90 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15593 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 57 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1574 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6119 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4359 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3688 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005554 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.969971 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 363588050 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 363588050 # Number of data accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 246 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 2414 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7618 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3564 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1751 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005493 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.951721 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 369059783 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 369059783 # Number of data accesses system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 348760 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155429 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 504189 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 4050331 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 4050331 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 6688666 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 6688666 # number of WritebackClean hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1054 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1054 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 613437 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 613437 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4306709 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 4306709 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3087044 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 3087044 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 164780 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 164780 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 348760 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 155429 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4306709 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3700481 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8511379 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 348760 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 155429 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4306709 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3700481 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8511379 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12218 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9629 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 21847 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 143649 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 143649 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 156474 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 156474 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 707649 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 707649 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 462285 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 462285 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1220972 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 1220972 # number of ReadSharedReq misses -system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 268887 # number of InvalidateReq misses -system.cpu1.l2cache.InvalidateReq_misses::total 268887 # number of InvalidateReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12218 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9629 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 462285 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1928621 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 2412753 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12218 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9629 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 462285 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1928621 # number of overall misses -system.cpu1.l2cache.overall_misses::total 2412753 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 360978 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 165058 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 526036 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4050331 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 4050331 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 6688666 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 6688666 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 144703 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 144703 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 156474 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 156474 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 338101 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 153667 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 491768 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 4061526 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 4061526 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 6677473 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 6677473 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614785 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 614785 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4308825 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 4308825 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3093892 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 3093892 # number of ReadSharedReq hits +system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 164960 # number of InvalidateReq hits +system.cpu1.l2cache.InvalidateReq_hits::total 164960 # number of InvalidateReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 338101 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 153667 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 4308825 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3708677 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 8509270 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 338101 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 153667 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 4308825 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3708677 # number of overall hits +system.cpu1.l2cache.overall_hits::total 8509270 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 22355 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10972 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 33327 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 145242 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 145242 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 156674 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 156674 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 706301 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 706301 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 460169 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 460169 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1214126 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 1214126 # number of ReadSharedReq misses +system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 268707 # number of InvalidateReq misses +system.cpu1.l2cache.InvalidateReq_misses::total 268707 # number of InvalidateReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 22355 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10972 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 460169 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1920427 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 2413923 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 22355 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10972 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 460169 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1920427 # number of overall misses +system.cpu1.l2cache.overall_misses::total 2413923 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 360456 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 164639 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 525095 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4061526 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 4061526 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 6677473 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 6677473 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 145242 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 145242 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 156674 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 156674 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1321086 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 1321086 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4768994 # number of ReadCleanReq accesses(hits+misses) system.cpu1.l2cache.ReadCleanReq_accesses::total 4768994 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4308016 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 4308016 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4308018 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 4308018 # number of ReadSharedReq accesses(hits+misses) system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 433667 # number of InvalidateReq accesses(hits+misses) system.cpu1.l2cache.InvalidateReq_accesses::total 433667 # number of InvalidateReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 360978 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 165058 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 360456 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 164639 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.inst 4768994 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 5629102 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 10924132 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 360978 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 165058 # number of overall (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 5629104 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 10923193 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 360456 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 164639 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.inst 4768994 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 5629102 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 10924132 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.033847 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.058337 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.041531 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.992716 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.992716 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 5629104 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 10923193 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.062019 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.066643 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.063469 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.535657 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.535657 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.096936 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.096936 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.283419 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.283419 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.620031 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.620031 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.033847 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.058337 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.096936 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.342616 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.220865 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.033847 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.058337 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.096936 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.342616 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.220865 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.534637 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.534637 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.096492 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.096492 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.281829 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.281829 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.619616 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.619616 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.062019 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.066643 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.096492 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.341160 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.220991 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.062019 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.066643 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.096492 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.341160 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.220991 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.writebacks::writebacks 1200117 # number of writebacks -system.cpu1.l2cache.writebacks::total 1200117 # number of writebacks -system.cpu1.toL2Bus.snoop_filter.tot_requests 22145801 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11314039 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.l2cache.writebacks::writebacks 1197912 # number of writebacks +system.cpu1.l2cache.writebacks::total 1197912 # number of writebacks +system.cpu1.toL2Bus.snoop_filter.tot_requests 22146544 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11314780 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 367 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 1748963 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1748793 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 170 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 285761 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 285759 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.cpu1.toL2Bus.trans_dist::ReadReq 607661 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9684671 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9684673 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 5564 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 5564 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4050331 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 6689033 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 144703 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 156474 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 301177 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4061526 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 6677840 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 145242 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 156674 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 301916 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 1321086 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 1321086 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4768994 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4308016 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4308018 # Transaction distribution system.cpu1.toL2Bus.trans_dist::InvalidateReq 433667 # Transaction distribution system.cpu1.toL2Bus.trans_dist::InvalidateResp 433667 # Transaction distribution system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14306730 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18721524 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18723008 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 366766 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 836674 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 34231694 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 34233178 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 610398984 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 742432303 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 742432559 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1467064 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3346696 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1357645047 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5675394 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 79399936 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 28001988 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.072258 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.258938 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size::total 1357645303 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4277162 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 79243712 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 26604267 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.021049 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.143548 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 25978793 92.77% 92.77% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2023025 7.22% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 170 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 26044274 97.90% 97.90% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 559991 2.10% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 2 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 28001988 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 26604267 # Request fanout histogram system.iobus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 40301 # Transaction distribution system.iobus.trans_dist::ReadResp 40301 # Transaction distribution @@ -1331,263 +1328,263 @@ system.iocache.avg_blocked_cycles::no_targets nan system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1774395 # number of replacements -system.l2c.tags.tagsinuse 63409.930559 # Cycle average of tags in use -system.l2c.tags.total_refs 4611925 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1833378 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.515534 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 514828500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 34658.678488 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 33.446161 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 43.299197 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3299.237288 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 7180.746684 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 272.688902 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 432.688870 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2834.364418 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 14654.780551 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.528849 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000510 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000661 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.050342 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.109569 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004161 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.006602 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.043249 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.223614 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.967559 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 232 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 58751 # Occupied blocks per task id +system.l2c.tags.replacements 1924793 # number of replacements +system.l2c.tags.tagsinuse 65250.197909 # Cycle average of tags in use +system.l2c.tags.total_refs 5713780 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1986359 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.876509 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 477350500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 10662.392220 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 41.728586 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 44.787257 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3175.849688 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 15990.343630 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 362.595804 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 421.087250 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2804.760651 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 31746.652822 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.162695 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000637 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000683 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.048460 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.243993 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005533 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.006425 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.042797 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.484415 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995639 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 224 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 61342 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 231 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 463 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3223 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5259 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 49760 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003540 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.896469 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 73267769 # Number of tag accesses -system.l2c.tags.data_accesses 73267769 # Number of data accesses +system.l2c.tags.age_task_id_blocks_1023::4 223 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3566 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4579 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52911 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.003418 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.936005 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 71904156 # Number of tag accesses +system.l2c.tags.data_accesses 71904156 # Number of data accesses system.l2c.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2760080 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2760080 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 17858 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 15288 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 33146 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2554 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 2409 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 4963 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 196672 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 175397 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 372069 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6428 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4634 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 441340 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 728132 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5456 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3654 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 420919 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 680845 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2291408 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 115975 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 102728 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 218703 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6428 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4634 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 441340 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 924804 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5456 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3654 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 420919 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 856242 # number of demand (read+write) hits -system.l2c.demand_hits::total 2663477 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6428 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4634 # number of overall hits -system.l2c.overall_hits::cpu0.inst 441340 # number of overall hits -system.l2c.overall_hits::cpu0.data 924804 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5456 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3654 # number of overall hits -system.l2c.overall_hits::cpu1.inst 420919 # number of overall hits -system.l2c.overall_hits::cpu1.data 856242 # number of overall hits -system.l2c.overall_hits::total 2663477 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 65292 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 60363 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 125655 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 6568 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 6268 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 12836 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 377580 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 423134 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 800714 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2366 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1943 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 57862 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 180178 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3474 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3458 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 41366 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 189464 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 480111 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 478573 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 160244 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 638817 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2366 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1943 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 57862 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 557758 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3474 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 3458 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 41366 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 612598 # number of demand (read+write) misses -system.l2c.demand_misses::total 1280825 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2366 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1943 # number of overall misses -system.l2c.overall_misses::cpu0.inst 57862 # number of overall misses -system.l2c.overall_misses::cpu0.data 557758 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3474 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 3458 # number of overall misses -system.l2c.overall_misses::cpu1.inst 41366 # number of overall misses -system.l2c.overall_misses::cpu1.data 612598 # number of overall misses -system.l2c.overall_misses::total 1280825 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 2760080 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 2760080 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 83150 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 75651 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 158801 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 9122 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 8677 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 17799 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 574252 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 598531 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 1172783 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8794 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6577 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 499202 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 908310 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8930 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7112 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 462285 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 870309 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 2771519 # number of ReadSharedReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu0.data 594548 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu1.data 262972 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::total 857520 # number of InvalidateReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8794 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6577 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 499202 # 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number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 498672 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1471429 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 15607 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7581 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 460169 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 1458864 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3934357 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 14787 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 7248 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 498672 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1471429 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 15607 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7581 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 460169 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 1458864 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3934357 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.266871 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.330367 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.297609 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.046551 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.093533 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.069467 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.651263 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.704095 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.678234 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.163590 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.276214 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.127408 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.213190 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.224386 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.459570 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.102197 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.229313 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.184919 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.780202 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.567734 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.714976 # miss rate for InvalidateReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.163590 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.276214 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.127408 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.383513 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.224386 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.459570 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.102197 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.423497 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.331466 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.163590 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.276214 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.127408 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.383513 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.224386 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.459570 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.102197 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.423497 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.331466 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 1478540 # number of writebacks -system.l2c.writebacks::total 1478540 # number of writebacks -system.membus.snoop_filter.tot_requests 4495065 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2597713 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3483 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.writebacks::writebacks 1492845 # number of writebacks +system.l2c.writebacks::total 1492845 # number of writebacks +system.membus.snoop_filter.tot_requests 4436915 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2508187 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3478 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 82130 # Transaction distribution -system.membus.trans_dist::ReadResp 571159 # Transaction distribution +system.membus.trans_dist::ReadResp 602460 # Transaction distribution system.membus.trans_dist::WriteReq 38798 # Transaction distribution system.membus.trans_dist::WriteResp 38798 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1585234 # Transaction distribution -system.membus.trans_dist::CleanEvict 247687 # Transaction distribution -system.membus.trans_dist::UpgradeReq 337993 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 306149 # Transaction distribution -system.membus.trans_dist::UpgradeResp 159131 # Transaction distribution -system.membus.trans_dist::ReadExReq 787924 # Transaction distribution -system.membus.trans_dist::ReadExResp 784573 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 489029 # Transaction distribution -system.membus.trans_dist::InvalidateReq 741049 # Transaction distribution -system.membus.trans_dist::InvalidateResp 741049 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1599539 # Transaction distribution +system.membus.trans_dist::CleanEvict 267122 # Transaction distribution +system.membus.trans_dist::UpgradeReq 245150 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 295293 # Transaction distribution +system.membus.trans_dist::UpgradeResp 53835 # Transaction distribution +system.membus.trans_dist::ReadExReq 792754 # Transaction distribution +system.membus.trans_dist::ReadExResp 789263 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 520330 # Transaction distribution +system.membus.trans_dist::InvalidateReq 716726 # Transaction distribution +system.membus.trans_dist::InvalidateResp 716726 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27542 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6413605 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6563815 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6261826 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 6412036 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346888 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 346888 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6910703 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6758924 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155683 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55084 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 175760092 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 175971063 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 178979036 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 179190007 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7399168 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 7399168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 183370231 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 186589175 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 4615993 # Request fanout histogram -system.membus.snoop_fanout::mean 0.007281 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.085020 # Request fanout histogram +system.membus.snoop_fanout::samples 4557842 # Request fanout histogram +system.membus.snoop_fanout::mean 0.007340 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.085359 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4582382 99.27% 99.27% # Request fanout histogram -system.membus.snoop_fanout::1 33611 0.73% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4524387 99.27% 99.27% # Request fanout histogram +system.membus.snoop_fanout::1 33455 0.73% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4615993 # Request fanout histogram +system.membus.snoop_fanout::total 4557842 # Request fanout histogram system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states @@ -1668,45 +1665,45 @@ system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 11098491 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5714084 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1638499 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 134977 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 121387 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 13590 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 11075061 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5706480 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1648775 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 269190 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 248390 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 20800 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 82132 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3539371 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3544615 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 38798 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 38798 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 2760080 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2007636 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 350499 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 311112 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 661611 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1354403 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1354403 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 3457239 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 857520 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 857520 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9497179 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8173943 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17671122 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 255360528 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 229634423 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 484994951 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1809010 # Total snoops (count) -system.toL2Bus.snoopTraffic 94667072 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 13026748 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.284748 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.453600 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 2750852 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1991304 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 351511 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 311488 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 662999 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1351623 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1351623 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3462483 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 855797 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 855797 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9483041 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8166779 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17649820 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 254997904 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 229564151 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 484562055 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1959256 # Total snoops (count) +system.toL2Bus.snoopTraffic 95582592 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 13153559 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.293824 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.458971 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 9330997 71.63% 71.63% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3682161 28.27% 99.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 13590 0.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 9309527 70.78% 70.78% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3823232 29.07% 99.84% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 20800 0.16% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 13026748 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 13153559 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt index e11d9e780..8ece6948a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt @@ -1,58 +1,58 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 51.111167 # Number of seconds simulated -sim_ticks 51111167192000 # Number of ticks simulated -final_tick 51111167192000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 51111167268500 # Number of ticks simulated +final_tick 51111167268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 779536 # Simulator instruction rate (inst/s) -host_op_rate 916124 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40565130498 # Simulator tick rate (ticks/s) -host_mem_usage 670816 # Number of bytes of host memory used -host_seconds 1259.98 # Real time elapsed on the host -sim_insts 982198638 # Number of instructions simulated -sim_ops 1154296340 # Number of ops (including micro ops) simulated +host_inst_rate 937025 # Simulator instruction rate (inst/s) +host_op_rate 1101207 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48760450215 # Simulator tick rate (ticks/s) +host_mem_usage 680056 # Number of bytes of host memory used +host_seconds 1048.21 # Real time elapsed on the host +sim_insts 982198023 # Number of instructions simulated +sim_ops 1154295627 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5484148 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 74913608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5483444 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 74913992 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory -system.physmem.bytes_read::total 81622588 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5484148 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5484148 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103278016 # Number of bytes written to this memory +system.physmem.bytes_read::total 81622268 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5483444 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5483444 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103278528 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103298596 # Number of bytes written to this memory +system.physmem.bytes_written::total 103299108 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 6476 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5837 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 126097 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1170538 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 126086 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1170544 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1315773 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1613719 # Number of write requests responded to by this memory +system.physmem.num_reads::total 1315768 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1613727 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1616292 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1616300 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 8109 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 7309 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 107298 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1465699 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 107285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1465707 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1596962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 107298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 107298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2020655 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1596956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 107285 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107285 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2020665 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2021057 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2020655 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2021067 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2020665 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 8109 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 7309 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 107298 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1466102 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 107285 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1466110 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3618019 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.physmem.bw_total::total 3618023 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -69,9 +69,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -79,7 +79,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -109,30 +109,30 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 266586 # Table walker walks requested -system.cpu.dtb.walker.walksLong 266586 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walkWaitTime::samples 266586 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 266586 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 266586 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 266581 # Table walker walks requested +system.cpu.dtb.walker.walksLong 266581 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walkWaitTime::samples 266581 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 266581 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 266581 # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution system.cpu.dtb.walker.walkPageSizes::4K 204774 89.35% 89.35% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 24416 10.65% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 229190 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 266586 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::2M 24411 10.65% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 229185 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 266581 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 266586 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 229190 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 266581 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 229185 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 229190 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 495776 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 229185 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 495766 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 183544097 # DTB read hits -system.cpu.dtb.read_misses 195348 # DTB read misses -system.cpu.dtb.write_hits 167774773 # DTB write hits +system.cpu.dtb.read_hits 183543984 # DTB read hits +system.cpu.dtb.read_misses 195343 # DTB read misses +system.cpu.dtb.write_hits 167774645 # DTB write hits system.cpu.dtb.write_misses 71238 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -140,16 +140,16 @@ system.cpu.dtb.flush_tlb_mva_asid 49771 # Nu system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 82439 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 9079 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 9074 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 183739445 # DTB read accesses -system.cpu.dtb.write_accesses 167846011 # DTB write accesses +system.cpu.dtb.read_accesses 183739327 # DTB read accesses +system.cpu.dtb.write_accesses 167845883 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 351318870 # DTB hits -system.cpu.dtb.misses 266586 # DTB misses -system.cpu.dtb.accesses 351585456 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 351318629 # DTB hits +system.cpu.dtb.misses 266581 # DTB misses +system.cpu.dtb.accesses 351585210 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -179,7 +179,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 126834 # Table walker walks requested system.cpu.itb.walker.walksLong 126834 # Table walker walks initiated with long descriptors system.cpu.itb.walker.walkWaitTime::samples 126834 # Table walker wait (enqueue to first request) latency @@ -198,7 +198,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114696 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 114696 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 241530 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 982675484 # ITB inst hits +system.cpu.itb.inst_hits 982674869 # ITB inst hits system.cpu.itb.inst_misses 126834 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -215,14 +215,14 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 982802318 # ITB inst accesses -system.cpu.itb.hits 982675484 # DTB hits +system.cpu.itb.inst_accesses 982801703 # ITB inst accesses +system.cpu.itb.hits 982674869 # DTB hits system.cpu.itb.misses 126834 # DTB misses -system.cpu.itb.accesses 982802318 # DTB accesses +system.cpu.itb.accesses 982801703 # DTB accesses system.cpu.numPwrStateTransitions 33550 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 16775 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3012440883.104620 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 59942517995.825706 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3012440908.824083 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 59942517661.771744 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 7454 44.44% 44.44% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 9286 55.36% 99.79% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state @@ -235,40 +235,40 @@ system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.89% system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 1988782948204 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 1988782931704 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 16775 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 577471377920 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50533695814080 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 102222351160 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 577471022976 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50533696245524 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 102222351313 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed -system.cpu.committedInsts 982198638 # Number of instructions committed -system.cpu.committedOps 1154296340 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1057877800 # Number of integer alu accesses +system.cpu.committedInsts 982198023 # Number of instructions committed +system.cpu.committedOps 1154295627 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1057877135 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 881349 # Number of float alu accesses -system.cpu.num_func_calls 56833909 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 151622723 # number of instructions that are conditional controls -system.cpu.num_int_insts 1057877800 # number of integer instructions +system.cpu.num_func_calls 56833843 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 151622640 # number of instructions that are conditional controls +system.cpu.num_int_insts 1057877135 # number of integer instructions system.cpu.num_fp_insts 881349 # number of float instructions -system.cpu.num_int_register_reads 1560754548 # number of times the integer registers were read -system.cpu.num_int_register_writes 840513636 # number of times the integer registers were written +system.cpu.num_int_register_reads 1560753668 # number of times the integer registers were read +system.cpu.num_int_register_writes 840513151 # number of times the integer registers were written system.cpu.num_fp_register_reads 1419767 # number of times the floating registers were read system.cpu.num_fp_register_writes 748560 # number of times the floating registers were written -system.cpu.num_cc_register_reads 264017562 # number of times the CC registers were read -system.cpu.num_cc_register_writes 263439787 # number of times the CC registers were written -system.cpu.num_mem_refs 351538306 # number of memory refs -system.cpu.num_load_insts 183711405 # Number of load instructions -system.cpu.num_store_insts 167826901 # Number of store instructions -system.cpu.num_idle_cycles 101067408214.617065 # Number of idle cycles -system.cpu.num_busy_cycles 1154942945.382940 # Number of busy cycles +system.cpu.num_cc_register_reads 264017457 # number of times the CC registers were read +system.cpu.num_cc_register_writes 263439679 # number of times the CC registers were written +system.cpu.num_mem_refs 351538055 # number of memory refs +system.cpu.num_load_insts 183711282 # Number of load instructions +system.cpu.num_store_insts 167826773 # Number of store instructions +system.cpu.num_idle_cycles 101067409077.505173 # Number of idle cycles +system.cpu.num_busy_cycles 1154942235.494823 # Number of busy cycles system.cpu.not_idle_fraction 0.011298 # Percentage of non-idle cycles system.cpu.idle_fraction 0.988702 # Percentage of idle cycles -system.cpu.Branches 219532347 # Number of branches fetched +system.cpu.Branches 219532189 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 800829907 69.34% 69.34% # Class of executed instruction -system.cpu.op_class::IntMult 2354386 0.20% 69.54% # Class of executed instruction +system.cpu.op_class::IntAlu 800829443 69.34% 69.34% # Class of executed instruction +system.cpu.op_class::IntMult 2354388 0.20% 69.54% # Class of executed instruction system.cpu.op_class::IntDiv 100543 0.01% 69.55% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction @@ -296,17 +296,17 @@ system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.56% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::MemRead 183711405 15.91% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 167826901 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 183711282 15.91% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 167826773 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1154931007 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 11605970 # number of replacements +system.cpu.op_class::total 1154930294 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 11606056 # number of replacements system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 339855114 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11606482 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.281492 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 339854782 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11606568 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.281247 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy @@ -316,87 +316,87 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 199 system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1417452931 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1417452931 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 171110382 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 171110382 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 159073547 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 159073547 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 424481 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 424481 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 1417452033 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1417452033 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 171110167 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 171110167 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 159090000 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 159090000 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 424478 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 424478 # number of SoftPFReq hits system.cpu.dcache.WriteLineReq_hits::cpu.data 336283 # number of WriteLineReq hits system.cpu.dcache.WriteLineReq_hits::total 336283 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303643 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4303643 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4555646 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4555646 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 330520212 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 330520212 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 330944693 # number of overall hits -system.cpu.dcache.overall_hits::total 330944693 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6002738 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6002738 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2568126 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2568126 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1586184 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1586184 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303639 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4303639 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4555644 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4555644 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 330536450 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 330536450 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 330960928 # number of overall hits +system.cpu.dcache.overall_hits::total 330960928 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6002834 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6002834 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2551547 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2551547 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1586190 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1586190 # number of SoftPFReq misses system.cpu.dcache.WriteLineReq_misses::cpu.data 1246772 # number of WriteLineReq misses system.cpu.dcache.WriteLineReq_misses::total 1246772 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 253806 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 253806 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 253808 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 253808 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 9817636 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9817636 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 11403820 # number of overall misses -system.cpu.dcache.overall_misses::total 11403820 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 177113120 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 177113120 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 161641673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 161641673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010665 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2010665 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9801153 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9801153 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 11387343 # number of overall misses +system.cpu.dcache.overall_misses::total 11387343 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 177113001 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 177113001 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 161641547 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 161641547 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010668 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2010668 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583055 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_accesses::total 1583055 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557449 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4557449 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555647 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4555647 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 340337848 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 340337848 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 342348513 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 342348513 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033892 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.033892 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015888 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015888 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788885 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.788885 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557447 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4557447 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555645 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4555645 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 340337603 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 340337603 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 342348271 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 342348271 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033893 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.033893 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015785 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015785 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788887 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.788887 # miss rate for SoftPFReq accesses system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787573 # miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_miss_rate::total 0.787573 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055690 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055690 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055691 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055691 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.028847 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.028847 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.033311 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.033311 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.028798 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.028798 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.033262 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.033262 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 8916642 # number of writebacks -system.cpu.dcache.writebacks::total 8916642 # number of writebacks -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 14265273 # number of replacements +system.cpu.dcache.writebacks::writebacks 8918956 # number of writebacks +system.cpu.dcache.writebacks::total 8918956 # number of writebacks +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 14265255 # number of replacements system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 968524390 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 14265785 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.891419 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 968523793 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 14265767 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.891463 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 6061932500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy @@ -406,27 +406,27 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 184 system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 997055970 # Number of tag accesses -system.cpu.icache.tags.data_accesses 997055970 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 968524390 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 968524390 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 968524390 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 968524390 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 968524390 # number of overall hits -system.cpu.icache.overall_hits::total 968524390 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14265790 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14265790 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14265790 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14265790 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14265790 # number of overall misses -system.cpu.icache.overall_misses::total 14265790 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 982790180 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 982790180 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 982790180 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 982790180 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 982790180 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 982790180 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 997055337 # Number of tag accesses +system.cpu.icache.tags.data_accesses 997055337 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 968523793 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 968523793 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 968523793 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 968523793 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 968523793 # number of overall hits +system.cpu.icache.overall_hits::total 968523793 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14265772 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14265772 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14265772 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14265772 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14265772 # number of overall misses +system.cpu.icache.overall_misses::total 14265772 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 982789565 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 982789565 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 982789565 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 982789565 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 982789565 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 982789565 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014516 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.014516 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.014516 # miss rate for demand accesses @@ -439,200 +439,200 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 14265273 # number of writebacks -system.cpu.icache.writebacks::total 14265273 # number of writebacks -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.cpu.icache.writebacks::writebacks 14265255 # number of writebacks +system.cpu.icache.writebacks::total 14265255 # number of writebacks +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1725823 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65319.568119 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 46895862 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1788839 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 26.215809 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37200.621218 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 312.625793 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 449.901085 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6075.914096 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 21280.505928 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.567636 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004770 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006865 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.092711 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.324715 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996698 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 317 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62699 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 317 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 608 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2778 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4924 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54253 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004837 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956711 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 425623617 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 425623617 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 509088 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255953 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 765041 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 8916642 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 8916642 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 14263696 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 14263696 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 11204 # 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Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 9615.361386 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 436.090806 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 495.840367 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6075.388739 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48781.220619 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.146719 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006654 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007566 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.092703 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.744342 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997984 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 373 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 62703 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 373 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1444 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5122 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55698 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.005692 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956772 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 422564531 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 422564531 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 480106 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 237369 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 717475 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 8918956 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 8918956 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 14263678 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 14263678 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 30692 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 30692 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1689371 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1689371 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14182774 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 14182774 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7498712 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 7498712 # number of ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 694558 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 694558 # number of InvalidateReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 480106 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 237369 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 14182774 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 9188083 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 24088332 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 480106 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 237369 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 14182774 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 9188083 # number of overall hits +system.cpu.l2cache.overall_hits::total 24088332 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6476 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5837 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 12313 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 39927 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 39927 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 3878 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 3878 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 827609 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 827609 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83009 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 83009 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344111 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 344111 # number of ReadSharedReq misses -system.cpu.l2cache.InvalidateReq_misses::cpu.data 552212 # number of InvalidateReq misses -system.cpu.l2cache.InvalidateReq_misses::total 552212 # number of InvalidateReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 827606 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 827606 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 82998 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 82998 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344120 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 344120 # number of ReadSharedReq misses +system.cpu.l2cache.InvalidateReq_misses::cpu.data 552214 # number of InvalidateReq misses +system.cpu.l2cache.InvalidateReq_misses::total 552214 # number of InvalidateReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 6476 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5837 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 83009 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1171720 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1267042 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 82998 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1171726 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1267037 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 6476 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5837 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 83009 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1171720 # number of overall misses -system.cpu.l2cache.overall_misses::total 1267042 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 515564 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261790 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 777354 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 8916642 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 8916642 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 14263696 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 14263696 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51131 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 51131 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.inst 82998 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1171726 # number of overall misses +system.cpu.l2cache.overall_misses::total 1267037 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 486582 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 243206 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 729788 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 8918956 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 8918956 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 14263678 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 14263678 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 34570 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 34570 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2516995 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2516995 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14265790 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 14265790 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7842728 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7842728 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2516977 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2516977 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14265772 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 14265772 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7842832 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 7842832 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1246772 # number of InvalidateReq accesses(hits+misses) system.cpu.l2cache.InvalidateReq_accesses::total 1246772 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 515564 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 261790 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 14265790 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 10359723 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 25402867 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 515564 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 261790 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 14265790 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 10359723 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 25402867 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012561 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022296 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015840 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780877 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780877 # miss rate for UpgradeReq accesses +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 486582 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 243206 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 14265772 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 10359809 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 25355369 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 486582 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 243206 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 14265772 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 10359809 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 25355369 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.013309 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.024000 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016872 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.112178 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.112178 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328808 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.328808 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005819 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005819 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043876 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043876 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442913 # miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442913 # miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012561 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022296 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005819 # miss rate for demand accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328810 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.328810 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005818 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005818 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043877 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043877 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442915 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442915 # miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.013309 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.024000 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005818 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.113103 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.049878 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012561 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022296 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005819 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.049971 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.013309 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.024000 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005818 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.113103 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.049878 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.049971 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1507088 # number of writebacks -system.cpu.l2cache.writebacks::total 1507088 # number of writebacks -system.cpu.toL2Bus.snoop_filter.tot_requests 52384615 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 26512337 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.writebacks::writebacks 1507096 # number of writebacks +system.cpu.l2cache.writebacks::total 1507096 # number of writebacks +system.cpu.toL2Bus.snoop_filter.tot_requests 52368206 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 26495860 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2694 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2694 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1229989 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23338507 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1229979 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23338583 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8916642 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 14265273 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2689328 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 51131 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 8918956 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 14265255 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2687100 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 34570 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 51132 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2516995 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2516995 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 14265790 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7842728 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 34571 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2516977 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2516977 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 14265772 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7842832 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 1246772 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateResp 1246772 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42883103 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35055544 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42883049 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35022680 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758208 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548412 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 80245267 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1826160532 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1233877030 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548392 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 80212329 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1826158228 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234030630 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 3069264042 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1957594 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 103278016 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 55015054 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.010836 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103531 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 3069415258 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1762518 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 96494656 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 54803543 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.010878 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103729 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 54418911 98.92% 98.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 596143 1.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 54207383 98.91% 98.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 596160 1.09% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 55015054 # Request fanout histogram -system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.snoop_fanout::total 54803543 # Request fanout histogram +system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 40242 # Transaction distribution system.iobus.trans_dist::ReadResp 40242 # Transaction distribution system.iobus.trans_dist::WriteReq 136515 # Transaction distribution @@ -675,13 +675,13 @@ system.iobus.pkt_size_system.realview.ide.dma::total 7334248 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 115459 # number of replacements system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13082113306009 # Cycle when the warmup percentage was hit. +system.iocache.tags.warmup_cycle 13082113307009 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy @@ -692,7 +692,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1039650 # Number of tag accesses system.iocache.tags.data_accesses 1039650 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses @@ -740,65 +740,71 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks -system.membus.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 3778694 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1875355 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 2861 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 76679 # Transaction distribution -system.membus.trans_dist::ReadResp 524962 # Transaction distribution +system.membus.trans_dist::ReadResp 524960 # Transaction distribution system.membus.trans_dist::WriteReq 33606 # Transaction distribution system.membus.trans_dist::WriteResp 33606 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1613719 # Transaction distribution -system.membus.trans_dist::CleanEvict 226329 # Transaction distribution -system.membus.trans_dist::UpgradeReq 40494 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1613727 # Transaction distribution +system.membus.trans_dist::CleanEvict 226320 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4445 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 40495 # Transaction distribution -system.membus.trans_dist::ReadExReq 827052 # Transaction distribution -system.membus.trans_dist::ReadExResp 827052 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 448283 # Transaction distribution -system.membus.trans_dist::InvalidateReq 658869 # Transaction distribution -system.membus.trans_dist::InvalidateResp 658869 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4446 # Transaction distribution +system.membus.trans_dist::ReadExReq 827049 # Transaction distribution +system.membus.trans_dist::ReadExResp 827049 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 448281 # Transaction distribution +system.membus.trans_dist::InvalidateReq 658871 # Transaction distribution +system.membus.trans_dist::InvalidateResp 658871 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5534331 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5663523 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5462226 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5591418 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346493 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 346493 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6010016 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5937911 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 177701792 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 177870842 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 177701984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 177871034 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 185261626 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 185261818 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3925032 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::samples 3888979 # Request fanout histogram +system.membus.snoop_fanout::mean 0.009406 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.096529 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3925032 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3852398 99.06% 99.06% # Request fanout histogram +system.membus.snoop_fanout::1 36581 0.94% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3925032 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.membus.snoop_fanout::total 3888979 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -841,28 +847,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167192000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index 815a8f351..c73396a86 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.403575 # Number of seconds simulated -sim_ticks 47403574916500 # Number of ticks simulated -final_tick 47403574916500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.374315 # Number of seconds simulated +sim_ticks 47374315410500 # Number of ticks simulated +final_tick 47374315410500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 473223 # Simulator instruction rate (inst/s) -host_op_rate 556671 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25492174892 # Simulator tick rate (ticks/s) -host_mem_usage 749540 # Number of bytes of host memory used -host_seconds 1859.53 # Real time elapsed on the host -sim_insts 879974755 # Number of instructions simulated -sim_ops 1035148021 # Number of ops (including micro ops) simulated +host_inst_rate 573964 # Simulator instruction rate (inst/s) +host_op_rate 675116 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30496109280 # Simulator tick rate (ticks/s) +host_mem_usage 762100 # Number of bytes of host memory used +host_seconds 1553.45 # Real time elapsed on the host +sim_insts 891626325 # Number of instructions simulated +sim_ops 1048762579 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 121792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 126720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3082292 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 13718664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 15413504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 111872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 105344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2806840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 9358928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 11301824 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 428736 # Number of bytes read from this memory -system.physmem.bytes_read::total 56576516 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3082292 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2806840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5889132 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 75184384 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 107264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 103104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3762996 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 12951880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 13484096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 112000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 117056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2426936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 10199632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 12856576 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 431488 # Number of bytes read from this memory +system.physmem.bytes_read::total 56553028 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3762996 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2426936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6189932 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 74832448 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 75204968 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1903 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1980 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 88568 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 214367 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 240836 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1748 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1646 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 43945 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 146246 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 176591 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6699 # Number of read requests responded to by this memory -system.physmem.num_reads::total 924529 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1174756 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 74853032 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1676 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1611 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 99204 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 202386 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 210689 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1750 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1829 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 38009 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 159382 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 200884 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6742 # Number of read requests responded to by this memory +system.physmem.num_reads::total 924162 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1169257 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1177330 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2569 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2673 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 65022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 289401 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 325155 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2222 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 59212 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 197431 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 238417 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1193507 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 65022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 59212 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 124234 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1586049 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1171831 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2176 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 79431 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 273395 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 284629 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2364 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 51229 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 215299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 271383 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9108 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1193749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 79431 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 51229 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 130660 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1579600 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1586483 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1586049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2569 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 65022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 289836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 325155 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 59212 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 197431 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 238417 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2779990 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 924529 # Number of read requests accepted -system.physmem.writeReqs 1177330 # Number of write requests accepted -system.physmem.readBursts 924529 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1177330 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 59142848 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 27008 # Total number of bytes read from write queue -system.physmem.bytesWritten 75203008 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 56576516 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 75204968 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 422 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2259 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1580034 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1579600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 79431 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 273829 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 284629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2364 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 51229 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 215299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 271383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9108 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2773783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 924162 # Number of read requests accepted +system.physmem.writeReqs 1171831 # Number of write requests accepted +system.physmem.readBursts 924162 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1171831 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 59123712 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 22656 # Total number of bytes read from write queue +system.physmem.bytesWritten 74852544 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 56553028 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 74853032 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 354 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 51848 # Per bank write bursts -system.physmem.perBankRdBursts::1 60547 # Per bank write bursts -system.physmem.perBankRdBursts::2 52943 # Per bank write bursts -system.physmem.perBankRdBursts::3 59873 # Per bank write bursts -system.physmem.perBankRdBursts::4 53995 # Per bank write bursts -system.physmem.perBankRdBursts::5 59394 # Per bank write bursts -system.physmem.perBankRdBursts::6 55656 # Per bank write bursts -system.physmem.perBankRdBursts::7 56350 # Per bank write bursts -system.physmem.perBankRdBursts::8 47470 # Per bank write bursts -system.physmem.perBankRdBursts::9 98045 # Per bank write bursts -system.physmem.perBankRdBursts::10 51346 # Per bank write bursts -system.physmem.perBankRdBursts::11 58216 # Per bank write bursts -system.physmem.perBankRdBursts::12 52575 # Per bank write bursts -system.physmem.perBankRdBursts::13 60842 # Per bank write bursts -system.physmem.perBankRdBursts::14 50185 # Per bank write bursts -system.physmem.perBankRdBursts::15 54822 # Per bank write bursts -system.physmem.perBankWrBursts::0 69717 # Per bank write bursts -system.physmem.perBankWrBursts::1 76530 # Per bank write bursts -system.physmem.perBankWrBursts::2 71410 # Per bank write bursts -system.physmem.perBankWrBursts::3 77292 # Per bank write bursts -system.physmem.perBankWrBursts::4 71372 # Per bank write bursts -system.physmem.perBankWrBursts::5 75019 # Per bank write bursts -system.physmem.perBankWrBursts::6 75211 # Per bank write bursts -system.physmem.perBankWrBursts::7 75617 # Per bank write bursts -system.physmem.perBankWrBursts::8 67898 # Per bank write bursts -system.physmem.perBankWrBursts::9 76939 # Per bank write bursts -system.physmem.perBankWrBursts::10 70016 # Per bank write bursts -system.physmem.perBankWrBursts::11 75357 # Per bank write bursts -system.physmem.perBankWrBursts::12 71664 # Per bank write bursts -system.physmem.perBankWrBursts::13 78615 # Per bank write bursts -system.physmem.perBankWrBursts::14 70257 # Per bank write bursts -system.physmem.perBankWrBursts::15 72133 # Per bank write bursts +system.physmem.perBankRdBursts::0 54791 # Per bank write bursts +system.physmem.perBankRdBursts::1 60963 # Per bank write bursts +system.physmem.perBankRdBursts::2 51680 # Per bank write bursts +system.physmem.perBankRdBursts::3 61600 # Per bank write bursts +system.physmem.perBankRdBursts::4 56399 # Per bank write bursts +system.physmem.perBankRdBursts::5 67623 # Per bank write bursts +system.physmem.perBankRdBursts::6 62592 # Per bank write bursts +system.physmem.perBankRdBursts::7 58195 # Per bank write bursts +system.physmem.perBankRdBursts::8 51047 # Per bank write bursts +system.physmem.perBankRdBursts::9 95684 # Per bank write bursts +system.physmem.perBankRdBursts::10 47816 # Per bank write bursts +system.physmem.perBankRdBursts::11 53141 # Per bank write bursts +system.physmem.perBankRdBursts::12 48535 # Per bank write bursts +system.physmem.perBankRdBursts::13 54663 # Per bank write bursts +system.physmem.perBankRdBursts::14 49130 # Per bank write bursts +system.physmem.perBankRdBursts::15 49949 # Per bank write bursts +system.physmem.perBankWrBursts::0 71660 # Per bank write bursts +system.physmem.perBankWrBursts::1 78743 # Per bank write bursts +system.physmem.perBankWrBursts::2 71851 # Per bank write bursts +system.physmem.perBankWrBursts::3 78616 # Per bank write bursts +system.physmem.perBankWrBursts::4 73485 # Per bank write bursts +system.physmem.perBankWrBursts::5 81529 # Per bank write bursts +system.physmem.perBankWrBursts::6 75635 # Per bank write bursts +system.physmem.perBankWrBursts::7 74455 # Per bank write bursts +system.physmem.perBankWrBursts::8 70456 # Per bank write bursts +system.physmem.perBankWrBursts::9 72917 # Per bank write bursts +system.physmem.perBankWrBursts::10 67611 # Per bank write bursts +system.physmem.perBankWrBursts::11 70918 # Per bank write bursts +system.physmem.perBankWrBursts::12 67621 # Per bank write bursts +system.physmem.perBankWrBursts::13 71486 # Per bank write bursts +system.physmem.perBankWrBursts::14 70570 # Per bank write bursts +system.physmem.perBankWrBursts::15 72018 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 33 # Number of times write queue was full causing retry -system.physmem.totGap 47403571626000 # Total gap between requests +system.physmem.numWrRetry 85 # Number of times write queue was full causing retry +system.physmem.totGap 47374312061000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 881304 # Read request sizes (log2) +system.physmem.readPktSize::6 880937 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1174756 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 659566 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 77579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33211 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 28414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 24996 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 21849 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 17731 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15667 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2476 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1265 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 800 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 630 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 261 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 87 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 57 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1169257 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 656925 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 77551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38628 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33370 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 28745 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 25204 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 22090 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 18063 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1283 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 912 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 744 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 565 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -189,169 +189,173 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 39858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 50403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 64323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 67039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 68725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 71220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 71835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 75432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 77625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 73262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 73463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 77885 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 70974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 65826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 63695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 98 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 970623 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 138.411655 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 95.318742 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 185.703174 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 665453 68.56% 68.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 189210 19.49% 88.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 42199 4.35% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 19114 1.97% 94.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13470 1.39% 95.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8660 0.89% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6031 0.62% 97.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4990 0.51% 97.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21496 2.21% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 970623 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60964 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 15.158028 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 130.577791 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60961 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 29578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 37673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 55472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 64054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 66659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 68456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 71033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 71567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 75072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 77359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 72847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 72784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 77929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 71715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 66943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 64345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2561 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 259 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 927168 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 144.500035 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 98.409552 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 191.008164 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 615708 66.41% 66.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 189300 20.42% 86.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 44500 4.80% 91.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20695 2.23% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14869 1.60% 95.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9173 0.99% 96.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6380 0.69% 97.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5518 0.60% 97.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21025 2.27% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 927168 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60983 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.148533 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 130.608088 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60979 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60964 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60964 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.274441 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.533375 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.742081 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 49066 80.48% 80.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 4709 7.72% 88.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 2977 4.88% 93.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1753 2.88% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 988 1.62% 97.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 316 0.52% 98.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 174 0.29% 98.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 124 0.20% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 67 0.11% 98.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 44 0.07% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 37 0.06% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 48 0.08% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 425 0.70% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 48 0.08% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 48 0.08% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 40 0.07% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 26 0.04% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 10 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 27 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60964 # Writes before turning the bus around for reads -system.physmem.totQLat 29056215697 # Total ticks spent queuing -system.physmem.totMemAccLat 46383221947 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4620535000 # Total ticks spent in databus transfers -system.physmem.avgQLat 31442.48 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 60983 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60983 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.178640 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.436589 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.785486 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 49393 80.99% 80.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 4571 7.50% 88.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 2800 4.59% 93.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1776 2.91% 95.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 1006 1.65% 97.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 308 0.51% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 149 0.24% 98.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 125 0.20% 98.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 64 0.10% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 38 0.06% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 29 0.05% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 41 0.07% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 435 0.71% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 54 0.09% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 52 0.09% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 40 0.07% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 33 0.05% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 5 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 5 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 5 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 4 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 9 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60983 # Writes before turning the bus around for reads +system.physmem.totQLat 30413749694 # Total ticks spent queuing +system.physmem.totMemAccLat 47735149694 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4619040000 # Total ticks spent in databus transfers +system.physmem.avgQLat 32922.15 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 50192.48 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 51672.15 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.59 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.59 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.95 # Average write queue length when enqueuing -system.physmem.readRowHits 688543 # Number of row buffer hits during reads -system.physmem.writeRowHits 439987 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 37.44 # Row buffer hit rate for writes -system.physmem.avgGap 22553164.43 # Average gap between requests -system.physmem.pageHitRate 53.76 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3707333280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2022850500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3514687800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3837248640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3096170747280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1188225117900 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27399839328750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31697317314150 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.669411 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45581711195731 # Time in different power states -system.physmem_0.memoryStateTime::REF 1582909380000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.27 # Average write queue length when enqueuing +system.physmem.readRowHits 683627 # Number of row buffer hits during reads +system.physmem.writeRowHits 482581 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.00 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.26 # Row buffer hit rate for writes +system.physmem.avgGap 22602323.61 # Average gap between requests +system.physmem.pageHitRate 55.71 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3700302480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2019014250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3695975400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3926705040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3094259578800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1192499073090 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27378533808750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31678634457810 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.688048 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45546210437205 # Time in different power states +system.physmem_0.memoryStateTime::REF 1581932300000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 238953890769 # Time in different power states +system.physmem_0.memoryStateTime::ACT 246167130795 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3630576600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1980969375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3693307800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3777055920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3096170747280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1193695955100 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27395040340500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31697988952575 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.683580 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45573641620138 # Time in different power states -system.physmem_1.memoryStateTime::REF 1582909380000 # Time in different power states +system.physmem_1.actEnergy 3308936400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1805471250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3509181000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3651784560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3094259578800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1178425765395 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27390878815500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31675839532905 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.629051 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45566794873385 # Time in different power states +system.physmem_1.memoryStateTime::REF 1581932300000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 247019106112 # Time in different power states +system.physmem_1.memoryStateTime::ACT 225582219115 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -378,17 +382,17 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1670 # Number of DMA write transactions. +system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1674 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -418,75 +422,73 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 114038 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 114038 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12642 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 85549 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 19 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 114019 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 0.228032 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 76.998938 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-2047 114018 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 114019 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 98210 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22487.465635 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 21018.091466 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 14315.982425 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 93486 95.19% 95.19% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3452 3.51% 98.70% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 155 0.16% 98.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 934 0.95% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 21 0.02% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 20 0.02% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 48 0.05% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 12 0.01% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 37 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 30 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 101108 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 101108 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9051 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76906 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 101094 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 101094 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 101094 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 85971 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 24170.842493 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 22339.898543 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 14600.032387 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 76182 88.61% 88.61% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 8727 10.15% 98.76% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 200 0.23% 99.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 718 0.84% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 29 0.03% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 15 0.02% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 34 0.04% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-262143 15 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 12 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 19 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-360447 11 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 98210 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 3576910072 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.522403 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -1868589580 -52.24% -52.24% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 5445499652 152.24% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 3576910072 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 85549 87.13% 87.13% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 12642 12.87% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 98191 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 114038 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 85971 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples -250064880 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.334382 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.471774 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -166447796 66.56% 66.56% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -83617084 33.44% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total -250064880 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 76906 89.47% 89.47% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 9051 10.53% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 85957 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 101108 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 114038 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 98191 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 101108 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85957 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 98191 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 212229 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85957 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 187065 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 86092375 # DTB read hits -system.cpu0.dtb.read_misses 87013 # DTB read misses -system.cpu0.dtb.write_hits 77928513 # DTB write hits -system.cpu0.dtb.write_misses 27025 # DTB write misses +system.cpu0.dtb.read_hits 84046306 # DTB read hits +system.cpu0.dtb.read_misses 73432 # DTB read misses +system.cpu0.dtb.write_hits 77237834 # DTB write hits +system.cpu0.dtb.write_misses 27676 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 38112 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 35922 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4351 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4635 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9561 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 86179388 # DTB read accesses -system.cpu0.dtb.write_accesses 77955538 # DTB write accesses +system.cpu0.dtb.perms_faults 9711 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 84119738 # DTB read accesses +system.cpu0.dtb.write_accesses 77265510 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 164020888 # DTB hits -system.cpu0.dtb.misses 114038 # DTB misses -system.cpu0.dtb.accesses 164134926 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 161284140 # DTB hits +system.cpu0.dtb.misses 101108 # DTB misses +system.cpu0.dtb.accesses 161385248 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -516,891 +518,888 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 57747 # Table walker walks requested -system.cpu0.itb.walker.walksLong 57747 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 561 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51498 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 57747 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 57747 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 57747 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 52059 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 25570.833093 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23301.899076 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 19704.068320 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 48075 92.35% 92.35% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 2753 5.29% 97.64% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 34 0.07% 97.70% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 1024 1.97% 99.67% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 15 0.03% 99.70% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.72% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 43 0.08% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 19 0.04% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 37 0.07% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 21 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 6 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 6 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::425984-458751 3 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-491519 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 52059 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 58460 # Table walker walks requested +system.cpu0.itb.walker.walksLong 58460 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 540 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52669 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 58460 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 58460 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 58460 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 53209 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 26190.982728 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 24044.890366 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 17871.734437 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 47169 88.65% 88.65% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 4943 9.29% 97.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 65 0.12% 98.06% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 859 1.61% 99.67% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 39 0.07% 99.75% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 17 0.03% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 47 0.09% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 13 0.02% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 25 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 20 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 53209 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples -282313796 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 -282313796 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total -282313796 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 51498 98.92% 98.92% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 561 1.08% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 52059 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 52669 98.99% 98.99% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 540 1.01% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 53209 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57747 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57747 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 58460 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 58460 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52059 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52059 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 109806 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 458544228 # ITB inst hits -system.cpu0.itb.inst_misses 57747 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 53209 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 53209 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 111669 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 449335815 # ITB inst hits +system.cpu0.itb.inst_misses 58460 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 26949 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 24946 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 458601975 # ITB inst accesses -system.cpu0.itb.hits 458544228 # DTB hits -system.cpu0.itb.misses 57747 # DTB misses -system.cpu0.itb.accesses 458601975 # DTB accesses -system.cpu0.numPwrStateTransitions 27516 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 13758 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 3404463734.886103 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 97180881292.374130 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3759 27.32% 27.32% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 9972 72.48% 99.80% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 11 0.08% 99.88% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 12 0.09% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 449394275 # ITB inst accesses +system.cpu0.itb.hits 449335815 # DTB hits +system.cpu0.itb.misses 58460 # DTB misses +system.cpu0.itb.accesses 449394275 # DTB accesses +system.cpu0.numPwrStateTransitions 8624 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 4312 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 10857440365.954313 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 156382311444.961365 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3059 70.94% 70.94% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 1229 28.50% 99.44% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 2 0.05% 99.49% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.05% 99.54% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.05% 99.58% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 1 0.02% 99.61% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.63% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.65% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.68% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 14 0.32% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 7033293879000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 13758 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 564962851937 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46838612064563 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 94807149833 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 7470353528320 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 4312 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 557032552505 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46817282857995 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 94748630821 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13758 # number of quiesce instructions executed -system.cpu0.committedInsts 458270897 # Number of instructions committed -system.cpu0.committedOps 538093671 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 494447989 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 420942 # Number of float alu accesses -system.cpu0.num_func_calls 27507374 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 69395953 # number of instructions that are conditional controls -system.cpu0.num_int_insts 494447989 # number of integer instructions -system.cpu0.num_fp_insts 420942 # number of float instructions -system.cpu0.num_int_register_reads 717601691 # number of times the integer registers were read -system.cpu0.num_int_register_writes 392303230 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 699105 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 312628 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 119518995 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 119177994 # number of times the CC registers were written -system.cpu0.num_mem_refs 164010919 # number of memory refs -system.cpu0.num_load_insts 86087147 # Number of load instructions -system.cpu0.num_store_insts 77923772 # Number of store instructions -system.cpu0.num_idle_cycles 93677224129.124023 # Number of idle cycles -system.cpu0.num_busy_cycles 1129925703.875976 # Number of busy cycles -system.cpu0.not_idle_fraction 0.011918 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.988082 # Percentage of idle cycles -system.cpu0.Branches 102213618 # Number of branches fetched -system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 373117768 69.30% 69.30% # Class of executed instruction -system.cpu0.op_class::IntMult 1177948 0.22% 69.52% # Class of executed instruction -system.cpu0.op_class::IntDiv 60910 0.01% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 42581 0.01% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::MemRead 86087147 15.99% 85.53% # Class of executed instruction -system.cpu0.op_class::MemWrite 77923772 14.47% 100.00% # Class of executed instruction +system.cpu0.kern.inst.quiesce 4312 # number of quiesce instructions executed +system.cpu0.committedInsts 449083110 # Number of instructions committed +system.cpu0.committedOps 528384419 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 485390643 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 507449 # Number of float alu accesses +system.cpu0.num_func_calls 26866500 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 68160489 # number of instructions that are conditional controls +system.cpu0.num_int_insts 485390643 # number of integer instructions +system.cpu0.num_fp_insts 507449 # number of float instructions +system.cpu0.num_int_register_reads 703891240 # number of times the integer registers were read +system.cpu0.num_int_register_writes 384865941 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 816779 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 435492 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 117650799 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 117386896 # number of times the CC registers were written +system.cpu0.num_mem_refs 161276211 # number of memory refs +system.cpu0.num_load_insts 84042257 # Number of load instructions +system.cpu0.num_store_insts 77233954 # Number of store instructions +system.cpu0.num_idle_cycles 93634565715.988022 # Number of idle cycles +system.cpu0.num_busy_cycles 1114065105.011976 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011758 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988242 # Percentage of idle cycles +system.cpu0.Branches 100200450 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 366086093 69.25% 69.25% # Class of executed instruction +system.cpu0.op_class::IntMult 1185979 0.22% 69.47% # Class of executed instruction +system.cpu0.op_class::IntDiv 59083 0.01% 69.48% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 72839 0.01% 69.49% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction +system.cpu0.op_class::MemRead 84042257 15.90% 85.39% # Class of executed instruction +system.cpu0.op_class::MemWrite 77233954 14.61% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 538410126 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 5755741 # number of replacements -system.cpu0.dcache.tags.tagsinuse 471.832715 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 158017240 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5756252 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.451411 # Average number of references to valid blocks. +system.cpu0.op_class::total 528680248 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 5566798 # number of replacements +system.cpu0.dcache.tags.tagsinuse 502.671926 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 155470196 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5567308 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.925560 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 4031081000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.832715 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.921548 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.921548 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 333769183 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 333769183 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 80089936 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 80089936 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 73524451 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 73524451 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 195750 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 195750 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 158273 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 158273 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1825906 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1825906 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1807959 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1807959 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 153772660 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 153772660 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 153968410 # number of overall hits -system.cpu0.dcache.overall_hits::total 153968410 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3122111 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3122111 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1430717 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1430717 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 657703 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 657703 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 783281 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 783281 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 173414 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 173414 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 190134 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 190134 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5336109 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5336109 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5993812 # number of overall misses -system.cpu0.dcache.overall_misses::total 5993812 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 46238724000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 46238724000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29544894000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 29544894000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25637315000 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 25637315000 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2487014500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2487014500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4740803500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4740803500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2810500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2810500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 101420933000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 101420933000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 101420933000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 101420933000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 83212047 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 83212047 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74955168 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 74955168 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 853453 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 853453 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 941554 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 941554 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1999320 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1999320 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1998093 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1998093 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 159108769 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 159108769 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 159962222 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 159962222 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037520 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037520 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019088 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.019088 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.770638 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.770638 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.831902 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.831902 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086736 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086736 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095158 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095158 # 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average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14341.486270 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24934.012328 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24934.012328 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.671926 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.981781 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.981781 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 419 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 328131694 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 328131694 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 78275725 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 78275725 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 72837974 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 72837974 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200143 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 200143 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 232092 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 232092 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1764306 # 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number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 28844482000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 28844482000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25694293000 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 25694293000 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2462602000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2462602000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4821620000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4821620000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2416000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2416000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 99036423000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 99036423000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 99036423000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 99036423000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 81249840 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 81249840 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 74250083 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 74250083 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 849997 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 849997 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1033762 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1033762 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1925464 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1925464 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1924313 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1924313 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 156533685 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 156533685 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 157383682 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 157383682 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036605 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036605 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019018 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.019018 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.764537 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.764537 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.775488 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.775488 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083698 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083698 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.105375 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.105375 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033142 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.033142 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037092 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.037092 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14961.643380 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14961.643380 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20426.526564 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20426.526564 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32050.959871 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32050.959871 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15280.668661 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15280.668661 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23778.177783 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23778.177783 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19006.533225 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19006.533225 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16920.939963 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 16920.939963 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19089.908738 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19089.908738 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16964.833528 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 16964.833528 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 5755741 # number of writebacks -system.cpu0.dcache.writebacks::total 5755741 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25545 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25545 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21233 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21233 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44607 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44607 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 46778 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 46778 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 46778 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 46778 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3096566 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3096566 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1409484 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1409484 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 656541 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 656541 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 783281 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 783281 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 128807 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 128807 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 190134 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 190134 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 5289331 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 5289331 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5945872 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5945872 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 27575 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 27575 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26540 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26540 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 54115 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 54115 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 42074729000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42074729000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27794776000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27794776000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13747691500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13747691500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24854034000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24854034000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1645535500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1645535500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4550721500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4550721500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2758500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2758500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 94723539000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 94723539000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 108471230500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 108471230500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5071681500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5071681500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5071681500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5071681500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037213 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037213 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018804 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018804 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.769276 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.769276 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.831902 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.831902 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064425 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064425 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095158 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095158 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033243 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.033243 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037170 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.037170 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13587.544719 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13587.544719 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19719.823709 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19719.823709 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20939.578031 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20939.578031 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31730.673922 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31730.673922 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12775.202435 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12775.202435 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23934.285819 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23934.285819 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5566798 # number of writebacks +system.cpu0.dcache.writebacks::total 5566798 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 29633 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 29633 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21518 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21518 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 45711 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 45711 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 51151 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 51151 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 51151 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 51151 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2944482 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2944482 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1390591 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1390591 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 648168 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 648168 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 801670 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 801670 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 115447 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 115447 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 202775 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 202775 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5136743 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5136743 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5784911 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5784911 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 21025 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 21025 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 22388 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 22388 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 43413 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 43413 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 40085054500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 40085054500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 26946583500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 26946583500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14957704500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14957704500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24892623000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24892623000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1575244000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1575244000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4618898000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4618898000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2363000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2363000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 91924261000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 91924261000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 106881965500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 106881965500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3989550000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3989550000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3989550000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3989550000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036240 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036240 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018728 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018728 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.762553 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.762553 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.775488 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.775488 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059958 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059958 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.105375 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.105375 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032816 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032816 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036757 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.036757 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13613.618456 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13613.618456 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19377.792248 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19377.792248 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23076.894416 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23076.894416 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31050.959871 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31050.959871 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13644.737412 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13644.737412 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22778.439157 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22778.439157 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17908.415828 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17908.415828 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18243.115644 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18243.115644 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183923.173164 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183923.173164 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93720.437956 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93720.437956 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 4916262 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.907947 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 453627454 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 4916774 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 92.261197 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 29905343000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.907947 # Average occupied blocks per requestor +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17895.437050 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17895.437050 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18475.991333 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18475.991333 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189752.675386 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189752.675386 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 91897.588280 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 91897.588280 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 5174135 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.907744 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 444161163 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5174647 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 85.834099 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 30089682000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.907744 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999820 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999820 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 186 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 922005230 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 922005230 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 453627454 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 453627454 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 453627454 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 453627454 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 453627454 # number of overall hits -system.cpu0.icache.overall_hits::total 453627454 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 4916774 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 4916774 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 4916774 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 4916774 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 4916774 # number of overall misses -system.cpu0.icache.overall_misses::total 4916774 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 52276659500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 52276659500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 52276659500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 52276659500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 52276659500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 52276659500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 458544228 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 458544228 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 458544228 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 458544228 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 458544228 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 458544228 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010723 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.010723 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010723 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.010723 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010723 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.010723 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10632.308807 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10632.308807 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10632.308807 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10632.308807 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10632.308807 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10632.308807 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 903846282 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 903846282 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 444161163 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 444161163 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 444161163 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 444161163 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 444161163 # number of overall hits +system.cpu0.icache.overall_hits::total 444161163 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 5174652 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 5174652 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 5174652 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 5174652 # 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number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 449335815 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 449335815 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 449335815 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011516 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011516 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011516 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011516 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011516 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011516 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10764.895205 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10764.895205 # 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Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 40 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2612 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5888 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5210 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.097229 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15297 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 130 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 167 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 29 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 18 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 53 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1333 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5696 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7896 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 254 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.021057 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004395 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.849915 # 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number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18732640000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18732640000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 452676000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 308308000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 14277477500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 37808584998 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 52847046498 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 452676000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 308308000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 14277477500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 37808584998 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 31463015041 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 84310061539 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3496032500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4850748500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8346781000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3820807000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7316839500 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3496032500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4850748500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8346781000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.036081 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052853 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.042089 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 3820807000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7316839500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.076420 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.066805 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.072634 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997739 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997739 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.208334 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.208334 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092312 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092312 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.237547 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.237547 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.734749 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.734749 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.036081 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052853 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092312 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.230709 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.157547 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.036081 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052853 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092312 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.230709 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.236016 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.236016 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092581 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092581 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.257538 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.257538 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.728943 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.728943 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.076420 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.066805 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092581 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.252419 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.166278 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.076420 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.066805 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092581 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.252419 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229341 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33277.010739 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45043.939327 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45043.939327 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20758.397340 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20758.397340 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16429.331447 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16429.331447 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 338357.142857 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 338357.142857 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43354.855932 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43354.855932 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28444.013466 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28444.013466 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29072.329738 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29072.329738 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32819.905779 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32819.905779 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28444.013466 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32091.506174 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31096.120257 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31541.674965 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 35399.573691 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28444.013466 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32091.506174 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45043.939327 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35462.445877 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.235841 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25987.228085 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43310.223511 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 43310.223511 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18525.289672 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18525.289672 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15274.090934 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15274.090934 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 163708.250000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 163708.250000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38278.277545 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38278.277545 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29802.051653 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29802.051653 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28643.524399 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28643.524399 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32147.228314 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32147.228314 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29802.051653 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30786.242975 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30433.782810 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29802.051653 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30786.242975 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43310.223511 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34231.791627 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 175911.097008 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 118059.137199 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 181726.848989 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114058.293063 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 89637.780652 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85836.908680 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 22110497 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11343995 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 879 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 1795730 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1795410 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 320 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 572087 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 9462372 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 26540 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 26540 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5352908 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 6850414 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2268094 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 917561 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 438813 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 347856 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 497865 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 109 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1218452 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1195725 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4916774 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4752404 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 832834 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 781464 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14836060 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18594952 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 327877 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 607160 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 34366049 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 629486804 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 699379029 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1242688 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2226528 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1332335049 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 6259200 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 105003768 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 17822799 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.114255 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.318177 # Request fanout histogram +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 88010.665008 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 84550.596270 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 22270826 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11431607 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1159 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 634641 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 634635 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 532548 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 9516927 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 22389 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 22388 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5262772 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 7044356 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1133181 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 892107 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 438346 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 371201 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 524392 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1190804 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1167926 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5174652 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4606140 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 845268 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 799396 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15609689 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18074319 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 333482 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 538074 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 34555564 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 662494868 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 674962485 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1270200 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1955080 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1340682633 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 5171785 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 107950516 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 16772894 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.051983 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.221994 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 15786774 88.58% 88.58% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2035705 11.42% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 320 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 15900995 94.80% 94.80% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 871893 5.20% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 17822799 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 21920125505 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 16772894 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 22046960997 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 184217084 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 203834159 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 7418286000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 7805103000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8250668056 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7957435977 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 172541000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 174707000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 328844000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 293689000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1430,69 +1429,75 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 102344 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 102344 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10188 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 77277 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 10 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 102334 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.244298 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 78.150189 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-2047 102333 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 113512 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 113512 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10824 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 86665 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 27 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 113485 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.290787 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 77.918264 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-2047 113483 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 102334 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 87475 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 22637.736496 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21131.866681 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 13933.012219 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 86378 98.75% 98.75% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 960 1.10% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 39 0.04% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 45 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 38 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 10 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 87475 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -5328755248 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.736470 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.440547 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1404285148 26.35% 26.35% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -3924470100 73.65% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -5328755248 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 77278 88.35% 88.35% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 10188 11.65% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 87466 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 102344 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::total 113485 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 97516 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23769.576275 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 22071.904189 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 14608.572728 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 88342 90.59% 90.59% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 8042 8.25% 98.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 147 0.15% 98.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 810 0.83% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 21 0.02% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 18 0.02% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 45 0.05% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 20 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 17 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 36 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 97516 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 14762172 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 194.841712 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -2861524688 -19384.17% -19384.17% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 2876286860 19484.17% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 14762172 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 86666 88.90% 88.90% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 10824 11.10% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 97490 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 113512 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 102344 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 87466 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 113512 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97490 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 87466 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 189810 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97490 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 211002 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 79660508 # DTB read hits -system.cpu1.dtb.read_misses 74735 # DTB read misses -system.cpu1.dtb.write_hits 72705787 # DTB write hits -system.cpu1.dtb.write_misses 27609 # DTB write misses +system.cpu1.dtb.read_hits 83873503 # DTB read hits +system.cpu1.dtb.read_misses 85876 # DTB read misses +system.cpu1.dtb.write_hits 75393075 # DTB write hits +system.cpu1.dtb.write_misses 27636 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 36374 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 39012 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4588 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 3907 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10004 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 79735243 # DTB read accesses -system.cpu1.dtb.write_accesses 72733396 # DTB write accesses +system.cpu1.dtb.perms_faults 10199 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 83959379 # DTB read accesses +system.cpu1.dtb.write_accesses 75420711 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 152366295 # DTB hits -system.cpu1.dtb.misses 102344 # DTB misses -system.cpu1.dtb.accesses 152468639 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 159266578 # DTB hits +system.cpu1.dtb.misses 113512 # DTB misses +system.cpu1.dtb.accesses 159380090 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1522,897 +1527,889 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 58593 # Table walker walks requested -system.cpu1.itb.walker.walksLong 58593 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 620 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 52801 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 58593 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 58593 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 58593 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 53421 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 25912.740308 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 23776.245370 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18077.529945 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 47948 89.75% 89.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 4330 8.11% 97.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 49 0.09% 97.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 923 1.73% 99.68% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 30 0.06% 99.74% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 25 0.05% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 42 0.08% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 13 0.02% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 27 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 20 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 3 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 53421 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1503171148 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1503171148 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1503171148 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 52801 98.84% 98.84% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 620 1.16% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 53421 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 59776 # Table walker walks requested +system.cpu1.itb.walker.walksLong 59776 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 674 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 53293 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 59776 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 59776 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 59776 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 53967 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 25622.306224 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23504.254601 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18586.945639 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 52820 97.87% 97.87% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 977 1.81% 99.68% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 34 0.06% 99.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 58 0.11% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 61 0.11% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 53967 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1314622148 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1314622148 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1314622148 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 53293 98.75% 98.75% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 674 1.25% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 53967 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 58593 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 58593 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 59776 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 59776 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53421 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53421 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 112014 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 421982441 # ITB inst hits -system.cpu1.itb.inst_misses 58593 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53967 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53967 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 113743 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 442849873 # ITB inst hits +system.cpu1.itb.inst_misses 59776 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 41066 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 25297 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 27503 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 422041034 # ITB inst accesses -system.cpu1.itb.hits 421982441 # DTB hits -system.cpu1.itb.misses 58593 # DTB misses -system.cpu1.itb.accesses 422041034 # DTB accesses -system.cpu1.numPwrStateTransitions 9904 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 4952 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 9471329494.171041 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 145765994017.543427 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3395 68.56% 68.56% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 1531 30.92% 99.47% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.02% 99.50% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.54% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.06% 99.60% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.04% 99.64% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.02% 99.66% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.68% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.02% 99.72% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 14 0.28% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 442909649 # ITB inst accesses +system.cpu1.itb.hits 442849873 # DTB hits +system.cpu1.itb.misses 59776 # DTB misses +system.cpu1.itb.accesses 442909649 # DTB accesses +system.cpu1.numPwrStateTransitions 28574 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 14287 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 3279405691.982362 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 123453533761.994095 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 4140 28.98% 28.98% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 10126 70.88% 99.85% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 7 0.05% 99.90% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.92% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.92% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.93% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 10 0.07% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 7470352176392 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 4952 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 501551261365 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 46902023655135 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 94807149833 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 11813601970000 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 14287 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 521446289148 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 46852869121352 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 94748630821 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 4952 # number of quiesce instructions executed -system.cpu1.committedInsts 421703858 # Number of instructions committed -system.cpu1.committedOps 497054350 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 456781482 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 475663 # Number of float alu accesses -system.cpu1.num_func_calls 25188507 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 64210733 # number of instructions that are conditional controls -system.cpu1.num_int_insts 456781482 # number of integer instructions -system.cpu1.num_fp_insts 475663 # number of float instructions -system.cpu1.num_int_register_reads 664763727 # number of times the integer registers were read -system.cpu1.num_int_register_writes 362355133 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 757340 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 426036 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 109701618 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 109432507 # number of times the CC registers were written -system.cpu1.num_mem_refs 152358964 # number of memory refs -system.cpu1.num_load_insts 79658830 # Number of load instructions -system.cpu1.num_store_insts 72700134 # Number of store instructions -system.cpu1.num_idle_cycles 93804047310.268021 # Number of idle cycles -system.cpu1.num_busy_cycles 1003102522.731979 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010580 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989420 # Percentage of idle cycles -system.cpu1.Branches 94064671 # Number of branches fetched -system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 343802607 69.13% 69.13% # Class of executed instruction -system.cpu1.op_class::IntMult 1044362 0.21% 69.34% # Class of executed instruction -system.cpu1.op_class::IntDiv 57840 0.01% 69.35% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 69226 0.01% 69.36% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.36% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.36% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.36% # Class of executed instruction -system.cpu1.op_class::MemRead 79658830 16.02% 85.38% # Class of executed instruction -system.cpu1.op_class::MemWrite 72700134 14.62% 100.00% # Class of executed instruction +system.cpu1.kern.inst.quiesce 14287 # number of quiesce instructions executed +system.cpu1.committedInsts 442543215 # Number of instructions committed +system.cpu1.committedOps 520378160 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 478315040 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 404780 # Number of float alu accesses +system.cpu1.num_func_calls 26483096 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 67217461 # number of instructions that are conditional controls +system.cpu1.num_int_insts 478315040 # number of integer instructions +system.cpu1.num_fp_insts 404780 # number of float instructions +system.cpu1.num_int_register_reads 696723237 # number of times the integer registers were read +system.cpu1.num_int_register_writes 379679857 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 664337 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 317564 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 114632172 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 114267384 # number of times the CC registers were written +system.cpu1.num_mem_refs 159256484 # number of memory refs +system.cpu1.num_load_insts 83870110 # Number of load instructions +system.cpu1.num_store_insts 75386374 # Number of store instructions +system.cpu1.num_idle_cycles 93705738242.702026 # Number of idle cycles +system.cpu1.num_busy_cycles 1042892578.297978 # Number of busy cycles +system.cpu1.not_idle_fraction 0.011007 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.988993 # Percentage of idle cycles +system.cpu1.Branches 98643380 # Number of branches fetched +system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 360264761 69.19% 69.19% # Class of executed instruction +system.cpu1.op_class::IntMult 1062033 0.20% 69.39% # Class of executed instruction +system.cpu1.op_class::IntDiv 60918 0.01% 69.41% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 40731 0.01% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction +system.cpu1.op_class::MemRead 83870110 16.11% 85.52% # Class of executed instruction +system.cpu1.op_class::MemWrite 75386374 14.48% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 497333042 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 5003393 # number of replacements -system.cpu1.dcache.tags.tagsinuse 453.941998 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 147178696 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5003905 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.412768 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8378733231000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 453.941998 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.886605 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.886605 # Average percentage of cache occupancy +system.cpu1.op_class::total 520684927 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 5203972 # number of replacements +system.cpu1.dcache.tags.tagsinuse 424.411021 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 153866536 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5204484 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.564225 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8378899013000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 424.411021 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.828928 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.828928 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 398 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 309758535 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 309758535 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 74209320 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 74209320 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 68941180 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 68941180 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 175621 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 175621 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 163479 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 163479 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1660182 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1660182 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1630108 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1630108 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 143313979 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 143313979 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 143489600 # number of overall hits -system.cpu1.dcache.overall_hits::total 143489600 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2836392 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2836392 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1297238 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1297238 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 605603 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 605603 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 460373 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 460373 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 162387 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 162387 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 191354 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 191354 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4594003 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4594003 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5199606 # number of overall misses -system.cpu1.dcache.overall_misses::total 5199606 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 40714366500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 40714366500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 24361465000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 24361465000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11037691000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 11037691000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2429522000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2429522000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4779056000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4779056000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2991500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2991500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 76113522500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 76113522500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 76113522500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 76113522500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 77045712 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 77045712 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 70238418 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 70238418 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 781224 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 781224 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 623852 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 623852 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1822569 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1822569 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1821462 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1821462 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 147907982 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 147907982 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 148689206 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 148689206 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036814 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036814 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018469 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018469 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.775198 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.775198 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.737952 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.737952 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089098 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089098 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105055 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105055 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031060 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031060 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034970 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.034970 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14354.280544 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14354.280544 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18779.487650 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18779.487650 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23975.539400 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23975.539400 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14961.308479 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14961.308479 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24974.946957 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24974.946957 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 323742508 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 323742508 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 78110378 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 78110378 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 71558729 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 71558729 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 177304 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 177304 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 95899 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 95899 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1773602 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1773602 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1738086 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1738086 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 149765006 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 149765006 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 149942310 # number of overall hits +system.cpu1.dcache.overall_hits::total 149942310 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2993339 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2993339 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1322577 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1322577 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 630415 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 630415 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 446111 # 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number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 24009342500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10785817000 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 10785817000 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2544188500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2544188500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4864957000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4864957000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2180500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2180500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 78282474500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 78282474500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 78282474500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 78282474500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 81103717 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 81103717 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 72881306 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 72881306 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 807719 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 807719 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 542010 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 542010 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1944508 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1944508 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1943249 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1943249 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 154527033 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 154527033 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 155334752 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 155334752 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036908 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036908 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018147 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018147 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.780488 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.780488 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.823068 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.823068 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.087892 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.087892 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105577 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105577 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.030817 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.030817 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034715 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.034715 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14528.028733 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14528.028733 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18153.455338 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18153.455338 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24177.428936 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24177.428936 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14886.478532 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14886.478532 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23712.643118 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23712.643118 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16568.017587 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16568.017587 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14638.325000 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14638.325000 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16438.897658 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16438.897658 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14517.073063 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14517.073063 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 5003393 # number of writebacks -system.cpu1.dcache.writebacks::total 5003393 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17753 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 17753 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 420 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 420 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44380 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44380 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 18173 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 18173 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 18173 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 18173 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2818639 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2818639 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1296818 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1296818 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 605603 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 605603 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 460373 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 460373 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 118007 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 118007 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 191354 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 191354 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4575830 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4575830 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5181433 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5181433 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 11021 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 11021 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11924 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11924 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 22945 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 22945 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 36912397500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 36912397500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23044975500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23044975500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12992134000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12992134000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10577318000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10577318000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1572635000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1572635000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4587759000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4587759000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2934500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2934500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 70534691000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 70534691000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83526825000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 83526825000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1888408000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1888408000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1888408000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1888408000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036584 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036584 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018463 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018463 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.775198 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.775198 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.737952 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.737952 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064748 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064748 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105055 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105055 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030937 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.030937 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034847 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.034847 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13095.823020 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13095.823020 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17770.400704 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17770.400704 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21453.219353 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21453.219353 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22975.539400 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22975.539400 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13326.624692 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13326.624692 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23975.244834 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23975.244834 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 5203972 # number of writebacks +system.cpu1.dcache.writebacks::total 5203972 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 14156 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 14156 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 216 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 216 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44175 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44175 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 14372 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 14372 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 14372 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 14372 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2979183 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2979183 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1322361 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1322361 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 630415 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 630415 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 446111 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 446111 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 126731 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 126731 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 205163 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 205163 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4747655 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4747655 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5378070 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5378070 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17577 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17577 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 16125 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 16125 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 33702 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 33702 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39805955500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39805955500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22681350000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22681350000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12330973000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12330973000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10339706000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10339706000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1686365000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1686365000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4659843000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4659843000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2131500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2131500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 72827011500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 72827011500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 85157984500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 85157984500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2978895500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2978895500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2978895500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2978895500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036733 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036733 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018144 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018144 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.780488 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.780488 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.823068 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.823068 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065174 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065174 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105577 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105577 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030724 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030724 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034622 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034622 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13361.366354 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13361.366354 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17152.161929 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17152.161929 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19560.088196 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19560.088196 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23177.428936 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23177.428936 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13306.649517 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13306.649517 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22712.881952 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22712.881952 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15414.622265 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15414.622265 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16120.410126 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16120.410126 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171346.338808 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171346.338808 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82301.503596 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82301.503596 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 5018955 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.221127 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 416962969 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5019467 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 83.069172 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8378705112000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.221127 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969182 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969182 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15339.575327 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15339.575327 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15834.301989 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15834.301989 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169476.901633 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 169476.901633 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 88389.279568 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 88389.279568 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 4895837 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.209399 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 437953524 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 4896349 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 89.444916 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8378871626000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.209399 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969159 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969159 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 848984354 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 848984354 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # 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average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10596.003524 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10596.003524 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 890596095 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 890596095 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 437953524 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 437953524 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 437953524 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 437953524 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 437953524 # number of overall hits +system.cpu1.icache.overall_hits::total 437953524 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 4896349 # 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number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 442849873 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 442849873 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 442849873 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 442849873 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 442849873 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011056 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.011056 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011056 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.011056 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011056 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.011056 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10506.638722 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10506.638722 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10506.638722 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10506.638722 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10506.638722 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10506.638722 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 5018955 # number of writebacks -system.cpu1.icache.writebacks::total 5018955 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5019472 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5019472 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5019472 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5019472 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5019472 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5019472 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 4895837 # number of writebacks +system.cpu1.icache.writebacks::total 4895837 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4896349 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 4896349 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 4896349 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 4896349 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 4896349 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 4896349 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 50676607000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 50676607000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 50676607000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 50676607000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 50676607000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 50676607000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10226000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10226000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10226000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 10226000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011895 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011895 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011895 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.011895 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011895 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.011895 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10096.003524 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10096.003524 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10096.003524 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10096.003524 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10096.003524 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10096.003524 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92963.636364 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92963.636364 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92963.636364 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92963.636364 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6881080 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6881096 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 48995995500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 48995995500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 48995995500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 48995995500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 48995995500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 48995995500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10402000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10402000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10402000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10402000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011056 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011056 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011056 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.011056 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011056 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.011056 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10006.638722 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10006.638722 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10006.638722 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 10006.638722 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10006.638722 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 10006.638722 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94563.636364 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 94563.636364 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94563.636364 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 94563.636364 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7252070 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7252079 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 8 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 855832 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 1952199 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13310.052713 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 14647404 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 1968271 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 7.441762 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9691338413500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12374.908537 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 46.710351 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 42.105943 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 846.327882 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.755304 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002851 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.002570 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.051656 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.812381 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1315 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 51 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14706 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 28 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 206 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 560 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 521 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 22 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 976 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4506 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5198 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3947 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.080261 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003113 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.897583 # 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average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27249.405073 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27249.405073 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28018.546747 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28138.881154 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28137.968207 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30537.783495 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31327.503279 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28018.546747 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28138.881154 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39436.606887 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31462.605744 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85463.636364 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163297.885854 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162528.703621 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85463.636364 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 78435.650469 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 78469.182390 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 20762161 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10650842 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 958 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 1727817 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1727605 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 212 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 482395 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9130479 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11924 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11924 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4254476 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 6851297 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2274133 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 818827 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 384823 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 346834 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 460171 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 59 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 109 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1120311 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1099104 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5019472 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4398430 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 506547 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 458275 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15058119 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16186537 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 334443 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 542756 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 32121855 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 642459768 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 622853650 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1275376 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1972104 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1268560898 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5663025 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 75880456 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 16447181 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.119069 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.323910 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.225464 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26936.029678 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41804.228740 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41804.228740 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18587.327591 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18587.327591 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15206.589959 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15206.589959 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 588000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 588000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34644.743535 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34644.743535 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 27535.565786 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27535.565786 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 27162.496717 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27162.496717 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27231.035824 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27231.035824 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27535.565786 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28691.702955 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28339.662371 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27535.565786 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28691.702955 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41804.228740 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32444.781937 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87063.636364 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161459.720089 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 160997.031718 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87063.636364 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 84207.984689 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 84217.274932 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 20954555 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10760929 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 751 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 564007 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 564007 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 525208 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9244496 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 16125 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 16125 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4351848 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 6833141 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 1083593 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 850253 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 408331 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 372440 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 477174 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 56 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1146242 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1123232 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4896349 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4644090 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 493781 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 444195 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14688755 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16849115 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 339302 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 606054 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 32483226 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 626700344 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 649733422 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1286368 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2216312 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1279936446 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4601099 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 75959664 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 15521649 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.052382 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.222797 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 14489040 88.09% 88.09% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 1957929 11.90% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 212 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 14708591 94.76% 94.76% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 813058 5.24% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 16447181 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 20541870997 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 15521649 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 20731667993 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 171936035 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 171895510 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7529318000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7344633500 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7396555908 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7734220026 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 175021499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 178506000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 296243499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 329015998 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40346 # Transaction distribution -system.iobus.trans_dist::ReadResp 40346 # Transaction distribution -system.iobus.trans_dist::WriteReq 136621 # Transaction distribution -system.iobus.trans_dist::WriteResp 136621 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47682 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40399 # Transaction distribution +system.iobus.trans_dist::ReadResp 40399 # Transaction distribution +system.iobus.trans_dist::WriteReq 136980 # Transaction distribution +system.iobus.trans_dist::WriteResp 136980 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47798 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2423,15 +2420,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122616 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231238 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231238 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231738 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231738 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47702 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354758 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47818 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2442,21 +2439,21 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155723 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338968 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338968 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155955 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355304 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7355304 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496777 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36887001 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7513345 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 37010502 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 320000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 320500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -2464,7 +2461,7 @@ system.iobus.reqLayer10.occupancy 8000 # La system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) @@ -2472,75 +2469,75 @@ system.iobus.reqLayer16.occupancy 14000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 26455501 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 26741000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 37419000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 37418500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 569241095 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 570750713 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92726000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92947000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147934000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148178000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115616 # number of replacements -system.iocache.tags.tagsinuse 11.233110 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115853 # number of replacements +system.iocache.tags.tagsinuse 11.245503 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115632 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115869 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9095552544000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.412176 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.820935 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463261 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.238808 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.702069 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9136243501000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.839816 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.405687 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239988 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.462855 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.702844 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040928 # Number of tag accesses -system.iocache.tags.data_accesses 1040928 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1043178 # Number of tag accesses +system.iocache.tags.data_accesses 1043178 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8891 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8928 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8885 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8922 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115619 # number of demand (read+write) misses -system.iocache.demand_misses::total 115659 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115869 # number of demand (read+write) misses +system.iocache.demand_misses::total 115909 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115619 # number of overall misses -system.iocache.overall_misses::total 115659 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1628324544 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1633522544 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115869 # number of overall misses +system.iocache.overall_misses::total 115909 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5278000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1633593087 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1638871087 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12891433551 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12891433551 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14519758095 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14525325095 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14519758095 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14525325095 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12911092626 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12911092626 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5647000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14544685713 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14550332713 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5647000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14544685713 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14550332713 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8891 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8928 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8885 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8922 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115619 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115659 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115869 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115909 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115619 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115659 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115869 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115909 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2554,53 +2551,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 183143.014734 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 182966.234767 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 142648.648649 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 183859.660889 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 183688.756669 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120787.736592 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120787.736592 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125582.802956 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125587.503739 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125582.802956 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125587.503739 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31812 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120682.463041 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120682.463041 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 141175 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125526.980582 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125532.380687 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 141175 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125526.980582 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125532.380687 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31750 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3498 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3454 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.094340 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.192241 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106695 # number of writebacks -system.iocache.writebacks::total 106695 # number of writebacks +system.iocache.writebacks::writebacks 106953 # number of writebacks +system.iocache.writebacks::total 106953 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8891 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8928 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8885 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8922 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115619 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115659 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115869 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115909 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115619 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115659 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1183774544 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1187122544 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115869 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115909 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3428000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1189343087 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1192771087 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7546042407 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7546042407 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 8729816951 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8733383951 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 8729816951 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8733383951 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7553188799 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7553188799 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3647000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8742531886 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8746178886 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3647000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8742531886 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8746178886 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2614,659 +2611,662 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133143.014734 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 132966.234767 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92648.648649 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133859.660889 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 133688.756669 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70703.493057 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70703.493057 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75505.037675 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75509.765353 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75505.037675 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75509.765353 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1334376 # number of replacements -system.l2c.tags.tagsinuse 63294.471519 # Cycle average of tags in use -system.l2c.tags.total_refs 5390543 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1393372 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.868703 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 9808893500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 22223.163606 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 261.500257 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 456.360455 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3501.846073 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 10429.068271 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 16721.904383 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 41.820782 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 49.581814 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3191.520948 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3798.713740 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2618.991189 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.339099 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003990 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.006964 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.053434 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.159135 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.255156 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000638 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000757 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.048699 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.057964 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.039963 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.965797 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10362 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 274 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 48360 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 240 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 245 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9869 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 274 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1630 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5501 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 41094 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.158112 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.004181 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.737915 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 69824789 # Number of tag accesses -system.l2c.tags.data_accesses 69824789 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2605015 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2605015 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 157240 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 131498 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 288738 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 36551 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 35663 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 72214 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 46670 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 57995 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 104665 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 4832 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3674 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 408343 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 539971 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 281420 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5997 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5496 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 419901 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 530515 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 275271 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2475420 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 117433 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 122622 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 240055 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4832 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3674 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 408343 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 586641 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 281420 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5997 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5496 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 419901 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 588510 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 275271 # number of demand (read+write) hits -system.l2c.demand_hits::total 2580085 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4832 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3674 # number of overall hits -system.l2c.overall_hits::cpu0.inst 408343 # number of overall hits -system.l2c.overall_hits::cpu0.data 586641 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 281420 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5997 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5496 # number of overall hits -system.l2c.overall_hits::cpu1.inst 419901 # number of overall hits -system.l2c.overall_hits::cpu1.data 588510 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 275271 # number of overall hits -system.l2c.overall_hits::total 2580085 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 61532 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 60685 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 122217 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 12602 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 13049 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 25651 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 81623 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 50736 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 132359 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1903 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1980 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 45534 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 135010 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 240877 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1748 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1646 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 43900 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 98157 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 176782 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 747537 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 445868 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 117477 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 563345 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1903 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1980 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 45534 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 216633 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 240877 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1748 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1646 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 43900 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 148893 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 176782 # number of demand (read+write) misses -system.l2c.demand_misses::total 879896 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1903 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1980 # number of overall misses -system.l2c.overall_misses::cpu0.inst 45534 # number of overall misses -system.l2c.overall_misses::cpu0.data 216633 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 240877 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1748 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1646 # number of overall misses -system.l2c.overall_misses::cpu1.inst 43900 # number of overall misses -system.l2c.overall_misses::cpu1.data 148893 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 176782 # number of overall misses -system.l2c.overall_misses::total 879896 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 390440000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 373608000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 764048000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 65654000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 76676500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 142330500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 7135565500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4240679000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 11376244500 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 166331500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 176995000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 3903055500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 11953058500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 28580004804 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 157717000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 151093000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3757434500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 9007178500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 21390253127 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 79243121431 # number of ReadSharedReq miss cycles -system.l2c.InvalidateReq_miss_latency::cpu0.data 55722000 # number of InvalidateReq miss cycles -system.l2c.InvalidateReq_miss_latency::cpu1.data 43983500 # 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number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 21390253127 # number of overall miss cycles -system.l2c.overall_miss_latency::total 90619365931 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 2605015 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 2605015 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 218772 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 192183 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 410955 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 49153 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 48712 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 97865 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 128293 # 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miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.094653 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.156134 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.391065 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.231941 # miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_miss_rate::cpu0.data 0.791527 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::cpu1.data 0.489286 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::total 0.701201 # miss rate for InvalidateReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.282554 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.350195 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.100322 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.269688 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.461188 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.225694 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.230468 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.094653 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.201915 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.391065 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.254307 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.282554 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.350195 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.100322 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.269688 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.461188 # 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Cycle average of tags in use +system.l2c.tags.total_refs 6107230 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1440978 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.238253 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 9552186500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 11716.268844 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 133.184810 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 146.917074 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4004.381376 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 14231.433494 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7902.194687 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 315.518093 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 369.695425 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2763.350410 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 11175.503416 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 12240.338524 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.178776 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002032 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.002242 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.061102 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.217154 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.120578 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004814 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.005641 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.042165 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.170525 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.186773 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.991803 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 12060 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 189 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 50714 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 60 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 153 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 1009 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 1115 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 9723 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 184 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1849 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 9563 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 39124 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.184021 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.002884 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.773834 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 69629880 # Number of tag accesses +system.l2c.tags.data_accesses 69629880 # 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number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5935 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 422841 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 567260 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 276728 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 9775 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4116 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 406188 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 512398 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 278781 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 2494703 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 136557 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 120325 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 256882 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 10681 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 5935 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 422841 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 630910 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 276728 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 9775 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4116 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 406188 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 561391 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 278781 # number of demand (read+write) hits +system.l2c.demand_hits::total 2607346 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 10681 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 5935 # 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number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1621 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 72583 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 52296 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 124879 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1676 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1611 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 56236 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 130395 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 210895 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1750 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1829 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 38017 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 107679 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 200910 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 750998 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 430773 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 119101 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 549874 # number of InvalidateReq misses +system.l2c.demand_misses::cpu0.dtb.walker 1676 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1611 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 56236 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 202978 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 210895 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 1750 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1829 # 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mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.213491 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.117106 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.243335 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.432496 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.151844 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.307653 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.085384 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.221745 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.418832 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.251369 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20538.269992 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20386.227310 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20460.713143 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24842.964824 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24346.060606 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24590.067859 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79084.015183 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 76663.895097 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 78070.533332 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 76244.907652 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80725.208799 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76423.394880 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80065.548777 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 97673.842846 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19906.284749 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19870.744158 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19898.586767 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76244.907652 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 80138.148487 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76423.394880 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78953.433292 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 94877.918238 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76244.907652 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 80138.148487 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76423.394880 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78953.433292 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 94877.918238 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 157908.812439 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 67459.090909 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145322.987748 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 106109.716665 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 163719.381879 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69050 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143473.769616 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 106203.079428 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 80464.483101 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 67459.090909 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 69795.318921 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 72180.858446 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 3668271 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2217535 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3152 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 79289.613802 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69050 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 74823.486677 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 72216.646766 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3586859 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2135577 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3113 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 81829 # Transaction distribution -system.membus.trans_dist::ReadResp 838129 # Transaction distribution -system.membus.trans_dist::WriteReq 38464 # Transaction distribution -system.membus.trans_dist::WriteResp 38464 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1174756 # Transaction distribution -system.membus.trans_dist::CleanEvict 216961 # Transaction distribution -system.membus.trans_dist::UpgradeReq 398327 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 309165 # Transaction distribution -system.membus.trans_dist::UpgradeResp 22 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 145872 # Transaction distribution -system.membus.trans_dist::ReadExResp 127949 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 756300 # Transaction distribution -system.membus.trans_dist::InvalidateReq 666856 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122616 # Packet count per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 81835 # Transaction distribution +system.membus.trans_dist::ReadResp 841453 # Transaction distribution +system.membus.trans_dist::WriteReq 38513 # Transaction distribution +system.membus.trans_dist::WriteResp 38513 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1169257 # Transaction distribution +system.membus.trans_dist::CleanEvict 224172 # Transaction distribution +system.membus.trans_dist::UpgradeReq 330190 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 306798 # Transaction distribution +system.membus.trans_dist::UpgradeResp 21 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 142313 # Transaction distribution +system.membus.trans_dist::ReadExResp 124217 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 759618 # Transaction distribution +system.membus.trans_dist::InvalidateReq 654423 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122940 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26280 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4403166 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4552154 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237974 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237974 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4790128 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155723 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26066 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4320804 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4469902 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238504 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238504 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4708406 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155955 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52560 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124524268 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 124732755 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7257216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7257216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 131989971 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 572885 # Total snoops (count) -system.membus.snoopTraffic 188480 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2396814 # Request fanout histogram -system.membus.snoop_fanout::mean 0.013654 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.116050 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52132 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124129580 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 124337871 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7276480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7276480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 131614351 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 603280 # Total snoops (count) +system.membus.snoopTraffic 185472 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2313692 # Request fanout histogram +system.membus.snoop_fanout::mean 0.013382 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.114902 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2364088 98.63% 98.63% # Request fanout histogram -system.membus.snoop_fanout::1 32726 1.37% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2282731 98.66% 98.66% # Request fanout histogram +system.membus.snoop_fanout::1 30961 1.34% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2396814 # Request fanout histogram -system.membus.reqLayer0.occupancy 101168498 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2313692 # Request fanout histogram +system.membus.reqLayer0.occupancy 101576998 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21745999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21542999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8211058586 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8037178912 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4830240380 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4828786098 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45484396 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45456460 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3309,78 +3309,78 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 10770571 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5860830 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1720391 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 132185 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 120739 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 11446 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47403574916500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 81831 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4048119 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38464 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38464 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3673076 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2310912 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 679438 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 381379 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1060817 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 109 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 109 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 291982 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 291982 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 3967045 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 832947 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 803400 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8640930 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7144066 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15784996 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 212830169 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 175839034 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 388669203 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2716758 # Total snoops (count) -system.toL2Bus.snoopTraffic 119453392 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 7607581 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.354994 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.481646 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 10929949 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5951808 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1800454 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 181173 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 166358 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 14815 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 81837 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4119674 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38513 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38513 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3703405 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2363493 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 695815 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 407836 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1103651 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 102 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 294367 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 294367 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4038548 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 834564 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 806756 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8843715 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7139942 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15983657 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 216752505 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 175713942 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 392466447 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2839573 # Total snoops (count) +system.toL2Bus.snoopTraffic 122328784 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 7769609 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.368989 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.486467 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4918380 64.65% 64.65% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 2677755 35.20% 99.85% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 11446 0.15% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4917524 63.29% 63.29% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2837270 36.52% 99.81% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 14815 0.19% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7607581 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8483488339 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 7769609 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8597464366 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2591888 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2599172 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3918166834 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4012155776 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3514899349 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3555978029 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index 89d0e34be..db63d86a7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.759348 # Number of seconds simulated -sim_ticks 51759347706500 # Number of ticks simulated -final_tick 51759347706500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.820895 # Number of seconds simulated +sim_ticks 51820894502500 # Number of ticks simulated +final_tick 51820894502500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 706961 # Simulator instruction rate (inst/s) -host_op_rate 830795 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43773319280 # Simulator tick rate (ticks/s) -host_mem_usage 670816 # Number of bytes of host memory used -host_seconds 1182.44 # Real time elapsed on the host -sim_insts 835939132 # Number of instructions simulated -sim_ops 982366087 # Number of ops (including micro ops) simulated +host_inst_rate 612269 # Simulator instruction rate (inst/s) +host_op_rate 719485 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35448799247 # Simulator tick rate (ticks/s) +host_mem_usage 680056 # Number of bytes of host memory used +host_seconds 1461.85 # Real time elapsed on the host +sim_insts 895045967 # Number of instructions simulated +sim_ops 1051780871 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 152192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 158144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 4715828 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 36073224 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 410496 # Number of bytes read from this memory -system.physmem.bytes_read::total 41509884 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 4715828 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 4715828 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 62909632 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 268032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 256704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5200500 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 51306824 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 409600 # Number of bytes read from this memory +system.physmem.bytes_read::total 57441660 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5200500 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5200500 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 78712256 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 62930212 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 2378 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2471 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 114092 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 563657 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6414 # Number of read requests responded to by this memory -system.physmem.num_reads::total 689012 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 982963 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 78732836 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 4188 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 4011 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 121665 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 801682 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6400 # Number of read requests responded to by this memory +system.physmem.num_reads::total 937946 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1229879 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 985536 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2940 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 3055 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 91111 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 696941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7931 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 801978 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 91111 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 91111 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1215426 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1215823 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1215426 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2940 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 3055 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 91111 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 697339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2017802 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 689012 # Number of read requests accepted -system.physmem.writeReqs 985536 # Number of write requests accepted -system.physmem.readBursts 689012 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 985536 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 44056384 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 40384 # Total number of bytes read from write queue -system.physmem.bytesWritten 62928960 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 41509884 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 62930212 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 631 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_writes::total 1232452 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 5172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 4954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 100355 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 990080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1108465 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 100355 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 100355 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1518929 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1519326 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1518929 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 5172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 4954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 100355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 990477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2627791 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 937946 # Number of read requests accepted +system.physmem.writeReqs 1232452 # Number of write requests accepted +system.physmem.readBursts 937946 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1232452 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 59993856 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 34688 # Total number of bytes read from write queue +system.physmem.bytesWritten 78731584 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 57441660 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 78732836 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 542 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 41424 # Per bank write bursts -system.physmem.perBankRdBursts::1 42196 # Per bank write bursts -system.physmem.perBankRdBursts::2 39305 # Per bank write bursts -system.physmem.perBankRdBursts::3 41228 # Per bank write bursts -system.physmem.perBankRdBursts::4 37796 # Per bank write bursts -system.physmem.perBankRdBursts::5 46284 # Per bank write bursts -system.physmem.perBankRdBursts::6 37646 # Per bank write bursts -system.physmem.perBankRdBursts::7 36984 # Per bank write bursts -system.physmem.perBankRdBursts::8 37874 # Per bank write bursts -system.physmem.perBankRdBursts::9 85067 # Per bank write bursts -system.physmem.perBankRdBursts::10 43899 # Per bank write bursts -system.physmem.perBankRdBursts::11 46232 # Per bank write bursts -system.physmem.perBankRdBursts::12 39321 # Per bank write bursts -system.physmem.perBankRdBursts::13 40035 # Per bank write bursts -system.physmem.perBankRdBursts::14 35465 # Per bank write bursts -system.physmem.perBankRdBursts::15 37625 # Per bank write bursts -system.physmem.perBankWrBursts::0 61899 # Per bank write bursts -system.physmem.perBankWrBursts::1 62487 # Per bank write bursts -system.physmem.perBankWrBursts::2 61087 # Per bank write bursts -system.physmem.perBankWrBursts::3 63695 # Per bank write bursts -system.physmem.perBankWrBursts::4 58991 # Per bank write bursts -system.physmem.perBankWrBursts::5 64628 # Per bank write bursts -system.physmem.perBankWrBursts::6 58592 # Per bank write bursts -system.physmem.perBankWrBursts::7 59025 # Per bank write bursts -system.physmem.perBankWrBursts::8 60354 # Per bank write bursts -system.physmem.perBankWrBursts::9 64900 # Per bank write bursts -system.physmem.perBankWrBursts::10 63044 # Per bank write bursts -system.physmem.perBankWrBursts::11 64791 # Per bank write bursts -system.physmem.perBankWrBursts::12 60176 # Per bank write bursts -system.physmem.perBankWrBursts::13 61598 # Per bank write bursts -system.physmem.perBankWrBursts::14 57895 # Per bank write bursts -system.physmem.perBankWrBursts::15 60103 # Per bank write bursts +system.physmem.perBankRdBursts::0 58989 # Per bank write bursts +system.physmem.perBankRdBursts::1 58919 # Per bank write bursts +system.physmem.perBankRdBursts::2 58679 # Per bank write bursts +system.physmem.perBankRdBursts::3 55735 # Per bank write bursts +system.physmem.perBankRdBursts::4 54249 # Per bank write bursts +system.physmem.perBankRdBursts::5 59544 # Per bank write bursts +system.physmem.perBankRdBursts::6 52586 # Per bank write bursts +system.physmem.perBankRdBursts::7 53926 # Per bank write bursts +system.physmem.perBankRdBursts::8 52975 # Per bank write bursts +system.physmem.perBankRdBursts::9 101116 # Per bank write bursts +system.physmem.perBankRdBursts::10 56481 # Per bank write bursts +system.physmem.perBankRdBursts::11 59298 # Per bank write bursts +system.physmem.perBankRdBursts::12 53072 # Per bank write bursts +system.physmem.perBankRdBursts::13 58564 # Per bank write bursts +system.physmem.perBankRdBursts::14 50527 # Per bank write bursts +system.physmem.perBankRdBursts::15 52744 # Per bank write bursts +system.physmem.perBankWrBursts::0 76908 # Per bank write bursts +system.physmem.perBankWrBursts::1 78477 # Per bank write bursts +system.physmem.perBankWrBursts::2 80133 # Per bank write bursts +system.physmem.perBankWrBursts::3 78953 # Per bank write bursts +system.physmem.perBankWrBursts::4 75778 # Per bank write bursts +system.physmem.perBankWrBursts::5 80212 # Per bank write bursts +system.physmem.perBankWrBursts::6 72590 # Per bank write bursts +system.physmem.perBankWrBursts::7 74527 # Per bank write bursts +system.physmem.perBankWrBursts::8 74121 # Per bank write bursts +system.physmem.perBankWrBursts::9 79665 # Per bank write bursts +system.physmem.perBankWrBursts::10 76241 # Per bank write bursts +system.physmem.perBankWrBursts::11 79585 # Per bank write bursts +system.physmem.perBankWrBursts::12 74881 # Per bank write bursts +system.physmem.perBankWrBursts::13 79432 # Per bank write bursts +system.physmem.perBankWrBursts::14 73606 # Per bank write bursts +system.physmem.perBankWrBursts::15 75072 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 19 # Number of times write queue was full causing retry -system.physmem.totGap 51759344769500 # Total gap between requests +system.physmem.numWrRetry 41 # Number of times write queue was full causing retry +system.physmem.totGap 51820891581500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 645896 # Read request sizes (log2) +system.physmem.readPktSize::6 894830 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 982963 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 659454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 23139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 474 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 555 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 545 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 279 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 358 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 92 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 47 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1229879 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 903506 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 28089 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 425 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 490 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 475 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 467 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1235 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 309 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 395 # 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What read queue length does an incoming req see @@ -160,168 +160,154 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 37580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 54935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 54491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 57672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 55206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 58598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 55686 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 254 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 47 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 438828 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 243.797169 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 147.013209 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 285.979705 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 194919 44.42% 44.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 116778 26.61% 71.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 38832 8.85% 79.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20430 4.66% 84.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13130 2.99% 87.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8793 2.00% 89.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7414 1.69% 91.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5819 1.33% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 32713 7.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 438828 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 52143 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 13.201312 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 141.003763 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 52140 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 33600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 39104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 67316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 70490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 74148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 71564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 70236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 72767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 75611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 72543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 77682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 76300 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 128 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 563432 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 246.214486 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 148.153142 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 287.290760 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 250076 44.38% 44.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 147098 26.11% 70.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 49891 8.85% 79.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 26994 4.79% 84.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18337 3.25% 87.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11939 2.12% 89.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8931 1.59% 91.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7653 1.36% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 42513 7.55% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 563432 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 66023 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.197810 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 125.335088 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 66020 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 52143 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 52143 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.857085 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.140227 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.284435 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 48446 92.91% 92.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1855 3.56% 96.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 116 0.22% 96.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 101 0.19% 96.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 48 0.09% 96.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 101 0.19% 97.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 252 0.48% 97.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 24 0.05% 97.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 307 0.59% 98.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 75 0.14% 98.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 29 0.06% 98.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 51 0.10% 98.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 313 0.60% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 41 0.08% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 37 0.07% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 129 0.25% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 166 0.32% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 3 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 15 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 52143 # Writes before turning the bus around for reads -system.physmem.totQLat 9222624910 # Total ticks spent queuing -system.physmem.totMemAccLat 22129768660 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3441905000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13397.56 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 66023 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 66023 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.632613 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.082710 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.894597 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 62853 95.20% 95.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 1132 1.71% 96.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 1165 1.76% 98.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 145 0.22% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 61 0.09% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 50 0.08% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 451 0.68% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 71 0.11% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 27 0.04% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 7 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 4 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 11 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 4 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 20 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 9 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 66023 # Writes before turning the bus around for reads +system.physmem.totQLat 12434281516 # Total ticks spent queuing +system.physmem.totMemAccLat 30010606516 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4687020000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13264.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32147.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.85 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.22 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.80 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.22 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 32014.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.16 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.52 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.11 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.52 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing -system.physmem.readRowHits 507228 # Number of row buffer hits during reads -system.physmem.writeRowHits 725589 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.79 # Row buffer hit rate for writes -system.physmem.avgGap 30909442.29 # Average gap between requests -system.physmem.pageHitRate 73.75 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1651557600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 901147500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2518331400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3177817920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3380668873920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1280908967265 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29932003411500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34601830107105 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.513662 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49794254360042 # Time in different power states -system.physmem_0.memoryStateTime::REF 1728358320000 # Time in different power states +system.physmem.avgWrQLen 23.96 # Average write queue length when enqueuing +system.physmem.readRowHits 702833 # Number of row buffer hits during reads +system.physmem.writeRowHits 901319 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.98 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.27 # Row buffer hit rate for writes +system.physmem.avgGap 23876216.06 # Average gap between requests +system.physmem.pageHitRate 74.01 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2165373000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1181503125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3530451600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4001905440 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3384688532160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1300349435715 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29951875881000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34647793082040 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.606693 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49827060150280 # Time in different power states +system.physmem_0.memoryStateTime::REF 1730413360000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 236733614958 # Time in different power states +system.physmem_0.memoryStateTime::ACT 263420580720 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1665982080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 909018000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2851001400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3193739280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3380668873920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1282600048680 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29930520006750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34602408670110 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.524840 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49791748874504 # Time in different power states -system.physmem_1.memoryStateTime::REF 1728358320000 # Time in different power states +system.physmem_1.actEnergy 2094172920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1142653875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3781260600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3969667440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3384688532160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1299689474040 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29952454794750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34647820555785 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.607223 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49827979372630 # Time in different power states +system.physmem_1.memoryStateTime::REF 1730413360000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 239239854996 # Time in different power states +system.physmem_1.memoryStateTime::ACT 262496082370 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -338,9 +324,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -348,7 +334,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -378,72 +364,69 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 186389 # Table walker walks requested -system.cpu.dtb.walker.walksLong 186389 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 11673 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 145933 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 20 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 186369 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 0.214628 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 70.564506 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-2047 186367 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 214264 # Table walker walks requested +system.cpu.dtb.walker.walksLong 214264 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 17030 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 164948 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 21 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 214243 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 0.140028 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 46.737844 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-2047 214241 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 186369 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 157626 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 24833.263548 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 20845.971920 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 18169.669952 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 156391 99.22% 99.22% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 5 0.00% 99.22% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 1058 0.67% 99.89% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 24 0.02% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 78 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 18 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 45 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 157626 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples -5176298892 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 1.304609 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 1576748204 -30.46% -30.46% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::1 -6753047096 130.46% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total -5176298892 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 145934 92.59% 92.59% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 11673 7.41% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 157607 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 186389 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkWaitTime::16384-18431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 214243 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 181999 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 24181.814186 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 20419.578200 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 15522.698406 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 180089 98.95% 98.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 1633 0.90% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 118 0.06% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 77 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 52 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 23 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 181999 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 4819875556 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 1.150179 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 -723841796 -15.02% -15.02% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::1 5543717352 115.02% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 4819875556 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 164949 90.64% 90.64% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 17030 9.36% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 181979 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 214264 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 186389 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 157607 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 214264 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 181979 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 157607 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 343996 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 181979 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 396243 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 157302470 # DTB read hits -system.cpu.dtb.read_misses 138254 # DTB read misses -system.cpu.dtb.write_hits 142797891 # DTB write hits -system.cpu.dtb.write_misses 48135 # DTB write misses +system.cpu.dtb.read_hits 168009449 # DTB read hits +system.cpu.dtb.read_misses 157878 # DTB read misses +system.cpu.dtb.write_hits 152852610 # DTB write hits +system.cpu.dtb.write_misses 56386 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 38509 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 71109 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb_mva_asid 43022 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 75936 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 6989 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 8201 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 18784 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 157440724 # DTB read accesses -system.cpu.dtb.write_accesses 142846026 # DTB write accesses +system.cpu.dtb.perms_faults 19949 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 168167327 # DTB read accesses +system.cpu.dtb.write_accesses 152908996 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 300100361 # DTB hits -system.cpu.dtb.misses 186389 # DTB misses -system.cpu.dtb.accesses 300286750 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 320862059 # DTB hits +system.cpu.dtb.misses 214264 # DTB misses +system.cpu.dtb.accesses 321076323 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -473,829 +456,832 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 119383 # Table walker walks requested -system.cpu.itb.walker.walksLong 119383 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 107813 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 119383 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 119383 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 119383 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 108935 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 28686.574563 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24766.127594 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 21816.949759 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 107446 98.63% 98.63% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 3 0.00% 98.64% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 1285 1.18% 99.82% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 37 0.03% 99.85% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 72 0.07% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 42 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 32 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 9 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 108935 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 1449611704 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 1449611704 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 1449611704 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 107813 98.97% 98.97% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1122 1.03% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 108935 # Table walker page sizes translated +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 122945 # Table walker walks requested +system.cpu.itb.walker.walksLong 122945 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1119 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 110624 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 122945 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 122945 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 122945 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 111743 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 27331.219853 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 23493.082733 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 18310.002732 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 109587 98.07% 98.07% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 1865 1.67% 99.74% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 133 0.12% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 84 0.08% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 40 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 22 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 5 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 111743 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples -850328296 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 -850328296 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total -850328296 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 110624 99.00% 99.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1119 1.00% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 111743 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 119383 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 119383 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 122945 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 122945 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 108935 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 108935 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 228318 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 836454912 # ITB inst hits -system.cpu.itb.inst_misses 119383 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 111743 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 111743 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 234688 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 895597591 # ITB inst hits +system.cpu.itb.inst_misses 122945 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 38509 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 50925 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 43022 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 53957 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 836574295 # ITB inst accesses -system.cpu.itb.hits 836454912 # DTB hits -system.cpu.itb.misses 119383 # DTB misses -system.cpu.itb.accesses 836574295 # DTB accesses -system.cpu.numPwrStateTransitions 32056 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 16028 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3133878336.314075 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 60741761061.559830 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 6738 42.04% 42.04% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9255 57.74% 99.78% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 895720536 # ITB inst accesses +system.cpu.itb.hits 895597591 # DTB hits +system.cpu.itb.misses 122945 # DTB misses +system.cpu.itb.accesses 895720536 # DTB accesses +system.cpu.numPwrStateTransitions 32698 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16349 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3072754762.549147 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 59826711358.002258 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7060 43.18% 43.18% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9253 56.60% 99.78% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+10-1e+11 6 0.04% 99.82% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::8e+11-8.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 1988775138696 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 16028 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 1529545732058 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50229801974442 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 103518695413 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 1988775178432 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 16349 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 1584426889584 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50236467612916 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 103641789005 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16028 # number of quiesce instructions executed -system.cpu.committedInsts 835939132 # Number of instructions committed -system.cpu.committedOps 982366087 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 902933087 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 900158 # Number of float alu accesses -system.cpu.num_func_calls 50090187 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 126876498 # number of instructions that are conditional controls -system.cpu.num_int_insts 902933087 # number of integer instructions -system.cpu.num_fp_insts 900158 # number of float instructions -system.cpu.num_int_register_reads 1308206945 # number of times the integer registers were read -system.cpu.num_int_register_writes 715740470 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1453094 # number of times the floating registers were read -system.cpu.num_fp_register_writes 759824 # number of times the floating registers were written -system.cpu.num_cc_register_reads 216985275 # number of times the CC registers were read -system.cpu.num_cc_register_writes 216380044 # number of times the CC registers were written -system.cpu.num_mem_refs 300079118 # number of memory refs -system.cpu.num_load_insts 157292666 # Number of load instructions -system.cpu.num_store_insts 142786452 # Number of store instructions -system.cpu.num_idle_cycles 100459603948.882050 # Number of idle cycles -system.cpu.num_busy_cycles 3059091464.117941 # Number of busy cycles -system.cpu.not_idle_fraction 0.029551 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.970449 # Percentage of idle cycles -system.cpu.Branches 186526742 # Number of branches fetched +system.cpu.kern.inst.quiesce 16349 # number of quiesce instructions executed +system.cpu.committedInsts 895045967 # Number of instructions committed +system.cpu.committedOps 1051780871 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 965574423 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 894989 # Number of float alu accesses +system.cpu.num_func_calls 52935800 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 136802593 # number of instructions that are conditional controls +system.cpu.num_int_insts 965574423 # number of integer instructions +system.cpu.num_fp_insts 894989 # number of float instructions +system.cpu.num_int_register_reads 1409614532 # number of times the integer registers were read +system.cpu.num_int_register_writes 766141547 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1442074 # number of times the floating registers were read +system.cpu.num_fp_register_writes 760100 # number of times the floating registers were written +system.cpu.num_cc_register_reads 235678872 # number of times the CC registers were read +system.cpu.num_cc_register_writes 235085086 # number of times the CC registers were written +system.cpu.num_mem_refs 320845878 # number of memory refs +system.cpu.num_load_insts 168002679 # Number of load instructions +system.cpu.num_store_insts 152843199 # Number of store instructions +system.cpu.num_idle_cycles 100472935225.830063 # Number of idle cycles +system.cpu.num_busy_cycles 3168853779.169939 # Number of busy cycles +system.cpu.not_idle_fraction 0.030575 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.969425 # Percentage of idle cycles +system.cpu.Branches 199903261 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 680504734 69.23% 69.23% # Class of executed instruction -system.cpu.op_class::IntMult 2132093 0.22% 69.45% # Class of executed instruction -system.cpu.op_class::IntDiv 96706 0.01% 69.46% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 69.46% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 69.46% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 69.46% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 69.46% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 69.46% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 69.46% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 69.46% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 69.46% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 69.46% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 69.46% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 69.46% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 69.46% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 69.46% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 69.46% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 69.46% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 69.46% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 69.46% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 8 0.00% 69.46% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 69.46% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 13 0.00% 69.46% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 21 0.00% 69.46% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 69.46% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 112297 0.01% 69.47% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::MemRead 157292666 16.00% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 142786452 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 729096517 69.28% 69.28% # Class of executed instruction +system.cpu.op_class::IntMult 2224980 0.21% 69.49% # Class of executed instruction +system.cpu.op_class::IntDiv 97778 0.01% 69.50% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 110423 0.01% 69.51% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu.op_class::MemRead 168002679 15.96% 85.48% # Class of executed instruction +system.cpu.op_class::MemWrite 152843199 14.52% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 982924991 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9370067 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.942718 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 290532688 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9370579 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 31.004774 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5830299500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.942718 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999888 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy +system.cpu.op_class::total 1052375619 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 10244350 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.965651 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 310416272 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 10244862 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 30.299703 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 3504161500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.965651 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999933 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999933 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 71 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1209437211 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1209437211 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 147248395 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 147248395 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 135579268 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 135579268 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 373548 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 373548 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 331872 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 331872 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3336329 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3336329 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3621011 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3621011 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 283159535 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 283159535 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 283533083 # number of overall hits -system.cpu.dcache.overall_hits::total 283533083 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4886658 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4886658 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1993718 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1993718 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1137538 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1137538 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1221988 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1221988 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 286320 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 286320 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 8102364 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8102364 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9239902 # number of overall misses -system.cpu.dcache.overall_misses::total 9239902 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 84160893500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 84160893500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 69982072000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 69982072000 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 48119896000 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 48119896000 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4409003500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4409003500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 162000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 162000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 202262861500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 202262861500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 202262861500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 202262861500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 152135053 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 152135053 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 137572986 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 137572986 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1511086 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1511086 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1553860 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1553860 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3622649 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3622649 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3621013 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3621013 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 291261899 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 291261899 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 292772985 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 292772985 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032121 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032121 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014492 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.014492 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.752795 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.752795 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786421 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.786421 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079036 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079036 # miss rate for LoadLockedReq accesses +system.cpu.dcache.tags.tag_accesses 1293353364 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1293353364 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 156944978 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 156944978 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 145025968 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 145025968 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 395817 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 395817 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 335163 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 335163 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3689072 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3689072 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3994801 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3994801 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 302306109 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 302306109 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 302701926 # number of overall hits +system.cpu.dcache.overall_hits::total 302701926 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 5326710 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 5326710 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2212553 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2212553 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1311764 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1311764 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1232866 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1232866 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 307422 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 307422 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 3 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 8772129 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8772129 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 10083893 # number of overall misses +system.cpu.dcache.overall_misses::total 10083893 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 84631439000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 84631439000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 66820707500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 66820707500 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 25293878500 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 25293878500 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4522600000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4522600000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 197000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 197000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 176746025000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 176746025000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 176746025000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 176746025000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 162271688 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 162271688 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 147238521 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 147238521 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1707581 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1707581 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1568029 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1568029 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3996494 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3996494 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3994804 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3994804 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 311078238 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 311078238 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 312785819 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 312785819 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032826 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032826 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015027 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015027 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.768200 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.768200 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786252 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.786252 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.076923 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.076923 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.027818 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.027818 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.031560 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.031560 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17222.587196 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17222.587196 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35101.289149 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35101.289149 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 39378.370328 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 39378.370328 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15398.866653 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15398.866653 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 81000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 81000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24963.438016 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24963.438016 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21890.152244 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21890.152244 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.028199 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.028199 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032239 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032239 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15888.125879 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15888.125879 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30200.726265 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30200.726265 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 20516.324159 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 20516.324159 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14711.373942 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14711.373942 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 65666.666667 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 65666.666667 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20148.589356 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20148.589356 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17527.558553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17527.558553 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 7310347 # number of writebacks -system.cpu.dcache.writebacks::total 7310347 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21149 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 21149 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21212 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 21212 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69210 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 69210 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 42361 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 42361 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 42361 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 42361 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 4865509 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 4865509 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1972506 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1972506 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1135773 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1135773 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1221988 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1221988 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 217110 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 217110 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 8060003 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 8060003 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9195776 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9195776 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 33702 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 67410 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 78024875000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 78024875000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67036106500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 67036106500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21307541000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21307541000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 46897908000 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 46897908000 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2989370500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2989370500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 160000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 160000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191958889500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 191958889500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213266430500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 213266430500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6199627500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6199627500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6199627500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6199627500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031982 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031982 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014338 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014338 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751627 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751627 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786421 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786421 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.059931 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.059931 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.writebacks::writebacks 7906430 # number of writebacks +system.cpu.dcache.writebacks::total 7906430 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21920 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 21920 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21246 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 21246 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70972 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 70972 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 43166 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 43166 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 43166 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 43166 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5304790 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5304790 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2191307 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2191307 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1309953 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1309953 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1232866 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1232866 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 236450 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 236450 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 3 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 8728963 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 8728963 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 10038916 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 10038916 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33706 # 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number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21083631000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 24061012500 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 24061012500 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3160913500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3160913500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 194000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 194000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 166774132000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 166774132000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187857763000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 187857763000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6233075000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6233075000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6233075000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6233075000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032691 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032691 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014883 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014883 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.767140 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.767140 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786252 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786252 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.059164 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.059164 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027673 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027673 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031409 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031409 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16036.323229 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16036.323229 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33985.248461 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33985.248461 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18760.386979 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18760.386979 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 38378.370328 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 38378.370328 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13768.921284 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13768.921284 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23816.230527 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23816.230527 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23191.781803 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23191.781803 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183954.290547 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183954.290547 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91968.958611 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91968.958611 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 13316326 # number of replacements -system.cpu.icache.tags.tagsinuse 511.820794 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 823138069 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 13316838 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 61.811826 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 49363844500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.820794 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999650 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999650 # Average percentage of cache occupancy +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028060 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028060 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032095 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032095 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14844.749462 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14844.749462 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29190.269095 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29190.269095 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16094.952262 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16094.952262 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 19516.324159 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 19516.324159 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13368.211038 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13368.211038 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 64666.666667 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 64666.666667 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19105.835596 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19105.835596 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18712.952972 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18712.952972 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184924.790838 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184924.790838 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92456.909339 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92456.909339 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 13792548 # number of replacements +system.cpu.icache.tags.tagsinuse 511.891104 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 881804526 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 13793060 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 63.931030 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 31603903500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.891104 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999787 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999787 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 200 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 849771755 # Number of tag accesses -system.cpu.icache.tags.data_accesses 849771755 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 823138069 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 823138069 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 823138069 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 823138069 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 823138069 # number of overall hits -system.cpu.icache.overall_hits::total 823138069 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13316843 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13316843 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13316843 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13316843 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13316843 # number of overall misses -system.cpu.icache.overall_misses::total 13316843 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 182043679500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 182043679500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 182043679500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 182043679500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 182043679500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 182043679500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 836454912 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 836454912 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 836454912 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 836454912 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 836454912 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 836454912 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015921 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015921 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015921 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015921 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015921 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015921 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13670.182903 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13670.182903 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13670.182903 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13670.182903 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13670.182903 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13670.182903 # average overall miss latency +system.cpu.icache.tags.tag_accesses 909390656 # Number of tag accesses +system.cpu.icache.tags.data_accesses 909390656 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 881804526 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 881804526 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 881804526 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 881804526 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 881804526 # number of overall hits +system.cpu.icache.overall_hits::total 881804526 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13793065 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13793065 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13793065 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13793065 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13793065 # number of overall misses +system.cpu.icache.overall_misses::total 13793065 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 185289814000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 185289814000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 185289814000 # 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number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 9521744500 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 9521744500 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 318149500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 314120500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5743922000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 58646443073 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 65022635073 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 318149500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 314120500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5743922000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 58646443073 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 65022635073 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2724311500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5810947000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8535258500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2724311500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5810947000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 8535258500 # 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mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.069317 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.029090 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007561 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010086 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005332 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.069317 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.029090 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126325.063078 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129154.593282 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127766.962260 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67939.425823 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67939.425823 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 121287.465079 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 121287.465079 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122456.389781 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122456.389781 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123386.224335 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123386.224335 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 67660.836582 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 67660.836582 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126325.063078 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129154.593282 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122456.389781 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 122122.717334 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 122202.413511 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126325.063078 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129154.593282 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122456.389781 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 122122.717334 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 122202.413511 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171430.404724 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138952.087157 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85707.573060 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96578.205998 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 45899412 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 23211953 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1753 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2701 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2701 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.242500 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.242500 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005697 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005697 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.040703 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.040703 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.413880 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.413880 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.011781 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.016831 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005697 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.089088 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.038021 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.011781 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.016831 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005697 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.089088 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.038021 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75966.929322 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 78314.759412 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77115.501890 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19066.354904 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19066.354904 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 53166.666667 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 53166.666667 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72151.110776 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72151.110776 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73099.278415 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73099.278415 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74728.074778 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74728.074778 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 18660.647163 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 18660.647163 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75966.929322 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 78314.759412 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73099.278415 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73046.183274 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73088.375882 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75966.929322 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 78314.759412 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73099.278415 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73046.183274 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73088.375882 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63172.440580 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172400.967187 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 111091.336830 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63172.440580 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86195.369052 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 77213.509015 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 48633709 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 24595755 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1745 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2030 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2030 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 979874 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 20515947 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8293329 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13316326 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2221598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 42266 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 42268 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1930243 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1930243 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 13316843 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6227282 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1328652 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1221988 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40036262 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28331504 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 601742 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 860807 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 69830315 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1704695316 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 989618926 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1959928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2516088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2698790258 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1604803 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 65712840 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 25003730 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.019507 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.138299 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 1068832 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 21713957 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 9029679 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13792548 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2522886 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 30473 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 30476 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2160837 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2160837 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 13793065 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6853863 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1261524 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1232866 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41464928 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30930790 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 605749 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 980040 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 73981507 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1765651732 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1083027398 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1906472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2843832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2853429434 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1738629 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 75129128 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 26510522 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.020074 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.140252 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 24515981 98.05% 98.05% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 487749 1.95% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 25978363 97.99% 97.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 532159 2.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 25003730 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 43858380000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 26510522 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 46319770000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1560894 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1608386 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20018389500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20732722500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 12905646976 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14200291468 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 356751000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 367440000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 546296000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 624561000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40338 # Transaction distribution -system.iobus.trans_dist::ReadResp 40338 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40312 # Transaction distribution +system.iobus.trans_dist::ReadResp 40312 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1312,11 +1298,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231034 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231034 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230982 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230982 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353818 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353766 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1331,16 +1317,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334360 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334360 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492488 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42150000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42148500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 322000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 320500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1348,9 +1334,9 @@ system.iobus.reqLayer4.occupancy 11000 # La system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) @@ -1358,75 +1344,75 @@ system.iobus.reqLayer16.occupancy 17000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25729000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25722000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38601000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38610500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 566926866 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 568931558 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147794000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147742000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115499 # number of replacements -system.iocache.tags.tagsinuse 10.446740 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115472 # number of replacements +system.iocache.tags.tagsinuse 10.457340 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115515 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115488 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13171623640000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 5.847996 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 4.598744 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.365500 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.287422 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.652921 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13153794616000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.511175 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.946165 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219448 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434135 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653584 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040010 # Number of tag accesses -system.iocache.tags.data_accesses 1040010 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039776 # Number of tag accesses +system.iocache.tags.data_accesses 1039776 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8853 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8890 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8827 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8864 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115517 # number of demand (read+write) misses -system.iocache.demand_misses::total 115557 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115491 # number of demand (read+write) misses +system.iocache.demand_misses::total 115531 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115517 # number of overall misses -system.iocache.overall_misses::total 115557 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5070500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1655174117 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1660244617 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115491 # number of overall misses +system.iocache.overall_misses::total 115531 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1606262152 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1611348152 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13409764249 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13409764249 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5421500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15064938366 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15070359866 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5421500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15064938366 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15070359866 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12771737406 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12771737406 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14377999558 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14383436558 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14377999558 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14383436558 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8853 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8890 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8827 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8864 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115517 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115557 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115491 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115531 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115517 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115557 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115491 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115531 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1440,53 +1426,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 186961.947024 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 186754.175141 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 181971.468449 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 181785.666968 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125719.682826 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125719.682826 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 130413.171793 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 130414.945577 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 130413.171793 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 130414.945577 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33045 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119738.031632 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 119738.031632 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124494.545532 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124498.503068 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124494.545532 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124498.503068 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31144 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3376 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3368 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.788211 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.247031 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106631 # number of writebacks -system.iocache.writebacks::total 106631 # number of writebacks +system.iocache.writebacks::writebacks 106630 # number of writebacks +system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8853 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8890 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8827 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8864 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115517 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115557 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115491 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115531 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115517 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115557 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1212524117 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1215744617 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115491 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115531 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1164912152 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1168148152 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8071395398 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8071395398 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3421500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9283919515 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9287341015 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3421500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9283919515 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9287341015 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7431704095 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7431704095 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8596616247 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8600053247 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8596616247 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8600053247 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1500,89 +1486,95 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136961.947024 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 136754.175141 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 131971.468449 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 131785.666968 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75671.223637 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75671.223637 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 80368.426422 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 80370.215694 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 80368.426422 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 80370.215694 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 76827 # Transaction distribution -system.membus.trans_dist::ReadResp 386363 # Transaction distribution -system.membus.trans_dist::WriteReq 33708 # Transaction distribution -system.membus.trans_dist::WriteResp 33708 # Transaction distribution -system.membus.trans_dist::WritebackDirty 982963 # Transaction distribution -system.membus.trans_dist::CleanEvict 160860 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33836 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7 # Transaction distribution -system.membus.trans_dist::ReadExReq 339489 # Transaction distribution -system.membus.trans_dist::ReadExResp 339489 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 309536 # Transaction distribution -system.membus.trans_dist::InvalidateReq 586610 # Transaction distribution +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69673.967740 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69673.967740 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 74435.378055 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 74439.356078 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74435.378055 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74439.356078 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 2941993 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1455813 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3308 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 76831 # Transaction distribution +system.membus.trans_dist::ReadResp 451336 # Transaction distribution +system.membus.trans_dist::WriteReq 33710 # Transaction distribution +system.membus.trans_dist::WriteResp 33710 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1229879 # Transaction distribution +system.membus.trans_dist::CleanEvict 192681 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4527 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 8 # Transaction distribution +system.membus.trans_dist::ReadExReq 523443 # Transaction distribution +system.membus.trans_dist::ReadExResp 523443 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 374505 # Transaction distribution +system.membus.trans_dist::InvalidateReq 616914 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6930 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2913100 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3042792 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237470 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237470 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3280262 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3690757 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3820461 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237403 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237403 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4057864 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13860 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 97205216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 97375042 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7234880 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7234880 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 104609922 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3136 # Total snoops (count) -system.membus.snoopTraffic 200256 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2523850 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 128940576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 129110426 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7233920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7233920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 136344346 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3126 # Total snoops (count) +system.membus.snoopTraffic 199552 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1629933 # Request fanout histogram +system.membus.snoop_fanout::mean 0.019638 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.138754 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2523850 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1597924 98.04% 98.04% # Request fanout histogram +system.membus.snoop_fanout::1 32009 1.96% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2523850 # Request fanout histogram -system.membus.reqLayer0.occupancy 106906000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1629933 # Request fanout histogram +system.membus.reqLayer0.occupancy 106906500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5727500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5804000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 6514212892 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8036011189 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3604018785 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4923968289 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44774812 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44661763 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1625,28 +1617,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51820894502500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt index 233e6de0a..2d1d5d137 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111167 # Nu sim_ticks 51111167268500 # Number of ticks simulated final_tick 51111167268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 810187 # Simulator instruction rate (inst/s) -host_op_rate 952145 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42160127212 # Simulator tick rate (ticks/s) -host_mem_usage 675168 # Number of bytes of host memory used -host_seconds 1212.31 # Real time elapsed on the host +host_inst_rate 933162 # Simulator instruction rate (inst/s) +host_op_rate 1096667 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48559439795 # Simulator tick rate (ticks/s) +host_mem_usage 681072 # Number of bytes of host memory used +host_seconds 1052.55 # Real time elapsed on the host sim_insts 982198023 # Number of instructions simulated sim_ops 1154295627 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -16,60 +16,60 @@ system.clk_domain.clock 1000 # Cl system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 206336 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 188224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3277940 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 38030472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3278004 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 38031624 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 207616 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 185152 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 2205440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 36882176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 36882368 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory -system.physmem.bytes_read::total 81620156 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3277940 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 81621564 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3278004 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 2205440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5483380 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103277952 # Number of bytes written to this memory +system.physmem.bytes_inst_read::total 5483444 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103278592 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103298532 # Number of bytes written to this memory +system.physmem.bytes_written::total 103299172 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 3224 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2941 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 91625 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 594239 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 91626 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 594257 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 3244 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 2893 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 34460 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 576284 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 576287 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1315735 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1613718 # Number of write requests responded to by this memory +system.physmem.num_reads::total 1315757 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1613728 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1616291 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1616301 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 4037 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 3683 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 64134 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 744074 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 64135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 744096 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 4062 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 3623 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 43150 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 721607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 721611 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1596914 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 64134 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1596942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 64135 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 43150 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 107283 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2020653 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107285 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2020666 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2021056 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2020653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2021069 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2020666 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 4037 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 3683 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 64134 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 744476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 64135 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 744499 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 4062 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 3623 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 43150 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 721607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 721611 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3617970 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3618010 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -338,9 +338,9 @@ system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51111167268500 system.cpu0.dcache.ReadReq_hits::cpu0.data 85600060 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 85509890 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 171109950 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 79543301 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 79530135 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 159073436 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 79551757 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 79538240 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 159089997 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 209327 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::cpu1.data 214988 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 424315 # number of SoftPFReq hits @@ -353,18 +353,18 @@ system.cpu0.dcache.LoadLockedReq_hits::total 4303549 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2274909 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2280735 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 4555644 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 165287591 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 165232078 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 330519669 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 165496918 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 165447066 # number of overall hits -system.cpu0.dcache.overall_hits::total 330943984 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 165296047 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 165240183 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 330536230 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 165505374 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 165455171 # number of overall hits +system.cpu0.dcache.overall_hits::total 330960545 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 3016323 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu1.data 2986728 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 6003051 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1295379 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1272732 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2568111 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1286923 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1264627 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2551550 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 788168 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::cpu1.data 797714 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 1585882 # number of SoftPFReq misses @@ -376,12 +376,12 @@ system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 127105 system.cpu0.dcache.LoadLockedReq_misses::total 253898 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5073259 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 4744675 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 9817934 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5861427 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 5542389 # number of overall misses -system.cpu0.dcache.overall_misses::total 11403816 # number of overall misses +system.cpu0.dcache.demand_misses::cpu0.data 5064803 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 4736570 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 9801373 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5852971 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 5534284 # number of overall misses +system.cpu0.dcache.overall_misses::total 11387255 # number of overall misses system.cpu0.dcache.ReadReq_accesses::cpu0.data 88616383 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu1.data 88496618 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 177113001 # number of ReadReq accesses(hits+misses) @@ -409,9 +409,9 @@ system.cpu0.dcache.overall_accesses::total 342347800 # system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.034038 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033750 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.033894 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016024 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015751 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.015888 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015920 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015651 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.015785 # miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.790147 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.787709 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788919 # miss rate for SoftPFReq accesses @@ -423,20 +423,20 @@ system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.055708 system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055711 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000000 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029779 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.027914 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.028848 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.034206 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.032414 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.033311 # miss rate for overall accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029730 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.027866 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.028799 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.034156 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.032366 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.033262 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 8916863 # number of writebacks -system.cpu0.dcache.writebacks::total 8916863 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 8918956 # number of writebacks +system.cpu0.dcache.writebacks::total 8918956 # number of writebacks system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.cpu0.icache.tags.replacements 14265255 # number of replacements system.cpu0.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use @@ -829,138 +829,138 @@ system.iocache.avg_blocked_cycles::no_targets nan system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1725785 # number of replacements -system.l2c.tags.tagsinuse 65319.566840 # Cycle average of tags in use -system.l2c.tags.total_refs 46977185 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1788801 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 26.261828 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37198.027902 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 157.533597 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 243.219072 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3426.787378 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9571.465720 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 153.009111 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 207.682961 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2648.640796 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 11713.200303 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.567597 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002404 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003711 # Average percentage of cache occupancy +system.l2c.tags.replacements 1725813 # number of replacements +system.l2c.tags.tagsinuse 65403.901917 # Cycle average of tags in use +system.l2c.tags.total_refs 49468109 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1788889 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 27.652978 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 395496000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 9615.108088 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 224.707200 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 268.802991 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3426.785629 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 22887.229719 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 209.300949 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 228.038258 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2648.603044 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 25895.326039 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.146715 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003429 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.004102 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.052289 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.146049 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002335 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003169 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.040415 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.178729 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996697 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 315 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62701 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 315 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 608 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2778 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4924 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54255 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.004807 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.956741 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 426273955 # Number of tag accesses -system.l2c.tags.data_accesses 426273955 # Number of data accesses +system.l2c.tags.occ_percent::cpu0.data 0.349231 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003194 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003480 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.040414 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.395131 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.997984 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 371 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62705 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 371 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1444 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5122 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55700 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.005661 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.956802 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 423190040 # Number of tag accesses +system.l2c.tags.data_accesses 423190040 # Number of data accesses system.l2c.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.l2c.ReadReq_hits::cpu0.dtb.walker 280712 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 145885 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 277418 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 142199 # number of ReadReq hits -system.l2c.ReadReq_hits::total 846214 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 8916863 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 8916863 # number of WritebackDirty hits +system.l2c.ReadReq_hits::cpu0.dtb.walker 265559 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 135827 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 262154 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 132135 # number of ReadReq hits +system.l2c.ReadReq_hits::total 795675 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 8918956 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 8918956 # number of WritebackDirty hits system.l2c.WritebackClean_hits::writebacks 14263678 # number of WritebackClean hits system.l2c.WritebackClean_hits::total 14263678 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 5752 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 5452 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 11204 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 852175 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 837197 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1689372 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 7090160 # number of ReadCleanReq hits +system.l2c.UpgradeReq_hits::cpu0.data 15680 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 15013 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 30693 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 852174 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 837196 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1689370 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 7090159 # number of ReadCleanReq hits system.l2c.ReadCleanReq_hits::cpu1.inst 7092615 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 14182775 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 3753750 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 3744981 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 7498731 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 340284 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 354276 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 694560 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 280712 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 145885 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 7090160 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 4605925 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 277418 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 142199 # number of demand (read+write) hits +system.l2c.ReadCleanReq_hits::total 14182774 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 3753733 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 3744979 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 7498712 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 340283 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 354274 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 694557 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 265559 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 135827 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 7090159 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 4605907 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 262154 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 132135 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 7092615 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4582178 # number of demand (read+write) hits -system.l2c.demand_hits::total 24217092 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 280712 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 145885 # number of overall hits -system.l2c.overall_hits::cpu0.inst 7090160 # number of overall hits -system.l2c.overall_hits::cpu0.data 4605925 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 277418 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 142199 # number of overall hits +system.l2c.demand_hits::cpu1.data 4582175 # number of demand (read+write) hits +system.l2c.demand_hits::total 24166531 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 265559 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 135827 # number of overall hits +system.l2c.overall_hits::cpu0.inst 7090159 # number of overall hits +system.l2c.overall_hits::cpu0.data 4605907 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 262154 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 132135 # number of overall hits system.l2c.overall_hits::cpu1.inst 7092615 # number of overall hits -system.l2c.overall_hits::cpu1.data 4582178 # number of overall hits -system.l2c.overall_hits::total 24217092 # number of overall hits +system.l2c.overall_hits::cpu1.data 4582175 # number of overall hits +system.l2c.overall_hits::total 24166531 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 3224 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2941 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 3244 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 2893 # number of ReadReq misses system.l2c.ReadReq_misses::total 12302 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 20291 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 19639 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 39930 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1907 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1973 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3880 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 417161 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 410444 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 827605 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 48524 # number of ReadCleanReq misses +system.l2c.ReadExReq_misses::cpu0.data 417162 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 410445 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 827607 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 48525 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::cpu1.inst 34473 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 82997 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 177534 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 166566 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 344100 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 421273 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 130939 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 552212 # number of InvalidateReq misses +system.l2c.ReadCleanReq_misses::total 82998 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 177551 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 166568 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 344119 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 421274 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 130941 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 552215 # number of InvalidateReq misses system.l2c.demand_misses::cpu0.dtb.walker 3224 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2941 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 48524 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 594695 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 48525 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 594713 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 3244 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 2893 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 34473 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 577010 # number of demand (read+write) misses -system.l2c.demand_misses::total 1267004 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 577013 # number of demand (read+write) misses +system.l2c.demand_misses::total 1267026 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 3224 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2941 # number of overall misses -system.l2c.overall_misses::cpu0.inst 48524 # number of overall misses -system.l2c.overall_misses::cpu0.data 594695 # number of overall misses +system.l2c.overall_misses::cpu0.inst 48525 # number of overall misses +system.l2c.overall_misses::cpu0.data 594713 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 3244 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 2893 # number of overall misses system.l2c.overall_misses::cpu1.inst 34473 # number of overall misses -system.l2c.overall_misses::cpu1.data 577010 # number of overall misses -system.l2c.overall_misses::total 1267004 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 283936 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 148826 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 280662 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 145092 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 858516 # number of ReadReq accesses(hits+misses) -system.l2c.WritebackDirty_accesses::writebacks 8916863 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 8916863 # number of WritebackDirty accesses(hits+misses) +system.l2c.overall_misses::cpu1.data 577013 # number of overall misses +system.l2c.overall_misses::total 1267026 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 268783 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 138768 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 265398 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 135028 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 807977 # number of ReadReq accesses(hits+misses) +system.l2c.WritebackDirty_accesses::writebacks 8918956 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 8918956 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackClean_accesses::writebacks 14263678 # number of WritebackClean accesses(hits+misses) system.l2c.WritebackClean_accesses::total 14263678 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 26043 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 25091 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 51134 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 17587 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 16986 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 34573 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 1 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 1269336 # number of ReadExReq accesses(hits+misses) @@ -975,122 +975,122 @@ system.l2c.ReadSharedReq_accesses::total 7842831 # nu system.l2c.InvalidateReq_accesses::cpu0.data 761557 # number of InvalidateReq accesses(hits+misses) system.l2c.InvalidateReq_accesses::cpu1.data 485215 # number of InvalidateReq accesses(hits+misses) system.l2c.InvalidateReq_accesses::total 1246772 # number of InvalidateReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 283936 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 148826 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.dtb.walker 268783 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 138768 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.inst 7138684 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 5200620 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 280662 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 145092 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 265398 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 135028 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 7127088 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 5159188 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 25484096 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 283936 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 148826 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 25433557 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 268783 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 138768 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.inst 7138684 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 5200620 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 280662 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 145092 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 265398 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 135028 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 7127088 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 5159188 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 25484096 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.011355 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.019761 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.011558 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.019939 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.014329 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.779135 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.782711 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.780889 # miss rate for UpgradeReq accesses +system.l2c.overall_accesses::total 25433557 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.011995 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.021194 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.012223 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.021425 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.015226 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.108432 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.116154 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.112226 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.328645 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.328976 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.328809 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.328646 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.328977 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.328810 # miss rate for ReadExReq accesses system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006797 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004837 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::total 0.005818 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.045159 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.042583 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.043874 # miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_miss_rate::cpu0.data 0.553173 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::cpu1.data 0.269858 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::total 0.442913 # miss rate for InvalidateReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.011355 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.019761 # miss rate for demand accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.045164 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.042584 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.043877 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.553175 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.269862 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.442916 # miss rate for InvalidateReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.011995 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.021194 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.006797 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.114351 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.011558 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.019939 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.114354 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.012223 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.021425 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.004837 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.111841 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.049717 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.011355 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.019761 # miss rate for overall accesses +system.l2c.demand_miss_rate::cpu1.data 0.111842 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.049817 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.011995 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.021194 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.006797 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.114351 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.011558 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.019939 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.114354 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.012223 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.021425 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.004837 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.111841 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.049717 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.111842 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.049817 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 1507087 # number of writebacks -system.l2c.writebacks::total 1507087 # number of writebacks -system.membus.snoop_filter.tot_requests 3814674 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1911370 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.writebacks::writebacks 1507097 # number of writebacks +system.l2c.writebacks::total 1507097 # number of writebacks +system.membus.snoop_filter.tot_requests 3778676 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1875347 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 2861 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 76679 # Transaction distribution -system.membus.trans_dist::ReadResp 524928 # Transaction distribution +system.membus.trans_dist::ReadResp 524948 # Transaction distribution system.membus.trans_dist::WriteReq 33606 # Transaction distribution system.membus.trans_dist::WriteResp 33606 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1613718 # Transaction distribution -system.membus.trans_dist::CleanEvict 226292 # Transaction distribution -system.membus.trans_dist::UpgradeReq 40497 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1613728 # Transaction distribution +system.membus.trans_dist::CleanEvict 226309 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4447 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 40498 # Transaction distribution -system.membus.trans_dist::ReadExReq 827048 # Transaction distribution -system.membus.trans_dist::ReadExResp 827048 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 448249 # Transaction distribution -system.membus.trans_dist::InvalidateReq 658869 # Transaction distribution -system.membus.trans_dist::InvalidateResp 658869 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4448 # Transaction distribution +system.membus.trans_dist::ReadExReq 827050 # Transaction distribution +system.membus.trans_dist::ReadExResp 827050 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 448269 # Transaction distribution +system.membus.trans_dist::InvalidateReq 658872 # Transaction distribution +system.membus.trans_dist::InvalidateResp 658872 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5534223 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5663415 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5462200 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5591392 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346493 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 346493 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6009908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5937885 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 177699296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 177868346 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 177701344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 177870394 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 185259130 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 185261178 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3924959 # Request fanout histogram -system.membus.snoop_fanout::mean 0.009320 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.096090 # Request fanout histogram +system.membus.snoop_fanout::samples 3888961 # Request fanout histogram +system.membus.snoop_fanout::mean 0.009406 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.096529 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3888378 99.07% 99.07% # Request fanout histogram -system.membus.snoop_fanout::1 36581 0.93% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3852380 99.06% 99.06% # Request fanout histogram +system.membus.snoop_fanout::1 36581 0.94% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3924959 # Request fanout histogram +system.membus.snoop_fanout::total 3888961 # Request fanout histogram system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states @@ -1171,23 +1171,23 @@ system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 52404582 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 26532237 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 52388021 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 26515676 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2694 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2694 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 1320370 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 23428973 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 8916863 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 8918956 # Transaction distribution system.toL2Bus.trans_dist::WritebackClean 14265255 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2689192 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 51134 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2687099 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 34573 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 51135 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 34574 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 2516977 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 2516977 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 14265772 # Transaction distribution @@ -1195,27 +1195,27 @@ system.toL2Bus.trans_dist::ReadSharedReq 7842831 # Tr system.toL2Bus.trans_dist::InvalidateReq 1246772 # Transaction distribution system.toL2Bus.trans_dist::InvalidateResp 1246772 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 42883049 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35055805 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35022683 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 830232 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1657150 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 80426236 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 80393114 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1826158228 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1233896614 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1234030566 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3320928 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6628600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 3070004370 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1762480 # Total snoops (count) -system.toL2Bus.snoopTraffic 96494080 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 54910458 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.011218 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.105318 # Request fanout histogram +system.toL2Bus.pkt_size::total 3070138322 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1762508 # Total snoops (count) +system.toL2Bus.snoopTraffic 96494720 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 54893925 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.011221 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.105334 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 54294485 98.88% 98.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 615973 1.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 54277951 98.88% 98.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 615974 1.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 54910458 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 54893925 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt index aa5265b3e..7b0e2ea39 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt @@ -1,193 +1,193 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.316261 # Number of seconds simulated -sim_ticks 51316261201000 # Number of ticks simulated -final_tick 51316261201000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.316276 # Number of seconds simulated +sim_ticks 51316275690000 # Number of ticks simulated +final_tick 51316275690000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 303672 # Simulator instruction rate (inst/s) -host_op_rate 356843 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18193830206 # Simulator tick rate (ticks/s) -host_mem_usage 686184 # Number of bytes of host memory used -host_seconds 2820.53 # Real time elapsed on the host -sim_insts 856517636 # Number of instructions simulated -sim_ops 1006486660 # Number of ops (including micro ops) simulated +host_inst_rate 326587 # Simulator instruction rate (inst/s) +host_op_rate 383768 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19561029283 # Simulator tick rate (ticks/s) +host_mem_usage 692584 # Number of bytes of host memory used +host_seconds 2623.39 # Real time elapsed on the host +sim_insts 856765339 # Number of instructions simulated +sim_ops 1006773904 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 89408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 88064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2284980 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 19216392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 19648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 18624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 651264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5282880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 33920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 30784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 1695808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 7120960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.dtb.walker 74240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.itb.walker 63168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 1609856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 11459776 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 417920 # Number of bytes read from this memory -system.physmem.bytes_read::total 50157692 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2284980 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 651264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 1695808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 1609856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6241908 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 69878272 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 86272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 86656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2383476 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 19569480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 22528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 19008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 645440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5197376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 31936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 29376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 1640192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 6901376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 81152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.itb.walker 66816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 1624448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 11589312 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 437504 # Number of bytes read from this memory +system.physmem.bytes_read::total 50412348 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2383476 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 645440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 1640192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 1624448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6293556 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70023744 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 69898852 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1397 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1376 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 76110 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 300269 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 307 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 291 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 10176 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82545 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 530 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 481 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 26497 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 111265 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.dtb.walker 1160 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.itb.walker 987 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 25154 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 179059 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6530 # Number of read requests responded to by this memory -system.physmem.num_reads::total 824134 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1091848 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 70044324 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1348 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1354 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 77649 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 305786 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 352 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 297 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10085 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81209 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 499 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 459 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 25628 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 107834 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 1268 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.itb.walker 1044 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 25382 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 181083 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6836 # Number of read requests responded to by this memory +system.physmem.num_reads::total 828113 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1094121 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1094421 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1742 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1716 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 44527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 374470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 383 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 12691 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 102947 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 661 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 600 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 33046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 138766 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.dtb.walker 1447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.itb.walker 1231 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 31371 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 223317 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8144 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 977423 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 44527 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 12691 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 33046 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 31371 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 121636 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1361718 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1096694 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1681 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1689 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 46447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 381350 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 370 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 12578 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 101281 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 31962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 134487 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 1581 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.itb.walker 1302 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 31656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 225841 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8526 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 982385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 46447 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 12578 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 31962 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 31656 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 122642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1364552 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1362119 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1361718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1742 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 44527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 374871 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 383 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 12691 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 102947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 661 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 33046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 138766 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.dtb.walker 1447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.itb.walker 1231 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 31371 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 223317 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8144 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2339542 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 438929 # Number of read requests accepted -system.physmem.writeReqs 487711 # Number of write requests accepted -system.physmem.readBursts 438929 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 487711 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28073280 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18176 # Total number of bytes read from write queue -system.physmem.bytesWritten 31211968 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28091456 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 31213504 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 284 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1364953 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1364552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1689 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 46447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 381751 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 370 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 12578 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 101281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 31962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 134487 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 1581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.itb.walker 1302 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 31656 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 225841 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2347339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 435200 # Number of read requests accepted +system.physmem.writeReqs 483804 # Number of write requests accepted +system.physmem.readBursts 435200 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 483804 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27836736 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 16064 # Total number of bytes read from write queue +system.physmem.bytesWritten 30961600 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27852800 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 30963456 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 251 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25285 # Per bank write bursts -system.physmem.perBankRdBursts::1 29259 # Per bank write bursts -system.physmem.perBankRdBursts::2 26350 # Per bank write bursts -system.physmem.perBankRdBursts::3 25668 # Per bank write bursts -system.physmem.perBankRdBursts::4 27357 # Per bank write bursts -system.physmem.perBankRdBursts::5 30719 # Per bank write bursts -system.physmem.perBankRdBursts::6 26473 # Per bank write bursts -system.physmem.perBankRdBursts::7 28031 # Per bank write bursts -system.physmem.perBankRdBursts::8 25079 # Per bank write bursts -system.physmem.perBankRdBursts::9 30131 # Per bank write bursts -system.physmem.perBankRdBursts::10 27758 # Per bank write bursts -system.physmem.perBankRdBursts::11 30805 # Per bank write bursts -system.physmem.perBankRdBursts::12 27043 # Per bank write bursts -system.physmem.perBankRdBursts::13 27394 # Per bank write bursts -system.physmem.perBankRdBursts::14 24672 # Per bank write bursts -system.physmem.perBankRdBursts::15 26621 # Per bank write bursts -system.physmem.perBankWrBursts::0 26756 # Per bank write bursts -system.physmem.perBankWrBursts::1 29816 # Per bank write bursts -system.physmem.perBankWrBursts::2 28574 # Per bank write bursts -system.physmem.perBankWrBursts::3 30074 # Per bank write bursts -system.physmem.perBankWrBursts::4 31364 # Per bank write bursts -system.physmem.perBankWrBursts::5 33348 # Per bank write bursts -system.physmem.perBankWrBursts::6 29983 # Per bank write bursts -system.physmem.perBankWrBursts::7 32184 # Per bank write bursts -system.physmem.perBankWrBursts::8 30191 # Per bank write bursts -system.physmem.perBankWrBursts::9 34064 # Per bank write bursts -system.physmem.perBankWrBursts::10 29741 # Per bank write bursts -system.physmem.perBankWrBursts::11 31916 # Per bank write bursts -system.physmem.perBankWrBursts::12 29919 # Per bank write bursts -system.physmem.perBankWrBursts::13 30461 # Per bank write bursts -system.physmem.perBankWrBursts::14 29114 # Per bank write bursts -system.physmem.perBankWrBursts::15 30182 # Per bank write bursts +system.physmem.perBankRdBursts::0 27905 # Per bank write bursts +system.physmem.perBankRdBursts::1 28763 # Per bank write bursts +system.physmem.perBankRdBursts::2 27094 # Per bank write bursts +system.physmem.perBankRdBursts::3 24985 # Per bank write bursts +system.physmem.perBankRdBursts::4 26681 # Per bank write bursts +system.physmem.perBankRdBursts::5 30728 # Per bank write bursts +system.physmem.perBankRdBursts::6 26238 # Per bank write bursts +system.physmem.perBankRdBursts::7 28208 # Per bank write bursts +system.physmem.perBankRdBursts::8 24817 # Per bank write bursts +system.physmem.perBankRdBursts::9 29447 # Per bank write bursts +system.physmem.perBankRdBursts::10 28003 # Per bank write bursts +system.physmem.perBankRdBursts::11 29718 # Per bank write bursts +system.physmem.perBankRdBursts::12 26417 # Per bank write bursts +system.physmem.perBankRdBursts::13 26875 # Per bank write bursts +system.physmem.perBankRdBursts::14 23221 # Per bank write bursts +system.physmem.perBankRdBursts::15 25849 # Per bank write bursts +system.physmem.perBankWrBursts::0 29439 # Per bank write bursts +system.physmem.perBankWrBursts::1 30169 # Per bank write bursts +system.physmem.perBankWrBursts::2 29222 # Per bank write bursts +system.physmem.perBankWrBursts::3 30308 # Per bank write bursts +system.physmem.perBankWrBursts::4 30582 # Per bank write bursts +system.physmem.perBankWrBursts::5 32929 # Per bank write bursts +system.physmem.perBankWrBursts::6 29622 # Per bank write bursts +system.physmem.perBankWrBursts::7 32397 # Per bank write bursts +system.physmem.perBankWrBursts::8 29255 # Per bank write bursts +system.physmem.perBankWrBursts::9 32999 # Per bank write bursts +system.physmem.perBankWrBursts::10 30308 # Per bank write bursts +system.physmem.perBankWrBursts::11 31541 # Per bank write bursts +system.physmem.perBankWrBursts::12 29215 # Per bank write bursts +system.physmem.perBankWrBursts::13 29346 # Per bank write bursts +system.physmem.perBankWrBursts::14 27349 # Per bank write bursts +system.physmem.perBankWrBursts::15 29094 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 51315260920500 # Total gap between requests +system.physmem.numWrRetry 19 # Number of times write queue was full causing retry +system.physmem.totGap 51315275469000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 438929 # Read request sizes (log2) +system.physmem.readPktSize::6 435200 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 487711 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 342866 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 67593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8245 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 44 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 89 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 483804 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 339047 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 67972 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19489 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8325 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -199,185 +199,191 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 569 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 581 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 556 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 551 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 10806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 21548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 23833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 26317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 27236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 28042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 28569 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 29592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 29655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 30940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 31802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 30047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 29665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 30409 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 27749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 27223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 26642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 10688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 12645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 21314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 23642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 26112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 26953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 27836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 28305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 29478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 29464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 30830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 31587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 29857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 29451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 30076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 27393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 27014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 26345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 203 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 18 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 279155 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 212.371879 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.666378 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 251.561006 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 134237 48.09% 48.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 73368 26.28% 74.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 25102 8.99% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 12608 4.52% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 8433 3.02% 90.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 5025 1.80% 92.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3984 1.43% 94.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2939 1.05% 95.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 13459 4.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 279155 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 26191 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.746211 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 10.447790 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-15 9423 35.98% 35.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16-31 15107 57.68% 93.66% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::32-47 1332 5.09% 98.74% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::48-63 231 0.88% 99.63% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::64-79 66 0.25% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::80-95 23 0.09% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::96-111 3 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::112-127 2 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::128-143 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::144-159 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-271 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::384-399 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 26191 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 26191 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.620404 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.778521 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 9.884507 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-7 23 0.09% 0.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-15 48 0.18% 0.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 24431 93.28% 93.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 637 2.43% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 499 1.91% 97.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 119 0.45% 98.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 74 0.28% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 52 0.20% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 187 0.71% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 21 0.08% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 13 0.05% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.02% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 5 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 20 0.08% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 7 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 6 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 18 0.07% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 7 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 4 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 2 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::46 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 59 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 275230 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 213.631363 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 134.345796 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 252.466079 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 131747 47.87% 47.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 72284 26.26% 74.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 24873 9.04% 83.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12745 4.63% 87.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8355 3.04% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4904 1.78% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4003 1.45% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2900 1.05% 95.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 13419 4.88% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 275230 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 25971 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.744908 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 10.064212 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-7 4094 15.76% 15.76% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8-15 5177 19.93% 35.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16-23 12484 48.07% 83.77% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24-31 2573 9.91% 93.67% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32-39 911 3.51% 97.18% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40-47 410 1.58% 98.76% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::48-55 151 0.58% 99.34% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::56-63 87 0.33% 99.68% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::64-71 41 0.16% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::72-79 17 0.07% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::80-87 14 0.05% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::88-95 7 0.03% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::96-103 1 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::136-143 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::144-151 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::208-215 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 25971 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 25971 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.627508 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.774611 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 9.820731 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-7 27 0.10% 0.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-15 58 0.22% 0.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 24184 93.12% 93.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 657 2.53% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 512 1.97% 97.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 109 0.42% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 61 0.23% 98.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 50 0.19% 98.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 187 0.72% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 29 0.11% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 13 0.05% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 6 0.02% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 4 0.02% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 13 0.05% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 7 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 7 0.03% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 17 0.07% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 7 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 5 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 4 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 2 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::240-247 1 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::248-255 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 2 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-311 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::488-495 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 26191 # Writes before turning the bus around for reads -system.physmem.totQLat 8271276046 # Total ticks spent queuing -system.physmem.totMemAccLat 16495869796 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2193225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18856.42 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::256-263 3 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::312-319 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 25971 # Writes before turning the bus around for reads +system.physmem.totQLat 8284996307 # Total ticks spent queuing +system.physmem.totMemAccLat 16440290057 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2174745000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19048.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37606.42 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.55 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.61 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.55 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.61 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37798.20 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.54 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.54 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.60 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.01 # Data bus utilization in percentage system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.58 # Average write queue length when enqueuing -system.physmem.readRowHits 320460 # Number of row buffer hits during reads -system.physmem.writeRowHits 326715 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.06 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.99 # Row buffer hit rate for writes -system.physmem.avgGap 55377774.45 # Average gap between requests -system.physmem.pageHitRate 69.86 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1063933920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 578980875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1709237400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1568801520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3313030902480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1175120467920 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 30458927805750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34952000129865 # Total energy per rank (pJ) -system.physmem_0.averagePower 665.969400 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 48914934224726 # Time in different power states -system.physmem_0.memoryStateTime::REF 1693778580000 # Time in different power states +system.physmem.avgWrQLen 8.48 # Average write queue length when enqueuing +system.physmem.readRowHits 317706 # Number of row buffer hits during reads +system.physmem.writeRowHits 325786 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.04 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 67.34 # Row buffer hit rate for writes +system.physmem.avgGap 55837923.96 # Average gap between requests +system.physmem.pageHitRate 70.04 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1063034280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 578527125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1720625400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1585448640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3313031919600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1176100438995 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29681595659250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34175675653290 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.640087 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 48913549174000 # Time in different power states +system.physmem_0.memoryStateTime::REF 1693779100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 115598736274 # Time in different power states +system.physmem_0.memoryStateTime::ACT 116961174250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1046477880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 569311875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1712123400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 1591410240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3313030902480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1175283684855 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29689572406500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34182806317230 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.621570 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 48914700007992 # Time in different power states -system.physmem_1.memoryStateTime::REF 1693778580000 # Time in different power states +system.physmem_1.actEnergy 1017704520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 553591500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1671906600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 1549413360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3313031919600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1173827506995 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29683698941250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34175350983825 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.631365 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 48916914851742 # Time in different power states +system.physmem_1.memoryStateTime::REF 1693779100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 115815403258 # Time in different power states +system.physmem_1.memoryStateTime::ACT 113597968758 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -394,9 +400,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -404,7 +410,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -434,49 +440,49 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 91599 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 91599 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 91599 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 91599 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 91599 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 396804151420 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.489246 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -194134706080 -48.92% -48.92% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 590938857500 148.92% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 396804151420 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 67399 85.01% 85.01% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 11889 14.99% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 79288 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 91599 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 90923 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 90923 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 90923 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 90923 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 90923 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 396801198420 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.489265 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -194140819580 -48.93% -48.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 590942018000 148.93% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 396801198420 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 66800 85.03% 85.03% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 11762 14.97% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 78562 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 90923 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 91599 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 79288 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 90923 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 78562 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 79288 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 170887 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 78562 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 169485 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 64302418 # DTB read hits -system.cpu0.dtb.read_misses 69160 # DTB read misses -system.cpu0.dtb.write_hits 58215557 # DTB write hits -system.cpu0.dtb.write_misses 22439 # DTB write misses +system.cpu0.dtb.read_hits 64271568 # DTB read hits +system.cpu0.dtb.read_misses 68949 # DTB read misses +system.cpu0.dtb.write_hits 58335276 # DTB write hits +system.cpu0.dtb.write_misses 21974 # DTB write misses system.cpu0.dtb.flush_tlb 1189 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 16108 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 410 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 41969 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 16131 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 408 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 41721 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2769 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 2805 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 7637 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 64371578 # DTB read accesses -system.cpu0.dtb.write_accesses 58237996 # DTB write accesses +system.cpu0.dtb.perms_faults 7542 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 64340517 # DTB read accesses +system.cpu0.dtb.write_accesses 58357250 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 122517975 # DTB hits -system.cpu0.dtb.misses 91599 # DTB misses -system.cpu0.dtb.accesses 122609574 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 122606844 # DTB hits +system.cpu0.dtb.misses 90923 # DTB misses +system.cpu0.dtb.accesses 122697767 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -506,54 +512,54 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 53904 # Table walker walks requested -system.cpu0.itb.walker.walksLong 53904 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 53904 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 53904 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 53904 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 396804151420 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.489341 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -194172707080 -48.93% -48.93% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 590976858500 148.93% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 396804151420 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 47053 95.04% 95.04% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2454 4.96% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 49507 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 54169 # Table walker walks requested +system.cpu0.itb.walker.walksLong 54169 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 54169 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 54169 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 54169 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 396801198420 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.489353 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -194175666580 -48.94% -48.94% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 590976865000 148.94% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 396801198420 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 47334 95.01% 95.01% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2486 4.99% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 49820 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53904 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53904 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 54169 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 54169 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 49507 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 49507 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 103411 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 341562377 # ITB inst hits -system.cpu0.itb.inst_misses 53904 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 49820 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 49820 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 103989 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 341484641 # ITB inst hits +system.cpu0.itb.inst_misses 54169 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 1189 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 16108 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 410 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 29855 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 16131 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 408 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 29832 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 341616281 # ITB inst accesses -system.cpu0.itb.hits 341562377 # DTB hits -system.cpu0.itb.misses 53904 # DTB misses -system.cpu0.itb.accesses 341616281 # DTB accesses -system.cpu0.numPwrStateTransitions 12142 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 6071 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 8248096077.910065 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 210376306672.099670 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 2573 42.38% 42.38% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 3474 57.22% 99.60% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 341538810 # ITB inst accesses +system.cpu0.itb.hits 341484641 # DTB hits +system.cpu0.itb.misses 54169 # DTB misses +system.cpu0.itb.accesses 341538810 # DTB accesses +system.cpu0.numPwrStateTransitions 12198 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 6099 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 8210231821.367437 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 209893503926.618408 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 2601 42.65% 42.65% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 3474 56.96% 99.61% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::5e+10-1e+11 5 0.08% 99.69% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 4 0.07% 99.77% # Distribution of time spent in the clock gated state @@ -563,652 +569,652 @@ system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.84 system.cpu0.pwrStateClkGateDist::8.5e+11-9e+11 1 0.02% 99.85% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::overflows 9 0.15% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 7947193303500 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 6071 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 1242069912008 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 50074191288992 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 412426852 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 7947193321500 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 6099 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 1242071811480 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 50074203878520 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 412415124 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16568 # number of quiesce instructions executed -system.cpu0.committedInsts 341412971 # Number of instructions committed -system.cpu0.committedOps 401608369 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 368837990 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 362244 # Number of float alu accesses -system.cpu0.num_func_calls 20461819 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 51941822 # number of instructions that are conditional controls -system.cpu0.num_int_insts 368837990 # number of integer instructions -system.cpu0.num_fp_insts 362244 # number of float instructions -system.cpu0.num_int_register_reads 539535569 # number of times the integer registers were read -system.cpu0.num_int_register_writes 292940682 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 578749 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 318148 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 89683557 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 89472336 # number of times the CC registers were written -system.cpu0.num_mem_refs 122593410 # number of memory refs -system.cpu0.num_load_insts 64360945 # Number of load instructions -system.cpu0.num_store_insts 58232465 # Number of store instructions -system.cpu0.num_idle_cycles 402405334.403935 # Number of idle cycles -system.cpu0.num_busy_cycles 10021517.596065 # Number of busy cycles +system.cpu0.kern.inst.quiesce 16566 # number of quiesce instructions executed +system.cpu0.committedInsts 341336485 # Number of instructions committed +system.cpu0.committedOps 401580232 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 368861574 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 359512 # Number of float alu accesses +system.cpu0.num_func_calls 20525784 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 51873404 # number of instructions that are conditional controls +system.cpu0.num_int_insts 368861574 # number of integer instructions +system.cpu0.num_fp_insts 359512 # number of float instructions +system.cpu0.num_int_register_reads 539079221 # number of times the integer registers were read +system.cpu0.num_int_register_writes 292860354 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 571011 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 323488 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 89499549 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 89284497 # number of times the CC registers were written +system.cpu0.num_mem_refs 122681510 # number of memory refs +system.cpu0.num_load_insts 64329809 # Number of load instructions +system.cpu0.num_store_insts 58351701 # Number of store instructions +system.cpu0.num_idle_cycles 402393876.753300 # Number of idle cycles +system.cpu0.num_busy_cycles 10021247.246700 # Number of busy cycles system.cpu0.not_idle_fraction 0.024299 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.975701 # Percentage of idle cycles -system.cpu0.Branches 76142746 # Number of branches fetched +system.cpu0.Branches 76154036 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 278290201 69.25% 69.25% # Class of executed instruction -system.cpu0.op_class::IntMult 876142 0.22% 69.47% # Class of executed instruction -system.cpu0.op_class::IntDiv 42968 0.01% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 47686 0.01% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::MemRead 64360945 16.02% 85.51% # Class of executed instruction -system.cpu0.op_class::MemWrite 58232465 14.49% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 278201506 69.24% 69.24% # Class of executed instruction +system.cpu0.op_class::IntMult 848038 0.21% 69.45% # Class of executed instruction +system.cpu0.op_class::IntDiv 41846 0.01% 69.46% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 1 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 48432 0.01% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::MemRead 64329809 16.01% 85.48% # Class of executed instruction +system.cpu0.op_class::MemWrite 58351701 14.52% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 401850407 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 9785258 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999715 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 296102427 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 9785770 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 30.258470 # Average number of references to valid blocks. +system.cpu0.op_class::total 401821333 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 9787095 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999716 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 296232659 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 9787607 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.266097 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.924139 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 4.613790 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.156237 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu3.data 5.305549 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970555 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.009011 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.010071 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu3.data 0.010362 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.142011 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 4.386995 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.164772 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu3.data 6.305937 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.969027 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.008568 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.010087 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu3.data 0.012316 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1254458148 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1254458148 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 60043274 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 19451230 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 26515970 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu3.data 46522470 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 152532944 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 55058218 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 17868348 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 23514922 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu3.data 39147049 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 135588537 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 161685 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 47989 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 79490 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu3.data 113267 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 402431 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 128215 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 43197 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu2.data 56794 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu3.data 101554 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 329760 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1440792 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 445911 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 586217 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 965735 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3438655 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1532117 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 486268 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 631716 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu3.data 1115803 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3765904 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 115229707 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 37362775 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 50087686 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu3.data 85771073 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 288451241 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 115391392 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 37410764 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 50167176 # number of overall hits -system.cpu0.dcache.overall_hits::cpu3.data 85884340 # number of overall hits -system.cpu0.dcache.overall_hits::total 288853672 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2089317 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 638437 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 880712 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu3.data 3494222 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7102688 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 831050 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 249767 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 653536 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu3.data 3486415 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 5220768 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 516569 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 133434 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 215040 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu3.data 331304 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1196347 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 659058 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 109033 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu2.data 156389 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu3.data 303598 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1228078 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 91970 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 40583 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 45717 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 183696 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 361966 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu3.data 11 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3579425 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 997237 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1690637 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu3.data 7284235 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 13551534 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 4095994 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1130671 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1905677 # number of overall misses -system.cpu0.dcache.overall_misses::cpu3.data 7615539 # number of overall misses -system.cpu0.dcache.overall_misses::total 14747881 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 9935057500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 14094035000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 51705605000 # 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number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 2284034500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 3520477000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 238500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 238500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 18740019500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 34915464000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu3.data 153701625134 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 207357108634 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 18740019500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 34915464000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu3.data 153701625134 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 207357108634 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 62132591 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 20089667 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 27396682 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu3.data 50016692 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 159635632 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 55889268 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 18118115 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 24168458 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu3.data 42633464 # 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number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1557838 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1532762 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 486494 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 631934 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 1149431 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 3800621 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1532117 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 486268 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 631716 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 1115814 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 3765915 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 118809132 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 38360012 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 51778323 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu3.data 93055308 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 302002775 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 119487386 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 38541435 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 52072853 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu3.data 93499879 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 303601553 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033627 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.031779 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.032147 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.069861 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.044493 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014870 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.013785 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.027041 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.081776 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.037077 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.761616 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.735486 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.730112 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.745222 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.748288 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.837140 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.716239 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data 0.733590 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data 0.749343 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.788322 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060003 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.083419 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.072345 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.159815 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.095239 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000010 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000003 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030128 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025997 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.032651 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu3.data 0.078279 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.044872 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.034280 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029337 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.036596 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu3.data 0.081450 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.048576 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15561.531522 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16003.000981 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 14797.458490 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10662.821949 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 27984.321388 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 27837.128330 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 27606.237163 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 23258.824149 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 16650.023387 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 16809.772426 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 18936.952144 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 8300.357385 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14510.607890 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14164.501170 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 12433.773735 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9725.988076 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 21681.818182 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21681.818182 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18791.941635 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20652.253559 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 21100.585735 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15301.375374 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16574.246178 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 18321.816341 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 20182.632527 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14060.128952 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9910258 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 8881 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 889663 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 270 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 11.139339 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 32.892593 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 7576706 # number of writebacks -system.cpu0.dcache.writebacks::total 7576706 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 2565 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 39446 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 1918307 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 1960318 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 33 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 288880 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 2890218 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 3179131 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data 17 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data 2227 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 2244 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 9010 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 10983 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 113640 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 133633 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 2598 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 328343 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu3.data 4810752 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 5141693 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 2598 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 328343 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu3.data 4810752 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 5141693 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 635872 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 841266 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 1575915 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3053053 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 249734 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 364656 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 596197 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1210587 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 133434 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 214937 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 326698 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 675069 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 109033 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data 156372 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data 301371 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 566776 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 31573 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 34734 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 70056 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 136363 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 11 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 994639 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 1362294 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu3.data 2473483 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4830416 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 1128073 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 1577231 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu3.data 2800181 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5505485 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 5165 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 4559 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 4594 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 14318 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 4682 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 4068 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 4289 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 13039 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 9847 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 8627 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 8883 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 27357 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 9259931500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 12493159000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 23820252500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45573343000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6737865000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 9614650500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 17374860004 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33727375504 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 2271729000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 3143350500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 4907861500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 10322941000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 1706369000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 2472082000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data 5367328797 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 9545779797 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 413953500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 450661000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 926981000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1791595500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 227500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 227500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 17704165500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 24579891500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 46562441301 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 88846498301 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 19975894500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 27723242000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 51470302801 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 99169439301 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 937823500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 818983500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 848897000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2605704000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 937823500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 818983500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 848897000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2605704000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031652 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.030707 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.031508 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019125 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013784 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.015088 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.013984 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008597 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.735486 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.729763 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.734861 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.422241 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.716239 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.733511 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.743847 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.363822 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064899 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.054965 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.060948 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.035879 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000010 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025929 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.026310 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.026581 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015995 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.029269 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.030289 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.029948 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018134 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14562.571555 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14850.426619 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15115.188636 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14927.137852 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26980.166898 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26366.357608 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 29142.816894 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27860.348330 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17025.113539 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14624.520208 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15022.624871 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15291.682776 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 15650.023387 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 15808.981148 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 17809.705635 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 16842.244197 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13110.996738 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12974.635804 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 13232.000114 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13138.428313 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 20681.818182 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20681.818182 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17799.589097 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18043.015311 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 18824.645773 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18393.135974 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17707.980335 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17577.160226 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 18381.062796 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18012.843428 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181572.797677 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 179641.039702 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 184783.848498 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 181987.987149 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95239.514573 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 94932.595340 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 95564.223798 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95248.163176 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 15885620 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.975044 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 560402159 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 15886132 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 35.276187 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 9934044500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 471.724807 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 2.897260 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 29.967538 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu3.inst 7.385439 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.921338 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.005659 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.058530 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu3.inst 0.014425 # Average percentage of cache occupancy +system.cpu0.dcache.tags.tag_accesses 1255111411 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1255111411 # 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number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 1157061 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1892812 # number of overall misses +system.cpu0.dcache.overall_misses::cpu3.data 7664358 # number of overall misses +system.cpu0.dcache.overall_misses::total 14764959 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 9992794500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 13884394000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 52878438500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 76755627000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6954335000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 17889776000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 96530515223 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 121374626223 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 1854766500 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data 2567644000 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data 5803246814 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 10225657314 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 554773000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 665492500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 2279898500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 3500164000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 188500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 188500 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 1160248 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 3801554 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1527210 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 478716 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 634274 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 1126452 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 3766652 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 118909009 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 38303542 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 51834774 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu3.data 93117105 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 302164430 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 119585281 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 38493619 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 52128684 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu3.data 93555156 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 303762740 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033188 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.031978 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.032038 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.071343 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.044830 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014656 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014295 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.026809 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.081170 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.036775 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.758816 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.749617 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.728903 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.742297 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.747694 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.835822 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.725923 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data 0.730039 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data 0.750911 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.788345 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060508 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081699 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.074399 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.158102 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.095283 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000006 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029750 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.026488 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.032383 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu3.data 0.078817 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.044909 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.033873 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.030059 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.036310 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu3.data 0.081923 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.048607 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15549.042811 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15851.628673 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 14763.049548 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10717.664628 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 26952.384090 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 27474.208628 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 27980.832731 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 23431.227658 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 16285.595750 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 16944.230706 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 18872.101872 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 8325.218143 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14178.414435 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14096.729437 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 12428.714334 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9663.035376 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 26928.571429 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26928.571429 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18531.776821 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20458.848551 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 21148.398658 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15354.256574 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16249.701615 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 18143.277832 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 20251.167878 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14111.512977 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9947101 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 9301 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 883316 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 261 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 11.261090 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 35.636015 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 7580739 # number of writebacks +system.cpu0.dcache.writebacks::total 7580739 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 2342 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 38832 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 1981448 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 2022622 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 31 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 288487 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 2860546 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 3149064 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data 16 # 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number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 327335 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu3.data 4844224 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 5173932 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 640321 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 837065 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 1600362 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3077748 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 257992 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 362661 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 589334 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1209987 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 142485 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 214116 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 320624 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 677225 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 113890 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data 151519 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data 305274 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 570683 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 30420 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 36530 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 70648 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 137598 # 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number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 4577 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 4597 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 14213 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 4567 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 4089 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 4315 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 12971 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 9606 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 8666 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 8912 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 27184 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 9316912500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 12310511500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 24145682500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45773106500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6694367500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 9409306500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 17283283287 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33386957287 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 2351295000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 3106665500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 4848120000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 10306080500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 1740876500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 2415825500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data 5418758314 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 9575460314 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 393499000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 471106000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 934011000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1798616000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 181500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 181500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 17752156500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 24135643500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 46847724101 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 88735524101 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 20103451500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 27242309000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 51695844101 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 99041604601 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 916274500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 823963000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 848646500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2588884000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 916274500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 823963000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 848646500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2588884000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031862 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.030618 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.031876 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019266 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014293 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.014932 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.013866 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008590 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.749617 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.728509 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.731933 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.423713 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.725923 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.729962 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.745465 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.366282 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063517 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.057570 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.060890 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.036195 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000006 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026426 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.026068 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.026794 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016079 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.029997 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.030029 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.030096 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018224 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14550.377857 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14706.756942 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15087.637984 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14872.272356 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25947.965441 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25945.184346 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 29326.804982 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27592.823135 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16502.052848 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14509.263670 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15120.889266 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15218.104027 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 15285.595750 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 15944.043321 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 17750.474374 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 16778.947882 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12935.535832 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12896.413906 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 13220.629034 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13071.527202 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 25928.571429 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25928.571429 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17538.138595 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17861.781912 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 18776.868700 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18264.283580 # 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number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 21435986000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 48533195500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 59905132390 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 129874313890 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015637 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.054865 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.088365 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.018016 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015637 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.054865 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.088365 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.018016 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015637 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.054865 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.088365 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.018016 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12443.979127 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12512.257622 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12512.178464 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12500.900107 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12443.979127 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12512.257622 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12512.178464 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12500.900107 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12443.979127 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12512.257622 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12512.178464 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12500.900107 # average overall mshr miss latency -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.writebacks::writebacks 15900081 # number of writebacks +system.cpu0.icache.writebacks::total 15900081 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 365435 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 365435 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu3.inst 365435 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 365435 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu3.inst 365435 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 365435 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 1701578 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 3909511 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 4778380 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 10389469 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 1701578 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 3909511 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu3.inst 4778380 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 10389469 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 1701578 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 3909511 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu3.inst 4778380 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 10389469 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 21180991500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 48845186500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 59808862373 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 129835040373 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 21180991500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 48845186500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 59808862373 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 129835040373 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 21180991500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 48845186500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 59808862373 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 129835040373 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015388 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.055352 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.087964 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.018004 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015388 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.055352 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.087964 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.018004 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015388 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.055352 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.087964 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.018004 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12447.852229 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12493.937605 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12516.556317 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12496.792702 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12447.852229 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12493.937605 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12516.556317 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12496.792702 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12447.852229 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12493.937605 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12516.556317 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12496.792702 # average overall mshr miss latency +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1238,69 +1244,65 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 31142 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 31142 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4562 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 22714 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 4 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 31138 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 31138 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 31138 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 27280 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 24555.205279 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21409.224401 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 12983.742991 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 17842 65.40% 65.40% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 9287 34.04% 99.45% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 82 0.30% 99.75% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 48 0.18% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 1 0.00% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 6 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 4 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 4 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 3 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 2 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 27280 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 2381232620 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.574632 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.494399 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1012901000 42.54% 42.54% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 1368331620 57.46% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 2381232620 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 22714 83.27% 83.27% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 4562 16.73% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 27276 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 31142 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 31190 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 31190 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4602 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 22894 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 2 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 31188 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 31188 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 31188 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 27498 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23439.468325 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 20168.956165 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 13617.892423 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 27307 99.31% 99.31% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 167 0.61% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 10 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 9 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 2 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 2 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 27498 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 2364440120 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.573010 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.494641 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1009591500 42.70% 42.70% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 1354848620 57.30% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 2364440120 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 22894 83.26% 83.26% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 4602 16.74% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 27496 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 31190 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 31142 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 27276 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 31190 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 27496 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 27276 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 58418 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 27496 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 58686 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 20762749 # DTB read hits -system.cpu1.dtb.read_misses 23873 # DTB read misses -system.cpu1.dtb.write_hits 18763804 # DTB write hits -system.cpu1.dtb.write_misses 7269 # DTB write misses +system.cpu1.dtb.read_hits 20771010 # DTB read hits +system.cpu1.dtb.read_misses 23692 # DTB read misses +system.cpu1.dtb.write_hits 18692480 # DTB write hits +system.cpu1.dtb.write_misses 7498 # DTB write misses system.cpu1.dtb.flush_tlb 1182 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 5192 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 138 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 17777 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 5140 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 135 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 17937 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 955 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 1005 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 2493 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 20786622 # DTB read accesses -system.cpu1.dtb.write_accesses 18771073 # DTB write accesses +system.cpu1.dtb.perms_faults 2603 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 20794702 # DTB read accesses +system.cpu1.dtb.write_accesses 18699978 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 39526553 # DTB hits -system.cpu1.dtb.misses 31142 # DTB misses -system.cpu1.dtb.accesses 39557695 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 39463490 # DTB hits +system.cpu1.dtb.misses 31190 # DTB misses +system.cpu1.dtb.accesses 39494680 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1330,154 +1332,155 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 19936 # Table walker walks requested -system.cpu1.itb.walker.walksLong 19936 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 932 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 17656 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 19936 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 19936 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 19936 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 18588 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 27393.103077 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 24671.512984 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 13247.215063 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 10003 53.81% 53.81% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 8429 45.35% 99.16% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 57 0.31% 99.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 80 0.43% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 2 0.01% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 6 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 2 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 4 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 3 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 18588 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 19592 # Table walker walks requested +system.cpu1.itb.walker.walksLong 19592 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 942 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 17338 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 19592 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 19592 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 19592 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 18280 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 26364.633479 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23452.518551 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 14371.838603 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 10663 58.33% 58.33% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 7451 40.76% 99.09% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 65 0.36% 99.45% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 75 0.41% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 1 0.01% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 10 0.05% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 1 0.01% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 7 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 1 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 3 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 2 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 18280 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 17656 94.99% 94.99% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 932 5.01% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 18588 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 17338 94.85% 94.85% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 942 5.15% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 18280 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 19936 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 19936 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 19592 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 19592 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18588 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18588 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 38524 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 110162476 # ITB inst hits -system.cpu1.itb.inst_misses 19936 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18280 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18280 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 37872 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 110580623 # ITB inst hits +system.cpu1.itb.inst_misses 19592 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 1182 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 5192 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 138 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 13192 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 5140 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 135 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 13235 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 110182412 # ITB inst accesses -system.cpu1.itb.hits 110162476 # DTB hits -system.cpu1.itb.misses 19936 # DTB misses -system.cpu1.itb.accesses 110182412 # DTB accesses -system.cpu1.numPwrStateTransitions 6038 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 3019 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 4031562886.362703 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 205285027256.597076 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 926 30.67% 30.67% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 2090 69.23% 99.90% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 110600215 # ITB inst accesses +system.cpu1.itb.hits 110580623 # DTB hits +system.cpu1.itb.misses 19592 # DTB misses +system.cpu1.itb.accesses 110600215 # DTB accesses +system.cpu1.numPwrStateTransitions 6016 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 3008 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 4046290699.440825 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 205659188461.921204 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 915 30.42% 30.42% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 2090 69.48% 99.90% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.03% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.03% 99.97% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::overflows 1 0.03% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 11261576634501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 3019 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 39144972847071 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 12171288353929 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 1182097366 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 11261531014001 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 3008 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 39145033266082 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 12171242423918 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 1182100228 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 110088686 # Number of instructions committed -system.cpu1.committedOps 129237809 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 118887794 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 113577 # Number of float alu accesses -system.cpu1.num_func_calls 6597658 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 16662523 # number of instructions that are conditional controls -system.cpu1.num_int_insts 118887794 # number of integer instructions -system.cpu1.num_fp_insts 113577 # number of float instructions -system.cpu1.num_int_register_reads 170702989 # number of times the integer registers were read -system.cpu1.num_int_register_writes 94155610 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 183331 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 96228 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 28150227 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 28060459 # number of times the CC registers were written -system.cpu1.num_mem_refs 39523640 # number of memory refs -system.cpu1.num_load_insts 20761578 # Number of load instructions -system.cpu1.num_store_insts 18762062 # Number of store instructions -system.cpu1.num_idle_cycles 1155305857.273267 # Number of idle cycles -system.cpu1.num_busy_cycles 26791508.726733 # Number of busy cycles -system.cpu1.not_idle_fraction 0.022664 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.977336 # Percentage of idle cycles -system.cpu1.Branches 24572277 # Number of branches fetched +system.cpu1.committedInsts 110507936 # Number of instructions committed +system.cpu1.committedOps 129543713 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 119008832 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 107333 # Number of float alu accesses +system.cpu1.num_func_calls 6516685 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 16787846 # number of instructions that are conditional controls +system.cpu1.num_int_insts 119008832 # number of integer instructions +system.cpu1.num_fp_insts 107333 # number of float instructions +system.cpu1.num_int_register_reads 172055074 # number of times the integer registers were read +system.cpu1.num_int_register_writes 94356642 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 176403 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 83340 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 28608279 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 28519816 # number of times the CC registers were written +system.cpu1.num_mem_refs 39460487 # number of memory refs +system.cpu1.num_load_insts 20769710 # Number of load instructions +system.cpu1.num_store_insts 18690777 # Number of store instructions +system.cpu1.num_idle_cycles 1155308161.927193 # Number of idle cycles +system.cpu1.num_busy_cycles 26792066.072807 # Number of busy cycles +system.cpu1.not_idle_fraction 0.022665 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.977335 # Percentage of idle cycles +system.cpu1.Branches 24662743 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 89498355 69.21% 69.21% # Class of executed instruction -system.cpu1.op_class::IntMult 266792 0.21% 69.42% # Class of executed instruction -system.cpu1.op_class::IntDiv 10604 0.01% 69.43% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 12166 0.01% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::MemRead 20761578 16.06% 85.49% # Class of executed instruction -system.cpu1.op_class::MemWrite 18762062 14.51% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 89857347 69.33% 69.33% # Class of executed instruction +system.cpu1.op_class::IntMult 277190 0.21% 69.54% # Class of executed instruction +system.cpu1.op_class::IntDiv 11015 0.01% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 20 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 10320 0.01% 69.56% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction +system.cpu1.op_class::MemRead 20769710 16.02% 85.58% # Class of executed instruction +system.cpu1.op_class::MemWrite 18690777 14.42% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 129311599 # Class of executed instruction -system.cpu2.branchPred.lookups 40882537 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28404958 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 2018640 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 29949697 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 20329283 # Number of BTB hits +system.cpu1.op_class::total 129616400 # Class of executed instruction +system.cpu2.branchPred.lookups 40854703 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28349635 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 2013069 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 29873482 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 20268490 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 67.878092 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 4945381 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 329320 # Number of incorrect RAS predictions. -system.cpu2.branchPred.indirectLookups 1144842 # Number of indirect predictor lookups. -system.cpu2.branchPred.indirectHits 797183 # Number of indirect target hits. -system.cpu2.branchPred.indirectMisses 347659 # Number of indirect misses. -system.cpu2.branchPredindirectMispredicted 143486 # Number of mispredicted indirect branches. -system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.cpu2.branchPred.BTBHitPct 67.847765 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 4987413 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 331344 # Number of incorrect RAS predictions. +system.cpu2.branchPred.indirectLookups 1163100 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 806401 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 356699 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 146740 # Number of mispredicted indirect branches. +system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1507,66 +1510,66 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.cpu2.dtb.walker.walks 93219 # Table walker walks requested -system.cpu2.dtb.walker.walksLong 93219 # Table walker walks initiated with long descriptors -system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 7034 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 30340 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walkWaitTime::samples 93219 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0 93219 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 93219 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 37374 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 25165.904104 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 22274.336205 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 12675.748220 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-32767 24476 65.49% 65.49% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::32768-65535 12701 33.98% 99.47% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::65536-98303 113 0.30% 99.78% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::98304-131071 53 0.14% 99.92% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::131072-163839 2 0.01% 99.92% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::163840-196607 11 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::196608-229375 2 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::229376-262143 5 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::262144-294911 6 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.cpu2.dtb.walker.walks 93799 # Table walker walks requested +system.cpu2.dtb.walker.walksLong 93799 # Table walker walks initiated with long descriptors +system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 7024 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 30187 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 93799 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 93799 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 93799 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 37211 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 23608.785037 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 20477.524093 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 12702.189700 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-32767 25796 69.32% 69.32% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::32768-65535 11234 30.19% 99.51% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::65536-98303 97 0.26% 99.77% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::98304-131071 57 0.15% 99.93% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::131072-163839 1 0.00% 99.93% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::163840-196607 11 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::196608-229375 2 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::229376-262143 5 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::262144-294911 3 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu2.dtb.walker.walkCompletionTime::294912-327679 2 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu2.dtb.walker.walkCompletionTime::327680-360447 2 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 37374 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 37211 # Table walker service (enqueue to completion) latency system.cpu2.dtb.walker.walksPending::samples 2000359000 # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::0 2000359000 100.00% 100.00% # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::total 2000359000 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 30340 81.18% 81.18% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::2M 7034 18.82% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 37374 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 93219 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkPageSizes::4K 30187 81.12% 81.12% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::2M 7024 18.88% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 37211 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 93799 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 93219 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 37374 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 93799 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 37211 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 37374 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 130593 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 37211 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 131010 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 28583495 # DTB read hits -system.cpu2.dtb.read_misses 77825 # DTB read misses -system.cpu2.dtb.write_hits 25112772 # DTB write hits -system.cpu2.dtb.write_misses 15394 # DTB write misses -system.cpu2.dtb.flush_tlb 1182 # Number of times complete TLB was flushed +system.cpu2.dtb.read_hits 28529245 # DTB read hits +system.cpu2.dtb.read_misses 78357 # DTB read misses +system.cpu2.dtb.write_hits 25227275 # DTB write hits +system.cpu2.dtb.write_misses 15442 # DTB write misses +system.cpu2.dtb.flush_tlb 1183 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 7038 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 188 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 22760 # Number of entries that have been flushed from TLB +system.cpu2.dtb.flush_tlb_mva_asid 7123 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 191 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 22552 # Number of entries that have been flushed from TLB system.cpu2.dtb.align_faults 83 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 2252 # Number of TLB faults due to prefetch +system.cpu2.dtb.prefetch_faults 2182 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 3984 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 28661320 # DTB read accesses -system.cpu2.dtb.write_accesses 25128166 # DTB write accesses +system.cpu2.dtb.perms_faults 3958 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 28607602 # DTB read accesses +system.cpu2.dtb.write_accesses 25242717 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 53696267 # DTB hits -system.cpu2.dtb.misses 93219 # DTB misses -system.cpu2.dtb.accesses 53789486 # DTB accesses -system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.cpu2.dtb.hits 53756520 # DTB hits +system.cpu2.dtb.misses 93799 # DTB misses +system.cpu2.dtb.accesses 53850319 # DTB accesses +system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1596,149 +1599,147 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.cpu2.itb.walker.walks 27359 # Table walker walks requested -system.cpu2.itb.walker.walksLong 27359 # Table walker walks initiated with long descriptors -system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1819 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22616 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walkWaitTime::samples 27359 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0 27359 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 27359 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 24435 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 28370.002046 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 25752.666599 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 13391.544423 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::0-32767 12572 51.45% 51.45% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::32768-65535 11615 47.53% 98.99% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::65536-98303 92 0.38% 99.36% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::98304-131071 132 0.54% 99.90% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::131072-163839 2 0.01% 99.91% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::163840-196607 9 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::196608-229375 5 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.cpu2.itb.walker.walks 27208 # Table walker walks requested +system.cpu2.itb.walker.walksLong 27208 # Table walker walks initiated with long descriptors +system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1843 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22528 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 27208 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 27208 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 27208 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 24371 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 26858.233146 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 23932.181675 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 13621.050617 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::0-32767 13667 56.08% 56.08% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::32768-65535 10461 42.92% 99.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::65536-98303 87 0.36% 99.36% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::98304-131071 133 0.55% 99.91% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::131072-163839 3 0.01% 99.92% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::163840-196607 12 0.05% 99.97% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::196608-229375 1 0.00% 99.97% # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walkCompletionTime::229376-262143 2 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::262144-294911 1 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::294912-327679 2 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::327680-360447 2 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 24435 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::360448-393215 2 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 24371 # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walksPending::samples 2000327000 # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::0 2000327000 100.00% 100.00% # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::total 2000327000 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 22616 92.56% 92.56% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::2M 1819 7.44% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 24435 # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::4K 22528 92.44% 92.44% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::2M 1843 7.56% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 24371 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27359 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27359 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27208 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27208 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24435 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24435 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 51794 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 70751081 # ITB inst hits -system.cpu2.itb.inst_misses 27359 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24371 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24371 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 51579 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 70683304 # ITB inst hits +system.cpu2.itb.inst_misses 27208 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 1182 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb 1183 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 7038 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 188 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 17251 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_tlb_mva_asid 7123 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 191 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 16893 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 50621 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 51118 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 70778440 # ITB inst accesses -system.cpu2.itb.hits 70751081 # DTB hits -system.cpu2.itb.misses 27359 # DTB misses -system.cpu2.itb.accesses 70778440 # DTB accesses -system.cpu2.numPwrStateTransitions 7068 # Number of power state transitions -system.cpu2.pwrStateClkGateDist::samples 3534 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::mean 14278760224.142614 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::stdev 128952650694.550415 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::underflows 1173 33.19% 33.19% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::1000-5e+10 2324 65.76% 98.95% # Distribution of time spent in the clock gated state +system.cpu2.itb.inst_accesses 70710512 # ITB inst accesses +system.cpu2.itb.hits 70683304 # DTB hits +system.cpu2.itb.misses 27208 # DTB misses +system.cpu2.itb.accesses 70710512 # DTB accesses +system.cpu2.numPwrStateTransitions 7024 # Number of power state transitions +system.cpu2.pwrStateClkGateDist::samples 3512 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::mean 14368150694.236048 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::stdev 129350965742.418961 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::underflows 1152 32.80% 32.80% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::1000-5e+10 2323 66.14% 98.95% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::5e+10-1e+11 6 0.17% 99.12% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::1e+11-1.5e+11 3 0.08% 99.21% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::1e+11-1.5e+11 3 0.09% 99.20% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::1.5e+11-2e+11 2 0.06% 99.26% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::2e+11-2.5e+11 2 0.06% 99.32% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::2.5e+11-3e+11 2 0.06% 99.38% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::3e+11-3.5e+11 1 0.03% 99.41% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::2.5e+11-3e+11 2 0.06% 99.37% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::3e+11-3.5e+11 1 0.03% 99.40% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::4.5e+11-5e+11 1 0.03% 99.43% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::5e+11-5.5e+11 1 0.03% 99.46% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::7e+11-7.5e+11 1 0.03% 99.49% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::overflows 18 0.51% 100.00% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::max_value 1988791938500 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::total 3534 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateResidencyTicks::ON 855122568880 # Cumulative time (in ticks) in various power states -system.cpu2.pwrStateResidencyTicks::CLK_GATED 50461138632120 # Cumulative time (in ticks) in various power states -system.cpu2.numCycles 1176514820 # number of cpu cycles simulated +system.cpu2.pwrStateClkGateDist::max_value 1988791978000 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::total 3512 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateResidencyTicks::ON 855330451843 # Cumulative time (in ticks) in various power states +system.cpu2.pwrStateResidencyTicks::CLK_GATED 50460945238157 # Cumulative time (in ticks) in various power states +system.cpu2.numCycles 1176516719 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 148015275 # Number of instructions committed -system.cpu2.committedOps 173576253 # Number of ops (including micro ops) committed -system.cpu2.discardedOps 15019689 # Number of ops (including micro ops) which were discarded before commit -system.cpu2.numFetchSuspends 1599 # Number of times Execute suspended instruction fetching -system.cpu2.quiesceCycles 5679254 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.cpi 7.948604 # CPI: cycles per instruction -system.cpu2.ipc 0.125808 # IPC: instructions per cycle +system.cpu2.committedInsts 147979887 # Number of instructions committed +system.cpu2.committedOps 173747082 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 15034502 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.numFetchSuspends 1577 # Number of times Execute suspended instruction fetching +system.cpu2.quiesceCycles 5675627 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 7.950518 # CPI: cycles per instruction +system.cpu2.ipc 0.125778 # IPC: instructions per cycle system.cpu2.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.op_class_0::IntAlu 120466035 69.40% 69.40% # Class of committed instruction -system.cpu2.op_class_0::IntMult 363809 0.21% 69.61% # Class of committed instruction -system.cpu2.op_class_0::IntDiv 14931 0.01% 69.62% # Class of committed instruction -system.cpu2.op_class_0::FloatAdd 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::FloatCmp 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::FloatCvt 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::FloatMult 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::FloatDiv 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::FloatSqrt 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdAdd 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdAddAcc 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdAlu 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdCmp 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdCvt 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdMisc 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdMult 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdMultAcc 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdShift 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdSqrt 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMisc 14962 0.01% 69.63% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMult 0 0.00% 69.63% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 69.63% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 69.63% # Class of committed instruction -system.cpu2.op_class_0::MemRead 27697831 15.96% 85.59% # Class of committed instruction -system.cpu2.op_class_0::MemWrite 25018685 14.41% 100.00% # Class of committed instruction +system.cpu2.op_class_0::IntAlu 120575025 69.40% 69.40% # Class of committed instruction +system.cpu2.op_class_0::IntMult 357276 0.21% 69.60% # Class of committed instruction +system.cpu2.op_class_0::IntDiv 14709 0.01% 69.61% # Class of committed instruction +system.cpu2.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMisc 16361 0.01% 69.62% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMult 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::MemRead 27648708 15.91% 85.53% # Class of committed instruction +system.cpu2.op_class_0::MemWrite 25135003 14.47% 100.00% # Class of committed instruction system.cpu2.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.op_class_0::total 173576253 # Class of committed instruction +system.cpu2.op_class_0::total 173747082 # Class of committed instruction system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 278505998 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 898008822 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 76056401 # Number of BP lookups -system.cpu3.branchPred.condPredicted 50755289 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 3415271 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 50793125 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 34573256 # Number of BTB hits +system.cpu2.tickCycles 278731731 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 897784988 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 76144884 # Number of BP lookups +system.cpu3.branchPred.condPredicted 50917651 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 3425676 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 51078726 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 34631446 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 68.066802 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 9840520 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 107050 # Number of incorrect RAS predictions. -system.cpu3.branchPred.indirectLookups 3054055 # Number of indirect predictor lookups. -system.cpu3.branchPred.indirectHits 1548215 # Number of indirect target hits. -system.cpu3.branchPred.indirectMisses 1505840 # Number of indirect misses. -system.cpu3.branchPredindirectMispredicted 248236 # Number of mispredicted indirect branches. -system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.cpu3.branchPred.BTBHitPct 67.800137 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 9824308 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 106925 # Number of incorrect RAS predictions. +system.cpu3.branchPred.indirectLookups 2992006 # Number of indirect predictor lookups. +system.cpu3.branchPred.indirectHits 1537953 # Number of indirect target hits. +system.cpu3.branchPred.indirectMisses 1454053 # Number of indirect misses. +system.cpu3.branchPredindirectMispredicted 245625 # Number of mispredicted indirect branches. +system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1768,95 +1769,89 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.cpu3.dtb.walker.walks 519832 # Table walker walks requested -system.cpu3.dtb.walker.walksLong 519832 # Table walker walks initiated with long descriptors -system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8563 # Level at which table walker walks with long descriptors terminate -system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 50762 # Level at which table walker walks with long descriptors terminate -system.cpu3.dtb.walker.walksSquashedBefore 324579 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 195253 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 2247.443061 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 12961.897479 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-32767 191171 97.91% 97.91% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::32768-65535 2882 1.48% 99.39% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::65536-98303 501 0.26% 99.64% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::98304-131071 350 0.18% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::131072-163839 155 0.08% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::163840-196607 49 0.03% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::196608-229375 39 0.02% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::229376-262143 21 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::262144-294911 33 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::294912-327679 19 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::327680-360447 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::360448-393215 6 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::393216-425983 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::425984-458751 14 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 195253 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkCompletionTime::samples 240674 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::mean 22283.310619 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::gmean 18185.362858 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::stdev 16504.392629 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::0-65535 236088 98.09% 98.09% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::65536-131071 4155 1.73% 99.82% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::131072-196607 185 0.08% 99.90% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::196608-262143 125 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::262144-327679 40 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::327680-393215 50 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::393216-458751 22 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::458752-524287 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::total 240674 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -21483315588 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean 0.617433 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-3 -22069775588 102.73% 102.73% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::4-7 326975000 -1.52% 101.21% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::8-11 109953500 -0.51% 100.70% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::12-15 66787000 -0.31% 100.39% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::16-19 27414500 -0.13% 100.26% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::20-23 14643500 -0.07% 100.19% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::24-27 14038500 -0.07% 100.12% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::28-31 22874000 -0.11% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::32-35 3351000 -0.02% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::36-39 112000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::40-43 25000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::44-47 22000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::48-51 17000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::52-55 205500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::56-59 41500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -21483315588 # Table walker pending requests distribution -system.cpu3.dtb.walker.walkPageSizes::4K 50762 85.57% 85.57% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::2M 8563 14.43% 100.00% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::total 59325 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 519832 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.cpu3.dtb.walker.walks 512874 # Table walker walks requested +system.cpu3.dtb.walker.walksLong 512874 # Table walker walks initiated with long descriptors +system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8606 # Level at which table walker walks with long descriptors terminate +system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 51328 # Level at which table walker walks with long descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 316923 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 195951 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 2195.235033 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 13338.016362 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-65535 194716 99.37% 99.37% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::65536-131071 870 0.44% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::131072-196607 208 0.11% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::196608-262143 62 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::262144-327679 47 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::327680-393215 18 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::393216-458751 23 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::458752-524287 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::total 195951 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 235338 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 21271.290654 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 17097.378529 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 15945.708212 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-32767 189296 80.44% 80.44% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::32768-65535 41383 17.58% 98.02% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::65536-98303 3580 1.52% 99.54% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::98304-131071 595 0.25% 99.79% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::131072-163839 139 0.06% 99.85% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::163840-196607 148 0.06% 99.92% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::196608-229375 80 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::229376-262143 73 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::262144-294911 24 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::327680-360447 5 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::360448-393215 11 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::total 235338 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -21468826588 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean 0.564464 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-3 -22023506588 102.58% 102.58% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-7 315278500 -1.47% 101.12% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-11 105205000 -0.49% 100.63% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-15 64047000 -0.30% 100.33% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-19 24089000 -0.11% 100.21% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-23 11371500 -0.05% 100.16% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-27 12408500 -0.06% 100.10% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::28-31 18570000 -0.09% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::32-35 3540000 -0.02% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::36-39 163500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::40-43 7000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -21468826588 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 51328 85.64% 85.64% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::2M 8606 14.36% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 59934 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 512874 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 519832 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 59325 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 512874 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 59934 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 59325 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 579157 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 59934 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 572808 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 59705170 # DTB read hits -system.cpu3.dtb.read_misses 356680 # DTB read misses -system.cpu3.dtb.write_hits 46676545 # DTB write hits -system.cpu3.dtb.write_misses 163152 # DTB write misses -system.cpu3.dtb.flush_tlb 1183 # Number of times complete TLB was flushed +system.cpu3.dtb.read_hits 59857088 # DTB read hits +system.cpu3.dtb.read_misses 352696 # DTB read misses +system.cpu3.dtb.write_hits 46573459 # DTB write hits +system.cpu3.dtb.write_misses 160178 # DTB write misses +system.cpu3.dtb.flush_tlb 1182 # Number of times complete TLB was flushed system.cpu3.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu3.dtb.flush_tlb_mva_asid 11749 # Number of times TLB was flushed by MVA & ASID -system.cpu3.dtb.flush_tlb_asid 293 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 29163 # Number of entries that have been flushed from TLB -system.cpu3.dtb.align_faults 78 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 4872 # Number of TLB faults due to prefetch +system.cpu3.dtb.flush_tlb_mva_asid 11696 # Number of times TLB was flushed by MVA & ASID +system.cpu3.dtb.flush_tlb_asid 295 # Number of times TLB was flushed by ASID +system.cpu3.dtb.flush_entries 29518 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 76 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 5036 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 30504 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 60061850 # DTB read accesses -system.cpu3.dtb.write_accesses 46839697 # DTB write accesses +system.cpu3.dtb.perms_faults 30761 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 60209784 # DTB read accesses +system.cpu3.dtb.write_accesses 46733637 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 106381715 # DTB hits -system.cpu3.dtb.misses 519832 # DTB misses -system.cpu3.dtb.accesses 106901547 # DTB accesses -system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.cpu3.dtb.hits 106430547 # DTB hits +system.cpu3.dtb.misses 512874 # DTB misses +system.cpu3.dtb.accesses 106943421 # DTB accesses +system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1886,393 +1881,401 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.cpu3.itb.walker.walks 58984 # Table walker walks requested -system.cpu3.itb.walker.walksLong 58984 # Table walker walks initiated with long descriptors -system.cpu3.itb.walker.walksLongTerminationLevel::Level2 2019 # Level at which table walker walks with long descriptors terminate -system.cpu3.itb.walker.walksLongTerminationLevel::Level3 40730 # Level at which table walker walks with long descriptors terminate -system.cpu3.itb.walker.walksSquashedBefore 8213 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 50771 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 1255.214591 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 7667.557499 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-32767 50302 99.08% 99.08% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-65535 327 0.64% 99.72% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::65536-98303 93 0.18% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::98304-131071 33 0.06% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::131072-163839 8 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::163840-196607 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::196608-229375 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.cpu3.itb.walker.walks 59319 # Table walker walks requested +system.cpu3.itb.walker.walksLong 59319 # Table walker walks initiated with long descriptors +system.cpu3.itb.walker.walksLongTerminationLevel::Level2 2009 # Level at which table walker walks with long descriptors terminate +system.cpu3.itb.walker.walksLongTerminationLevel::Level3 40532 # Level at which table walker walks with long descriptors terminate +system.cpu3.itb.walker.walksSquashedBefore 8154 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 51165 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1195.836998 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 7646.415303 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-32767 50755 99.20% 99.20% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::32768-65535 251 0.49% 99.69% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::65536-98303 94 0.18% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::98304-131071 39 0.08% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::131072-163839 13 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::163840-196607 9 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::196608-229375 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::229376-262143 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu3.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 50771 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkCompletionTime::samples 50962 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 27876.584514 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 23887.788397 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 16739.526598 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::0-65535 49958 98.03% 98.03% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::65536-131071 889 1.74% 99.77% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::131072-196607 72 0.14% 99.92% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::196608-262143 26 0.05% 99.97% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::262144-327679 9 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::327680-393215 7 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::total 50962 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -21485924088 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean 1.063775 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::0 1402683284 -6.53% -6.53% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 -22917683872 106.66% 100.14% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::2 26044500 -0.12% 100.01% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::3 2758500 -0.01% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::4 237000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::5 36500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -21485924088 # Table walker pending requests distribution -system.cpu3.itb.walker.walkPageSizes::4K 40730 95.28% 95.28% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::2M 2019 4.72% 100.00% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::total 42749 # Table walker page sizes translated +system.cpu3.itb.walker.walkWaitTime::total 51165 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkCompletionTime::samples 50695 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 26787.010553 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 22469.536393 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 17840.810022 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-32767 30103 59.38% 59.38% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::32768-65535 19510 38.49% 97.87% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::65536-98303 511 1.01% 98.87% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::98304-131071 427 0.84% 99.72% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::131072-163839 38 0.07% 99.79% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::163840-196607 57 0.11% 99.90% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::196608-229375 19 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::262144-294911 8 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::294912-327679 3 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::total 50695 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksPending::samples -25766386884 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 0.899092 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::stdev 0.296211 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 -2567658104 9.97% 9.97% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -23226705280 90.14% 100.11% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 24531500 -0.10% 100.01% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 2936500 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 267500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::5 75500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::6 120000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::7 45500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -25766386884 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 40532 95.28% 95.28% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::2M 2009 4.72% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 42541 # Table walker page sizes translated system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 58984 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 58984 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 59319 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 59319 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 42749 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::total 42749 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 101733 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 54309249 # ITB inst hits -system.cpu3.itb.inst_misses 58984 # ITB inst misses +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 42541 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 42541 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 101860 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 54449151 # ITB inst hits +system.cpu3.itb.inst_misses 59319 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.write_hits 0 # DTB write hits system.cpu3.itb.write_misses 0 # DTB write misses -system.cpu3.itb.flush_tlb 1183 # Number of times complete TLB was flushed +system.cpu3.itb.flush_tlb 1182 # Number of times complete TLB was flushed system.cpu3.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu3.itb.flush_tlb_mva_asid 11749 # Number of times TLB was flushed by MVA & ASID -system.cpu3.itb.flush_tlb_asid 293 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 22226 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_tlb_mva_asid 11696 # Number of times TLB was flushed by MVA & ASID +system.cpu3.itb.flush_tlb_asid 295 # Number of times TLB was flushed by ASID +system.cpu3.itb.flush_entries 22325 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 110359 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.perms_faults 110276 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 54368233 # ITB inst accesses -system.cpu3.itb.hits 54309249 # DTB hits -system.cpu3.itb.misses 58984 # DTB misses -system.cpu3.itb.accesses 54368233 # DTB accesses -system.cpu3.numPwrStateTransitions 7050 # Number of power state transitions -system.cpu3.pwrStateClkGateDist::samples 3525 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::mean 48150318.502695 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::stdev 1097902153.303432 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::underflows 2138 60.65% 60.65% # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::1000-5e+10 1387 39.35% 100.00% # Distribution of time spent in the clock gated state +system.cpu3.itb.inst_accesses 54508470 # ITB inst accesses +system.cpu3.itb.hits 54449151 # DTB hits +system.cpu3.itb.misses 59319 # DTB misses +system.cpu3.itb.accesses 54508470 # DTB accesses +system.cpu3.numPwrStateTransitions 7056 # Number of power state transitions +system.cpu3.pwrStateClkGateDist::samples 3528 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::mean 48263626.625000 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::stdev 1100096495.861649 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::underflows 2141 60.69% 60.69% # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::1000-5e+10 1387 39.31% 100.00% # Distribution of time spent in the clock gated state system.cpu3.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::max_value 36013437604 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::total 3525 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateResidencyTicks::ON 51146531328278 # Cumulative time (in ticks) in various power states -system.cpu3.pwrStateResidencyTicks::CLK_GATED 169729872722 # Cumulative time (in ticks) in various power states -system.cpu3.numCycles 361675800 # number of cpu cycles simulated +system.cpu3.pwrStateClkGateDist::max_value 36012902604 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::total 3528 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateResidencyTicks::ON 51146001615267 # Cumulative time (in ticks) in various power states +system.cpu3.pwrStateResidencyTicks::CLK_GATED 170274074733 # Cumulative time (in ticks) in various power states +system.cpu3.numCycles 360624311 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 142734990 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 337553362 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 76056401 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 45961991 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 197659540 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 7720824 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 1399327 # Number of cycles fetch has spent waiting for tlb -system.cpu3.fetch.MiscStallCycles 5628 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.PendingDrainCycles 1517 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 2684967 # Number of stall cycles due to pending traps -system.cpu3.fetch.PendingQuiesceStallCycles 90171 # Number of stall cycles due to pending quiesce instructions -system.cpu3.fetch.IcacheWaitRetryStallCycles 3829 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 54181818 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 2125134 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 22298 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 348440253 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.132379 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.378502 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 142734409 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 337961407 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 76144884 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 45993707 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 196711593 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 7739189 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 1372744 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 5006 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 1830 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 2692575 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 88196 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 3852 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 54321925 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 2128480 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 22518 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 347479672 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.136573 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.381700 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 265738138 76.27% 76.27% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 10408686 2.99% 79.25% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 10350946 2.97% 82.22% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 7718330 2.22% 84.44% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 15611358 4.48% 88.92% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 5061575 1.45% 90.37% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 5537323 1.59% 91.96% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 4787480 1.37% 93.33% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 23226417 6.67% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 264664577 76.17% 76.17% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 10448751 3.01% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 10389657 2.99% 82.16% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 7726776 2.22% 84.39% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 15569597 4.48% 88.87% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 5085732 1.46% 90.33% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 5566487 1.60% 91.93% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 4803146 1.38% 93.32% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 23224949 6.68% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 348440253 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.210289 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.933304 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 116402482 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 160353660 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 61341979 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 7283918 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 3056510 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 11212857 # Number of times decode resolved a branch -system.cpu3.decode.BranchMispred 815162 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 368532981 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 2520228 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 3056510 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 120624207 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 11509026 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 131064171 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 64320905 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 17863677 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 359702121 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 43833 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 968665 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 780315 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 7689356 # Number of times rename has blocked due to SQ full -system.cpu3.rename.FullRegisterEvents 2098 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 342552995 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 547002223 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 423527131 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 526597 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 286388562 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 56164428 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 8049002 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 6906783 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 40039981 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 58078564 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 48988354 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 7585006 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 8037000 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 341408601 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 8081994 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 340240717 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 497823 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 47426361 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 29768333 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 191877 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 348440253 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.976468 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.690233 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 347479672 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.211147 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.937156 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 116319092 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 159338087 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 61493208 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 7257195 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 3070348 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 11216097 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 810528 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 368877230 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 2502393 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 3070348 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 120537316 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 11607372 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 129961960 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 64445904 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 17854957 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 360009684 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 40582 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 995330 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 792465 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 7726817 # Number of times rename has blocked due to SQ full +system.cpu3.rename.FullRegisterEvents 2104 # Number of times there has been no free registers +system.cpu3.rename.RenamedOperands 342963420 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 547080576 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 423978365 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 517857 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 286215822 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 56747593 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 7972839 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 6835897 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 39855447 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 58319848 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 48888042 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 7618365 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 8042184 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 341704043 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 8022599 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 340232336 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 497337 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 47823760 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 30164946 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 192380 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 347479672 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.979143 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.691890 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 216890475 62.25% 62.25% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 53877096 15.46% 77.71% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 24807816 7.12% 84.83% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 17922235 5.14% 89.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 13075143 3.75% 93.72% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 9287871 2.67% 96.39% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 6359964 1.83% 98.22% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 3675651 1.05% 99.27% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 2544002 0.73% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 216057167 62.18% 62.18% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 53646928 15.44% 77.62% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 24868918 7.16% 84.77% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 17968855 5.17% 89.95% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 13078366 3.76% 93.71% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 9279622 2.67% 96.38% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 6367435 1.83% 98.21% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 3674225 1.06% 99.27% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 2538156 0.73% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 348440253 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 347479672 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 1734447 26.04% 26.04% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 17043 0.26% 26.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 1093 0.02% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 2643216 39.68% 66.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 2264697 34.00% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 1739394 26.12% 26.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 17216 0.26% 26.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 1075 0.02% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 2643113 39.69% 66.09% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 2258125 33.91% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.FU_type_0::No_OpClass 10 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 231030792 67.90% 67.90% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 845869 0.25% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 38944 0.01% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 198 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 42651 0.01% 68.17% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.17% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.17% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.17% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 61002567 17.93% 86.10% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 47279686 13.90% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::No_OpClass 5 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 230928850 67.87% 67.87% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 888251 0.26% 68.13% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 40201 0.01% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 204 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 42408 0.01% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 61160195 17.98% 86.14% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 47172222 13.86% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 340240717 # Type of FU issued -system.cpu3.iq.rate 0.940734 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 6660496 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.019576 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 1035420885 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 396967626 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 327898797 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 659121 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 337856 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 293479 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 346548979 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 352224 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 2687529 # Number of loads that had data forwarded from stores +system.cpu3.iq.FU_type_0::total 340232336 # Type of FU issued +system.cpu3.iq.rate 0.943454 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 6658923 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.019572 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 1034449548 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 397601121 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 327921647 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 651056 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 333937 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 289983 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 346543457 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 347797 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 2684612 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 9720232 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 11871 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 394856 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 4837016 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 9848030 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 12099 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 390855 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 4852885 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 2125891 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 3923806 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.rescheduledLoads 2121686 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 3886704 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 3056510 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 7986555 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 2673304 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 349575098 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 1017291 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 58078564 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 48988354 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 6756692 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 121038 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 2506923 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 394856 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 1446513 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1609649 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 3056162 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 336167665 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 59696171 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 3560031 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewSquashCycles 3070348 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 8044361 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 2703635 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 349811697 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 1019337 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 58319848 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 48888042 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 6684338 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 123262 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 2534169 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 390855 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 1464138 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1603865 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 3068003 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 336172243 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 59848506 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 3553985 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 84503 # number of nop insts executed -system.cpu3.iew.exec_refs 106371515 # number of memory reference insts executed -system.cpu3.iew.exec_branches 62288679 # Number of branches executed -system.cpu3.iew.exec_stores 46675344 # Number of stores executed -system.cpu3.iew.exec_rate 0.929472 # Inst execution rate -system.cpu3.iew.wb_sent 329005088 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 328192276 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 162018804 # num instructions producing a value -system.cpu3.iew.wb_consumers 281033502 # num instructions consuming a value -system.cpu3.iew.wb_rate 0.907421 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.576511 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 47454465 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7890117 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 2611241 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 340404707 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.887368 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.879512 # Number of insts commited each cycle +system.cpu3.iew.exec_nop 85055 # number of nop insts executed +system.cpu3.iew.exec_refs 106421072 # number of memory reference insts executed +system.cpu3.iew.exec_branches 62316621 # Number of branches executed +system.cpu3.iew.exec_stores 46572566 # Number of stores executed +system.cpu3.iew.exec_rate 0.932195 # Inst execution rate +system.cpu3.iew.wb_sent 329026261 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 328211630 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 162144042 # num instructions producing a value +system.cpu3.iew.wb_consumers 281134898 # num instructions consuming a value +system.cpu3.iew.wb_rate 0.910121 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.576748 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 47849721 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7830219 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 2626302 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 339381548 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.889568 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.882377 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 230935782 67.84% 67.84% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 52807469 15.51% 83.35% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 18991951 5.58% 88.93% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8773061 2.58% 91.51% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 6429800 1.89% 93.40% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 3748451 1.10% 94.50% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 3528982 1.04% 95.54% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 2195360 0.64% 96.18% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 12993851 3.82% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 230141242 67.81% 67.81% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 52578609 15.49% 83.30% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 18989562 5.60% 88.90% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8770494 2.58% 91.48% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 6420925 1.89% 93.38% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 3757747 1.11% 94.48% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 3513397 1.04% 95.52% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 2195731 0.65% 96.17% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 13013841 3.83% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 340404707 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 257000704 # Number of instructions committed -system.cpu3.commit.committedOps 302064229 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 339381548 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 256941031 # Number of instructions committed +system.cpu3.commit.committedOps 301902877 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 92509669 # Number of memory references committed -system.cpu3.commit.loads 48358331 # Number of loads committed -system.cpu3.commit.membars 2078465 # Number of memory barriers committed -system.cpu3.commit.branches 57378073 # Number of branches committed -system.cpu3.commit.fp_insts 281556 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 277690269 # Number of committed integer instructions. -system.cpu3.commit.function_calls 7642177 # Number of function calls committed. +system.cpu3.commit.refs 92506974 # Number of memory references committed +system.cpu3.commit.loads 48471817 # Number of loads committed +system.cpu3.commit.membars 2097304 # Number of memory barriers committed +system.cpu3.commit.branches 57364518 # Number of branches committed +system.cpu3.commit.fp_insts 278173 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 277550130 # Number of committed integer instructions. +system.cpu3.commit.function_calls 7627094 # Number of function calls committed. system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 208831181 69.13% 69.13% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 657786 0.22% 69.35% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 28932 0.01% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 36661 0.01% 69.37% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.37% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.37% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.37% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 48358331 16.01% 85.38% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 44151338 14.62% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 208647320 69.11% 69.11% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 682317 0.23% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 29904 0.01% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 36362 0.01% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 48471817 16.06% 85.41% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 44035157 14.59% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 302064229 # Class of committed instruction -system.cpu3.commit.bw_lim_events 12993851 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 674816220 # The number of ROB reads -system.cpu3.rob.rob_writes 707084678 # The number of ROB writes -system.cpu3.timesIdled 2433054 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 13235547 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 98724531811 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 257000704 # Number of Instructions Simulated -system.cpu3.committedOps 302064229 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.407295 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.407295 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.710583 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.710583 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 395540710 # number of integer regfile reads -system.cpu3.int_regfile_writes 235084371 # number of integer regfile writes -system.cpu3.fp_regfile_reads 573493 # number of floating regfile reads -system.cpu3.fp_regfile_writes 349924 # number of floating regfile writes -system.cpu3.cc_regfile_reads 70842645 # number of cc regfile reads -system.cpu3.cc_regfile_writes 71511543 # number of cc regfile writes -system.cpu3.misc_regfile_reads 658562640 # number of misc regfile reads -system.cpu3.misc_regfile_writes 7924534 # number of misc regfile writes -system.iobus.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40262 # Transaction distribution -system.iobus.trans_dist::ReadResp 40262 # Transaction distribution +system.cpu3.commit.op_class_0::total 301902877 # Class of committed instruction +system.cpu3.commit.bw_lim_events 13013841 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 673991782 # The number of ROB reads +system.cpu3.rob.rob_writes 707616779 # The number of ROB writes +system.cpu3.timesIdled 2425895 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 13144639 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 98725614751 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 256941031 # Number of Instructions Simulated +system.cpu3.committedOps 301902877 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.403529 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.403529 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.712489 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.712489 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 395604640 # number of integer regfile reads +system.cpu3.int_regfile_writes 235195836 # number of integer regfile writes +system.cpu3.fp_regfile_reads 565870 # number of floating regfile reads +system.cpu3.fp_regfile_writes 351196 # number of floating regfile writes +system.cpu3.cc_regfile_reads 70807437 # number of cc regfile reads +system.cpu3.cc_regfile_writes 71493240 # number of cc regfile writes +system.cpu3.misc_regfile_reads 657110629 # number of misc regfile reads +system.cpu3.misc_regfile_writes 7862543 # number of misc regfile writes +system.iobus.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40272 # Transaction distribution +system.iobus.trans_dist::ReadResp 40272 # Transaction distribution system.iobus.trans_dist::WriteReq 136539 # Transaction distribution system.iobus.trans_dist::WriteResp 136539 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes) @@ -2289,11 +2292,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230966 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230966 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353602 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353622 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -2308,22 +2311,22 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155706 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334216 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334216 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334296 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334296 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492008 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13479500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492088 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13499000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 5500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 17500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) @@ -2335,68 +2338,68 @@ system.iobus.reqLayer16.occupancy 5000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 10717000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 10442000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 21643000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 21712500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 229106103 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 227539905 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 40091000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 39848000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 47420000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 45034000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115455 # number of replacements -system.iocache.tags.tagsinuse 10.425438 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115465 # number of replacements +system.iocache.tags.tagsinuse 10.425444 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115471 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115481 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13087296764009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544648 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.880790 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 13087293844009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544651 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.880792 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.221541 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.430049 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.430050 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.651590 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039614 # Number of tag accesses -system.iocache.tags.data_accesses 1039614 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039704 # Number of tag accesses +system.iocache.tags.data_accesses 1039704 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8809 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8846 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8819 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8856 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115473 # number of demand (read+write) misses -system.iocache.demand_misses::total 115513 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115483 # number of demand (read+write) misses +system.iocache.demand_misses::total 115523 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115473 # number of overall misses -system.iocache.overall_misses::total 115513 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 148237434 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 148237434 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 5184314669 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5184314669 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 5332552103 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5332552103 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 5332552103 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5332552103 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 115483 # number of overall misses +system.iocache.overall_misses::total 115523 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 61770218 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 61770218 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 5167926687 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5167926687 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 5229696905 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5229696905 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 5229696905 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5229696905 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8809 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8846 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8819 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8856 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115473 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115513 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115483 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115523 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115473 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115513 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115483 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115523 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2410,861 +2413,862 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 16827.952549 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 16757.566584 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 48604.165126 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 48604.165126 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 46180.077620 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 46164.086319 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 46180.077620 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 46164.086319 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 2296 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 7004.220206 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 6974.956865 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 48450.523954 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 48450.523954 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 45285.426470 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 45269.746328 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 45285.426470 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 45269.746328 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 417 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 267 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 40 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.599251 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.425000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 910 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 43872 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 43872 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 44782 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 44782 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 44782 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 44782 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 102737434 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 102737434 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2987814984 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2987814984 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 3090552418 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3090552418 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 3090552418 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3090552418 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.103303 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.102871 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.411310 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.411310 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.387814 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.387679 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.387814 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.387679 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112898.279121 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 112898.279121 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68103.003829 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68103.003829 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 69013.273592 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 69013.273592 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 69013.273592 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 69013.273592 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1178177 # number of replacements -system.l2c.tags.tagsinuse 65299.544871 # Cycle average of tags in use -system.l2c.tags.total_refs 47783107 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1240954 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 38.505140 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36300.809857 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 130.329243 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 195.620388 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3095.266131 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 10240.571353 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 40.874592 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 51.867132 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1035.336911 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2451.400254 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 46.677403 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 75.693349 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2509.241112 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 3335.896210 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.dtb.walker 90.056966 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.itb.walker 140.583636 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 1763.583672 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 3795.736663 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.553906 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001989 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.002985 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.047230 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.156259 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000624 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000791 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.015798 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.037405 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000712 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.001155 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.038288 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.050902 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.dtb.walker 0.001374 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.itb.walker 0.002145 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.026910 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.057918 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996392 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 349 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62428 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 348 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 625 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2851 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5174 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53676 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.005325 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.952576 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 423034153 # Number of tag accesses -system.l2c.tags.data_accesses 423034153 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.l2c.ReadReq_hits::cpu0.dtb.walker 166077 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 112464 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 54587 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 40813 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 152672 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 58108 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.dtb.walker 295679 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.itb.walker 104923 # number of ReadReq hits -system.l2c.ReadReq_hits::total 985323 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 7576706 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 7576706 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 15883082 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 15883082 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 3816 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1201 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 1641 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3.data 2839 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 9497 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu3.data 9 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 631099 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 192720 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 285985 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3.data 475632 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1585436 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 5464021 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 1712423 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 3852354 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 4762402 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 15791200 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 2579009 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 769324 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 1050953 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3.data 1900864 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 6300150 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 286592 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 87209 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu2.data 126708 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu3.data 229462 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 729971 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 166077 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 112464 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 5464021 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 3210108 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 54587 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 40813 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 1712423 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 962044 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 152672 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 58108 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 3852354 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 1336938 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.dtb.walker 295679 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.itb.walker 104923 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 4762402 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 2376496 # number of demand (read+write) hits -system.l2c.demand_hits::total 24662109 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 166077 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 112464 # number of overall hits -system.l2c.overall_hits::cpu0.inst 5464021 # number of overall hits -system.l2c.overall_hits::cpu0.data 3210108 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 54587 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 40813 # number of overall hits -system.l2c.overall_hits::cpu1.inst 1712423 # number of overall hits -system.l2c.overall_hits::cpu1.data 962044 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 152672 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 58108 # number of overall hits -system.l2c.overall_hits::cpu2.inst 3852354 # number of overall hits -system.l2c.overall_hits::cpu2.data 1336938 # number of overall hits -system.l2c.overall_hits::cpu3.dtb.walker 295679 # number of overall hits -system.l2c.overall_hits::cpu3.itb.walker 104923 # number of overall hits -system.l2c.overall_hits::cpu3.inst 4762402 # number of overall hits -system.l2c.overall_hits::cpu3.data 2376496 # number of overall hits -system.l2c.overall_hits::total 24662109 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1397 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1376 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 307 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 291 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 530 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.itb.walker 481 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.dtb.walker 1161 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.itb.walker 997 # number of ReadReq misses -system.l2c.ReadReq_misses::total 6540 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 13913 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4659 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 5652 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 10300 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 34524 # number of UpgradeReq misses +system.iocache.ReadReq_mshr_misses::realview.ide 453 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 453 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 43744 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 43744 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 44197 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 44197 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 44197 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 44197 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 39120218 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 39120218 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2977819124 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2977819124 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 3016939342 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3016939342 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 3016939342 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3016939342 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.051366 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.051152 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.410110 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.410110 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.382714 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.382582 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.382714 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.382582 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 86358.097130 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 86358.097130 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68073.772952 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68073.772952 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68261.179311 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68261.179311 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68261.179311 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68261.179311 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1182494 # number of replacements +system.l2c.tags.tagsinuse 65447.621193 # Cycle average of tags in use +system.l2c.tags.total_refs 49776356 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1245426 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 39.967333 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 395496000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 10450.326675 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 193.502647 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 222.666592 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3323.622390 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 21949.117178 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 56.686764 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 60.274211 # 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average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 74608.649517 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 80486.688431 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 77402.173905 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18735.566349 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 19463.878776 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 20265.380550 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19802.140652 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76247.557003 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76501.718213 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72230.738994 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72732.217945 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77517.924528 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 79884.615385 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 74128.467374 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73119.343807 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 81078.018966 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 78567.376900 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 76493.778962 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 86156.495668 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 78654.645010 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76247.557003 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76501.718213 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72230.738994 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72732.217945 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77517.924528 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 79884.615385 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 74128.467374 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73119.343807 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 81078.018966 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 78567.376900 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 76493.778962 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 86156.495668 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 78654.645010 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169058.180058 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 167139.504277 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 172277.427079 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169480.164827 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 88675.281812 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 88326.069317 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 89096.307554 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 88701.867895 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 2714288 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1358609 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3170 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.131264 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.126485 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.144501 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.081310 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.285714 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.198058 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.196303 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.191022 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.115750 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005927 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006555 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.005312 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.003842 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.038099 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.034659 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.035063 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.021111 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.180077 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data 0.197064 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data 0.235847 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.099807 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.006856 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.007783 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005927 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.076206 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003414 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.008524 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006555 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.074665 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.004412 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.010460 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.005312 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.070449 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.017151 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.006856 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.007783 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005927 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.076206 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003414 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.008524 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006555 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.074665 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.004412 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.010460 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.005312 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.070449 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.017151 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 73532.670455 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 79208.754209 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77850.701403 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 78091.503268 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 78846.609621 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 79183.908046 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 78271.370503 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18983.402490 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 18979.299363 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 18993.907392 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18987.825716 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 47750 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 47750 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71639.259480 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 72271.039815 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 90198.708570 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 80746.334432 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72645.761031 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 74466.403972 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 76479.277362 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 75002.119961 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74522.093180 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 74761.883946 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 80238.463604 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 77467.290341 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18745.477595 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 19446.900432 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 20257.972444 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19806.559829 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 73532.670455 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79208.754209 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72645.761031 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72737.176416 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77850.701403 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 78091.503268 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 74466.403972 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73141.111182 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 78846.609621 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 79183.908046 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 76479.277362 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 86366.234369 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 78876.128753 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73532.670455 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79208.754209 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72645.761031 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72737.176416 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77850.701403 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 78091.503268 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 74466.403972 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73141.111182 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 78846.609621 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 79183.908046 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 76479.277362 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 86366.234369 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 78876.128753 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169322.186942 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 167521.083679 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 172100.826626 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169640.892141 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 88820.997293 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 88477.267482 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 88773.283214 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 88695.776928 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 2692221 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1332095 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 2857 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 76739 # Transaction distribution -system.membus.trans_dist::ReadResp 446283 # Transaction distribution +system.membus.trans_dist::ReadResp 448186 # Transaction distribution system.membus.trans_dist::WriteReq 33648 # Transaction distribution system.membus.trans_dist::WriteResp 33648 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1091848 # Transaction distribution -system.membus.trans_dist::CleanEvict 200785 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35184 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1094121 # Transaction distribution +system.membus.trans_dist::CleanEvict 202838 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4443 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14271 # Transaction distribution -system.membus.trans_dist::ReadExReq 414448 # Transaction distribution -system.membus.trans_dist::ReadExResp 414448 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 369544 # Transaction distribution -system.membus.trans_dist::InvalidateReq 602468 # Transaction distribution -system.membus.trans_dist::InvalidateResp 435243 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1867 # Transaction distribution +system.membus.trans_dist::ReadExReq 416227 # Transaction distribution +system.membus.trans_dist::ReadExResp 416227 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 371447 # Transaction distribution +system.membus.trans_dist::InvalidateReq 603124 # Transaction distribution +system.membus.trans_dist::InvalidateResp 437026 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6762 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3736384 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3865780 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 302176 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 302176 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4167956 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3707227 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3836623 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 302374 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 302374 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4138997 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155706 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13524 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 112845536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 113014898 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7362816 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7362816 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 120377714 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 603 # Total snoops (count) -system.membus.snoopTraffic 38528 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2230474 # Request fanout histogram -system.membus.snoop_fanout::mean 0.016353 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.126827 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 113227104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 113396466 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7366016 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7366016 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 120762482 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 546 # Total snoops (count) +system.membus.snoopTraffic 34880 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2213347 # Request fanout histogram +system.membus.snoop_fanout::mean 0.016167 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.126119 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2194000 98.36% 98.36% # Request fanout histogram -system.membus.snoop_fanout::1 36474 1.64% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2177563 98.38% 98.38% # Request fanout histogram +system.membus.snoop_fanout::1 35784 1.62% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2230474 # Request fanout histogram -system.membus.reqLayer0.occupancy 45941500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2213347 # Request fanout histogram +system.membus.reqLayer0.occupancy 45757000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1601000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1572000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 3279160105 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 3230054159 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2368546008 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2350415750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 4606769 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 2301227 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3307,86 +3311,86 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 52014816 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 26342736 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 3149 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2216 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2216 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 52031861 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 26343539 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 3136 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2272 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2272 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 1497604 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 23943591 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 1497693 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 23955179 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33648 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33648 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 8020601 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 15885620 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2314166 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 44021 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 44032 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2000482 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2000482 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 15886240 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 6559913 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1231249 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1225834 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47744160 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29579701 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 811490 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1741524 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 79876875 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2033559380 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1032953822 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2918064 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6139128 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 3075570394 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1503666 # Total snoops (count) -system.toL2Bus.snoopTraffic 65422752 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 38127714 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.016625 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.127861 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 8020839 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 15900080 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2311396 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 28791 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28798 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2005082 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2005082 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 15900700 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 6556911 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1231319 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1226027 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47787527 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29554737 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 797902 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1720271 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 79860437 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2035409428 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1033316830 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2813832 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 5963920 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 3077504010 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1542362 # Total snoops (count) +system.toL2Bus.snoopTraffic 65849016 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 38107926 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.016628 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.127874 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 37493845 98.34% 98.34% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 633869 1.66% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 37474258 98.34% 98.34% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 633668 1.66% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 38127714 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 31242309916 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 38107926 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 31293825988 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 523765 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 519265 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 15589083360 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 15589080685 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 7892971168 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 7944642139 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 287709740 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 286385229 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 712482327 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 714971913 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu3.kern.inst.arm 0 # number of arm instructions executed system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt index 1ebab8c9c..cbc921b4f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt @@ -1,158 +1,158 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.317224 # Number of seconds simulated -sim_ticks 51317223946000 # Number of ticks simulated -final_tick 51317223946000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.317217 # Number of seconds simulated +sim_ticks 51317217215000 # Number of ticks simulated +final_tick 51317217215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 175740 # Simulator instruction rate (inst/s) -host_op_rate 206507 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9897363484 # Simulator tick rate (ticks/s) -host_mem_usage 694116 # Number of bytes of host memory used -host_seconds 5184.94 # Real time elapsed on the host -sim_insts 911201050 # Number of instructions simulated -sim_ops 1070728401 # Number of ops (including micro ops) simulated +host_inst_rate 222365 # Simulator instruction rate (inst/s) +host_op_rate 261300 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12534471719 # Simulator tick rate (ticks/s) +host_mem_usage 700016 # Number of bytes of host memory used +host_seconds 4094.09 # Real time elapsed on the host +sim_insts 910382802 # Number of instructions simulated +sim_ops 1069785844 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 175488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 146560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3612352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 27482328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 187136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 157760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3726080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 29409648 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 423552 # Number of bytes read from this memory -system.physmem.bytes_read::total 65320904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3612352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3726080 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7338432 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 83980672 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 183360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 154432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3744320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 27933912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 182144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 147072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3576960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 29113392 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 413632 # Number of bytes read from this memory +system.physmem.bytes_read::total 65449224 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3744320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3576960 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7321280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 83967296 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 84001252 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2742 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2290 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 56443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 429419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2924 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2465 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 58220 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 459531 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6618 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1020652 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1312198 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 83987876 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2865 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2413 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 58505 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 436475 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2846 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2298 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 55890 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 454902 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6463 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1022657 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1311989 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1314771 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 70393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 535538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3647 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 72609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 573095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8254 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1272885 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 70393 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 72609 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 143001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1636501 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1314562 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3573 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3009 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 72964 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 544338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3549 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2866 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 69703 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 567322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8060 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1275385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 72964 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 69703 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 142667 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1636240 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1636902 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1636501 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 70393 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 535939 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3074 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 72609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 573095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8254 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2909786 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1020652 # Number of read requests accepted -system.physmem.writeReqs 1314771 # Number of write requests accepted -system.physmem.readBursts 1020652 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1314771 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 65284928 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 36800 # Total number of bytes read from write queue -system.physmem.bytesWritten 84000896 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 65320904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 84001252 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 575 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2239 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1636641 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1636240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3009 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 72964 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 544739 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3549 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2866 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 69703 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 567322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8060 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2912027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1022657 # Number of read requests accepted +system.physmem.writeReqs 1314562 # Number of write requests accepted +system.physmem.readBursts 1022657 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1314562 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 65407680 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 42368 # Total number of bytes read from write queue +system.physmem.bytesWritten 83988672 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 65449224 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 83987876 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 662 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2238 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 60738 # Per bank write bursts -system.physmem.perBankRdBursts::1 63324 # Per bank write bursts -system.physmem.perBankRdBursts::2 61558 # Per bank write bursts -system.physmem.perBankRdBursts::3 59296 # Per bank write bursts -system.physmem.perBankRdBursts::4 63003 # Per bank write bursts -system.physmem.perBankRdBursts::5 70930 # Per bank write bursts -system.physmem.perBankRdBursts::6 62473 # Per bank write bursts -system.physmem.perBankRdBursts::7 61273 # Per bank write bursts -system.physmem.perBankRdBursts::8 57204 # Per bank write bursts -system.physmem.perBankRdBursts::9 83606 # Per bank write bursts -system.physmem.perBankRdBursts::10 64602 # Per bank write bursts -system.physmem.perBankRdBursts::11 64452 # Per bank write bursts -system.physmem.perBankRdBursts::12 60809 # Per bank write bursts -system.physmem.perBankRdBursts::13 66792 # Per bank write bursts -system.physmem.perBankRdBursts::14 61061 # Per bank write bursts -system.physmem.perBankRdBursts::15 58956 # Per bank write bursts -system.physmem.perBankWrBursts::0 80045 # Per bank write bursts -system.physmem.perBankWrBursts::1 81301 # Per bank write bursts -system.physmem.perBankWrBursts::2 81272 # Per bank write bursts -system.physmem.perBankWrBursts::3 81440 # Per bank write bursts -system.physmem.perBankWrBursts::4 83523 # Per bank write bursts -system.physmem.perBankWrBursts::5 87218 # Per bank write bursts -system.physmem.perBankWrBursts::6 82653 # Per bank write bursts -system.physmem.perBankWrBursts::7 82595 # Per bank write bursts -system.physmem.perBankWrBursts::8 79330 # Per bank write bursts -system.physmem.perBankWrBursts::9 83624 # Per bank write bursts -system.physmem.perBankWrBursts::10 82850 # Per bank write bursts -system.physmem.perBankWrBursts::11 84015 # Per bank write bursts -system.physmem.perBankWrBursts::12 79570 # Per bank write bursts -system.physmem.perBankWrBursts::13 84630 # Per bank write bursts -system.physmem.perBankWrBursts::14 79832 # Per bank write bursts -system.physmem.perBankWrBursts::15 78616 # Per bank write bursts +system.physmem.perBankRdBursts::0 60981 # Per bank write bursts +system.physmem.perBankRdBursts::1 62566 # Per bank write bursts +system.physmem.perBankRdBursts::2 61229 # Per bank write bursts +system.physmem.perBankRdBursts::3 58916 # Per bank write bursts +system.physmem.perBankRdBursts::4 63354 # Per bank write bursts +system.physmem.perBankRdBursts::5 70912 # Per bank write bursts +system.physmem.perBankRdBursts::6 62699 # Per bank write bursts +system.physmem.perBankRdBursts::7 61112 # Per bank write bursts +system.physmem.perBankRdBursts::8 58244 # Per bank write bursts +system.physmem.perBankRdBursts::9 84348 # Per bank write bursts +system.physmem.perBankRdBursts::10 65094 # Per bank write bursts +system.physmem.perBankRdBursts::11 66290 # Per bank write bursts +system.physmem.perBankRdBursts::12 61782 # Per bank write bursts +system.physmem.perBankRdBursts::13 66140 # Per bank write bursts +system.physmem.perBankRdBursts::14 59027 # Per bank write bursts +system.physmem.perBankRdBursts::15 59301 # Per bank write bursts +system.physmem.perBankWrBursts::0 79428 # Per bank write bursts +system.physmem.perBankWrBursts::1 80879 # Per bank write bursts +system.physmem.perBankWrBursts::2 81341 # Per bank write bursts +system.physmem.perBankWrBursts::3 82396 # Per bank write bursts +system.physmem.perBankWrBursts::4 84257 # Per bank write bursts +system.physmem.perBankWrBursts::5 87543 # Per bank write bursts +system.physmem.perBankWrBursts::6 80825 # Per bank write bursts +system.physmem.perBankWrBursts::7 81935 # Per bank write bursts +system.physmem.perBankWrBursts::8 79231 # Per bank write bursts +system.physmem.perBankWrBursts::9 83962 # Per bank write bursts +system.physmem.perBankWrBursts::10 83023 # Per bank write bursts +system.physmem.perBankWrBursts::11 84619 # Per bank write bursts +system.physmem.perBankWrBursts::12 80226 # Per bank write bursts +system.physmem.perBankWrBursts::13 84960 # Per bank write bursts +system.physmem.perBankWrBursts::14 78537 # Per bank write bursts +system.physmem.perBankWrBursts::15 79161 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 119 # Number of times write queue was full causing retry -system.physmem.totGap 51317222751500 # Total gap between requests +system.physmem.numWrRetry 117 # Number of times write queue was full causing retry +system.physmem.totGap 51317216009000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1020637 # Read request sizes (log2) +system.physmem.readPktSize::6 1022642 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1312198 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 562832 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 301764 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 103549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 46162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 768 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 224 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 89 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 65 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1311989 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 563394 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 302594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 104127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 46335 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 752 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 511 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 662 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1269 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 99 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 84 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -163,176 +163,190 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 726 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 22114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 30315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 42487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 50854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 67639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 74945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 78298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 83924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 86856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 84418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 87663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 90523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 82299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 81232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 81562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 72278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 70890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 67228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 1046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 298 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 586236 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 254.650755 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 152.083309 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 294.038467 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 256952 43.83% 43.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 146727 25.03% 68.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 55530 9.47% 78.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 27689 4.72% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 21119 3.60% 86.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11926 2.03% 88.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10672 1.82% 90.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7426 1.27% 91.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 48195 8.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 586236 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61671 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.539767 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 65.609404 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 61664 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::6 723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 21758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 29866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 42370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 50746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 67407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 74973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 78027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 83029 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 86506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 84131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 87193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 90592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 82439 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 80936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 81560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 72513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 71387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 67468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3626 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 1091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 292 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 584051 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 255.792785 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 152.875634 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 294.556382 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 254148 43.51% 43.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 146795 25.13% 68.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 55909 9.57% 78.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27613 4.73% 82.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 21352 3.66% 86.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11974 2.05% 88.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10495 1.80% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7232 1.24% 91.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 48533 8.31% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 584051 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61706 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.562133 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 65.554683 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 61699 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::512-1023 3 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-2559 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61671 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61671 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.282515 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.526147 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.873212 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-31 57372 93.03% 93.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-63 2142 3.47% 96.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-95 1045 1.69% 98.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-127 638 1.03% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-159 205 0.33% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-191 106 0.17% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-223 28 0.05% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-255 57 0.09% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-287 30 0.05% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-319 6 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-351 4 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-383 11 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-415 7 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-447 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-479 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-511 4 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-543 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-607 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::608-639 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-671 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::736-767 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::864-895 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::896-927 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::960-991 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::992-1023 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1504-1535 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61671 # Writes before turning the bus around for reads -system.physmem.totQLat 27430760765 # Total ticks spent queuing -system.physmem.totMemAccLat 46557204515 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5100385000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26890.87 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 61706 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61706 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.267348 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.511616 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.799712 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-15 139 0.23% 0.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 57235 92.75% 92.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 1751 2.84% 95.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 438 0.71% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 620 1.00% 97.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 435 0.70% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 261 0.42% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 360 0.58% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 146 0.24% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 47 0.08% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 57 0.09% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 58 0.09% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 16 0.03% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 17 0.03% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 19 0.03% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 28 0.05% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 17 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 15 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 6 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 3 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 5 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 4 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 4 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-623 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::752-767 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::768-783 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::784-799 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::832-847 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::848-863 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::864-879 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::880-895 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::896-911 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 61706 # Writes before turning the bus around for reads +system.physmem.totQLat 27544031458 # Total ticks spent queuing +system.physmem.totMemAccLat 46706437708 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5109975000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26951.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45640.87 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 45701.24 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.64 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.27 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.28 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.64 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.21 # Average write queue length when enqueuing -system.physmem.readRowHits 787981 # Number of row buffer hits during reads -system.physmem.writeRowHits 958372 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.02 # Row buffer hit rate for writes -system.physmem.avgGap 21973416.70 # Average gap between requests -system.physmem.pageHitRate 74.87 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2249478000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1227393750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3920233200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4277104560 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3351791311440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1233069997860 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29708691447750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34305226966560 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.493484 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49422945373021 # Time in different power states -system.physmem_0.memoryStateTime::REF 1713594740000 # Time in different power states +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 9.79 # Average write queue length when enqueuing +system.physmem.readRowHits 789656 # Number of row buffer hits during reads +system.physmem.writeRowHits 960610 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.27 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.20 # Row buffer hit rate for writes +system.physmem.avgGap 21956528.68 # Average gap between requests +system.physmem.pageHitRate 74.98 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2223494280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1213216125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3913798200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4267753920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3351790802880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1231075762515 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29710436097000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34304920924920 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.487622 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49425844576094 # Time in different power states +system.physmem_0.memoryStateTime::REF 1713594480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 180683706479 # Time in different power states +system.physmem_0.memoryStateTime::ACT 177772818906 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2182466160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1190829750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4036320600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4227986160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3351791311440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1230809355630 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29710674459000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34304912728740 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.487361 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49426230251457 # Time in different power states -system.physmem_1.memoryStateTime::REF 1713594740000 # Time in different power states +system.physmem_1.actEnergy 2191931280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1195994250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4057723800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4236099120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3351790802880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1231757755830 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29709837865500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34305068172660 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.490491 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49424824907095 # Time in different power states +system.physmem_1.memoryStateTime::REF 1713594480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 177398580543 # Time in different power states +system.physmem_1.memoryStateTime::ACT 178797453905 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 1408 # Number of bytes read from this memory @@ -355,30 +369,30 @@ system.realview.nvmem.bw_total::cpu0.inst 15 # T system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 27 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 43 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 134105303 # Number of BP lookups -system.cpu0.branchPred.condPredicted 90165699 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5786352 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 89882943 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 61723151 # Number of BTB hits +system.cpu0.branchPred.lookups 134591179 # Number of BP lookups +system.cpu0.branchPred.condPredicted 90304193 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5810526 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 90589543 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 61837798 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 68.670594 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 17198111 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 190210 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 5005537 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2645934 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 2359603 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 409587 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 68.261519 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17370059 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 190077 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 5078772 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2686505 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 2392267 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 411015 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -408,95 +422,89 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 899770 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 899770 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17075 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 93436 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 556454 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 343316 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2623.475166 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 14944.534863 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-32767 334883 97.54% 97.54% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-65535 5615 1.64% 99.18% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-98303 1161 0.34% 99.52% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::98304-131071 826 0.24% 99.76% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-163839 305 0.09% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::163840-196607 149 0.04% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-229375 96 0.03% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::229376-262143 57 0.02% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-294911 86 0.03% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::294912-327679 45 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-360447 14 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::360448-393215 18 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-425983 26 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::425984-458751 33 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 343316 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 426919 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 23051.464095 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 18844.709714 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 16480.973938 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 417565 97.81% 97.81% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 8400 1.97% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 455 0.11% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 392 0.09% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 913460 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 913460 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17456 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 94858 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 564703 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 348757 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2510.769676 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 14687.468261 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 346035 99.22% 99.22% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1894 0.54% 99.76% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 459 0.13% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 149 0.04% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 127 0.04% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 27 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 61 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 348757 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 428972 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 22512.397080 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18206.266840 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 16738.101214 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 419694 97.84% 97.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 8206 1.91% 99.75% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 548 0.13% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 418 0.10% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::262144-327679 68 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 32 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 426919 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 352898234664 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.139794 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.715758 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-3 351858805164 99.71% 99.71% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-7 566388500 0.16% 99.87% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-11 206550000 0.06% 99.92% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-15 120953500 0.03% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-19 47115000 0.01% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-23 25743000 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-27 26226000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-31 38984000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::32-35 6924500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::36-39 487500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::40-43 24000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::44-47 16500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::48-51 16500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::52-55 500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 352898234664 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 93436 84.55% 84.55% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 17075 15.45% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 110511 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 899770 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 26 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 428972 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 361724793256 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.150757 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.705483 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-3 360695140256 99.72% 99.72% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-7 568723500 0.16% 99.87% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-11 203544500 0.06% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-15 117776000 0.03% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-19 46114500 0.01% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-23 23872000 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-27 26539000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-31 36172500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::32-35 6478000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::36-39 375000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::40-43 38000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::44-47 6500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::48-51 12500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::52-55 1000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 361724793256 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 94859 84.46% 84.46% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 17456 15.54% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 112315 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 913460 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 899770 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 110511 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 913460 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 112315 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 110511 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 1010281 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 112315 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 1025775 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 105998610 # DTB read hits -system.cpu0.dtb.read_misses 619021 # DTB read misses -system.cpu0.dtb.write_hits 82262350 # DTB write hits -system.cpu0.dtb.write_misses 280749 # DTB write misses -system.cpu0.dtb.flush_tlb 1081 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 106460809 # DTB read hits +system.cpu0.dtb.read_misses 623704 # DTB read misses +system.cpu0.dtb.write_hits 82932208 # DTB write hits +system.cpu0.dtb.write_misses 289756 # DTB write misses +system.cpu0.dtb.flush_tlb 1080 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 22329 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 21954 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 55918 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 189 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9571 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 55225 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 193 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9182 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 57075 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 106617631 # DTB read accesses -system.cpu0.dtb.write_accesses 82543099 # DTB write accesses +system.cpu0.dtb.perms_faults 56785 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 107084513 # DTB read accesses +system.cpu0.dtb.write_accesses 83221964 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 188260960 # DTB hits -system.cpu0.dtb.misses 899770 # DTB misses -system.cpu0.dtb.accesses 189160730 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 189393017 # DTB hits +system.cpu0.dtb.misses 913460 # DTB misses +system.cpu0.dtb.accesses 190306477 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -526,859 +534,861 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 102467 # Table walker walks requested -system.cpu0.itb.walker.walksLong 102467 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 2998 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 69670 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 14196 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 88271 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1375.933206 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 8810.022108 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 87313 98.91% 98.91% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 590 0.67% 99.58% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 225 0.25% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 97 0.11% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 16 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 14 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 88271 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 86864 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 28386.103564 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 24197.471815 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 17986.515042 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 84889 97.73% 97.73% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1706 1.96% 99.69% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 161 0.19% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 62 0.07% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 31 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 13 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 102224 # Table walker walks requested +system.cpu0.itb.walker.walksLong 102224 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 2961 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 69807 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 13996 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 88228 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1371.061341 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 8977.114896 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 87329 98.98% 98.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 530 0.60% 99.58% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 216 0.24% 99.83% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 99 0.11% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 20 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 15 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 88228 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 86764 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 27719.480430 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23267.563993 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 18820.928470 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 84648 97.56% 97.56% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1819 2.10% 99.66% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 174 0.20% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 69 0.08% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 30 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 20 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 86864 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 606302699128 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.904496 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.294288 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 57963600068 9.56% 9.56% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 548286629060 90.43% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 47140500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 4566000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 404000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 270000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::6 89500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 606302699128 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 69670 95.87% 95.87% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2998 4.13% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 72668 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 86764 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 597945449536 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.915932 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.277880 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 50325346976 8.42% 8.42% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 547568596060 91.58% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 46828000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 4056500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 391500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 54500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::6 126500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::7 49500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 597945449536 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 69807 95.93% 95.93% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2961 4.07% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 72768 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 102467 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 102467 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 102224 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 102224 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72668 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72668 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 175135 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 94697092 # ITB inst hits -system.cpu0.itb.inst_misses 102467 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72768 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72768 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 174992 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 95313688 # ITB inst hits +system.cpu0.itb.inst_misses 102224 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1081 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1080 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 22329 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 21954 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 41669 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 40789 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 188921 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 189995 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 94799559 # ITB inst accesses -system.cpu0.itb.hits 94697092 # DTB hits -system.cpu0.itb.misses 102467 # DTB misses -system.cpu0.itb.accesses 94799559 # DTB accesses -system.cpu0.numPwrStateTransitions 15974 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 7987 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 2945663211.345562 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 55329339473.705994 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3525 44.13% 44.13% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 4444 55.64% 99.77% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 2 0.03% 99.80% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.03% 99.82% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.85% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 3 0.04% 99.89% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 8 0.10% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 95415912 # ITB inst accesses +system.cpu0.itb.hits 95313688 # DTB hits +system.cpu0.itb.misses 102224 # DTB misses +system.cpu0.itb.accesses 95415912 # DTB accesses +system.cpu0.numPwrStateTransitions 16182 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 8091 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 3359442146.645409 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 64779765350.946983 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3624 44.79% 44.79% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 4450 55.00% 99.79% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.80% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 3 0.04% 99.84% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 10 0.12% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 1988782294428 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 7987 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 27790211876983 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 23527012069017 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 671968082 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 1988782283928 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 8091 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 24135970806492 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 27181246408508 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 673796045 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 245522731 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 595240198 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 134105303 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 81567196 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 387351290 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 13225502 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2523731 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 22012 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 3023 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 4782962 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 167694 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 2395 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 94491838 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 3604496 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 39400 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 646988319 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.075576 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.327336 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 248201376 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 597842349 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 134591179 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 81894362 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 386081151 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 13278647 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2497741 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 21664 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 3050 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 4790854 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 168722 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 2591 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 95107499 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 3628886 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 39039 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 648406203 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.078367 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.330450 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 500985180 77.43% 77.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 18129867 2.80% 80.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 18167874 2.81% 83.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 13357518 2.06% 85.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 28640593 4.43% 89.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 8987633 1.39% 90.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 9763680 1.51% 92.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 8383348 1.30% 93.73% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 40572626 6.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 501760932 77.38% 77.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 18256203 2.82% 80.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 18220690 2.81% 83.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 13435350 2.07% 85.08% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 28609960 4.41% 89.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 9048805 1.40% 90.89% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 9824320 1.52% 92.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 8413306 1.30% 93.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 40836637 6.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 646988319 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.199571 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.885816 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 199030326 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 322925985 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 105893213 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 13875278 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5261155 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19621820 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 1370848 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 649217042 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 4232345 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5261155 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 206721651 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 22515587 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 261202094 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 111943526 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 39341608 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 633848526 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 79662 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1830943 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 1627304 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 19580203 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 3993 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 606139321 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 975790571 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 747374109 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 852582 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 509962376 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 96176945 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 15656160 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 13698263 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 77451785 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 102163876 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 86418656 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 13880040 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 14667641 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 600742993 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 15759066 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 601574255 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 855603 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 81711782 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 51353600 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 357908 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 646988319 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.929807 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.657116 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 648406203 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.199751 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.887275 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 201305382 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 321428647 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 106579942 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 13809088 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5281102 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19732890 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 1377081 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 652345167 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 4243358 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5281102 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 208974593 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 22808368 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 259762289 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 112590129 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 38987372 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 636948284 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 76415 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1870283 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 1736148 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 19269388 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 3866 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 608166873 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 978325960 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 751087221 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 834633 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 511551111 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 96615757 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 15505583 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 13521940 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 76964594 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 102747908 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 87125063 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 13952178 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 14707468 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 603971660 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 15594199 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 604455425 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 868037 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 82226578 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 51472860 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 368538 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 648406203 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.932217 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.660002 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 411195381 63.56% 63.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 99990691 15.45% 79.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 43358439 6.70% 85.71% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 31042131 4.80% 90.51% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 23015507 3.56% 94.07% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 16185943 2.50% 96.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 11141665 1.72% 98.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 6569936 1.02% 99.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 4488626 0.69% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 412086930 63.55% 63.55% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 99690109 15.37% 78.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 43563237 6.72% 85.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 31279787 4.82% 90.47% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 23126821 3.57% 94.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 16303260 2.51% 96.55% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 11232229 1.73% 98.28% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 6608117 1.02% 99.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 4515713 0.70% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 646988319 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 648406203 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 2994179 25.40% 25.40% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 22123 0.19% 25.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 2181 0.02% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4797008 40.69% 66.30% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 3972728 33.70% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 3047764 25.70% 25.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 24416 0.21% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 3438 0.03% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4792960 40.42% 66.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 3990225 33.65% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 51 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 408493998 67.90% 67.90% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1413538 0.23% 68.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 65279 0.01% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 146 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 55915 0.01% 68.16% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.16% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.16% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.16% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 108222779 17.99% 86.15% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 83322549 13.85% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 49 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 410215443 67.87% 67.87% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1414052 0.23% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 66288 0.01% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 164 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 69960 0.01% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 108687129 17.98% 86.10% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 84002340 13.90% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 601574255 # Type of FU issued -system.cpu0.iq.rate 0.895242 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 11788219 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019596 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1861718464 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 698381981 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 579322691 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1062187 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 541590 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 470908 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 612794722 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 567701 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 4798771 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 604455425 # Type of FU issued +system.cpu0.iq.rate 0.897090 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 11858803 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019619 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1868979076 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 701958936 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 582265082 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1064817 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 542988 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 473036 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 615746479 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 567700 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 4852034 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 16823750 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 20061 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 720899 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 8636995 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 16874429 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 20604 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 721236 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 8753871 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 4014042 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 7828481 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 4029020 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 7690355 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5261155 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14418671 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 6592888 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 616647515 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 1731555 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 102163876 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 86418656 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13404445 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 244099 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 6259110 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 720899 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2467872 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2697760 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5165632 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 594649792 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 105987908 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 6038347 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 5281102 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14719425 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 6525674 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 619711534 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 1741377 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 102747908 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 87125063 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13231258 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 247990 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 6185988 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 721236 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2486586 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2703924 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5190510 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 597504652 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 106449995 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 6051495 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 145456 # number of nop insts executed -system.cpu0.iew.exec_refs 188253040 # number of memory reference insts executed -system.cpu0.iew.exec_branches 110177692 # Number of branches executed -system.cpu0.iew.exec_stores 82265132 # Number of stores executed -system.cpu0.iew.exec_rate 0.884938 # Inst execution rate -system.cpu0.iew.wb_sent 581218511 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 579793599 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 286101590 # num instructions producing a value -system.cpu0.iew.wb_consumers 497649201 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.862829 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.574906 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 81765486 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 15401158 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4434486 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 633109401 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.844704 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.839642 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 145675 # number of nop insts executed +system.cpu0.iew.exec_refs 189385273 # number of memory reference insts executed +system.cpu0.iew.exec_branches 110604743 # Number of branches executed +system.cpu0.iew.exec_stores 82935278 # Number of stores executed +system.cpu0.iew.exec_rate 0.886774 # Inst execution rate +system.cpu0.iew.wb_sent 584170266 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 582738118 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 287532720 # num instructions producing a value +system.cpu0.iew.wb_consumers 500025728 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.864858 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.575036 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 82281412 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 15225661 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4452035 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 634456144 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.846929 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.842512 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 436470478 68.94% 68.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 97716674 15.43% 84.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 32967148 5.21% 89.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 15484157 2.45% 92.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 10846506 1.71% 93.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 6530507 1.03% 94.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6073156 0.96% 95.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3956859 0.62% 96.36% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 23063916 3.64% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 437517078 68.96% 68.96% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 97256113 15.33% 84.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 33197387 5.23% 89.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 15688308 2.47% 91.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 10938676 1.72% 93.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 6579950 1.04% 94.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6141511 0.97% 95.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3977023 0.63% 96.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 23160098 3.65% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 633109401 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 455072762 # Number of instructions committed -system.cpu0.commit.committedOps 534790277 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 634456144 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 457096110 # Number of instructions committed +system.cpu0.commit.committedOps 537339276 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 163121787 # Number of memory references committed -system.cpu0.commit.loads 85340126 # Number of loads committed -system.cpu0.commit.membars 3736581 # Number of memory barriers committed -system.cpu0.commit.branches 101711661 # Number of branches committed -system.cpu0.commit.fp_insts 451530 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 490677146 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13330927 # Number of function calls committed. +system.cpu0.commit.refs 164244670 # Number of memory references committed +system.cpu0.commit.loads 85873478 # Number of loads committed +system.cpu0.commit.membars 3759461 # Number of memory barriers committed +system.cpu0.commit.branches 102099172 # Number of branches committed +system.cpu0.commit.fp_insts 454376 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 493297626 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13466186 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 370465668 69.27% 69.27% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1106577 0.21% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 48950 0.01% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 47295 0.01% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 85340126 15.96% 85.46% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 77781661 14.54% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 371876704 69.21% 69.21% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1107747 0.21% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 49726 0.01% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 60429 0.01% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 85873478 15.98% 85.41% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 78371192 14.59% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 534790277 # Class of committed instruction -system.cpu0.commit.bw_lim_events 23063916 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1222566942 # The number of ROB reads -system.cpu0.rob.rob_writes 1247016110 # The number of ROB writes -system.cpu0.timesIdled 4124153 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 24979763 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 47054019698 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 455072762 # Number of Instructions Simulated -system.cpu0.committedOps 534790277 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.476617 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.476617 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.677224 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.677224 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 700310786 # number of integer regfile reads -system.cpu0.int_regfile_writes 414023994 # number of integer regfile writes -system.cpu0.fp_regfile_reads 859135 # number of floating regfile reads -system.cpu0.fp_regfile_writes 476716 # number of floating regfile writes -system.cpu0.cc_regfile_reads 127822251 # number of cc regfile reads -system.cpu0.cc_regfile_writes 129020802 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1207381115 # number of misc regfile reads -system.cpu0.misc_regfile_writes 15553504 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 10794591 # number of replacements +system.cpu0.commit.op_class_0::total 537339276 # Class of committed instruction +system.cpu0.commit.bw_lim_events 23160098 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1226917419 # The number of ROB reads +system.cpu0.rob.rob_writes 1253216154 # The number of ROB writes +system.cpu0.timesIdled 4189702 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 25389842 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 54362488365 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 457096110 # Number of Instructions Simulated +system.cpu0.committedOps 537339276 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.474080 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.474080 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.678389 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.678389 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 703759932 # number of integer regfile reads +system.cpu0.int_regfile_writes 416323236 # number of integer regfile writes +system.cpu0.fp_regfile_reads 842814 # number of floating regfile reads +system.cpu0.fp_regfile_writes 524896 # number of floating regfile writes +system.cpu0.cc_regfile_reads 127590054 # number of cc regfile reads +system.cpu0.cc_regfile_writes 128777466 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1210356696 # number of misc regfile reads +system.cpu0.misc_regfile_writes 15381690 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 10779491 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.983410 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 308312311 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10795103 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.560386 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 308062266 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10780003 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.577197 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1667914500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 290.025597 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 221.957813 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.566456 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.433511 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 303.491043 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 208.492367 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.592756 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.407212 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1361016734 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1361016734 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 81465542 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 81638403 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 163103945 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 68252369 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 68428120 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 136680489 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200713 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 207163 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 407876 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 171912 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 153997 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 325909 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1802432 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1798763 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3601195 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2076413 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2068312 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 4144725 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 149889823 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 150220520 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 300110343 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 150090536 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 150427683 # number of overall hits -system.cpu0.dcache.overall_hits::total 300518219 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6267923 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 6604970 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 12872893 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 6633530 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 6545682 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 13179212 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 651993 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 686156 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1338149 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 638733 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 602965 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1241698 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 328325 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 330976 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 659301 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 8 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 5 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 13540186 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 13753617 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 27293803 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 14192179 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 14439773 # number of overall misses -system.cpu0.dcache.overall_misses::total 28631952 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 95137339500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 103283573000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 198420912500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 235524203196 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 229624162852 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 465148366048 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 14948853955 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 13357374592 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 28306228547 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4139762000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 4347889500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 8487651500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 110000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 214000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 324000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 345610396651 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 346265110444 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 691875507095 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 345610396651 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 346265110444 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 691875507095 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 87733465 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 88243373 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 175976838 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74885899 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 74973802 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 149859701 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 852706 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 893319 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1746025 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 810645 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 756962 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1567607 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2130757 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2129739 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 4260496 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2076421 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2068317 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 4144738 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 163430009 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 163974137 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 327404146 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 164282715 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 164867456 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 329150171 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.071443 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.074849 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.073151 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.088582 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.087306 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.087944 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.764616 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.768097 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766397 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.787932 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.796559 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.792098 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.154088 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155407 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.154747 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000004 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000002 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000003 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.082850 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.083877 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.083364 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086389 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.087584 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.086988 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15178.447390 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15637.250888 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15413.855495 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35505.108622 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35080.250286 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 35294.095432 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 23403.916746 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 22152.819139 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 22796.387324 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12608.732201 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13136.570325 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12873.712462 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13750 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 42800 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24923.076923 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25524.789442 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25176.294385 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25349.179339 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24352.172887 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23979.955256 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 24164.454701 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 50137821 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 53336 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3624490 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 999 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.833069 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 53.389389 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 8255712 # number of writebacks -system.cpu0.dcache.writebacks::total 8255712 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3390240 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3655769 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 7046009 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5522660 # 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number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 635271 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 599436 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 1234707 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 125907 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 127277 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 253184 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 8 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 5 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4623824 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 4652528 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 9276352 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5266743 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 5322554 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 10589297 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 18054 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 15626 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.tags.tag_accesses 1359846782 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1359846782 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 81913095 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 81085676 # 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number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 254000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 433500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 341802090861 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 349957613760 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 691759704621 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 341802090861 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 349957613760 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 691759704621 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 88246426 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 87601496 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 175847922 # 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number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 328866363 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.071769 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.074380 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.073070 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.086327 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.089382 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.087842 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.759137 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.773175 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766396 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.789455 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.794768 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.791995 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.155801 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152536 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.154178 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000006 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000004 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.082014 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.084551 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.083275 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085470 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.088356 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.086905 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15615.992201 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15276.206525 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15443.686474 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34978.188466 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35746.359982 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 35365.835140 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 23298.359218 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 22166.262373 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 22755.166688 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13128.598069 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12633.602612 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12885.138295 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13807.692308 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 31750 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20642.857143 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25331.171985 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25455.878257 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25394.107145 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24183.132040 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 24224.977742 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 24204.283478 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 50179402 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 52249 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 3620965 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 1011 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.858019 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 51.680514 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 8246145 # number of writebacks +system.cpu0.dcache.writebacks::total 8246145 # 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number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 8 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 21 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4643921 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 4600061 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 9243982 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5275795 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 5282625 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 10558420 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17861 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 15819 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33680 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19503 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 14194 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18882 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 14815 # number of WriteReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33697 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 37557 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 29820 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 36743 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 30634 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67377 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44005676000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 46542154500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 90547830500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 40688703147 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 39847716140 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 80536419287 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 10144598500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12204187000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 22348785500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 14171149455 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 12627536592 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 26798686047 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1695865500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1763125500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3458991000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 102000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 209000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 311000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 98865528602 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 99017407232 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 197882935834 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 109010127102 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 111221594232 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 220231721334 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3418077000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2846181000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6264258000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3418077000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2846181000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6264258000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032800 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033421 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033112 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014834 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014724 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014779 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.753975 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.750041 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.751962 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.783661 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.791897 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787638 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059090 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059762 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059426 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028292 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028374 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028333 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032059 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.032284 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032172 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15292.051279 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15781.275844 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15539.665883 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36627.781061 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36097.509754 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36363.480884 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15778.968268 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18214.497646 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17021.874869 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 22307.250693 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 21065.696074 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 21704.490253 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13469.191546 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13852.663875 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13661.965211 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 12750 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 41800 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23923.076923 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21381.767256 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21282.495717 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21331.977898 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20697.825412 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20896.282918 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20797.577151 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189325.191093 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 182143.926789 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185993.408551 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 91010.384216 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95445.372233 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92973.240126 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 16455853 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.958473 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 172258590 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 16456365 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.467597 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 12245675500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 274.034812 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 237.923660 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.535224 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.464695 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 45537932500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 44832999500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 90370932000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 39266250291 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 40577595959 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 79843846250 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 10081360000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12415038000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 22496398000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 14258396422 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 12486057493 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 26744453915 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1802187500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1654747000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3456934500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 166500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 246000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 412500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99062579213 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 97896652952 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 196959232165 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 109143939213 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 110311690952 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 219455630165 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3399664500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2864633000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6264297500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3399664500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2864633000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6264297500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032988 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033136 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033062 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014452 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014883 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014666 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.748836 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.755500 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.752282 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.785076 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.790227 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787539 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060313 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058538 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059431 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000006 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028226 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028292 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028259 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031903 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.032310 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032106 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15642.828705 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15444.929059 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15544.020843 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36005.584554 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36722.005693 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36366.150070 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15954.699829 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18188.826249 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17114.841476 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 22200.522257 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 21080.559399 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 21663.198957 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13957.245861 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13356.151226 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13662.908670 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 12807.692308 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 30750 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19642.857143 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21331.667617 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21281.598864 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21306.752021 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20687.676305 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 103166162413 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 103212304918 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 206378467331 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 974276500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 641521000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1615797500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 974276500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 641521000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 1615797500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086009 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.087244 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.086630 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086009 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.087244 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.086630 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086009 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.087244 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.086630 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12522.710055 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12566.939486 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12545.099403 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12522.710055 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12566.939486 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12545.099403 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12522.710055 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12566.939486 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12545.099403 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086531 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.086905 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.086717 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086531 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.086905 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.086717 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086531 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.086905 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.086717 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12537.425603 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12550.894366 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12544.157875 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12537.425603 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12550.894366 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12544.157875 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12537.425603 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12550.894366 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12544.157875 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 78330.639974 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78234.268293 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 78292.349065 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 78330.639974 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78234.268293 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 78292.349065 # average overall mshr uncacheable latency -system.cpu1.branchPred.lookups 134713045 # Number of BP lookups -system.cpu1.branchPred.condPredicted 90294354 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5910949 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 91937142 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 61863845 # Number of BTB hits +system.cpu1.branchPred.lookups 133897441 # Number of BP lookups +system.cpu1.branchPred.condPredicted 89938186 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5869763 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 91159166 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 61608831 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 67.289284 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17423003 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 191945 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 5099062 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 2694305 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 2404757 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 414905 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 67.583803 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17197784 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 191914 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 5022071 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2642299 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 2379772 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 413417 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1408,89 +1418,93 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 940458 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 940458 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17835 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93375 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 588116 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 352342 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2605.512542 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 15403.554578 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 349554 99.21% 99.21% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1910 0.54% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 467 0.13% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 147 0.04% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 145 0.04% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 35 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 66 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::458752-524287 10 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::524288-589823 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 352342 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 440653 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 22932.098499 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 18696.328712 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 16830.741238 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 430922 97.79% 97.79% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 8564 1.94% 99.74% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 599 0.14% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 434 0.10% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 89 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 36 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 440653 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 323076797592 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.107209 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.744323 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-3 321987662592 99.66% 99.66% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-7 587014500 0.18% 99.84% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-11 213123500 0.07% 99.91% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-15 130553500 0.04% 99.95% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-19 52805000 0.02% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-23 28221000 0.01% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-27 26598000 0.01% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-31 43358000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::32-35 6987500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::36-39 426000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::40-43 21000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::44-47 16500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::48-51 10000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::52-55 500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 323076797592 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 93376 83.96% 83.96% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 17835 16.04% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 111211 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 940458 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 900943 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 900943 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17588 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 92135 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 552674 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 348269 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2521.581019 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 15048.371457 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 345488 99.20% 99.20% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1911 0.55% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 471 0.14% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 154 0.04% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 142 0.04% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 31 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 66 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 348269 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 416714 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 22183.198789 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17895.949159 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 17072.754814 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 407840 97.87% 97.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 7849 1.88% 99.75% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 499 0.12% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 336 0.08% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 108 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 63 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 13 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 416714 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 309953543704 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.014716 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.659727 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-3 308957195204 99.68% 99.68% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-7 543608000 0.18% 99.85% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-11 198540500 0.06% 99.92% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-15 120617500 0.04% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-19 43978000 0.01% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-23 24203000 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-27 22128500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-31 36223000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::32-35 6651000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::36-39 321500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::40-43 27000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::44-47 20000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::48-51 8000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::52-55 5500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::56-59 6000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::60-63 11000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 309953543704 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 92135 83.97% 83.97% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 17588 16.03% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 109723 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 900943 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 940458 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 111211 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 900943 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 109723 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 111211 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 1051669 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 109723 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 1010666 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 107105213 # DTB read hits -system.cpu1.dtb.read_misses 647862 # DTB read misses -system.cpu1.dtb.write_hits 82338491 # DTB write hits -system.cpu1.dtb.write_misses 292596 # DTB write misses -system.cpu1.dtb.flush_tlb 1087 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 106418453 # DTB read hits +system.cpu1.dtb.read_misses 624156 # DTB read misses +system.cpu1.dtb.write_hits 81533380 # DTB write hits +system.cpu1.dtb.write_misses 276787 # DTB write misses +system.cpu1.dtb.flush_tlb 1086 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 21707 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 22079 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 54922 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 184 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 9726 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 55782 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 176 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 9564 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 55049 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 107753075 # DTB read accesses -system.cpu1.dtb.write_accesses 82631087 # DTB write accesses +system.cpu1.dtb.perms_faults 55148 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 107042609 # DTB read accesses +system.cpu1.dtb.write_accesses 81810167 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 189443704 # DTB hits -system.cpu1.dtb.misses 940458 # DTB misses -system.cpu1.dtb.accesses 190384162 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 187951833 # DTB hits +system.cpu1.dtb.misses 900943 # DTB misses +system.cpu1.dtb.accesses 188852776 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1520,410 +1534,404 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 101953 # Table walker walks requested -system.cpu1.itb.walker.walksLong 101953 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3135 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 69070 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 14166 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 87787 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1451.501931 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 9077.444806 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 86783 98.86% 98.86% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 614 0.70% 99.56% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 230 0.26% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 110 0.13% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 22 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 102336 # Table walker walks requested +system.cpu1.itb.walker.walksLong 102336 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3041 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 69360 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 14089 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 88247 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1349.994901 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 8816.342326 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 87374 99.01% 99.01% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 501 0.57% 99.58% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 211 0.24% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 117 0.13% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 19 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::294912-327679 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 87787 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 86371 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 28729.370969 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 24395.132531 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18742.067885 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 47141 54.58% 54.58% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 37044 42.89% 97.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 924 1.07% 98.54% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 961 1.11% 99.65% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 89 0.10% 99.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 90 0.10% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 58 0.07% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 20 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 15 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 13 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 86371 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 610837012424 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.919047 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.273178 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 49510897620 8.11% 8.11% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 561270328804 91.89% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 50540500 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 4377500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 769000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 99000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 610837012424 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 69070 95.66% 95.66% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 3135 4.34% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 72205 # Table walker page sizes translated +system.cpu1.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 88247 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 86490 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 27376.708290 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 22843.157676 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18954.672615 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 84456 97.65% 97.65% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1746 2.02% 99.67% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 174 0.20% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 67 0.08% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 29 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 9 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 86490 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 610599891424 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.922621 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.267613 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 47307697252 7.75% 7.75% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 563239770172 92.24% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 45620000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 5915500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 874500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 14000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 610599891424 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 69360 95.80% 95.80% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 3041 4.20% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 72401 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 101953 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 101953 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 102336 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 102336 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 72205 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 72205 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 174158 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 95706620 # ITB inst hits -system.cpu1.itb.inst_misses 101953 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 72401 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 72401 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 174737 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 94847182 # ITB inst hits +system.cpu1.itb.inst_misses 102336 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1087 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1086 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 21707 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 22079 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 39902 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 41108 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 192638 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 191650 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 95808573 # ITB inst accesses -system.cpu1.itb.hits 95706620 # DTB hits -system.cpu1.itb.misses 101953 # DTB misses -system.cpu1.itb.accesses 95808573 # DTB accesses -system.cpu1.numPwrStateTransitions 16900 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 8450 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 3209165135.406272 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 63386513065.949989 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3583 42.40% 42.40% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 4849 57.38% 99.79% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 3 0.04% 99.82% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 10 0.12% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 94949518 # ITB inst accesses +system.cpu1.itb.hits 94847182 # DTB hits +system.cpu1.itb.misses 102336 # DTB misses +system.cpu1.itb.accesses 94949518 # DTB accesses +system.cpu1.numPwrStateTransitions 16690 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 8345 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 2811784025.136968 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 54125884171.976646 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3484 41.75% 41.75% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 4842 58.02% 99.77% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 4 0.05% 99.82% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 3 0.04% 99.89% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 8 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 1988782300428 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 8450 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 24199778551817 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 27117445394183 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 673200080 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 1988782282928 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 8345 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 27852879525232 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 23464337689768 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 669110072 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 250326293 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 598056519 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 134713045 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 81981153 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 383149579 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13468488 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 2515216 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 21179 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 3210 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 4838435 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 163101 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 2842 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 95493345 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 3679546 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 39276 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 647753829 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.079477 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.330780 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 247318637 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 594168769 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 133897441 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 81448914 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 382780415 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13369418 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 2469656 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 22020 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 2942 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 4831905 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 160199 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 2485 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 94635082 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 3655757 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 39111 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 644272699 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.077858 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.328781 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 500909169 77.33% 77.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 18369194 2.84% 80.17% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 18392289 2.84% 83.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 13444419 2.08% 85.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 28522776 4.40% 89.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 9079206 1.40% 90.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 9809102 1.51% 92.40% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 8415106 1.30% 93.70% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 40812568 6.30% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 498403789 77.36% 77.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 18180113 2.82% 80.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 18298329 2.84% 83.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 13344455 2.07% 85.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 28485052 4.42% 89.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 9005401 1.40% 90.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 9710824 1.51% 92.42% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 8365736 1.30% 93.72% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 40479000 6.28% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 647753829 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.200108 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.888379 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 203038997 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 318780583 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 106758002 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 13823689 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5350357 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 19769330 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1403755 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 652115787 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 4334955 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5350357 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 210763548 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 23644830 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 256196843 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 112721527 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 39074336 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 636556128 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 84527 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 2214646 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 1724456 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 19278197 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 3720 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 608321142 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 977030287 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 750414618 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 813643 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 510669806 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 97651331 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15437965 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13428690 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 76999253 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 102745060 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 86542127 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 13847171 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 14669306 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 603448531 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15520984 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 604287606 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 888730 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 83031386 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 52028805 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 367516 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 647753829 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.932897 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.658052 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 644272699 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.200113 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.887999 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 200592206 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 318637226 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 105865940 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 13861849 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5313208 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 19620033 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1391095 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 647812132 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 4304218 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5313208 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 208315491 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 23091878 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 256219950 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 111868936 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 39460643 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 632346200 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 89809 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 2171113 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 1552755 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 19722377 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 3888 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 605326116 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 973029596 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 745395954 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 835166 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 508286647 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 97039469 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15581908 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13599233 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 77351395 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 101957824 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 85683722 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 13730276 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 14508656 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 599162654 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15675959 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 600368831 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 870257 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 82392045 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 51705579 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 355230 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 644272699 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.931855 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.655757 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 411149730 63.47% 63.47% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 99844018 15.41% 78.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 43674585 6.74% 85.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 31388880 4.85% 90.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 23216755 3.58% 94.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 16246972 2.51% 96.57% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 11234988 1.73% 98.30% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 6567238 1.01% 99.32% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 4430663 0.68% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 408550840 63.41% 63.41% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 100016688 15.52% 78.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 43398898 6.74% 85.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 31119922 4.83% 90.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 23055723 3.58% 94.08% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 16110351 2.50% 96.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 11122843 1.73% 98.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 6496596 1.01% 99.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 4400838 0.68% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 647753829 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 644272699 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3092955 25.56% 25.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 25896 0.21% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 3078 0.03% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4978648 41.15% 66.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 3998858 33.05% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3033866 25.31% 25.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 23473 0.20% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 1799 0.02% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4963680 41.42% 66.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 3962195 33.06% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 54 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 409873437 67.83% 67.83% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1473632 0.24% 68.07% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 67911 0.01% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 190 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 16 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 1 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 71982 0.01% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 109389956 18.10% 86.20% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 83410380 13.80% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 57 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 407511218 67.88% 67.88% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1473925 0.25% 68.12% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 66979 0.01% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 186 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 16 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 1 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 9 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 14 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 58109 0.01% 68.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.14% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 108674321 18.10% 86.24% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 82583972 13.76% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 604287606 # Type of FU issued -system.cpu1.iq.rate 0.897634 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 12099435 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020023 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1868279780 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 702174546 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 581222842 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1037426 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 531508 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 461103 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 615834413 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 552574 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 4729905 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 600368831 # Type of FU issued +system.cpu1.iq.rate 0.897265 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 11985013 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.019963 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1856828451 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 697391618 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 577348747 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1037180 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 532278 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 459183 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 611800062 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 553725 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 4645881 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 17106229 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 20767 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 716806 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 8739633 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 16996855 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 20011 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 704534 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 8628630 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 3947805 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 8490514 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 3900409 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 8595303 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5350357 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 15089845 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 6765703 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 619117650 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 1756443 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 102745060 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 86542127 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 13138616 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 241917 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 6436383 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 716806 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 2534366 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2735696 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 5270062 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 597242145 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 107094882 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6118047 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 5313208 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14601213 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 6790244 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 614987274 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 1737370 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 101957824 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 85683722 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 13306309 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 234327 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 6472536 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 704534 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 2511910 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2724374 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 5236284 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 593397792 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 106407717 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6082445 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 148135 # number of nop insts executed -system.cpu1.iew.exec_refs 189434078 # number of memory reference insts executed -system.cpu1.iew.exec_branches 110489810 # Number of branches executed -system.cpu1.iew.exec_stores 82339196 # Number of stores executed -system.cpu1.iew.exec_rate 0.887169 # Inst execution rate -system.cpu1.iew.wb_sent 583107932 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 581683945 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 287154690 # num instructions producing a value -system.cpu1.iew.wb_consumers 498859903 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.864058 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.575622 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 83090114 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 15153468 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4526792 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 633652727 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.845792 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.838559 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 148661 # number of nop insts executed +system.cpu1.iew.exec_refs 187941905 # number of memory reference insts executed +system.cpu1.iew.exec_branches 109851293 # Number of branches executed +system.cpu1.iew.exec_stores 81534188 # Number of stores executed +system.cpu1.iew.exec_rate 0.886846 # Inst execution rate +system.cpu1.iew.wb_sent 579236319 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 577807930 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 285288573 # num instructions producing a value +system.cpu1.iew.wb_consumers 495728954 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.863547 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.575493 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 82442886 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 15320729 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4497993 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 630278595 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.844780 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.835584 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 436801872 68.93% 68.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 97306167 15.36% 84.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 33196725 5.24% 89.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 15570610 2.46% 91.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 11096620 1.75% 93.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 6694600 1.06% 94.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 6152090 0.97% 95.77% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3917687 0.62% 96.38% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 22916356 3.62% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 433887749 68.84% 68.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 97721864 15.50% 84.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 32952593 5.23% 89.57% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 15389192 2.44% 92.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 10994625 1.74% 93.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 6638239 1.05% 94.81% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 6092126 0.97% 95.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3888165 0.62% 96.40% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 22714042 3.60% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 633652727 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 456128288 # Number of instructions committed -system.cpu1.commit.committedOps 535938124 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 630278595 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 453286692 # Number of instructions committed +system.cpu1.commit.committedOps 532446568 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 163441324 # Number of memory references committed -system.cpu1.commit.loads 85638830 # Number of loads committed -system.cpu1.commit.membars 3762780 # Number of memory barriers committed -system.cpu1.commit.branches 101898340 # Number of branches committed -system.cpu1.commit.fp_insts 443284 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 491997101 # Number of committed integer instructions. -system.cpu1.commit.function_calls 13483818 # Number of function calls committed. +system.cpu1.commit.refs 162016061 # Number of memory references committed +system.cpu1.commit.loads 84960969 # Number of loads committed +system.cpu1.commit.membars 3734725 # Number of memory barriers committed +system.cpu1.commit.branches 101308962 # Number of branches committed +system.cpu1.commit.fp_insts 440790 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 488486887 # Number of committed integer instructions. +system.cpu1.commit.function_calls 13305521 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 371242424 69.27% 69.27% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1140857 0.21% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 50916 0.01% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 62561 0.01% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 85638830 15.98% 85.48% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 77802494 14.52% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 369191199 69.34% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1139544 0.21% 69.55% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 50295 0.01% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 49427 0.01% 69.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.57% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 84960969 15.96% 85.53% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 77055092 14.47% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 535938124 # Class of committed instruction -system.cpu1.commit.bw_lim_events 22916356 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1225792229 # The number of ROB reads -system.cpu1.rob.rob_writes 1252182686 # The number of ROB writes -system.cpu1.timesIdled 4237640 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 25446251 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 54234885938 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 456128288 # Number of Instructions Simulated -system.cpu1.committedOps 535938124 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.475901 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.475901 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.677552 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.677552 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 703163553 # number of integer regfile reads -system.cpu1.int_regfile_writes 415853151 # number of integer regfile writes -system.cpu1.fp_regfile_reads 819685 # number of floating regfile reads -system.cpu1.fp_regfile_writes 527216 # number of floating regfile writes -system.cpu1.cc_regfile_reads 127646217 # number of cc regfile reads -system.cpu1.cc_regfile_writes 128772606 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1207600226 # number of misc regfile reads -system.cpu1.misc_regfile_writes 15276931 # number of misc regfile writes -system.iobus.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40295 # Transaction distribution -system.iobus.trans_dist::ReadResp 40295 # Transaction distribution +system.cpu1.commit.op_class_0::total 532446568 # Class of committed instruction +system.cpu1.commit.bw_lim_events 22714042 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1218446611 # The number of ROB reads +system.cpu1.rob.rob_writes 1243796841 # The number of ROB writes +system.cpu1.timesIdled 4173884 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 24837373 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 46928670537 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 453286692 # Number of Instructions Simulated +system.cpu1.committedOps 532446568 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.476130 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.476130 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.677447 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.677447 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 698541221 # number of integer regfile reads +system.cpu1.int_regfile_writes 412892879 # number of integer regfile writes +system.cpu1.fp_regfile_reads 836436 # number of floating regfile reads +system.cpu1.fp_regfile_writes 478776 # number of floating regfile writes +system.cpu1.cc_regfile_reads 127759728 # number of cc regfile reads +system.cpu1.cc_regfile_writes 128888879 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1201368002 # number of misc regfile reads +system.cpu1.misc_regfile_writes 15442226 # number of misc regfile writes +system.iobus.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40306 # Transaction distribution +system.iobus.trans_dist::ReadResp 40306 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1940,11 +1948,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230948 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230948 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230970 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230970 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353732 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353754 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1959,18 +1967,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334224 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334312 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492144 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 47814500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 47813000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 345500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 348500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1982,79 +1990,79 @@ system.iobus.reqLayer14.occupancy 9500 # La system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25714000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25706500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 40142500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 568747115 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 568865504 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147708000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147730000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115455 # number of replacements -system.iocache.tags.tagsinuse 10.425592 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115466 # number of replacements +system.iocache.tags.tagsinuse 10.425537 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115471 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115482 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13089208185000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544364 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.881227 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221523 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.430077 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651599 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13089208816000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 5.904041 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 4.521495 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.369003 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.282593 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651596 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039623 # Number of tag accesses -system.iocache.tags.data_accesses 1039623 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039722 # Number of tag accesses +system.iocache.tags.data_accesses 1039722 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8810 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8847 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8821 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8858 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115474 # number of demand (read+write) misses -system.iocache.demand_misses::total 115514 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115485 # number of demand (read+write) misses +system.iocache.demand_misses::total 115525 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115474 # number of overall misses -system.iocache.overall_misses::total 115514 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5085500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1644992106 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1650077606 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115485 # number of overall misses +system.iocache.overall_misses::total 115525 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5166000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1639680634 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1644846634 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12805896509 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12805896509 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5436500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14450888615 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14456325115 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5436500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14450888615 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14456325115 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12789916870 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12789916870 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5517000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14429597504 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14435114504 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5517000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14429597504 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14435114504 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8810 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8847 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8821 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8858 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115474 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115514 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115485 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115525 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115474 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115514 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115485 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115525 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2068,53 +2076,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 186718.740749 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 186512.671640 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 139621.621622 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 185883.758531 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 185690.520885 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120058.281229 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120058.281229 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125144.089709 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125147.818576 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125144.089709 # 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Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4278.290194 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 23306.302204 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 255.590373 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 270.257283 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2928.362959 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 24620.242304 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.141058 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003571 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.004303 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.065282 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.355626 # 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Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5073 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54349 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.004791 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 452419027 # Number of tag accesses -system.l2c.tags.data_accesses 452419027 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.l2c.ReadReq_hits::cpu0.dtb.walker 530836 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 183475 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 545490 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 182908 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1442709 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 8255712 # 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number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 8280218 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4366494 # number of demand (read+write) hits -system.l2c.demand_hits::total 26474941 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 530836 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 183475 # number of overall hits -system.l2c.overall_hits::cpu0.inst 8081848 # number of overall hits -system.l2c.overall_hits::cpu0.data 4303672 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 545490 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 182908 # number of overall hits -system.l2c.overall_hits::cpu1.inst 8280218 # number of overall hits -system.l2c.overall_hits::cpu1.data 4366494 # number of overall hits -system.l2c.overall_hits::total 26474941 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 2747 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2312 # 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number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 7138997999 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.005139 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012326 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.005332 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.013295 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.007171 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2666808000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 7139023499 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.005377 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013564 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.005409 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.013117 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.007381 # mshr miss rate for ReadReq accesses system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.782486 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.784945 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.783715 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.153846 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.266360 # 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mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.012326 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005417 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.090839 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.005332 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.013295 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006009 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.095347 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.036211 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79480.672502 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 79973.799127 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 78926.984952 # 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average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 92209.119710 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 76247.904832 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 76104.413936 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 76171.553698 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80764.461337 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 82677.046081 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 81839.627062 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20804.352231 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20903.544980 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20848.855624 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79973.799127 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76247.904832 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 88468.255214 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78926.984952 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 80245.841785 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76104.413936 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 88572.896818 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 87260.977881 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 91994.532955 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92522.282420 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 92263.003062 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 76403.188850 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 76035.170180 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 76215.948734 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80613.042243 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 83179.567594 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 81929.786467 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20807.504530 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20901.302761 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20849.371468 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78403.491449 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80889.556983 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76403.188850 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 87968.507633 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78283.557273 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79847.693647 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76035.170180 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 89180.270785 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 87325.160425 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78403.491449 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80889.556983 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76403.188850 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 87968.507633 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78283.557273 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79847.693647 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76035.170180 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 89180.270785 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 87325.160425 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62829.433912 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176820.593774 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177835.619506 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 62734.268293 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169639.415077 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131429.691796 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168582.590556 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131430.161254 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62829.433912 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84999.307719 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 86446.996707 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62734.268293 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 88892.873910 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 81111.151497 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 3206101 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1605959 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3062 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 87053.861722 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 81111.441220 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3173701 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1572230 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3254 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 54318 # Transaction distribution -system.membus.trans_dist::ReadResp 484167 # Transaction distribution +system.membus.trans_dist::ReadResp 484946 # Transaction distribution system.membus.trans_dist::WriteReq 33697 # Transaction distribution system.membus.trans_dist::WriteResp 33697 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1312198 # Transaction distribution -system.membus.trans_dist::CleanEvict 224447 # Transaction distribution -system.membus.trans_dist::UpgradeReq 37872 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1311989 # Transaction distribution +system.membus.trans_dist::CleanEvict 225778 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4711 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 573072 # Transaction distribution -system.membus.trans_dist::ReadExResp 573072 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 429849 # Transaction distribution -system.membus.trans_dist::InvalidateReq 628542 # Transaction distribution +system.membus.trans_dist::ReadExReq 574465 # Transaction distribution +system.membus.trans_dist::ReadExResp 574465 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 430628 # Transaction distribution +system.membus.trans_dist::InvalidateReq 626011 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6864 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4014812 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4144458 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237587 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237587 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4382045 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3984552 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4114198 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237454 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237454 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4351652 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2212 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 142074284 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 142246058 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7247872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7247872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 149493930 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2896 # Total snoops (count) -system.membus.snoopTraffic 184832 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1757355 # Request fanout histogram -system.membus.snoop_fanout::mean 0.019576 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.138538 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 142199148 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 142370922 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7237952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7237952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 149608874 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3063 # Total snoops (count) +system.membus.snoopTraffic 195520 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1723835 # Request fanout histogram +system.membus.snoop_fanout::mean 0.019089 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.136837 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1722953 98.04% 98.04% # Request fanout histogram -system.membus.snoop_fanout::1 34402 1.96% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1690929 98.09% 98.09% # Request fanout histogram +system.membus.snoop_fanout::1 32906 1.91% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1757355 # Request fanout histogram -system.membus.reqLayer0.occupancy 114108500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1723835 # Request fanout histogram +system.membus.reqLayer0.occupancy 114103500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 51156 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5404000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5424500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8771663634 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8729629317 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5453450415 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5464439160 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44589202 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44651356 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -2777,89 +2782,89 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 55371072 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 28119352 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 4995 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 55313500 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 28081340 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 5055 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 1866 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 1866 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 2053309 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 25890690 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 2056199 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 25877432 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33697 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33697 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 9461280 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 16455852 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2755609 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 47371 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 13 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 47384 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2180359 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2180359 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 16456589 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 7382467 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1266004 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1234707 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 49409857 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32615082 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 883766 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2568418 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 85477123 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2107688320 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1140469546 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2969568 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8655976 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 3259783410 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2003011 # Total snoops (count) -system.toL2Bus.snoopTraffic 81599088 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 30844610 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.026862 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.161680 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 9451504 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 16451372 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2751395 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 31429 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 21 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 31450 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2177126 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2177126 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 16452157 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 7370941 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1264166 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1234557 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 49396440 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32537915 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 866839 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2547134 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 85348328 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2107113280 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1138900522 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2824688 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8472048 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 3257310538 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2046689 # Total snoops (count) +system.toL2Bus.snoopTraffic 81942376 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 30811624 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.026814 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.161540 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 30016066 97.31% 97.31% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 828544 2.69% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 29985433 97.32% 97.32% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 826191 2.68% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 30844610 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 53049239176 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 30811624 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 53009049492 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1413407 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1413410 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 24732629203 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 24725297607 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 15040354777 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 15008598618 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 512966184 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 514146176 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1489584962 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1491177210 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16437 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 16436 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt index 3836d4f0c..bda055a3e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt @@ -1,160 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.820975 # Number of seconds simulated -sim_ticks 51820974875500 # Number of ticks simulated -final_tick 51820974875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.820973 # Number of seconds simulated +sim_ticks 51820973246500 # Number of ticks simulated +final_tick 51820973246500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 496355 # Simulator instruction rate (inst/s) -host_op_rate 583273 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28752228320 # Simulator tick rate (ticks/s) -host_mem_usage 675168 # Number of bytes of host memory used -host_seconds 1802.33 # Real time elapsed on the host -sim_insts 894595581 # Number of instructions simulated -sim_ops 1051249500 # Number of ops (including micro ops) simulated +host_inst_rate 758799 # Simulator instruction rate (inst/s) +host_op_rate 891661 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43998522404 # Simulator tick rate (ticks/s) +host_mem_usage 681336 # Number of bytes of host memory used +host_seconds 1177.79 # Real time elapsed on the host +sim_insts 893704771 # Number of instructions simulated +sim_ops 1050188306 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 122624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 122112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2604528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 25895856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 149760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 136256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2570820 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 25432280 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 409472 # Number of bytes read from this memory -system.physmem.bytes_read::total 57443708 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2604528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2570820 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5175348 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 78747648 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 125632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 134272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2648688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 26060912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 150272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 137792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2660612 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 25358744 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 379264 # Number of bytes read from this memory +system.physmem.bytes_read::total 57656188 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2648688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2660612 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5309300 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 78776832 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 4 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 20576 # Number of bytes written to this memory -system.physmem.bytes_written::total 78768228 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1916 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1908 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 64977 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 404626 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2340 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2129 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56295 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 397389 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6398 # Number of read requests responded to by this memory -system.physmem.num_reads::total 937978 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1230432 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 78797412 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1963 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2098 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 65667 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 407205 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2348 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2153 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 57698 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 396240 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 5926 # Number of read requests responded to by this memory +system.physmem.num_reads::total 941298 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1230888 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 1 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2572 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1233005 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2356 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 50260 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 499718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2890 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2629 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 49610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 490772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7902 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1108503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 50260 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 49610 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 99870 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1519610 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1233461 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2424 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2591 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 51112 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 502903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2900 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2659 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 51342 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 489353 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1112603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 51112 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 51342 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 102455 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1520173 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1520007 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1519610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2366 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2356 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 50260 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 499718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2890 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2629 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 49610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 491169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7902 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2628510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 937978 # Number of read requests accepted -system.physmem.writeReqs 1233005 # Number of write requests accepted -system.physmem.readBursts 937978 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1233005 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 59999232 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 31360 # Total number of bytes read from write queue -system.physmem.bytesWritten 78767552 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 57443708 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 78768228 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 490 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2262 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1520570 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1520173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2591 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 51112 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 502903 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2900 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 51342 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 489750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2633173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 941298 # Number of read requests accepted +system.physmem.writeReqs 1233461 # Number of write requests accepted +system.physmem.readBursts 941298 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1233461 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 60206144 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 36928 # Total number of bytes read from write queue +system.physmem.bytesWritten 78797632 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 57656188 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 78797412 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 577 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 55925 # Per bank write bursts -system.physmem.perBankRdBursts::1 62794 # Per bank write bursts -system.physmem.perBankRdBursts::2 56907 # Per bank write bursts -system.physmem.perBankRdBursts::3 56516 # Per bank write bursts -system.physmem.perBankRdBursts::4 54249 # Per bank write bursts -system.physmem.perBankRdBursts::5 59650 # Per bank write bursts -system.physmem.perBankRdBursts::6 52080 # Per bank write bursts -system.physmem.perBankRdBursts::7 52710 # Per bank write bursts -system.physmem.perBankRdBursts::8 54230 # Per bank write bursts -system.physmem.perBankRdBursts::9 101225 # Per bank write bursts -system.physmem.perBankRdBursts::10 56377 # Per bank write bursts -system.physmem.perBankRdBursts::11 58912 # Per bank write bursts -system.physmem.perBankRdBursts::12 52835 # Per bank write bursts -system.physmem.perBankRdBursts::13 56393 # Per bank write bursts -system.physmem.perBankRdBursts::14 52915 # Per bank write bursts -system.physmem.perBankRdBursts::15 53770 # Per bank write bursts -system.physmem.perBankWrBursts::0 75516 # Per bank write bursts -system.physmem.perBankWrBursts::1 81375 # Per bank write bursts -system.physmem.perBankWrBursts::2 78514 # Per bank write bursts -system.physmem.perBankWrBursts::3 79379 # Per bank write bursts -system.physmem.perBankWrBursts::4 75747 # Per bank write bursts -system.physmem.perBankWrBursts::5 80437 # Per bank write bursts -system.physmem.perBankWrBursts::6 73343 # Per bank write bursts -system.physmem.perBankWrBursts::7 74340 # Per bank write bursts -system.physmem.perBankWrBursts::8 74711 # Per bank write bursts -system.physmem.perBankWrBursts::9 79754 # Per bank write bursts -system.physmem.perBankWrBursts::10 76052 # Per bank write bursts -system.physmem.perBankWrBursts::11 78875 # Per bank write bursts -system.physmem.perBankWrBursts::12 73771 # Per bank write bursts -system.physmem.perBankWrBursts::13 78567 # Per bank write bursts -system.physmem.perBankWrBursts::14 74862 # Per bank write bursts -system.physmem.perBankWrBursts::15 75500 # Per bank write bursts +system.physmem.perBankRdBursts::0 57499 # Per bank write bursts +system.physmem.perBankRdBursts::1 62142 # Per bank write bursts +system.physmem.perBankRdBursts::2 57490 # Per bank write bursts +system.physmem.perBankRdBursts::3 55825 # Per bank write bursts +system.physmem.perBankRdBursts::4 53833 # Per bank write bursts +system.physmem.perBankRdBursts::5 61722 # Per bank write bursts +system.physmem.perBankRdBursts::6 53577 # Per bank write bursts +system.physmem.perBankRdBursts::7 53386 # Per bank write bursts +system.physmem.perBankRdBursts::8 55741 # Per bank write bursts +system.physmem.perBankRdBursts::9 100411 # Per bank write bursts +system.physmem.perBankRdBursts::10 55379 # Per bank write bursts +system.physmem.perBankRdBursts::11 62273 # Per bank write bursts +system.physmem.perBankRdBursts::12 51298 # Per bank write bursts +system.physmem.perBankRdBursts::13 56710 # Per bank write bursts +system.physmem.perBankRdBursts::14 52113 # Per bank write bursts +system.physmem.perBankRdBursts::15 51322 # Per bank write bursts +system.physmem.perBankWrBursts::0 75972 # Per bank write bursts +system.physmem.perBankWrBursts::1 80204 # Per bank write bursts +system.physmem.perBankWrBursts::2 78083 # Per bank write bursts +system.physmem.perBankWrBursts::3 78701 # Per bank write bursts +system.physmem.perBankWrBursts::4 75891 # Per bank write bursts +system.physmem.perBankWrBursts::5 81886 # Per bank write bursts +system.physmem.perBankWrBursts::6 74948 # Per bank write bursts +system.physmem.perBankWrBursts::7 74400 # Per bank write bursts +system.physmem.perBankWrBursts::8 74844 # Per bank write bursts +system.physmem.perBankWrBursts::9 78454 # Per bank write bursts +system.physmem.perBankWrBursts::10 75419 # Per bank write bursts +system.physmem.perBankWrBursts::11 80852 # Per bank write bursts +system.physmem.perBankWrBursts::12 73391 # Per bank write bursts +system.physmem.perBankWrBursts::13 78907 # Per bank write bursts +system.physmem.perBankWrBursts::14 74453 # Per bank write bursts +system.physmem.perBankWrBursts::15 74808 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 33 # Number of times write queue was full causing retry -system.physmem.totGap 51820971954500 # Total gap between requests +system.physmem.numWrRetry 19 # Number of times write queue was full causing retry +system.physmem.totGap 51820970325500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 894862 # Read request sizes (log2) +system.physmem.readPktSize::6 898182 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1230432 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 903465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 28234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 470 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 661 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 317 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 178 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 117 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 92 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1230888 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 907166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 28188 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 382 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 299 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 464 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 583 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 288 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 345 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 154 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 65 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 45 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -166,149 +166,144 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 33891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 39270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 66568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 69647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 73027 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 569 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 375 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 127 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 564009 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 246.035904 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 148.070971 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 287.068931 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 250512 44.42% 44.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 146974 26.06% 70.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 49960 8.86% 79.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 27236 4.83% 84.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 18139 3.22% 87.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12170 2.16% 89.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8948 1.59% 91.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7660 1.36% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 42410 7.52% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 564009 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 65824 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.242267 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 106.817618 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 65819 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::42 341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 61 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 566411 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 245.410940 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 147.848960 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 286.502889 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 251457 44.39% 44.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 147984 26.13% 70.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 50578 8.93% 79.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27084 4.78% 84.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18527 3.27% 87.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12015 2.12% 89.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8676 1.53% 91.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7490 1.32% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 42600 7.52% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 566411 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 65859 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.283773 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 106.722670 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 65854 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::7168-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 65824 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 65824 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.697481 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.054439 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.954009 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 139 0.21% 0.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 76 0.12% 0.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 52 0.08% 0.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 125 0.19% 0.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 51932 78.90% 79.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 9755 14.82% 94.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 1068 1.62% 95.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 579 0.88% 96.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 868 1.32% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 349 0.53% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 83 0.13% 98.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 31 0.05% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 49 0.07% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 50 0.08% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 24 0.04% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 26 0.04% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 422 0.64% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 35 0.05% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 36 0.05% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 31 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 19 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 5 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 16 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 65859 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 65859 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.694681 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.068066 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.774692 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 123 0.19% 0.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 75 0.11% 0.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 55 0.08% 0.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 134 0.20% 0.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 51847 78.72% 79.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 9800 14.88% 94.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 1125 1.71% 95.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 552 0.84% 96.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 892 1.35% 98.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 360 0.55% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 86 0.13% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 48 0.07% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 56 0.09% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 44 0.07% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 24 0.04% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 39 0.06% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 432 0.66% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 30 0.05% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 32 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 26 0.04% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 20 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 4 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 6 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 7 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.00% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::124-127 3 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 12 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 6 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 17 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 65824 # Writes before turning the bus around for reads -system.physmem.totQLat 12248455604 # Total ticks spent queuing -system.physmem.totMemAccLat 29826355604 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4687440000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13065.19 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 65859 # Writes before turning the bus around for reads +system.physmem.totQLat 12279482516 # Total ticks spent queuing +system.physmem.totMemAccLat 29918001266 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4703605000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13053.27 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31815.19 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31803.27 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.52 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.11 # Average system read bandwidth in MiByte/s @@ -318,42 +313,42 @@ system.physmem.busUtil 0.02 # Da system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.53 # Average write queue length when enqueuing -system.physmem.readRowHits 705562 # Number of row buffer hits during reads -system.physmem.writeRowHits 898659 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.26 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.02 # Row buffer hit rate for writes -system.physmem.avgGap 23869819.32 # Average gap between requests -system.physmem.pageHitRate 73.99 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2151787680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1174090500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3516442800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4008858480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3384694126320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1301405336775 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29951001041250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34647951683805 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.608648 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49825590774964 # Time in different power states -system.physmem_0.memoryStateTime::REF 1730416220000 # Time in different power states +system.physmem.avgWrQLen 11.56 # Average write queue length when enqueuing +system.physmem.readRowHits 706352 # Number of row buffer hits during reads +system.physmem.writeRowHits 899170 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.09 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.03 # Row buffer hit rate for writes +system.physmem.avgGap 23828373.78 # Average gap between requests +system.physmem.pageHitRate 73.92 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2184439320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1191906375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3552658200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4018150800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3384693617760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1306740976245 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29946315984000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34648697732700 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.623145 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49817760765674 # Time in different power states +system.physmem_0.memoryStateTime::REF 1730415960000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 264967468786 # Time in different power states +system.physmem_0.memoryStateTime::ACT 272796109326 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2112120360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1152446625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3795924600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3966356160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3384694126320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1300719308715 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29951602820250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34648043103030 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.610412 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49826557272121 # Time in different power states -system.physmem_1.memoryStateTime::REF 1730416220000 # Time in different power states +system.physmem_1.actEnergy 2097627840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1144539000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3784926600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3960109440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3384693617760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1304293519080 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29948462876250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34648437215970 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.618118 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49821299610951 # Time in different power states +system.physmem_1.memoryStateTime::REF 1730415960000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 264000971629 # Time in different power states +system.physmem_1.memoryStateTime::ACT 269251106549 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -370,9 +365,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -380,7 +375,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -410,66 +405,66 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 134174 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 134174 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 20899 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 96911 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 13 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 134161 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 134161 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 134161 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 117823 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 25678.780883 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 22579.177668 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 13711.855097 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 116916 99.23% 99.23% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 782 0.66% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 48 0.04% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 40 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 26 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 7 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 117823 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 4912294556 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.048082 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -236192296 -4.81% -4.81% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 5148486852 104.81% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 4912294556 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 96912 82.26% 82.26% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 20899 17.74% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 117811 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 134174 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 131570 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 131570 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 20583 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 94968 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 7 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 131563 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 131563 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 131563 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 115558 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 24585.701552 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 21339.790503 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 14301.317993 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 114596 99.17% 99.17% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 825 0.71% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 55 0.05% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 40 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 25 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 115558 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 4911919556 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.054990 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -270104796 -5.50% -5.50% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 5182024352 105.50% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 4911919556 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 94969 82.19% 82.19% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 20583 17.81% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 115552 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 131570 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 134174 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 117811 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 131570 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 115552 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 117811 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 251985 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 115552 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 247122 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 83610055 # DTB read hits -system.cpu0.dtb.read_misses 101997 # DTB read misses -system.cpu0.dtb.write_hits 76232981 # DTB write hits -system.cpu0.dtb.write_misses 32177 # DTB write misses +system.cpu0.dtb.read_hits 83870325 # DTB read hits +system.cpu0.dtb.read_misses 100143 # DTB read misses +system.cpu0.dtb.write_hits 76256860 # DTB write hits +system.cpu0.dtb.write_misses 31427 # DTB write misses system.cpu0.dtb.flush_tlb 51828 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 22117 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 537 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 74001 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 21293 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 538 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 73309 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4744 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4917 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10268 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 83712052 # DTB read accesses -system.cpu0.dtb.write_accesses 76265158 # DTB write accesses +system.cpu0.dtb.perms_faults 9888 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 83970468 # DTB read accesses +system.cpu0.dtb.write_accesses 76288287 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 159843036 # DTB hits -system.cpu0.dtb.misses 134174 # DTB misses -system.cpu0.dtb.accesses 159977210 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 160127185 # DTB hits +system.cpu0.dtb.misses 131570 # DTB misses +system.cpu0.dtb.accesses 160258755 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -499,586 +494,580 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 79618 # Table walker walks requested -system.cpu0.itb.walker.walksLong 79618 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4423 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 69406 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 79618 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 79618 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 79618 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 73829 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 28640.046594 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 25708.417232 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 15347.109309 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 36310 49.18% 49.18% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 36530 49.48% 98.66% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 322 0.44% 99.10% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 541 0.73% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 9 0.01% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 50 0.07% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 12 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 20 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 14 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 73829 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 77633 # Table walker walks requested +system.cpu0.itb.walker.walksLong 77633 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4406 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 67615 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 77633 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 77633 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 77633 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 72021 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 27701.552325 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 24376.545883 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 16846.806682 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 70875 98.41% 98.41% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 990 1.37% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 61 0.08% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 51 0.07% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 30 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 72021 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples -294749296 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 -294749296 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total -294749296 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 69406 94.01% 94.01% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 4423 5.99% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 73829 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 67615 93.88% 93.88% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 4406 6.12% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 72021 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 79618 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 79618 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 77633 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 77633 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 73829 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 73829 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 153447 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 446783848 # ITB inst hits -system.cpu0.itb.inst_misses 79618 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72021 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72021 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 149654 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 447669719 # ITB inst hits +system.cpu0.itb.inst_misses 77633 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 51828 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 22117 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 537 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 55085 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 21293 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 538 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 53432 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 446863466 # ITB inst accesses -system.cpu0.itb.hits 446783848 # DTB hits -system.cpu0.itb.misses 79618 # DTB misses -system.cpu0.itb.accesses 446863466 # DTB accesses -system.cpu0.numPwrStateTransitions 16584 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 8292 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 5987638231.190425 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 124545672847.091751 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3540 42.69% 42.69% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 4687 56.52% 99.22% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.23% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 5 0.06% 99.29% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 45 0.54% 99.83% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 447747352 # ITB inst accesses +system.cpu0.itb.hits 447669719 # DTB hits +system.cpu0.itb.misses 77633 # DTB misses +system.cpu0.itb.accesses 447747352 # DTB accesses +system.cpu0.numPwrStateTransitions 16472 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 8236 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 5647358953.626396 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 114048668982.955048 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3496 42.45% 42.45% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 4676 56.78% 99.22% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.24% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 4 0.05% 99.28% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 45 0.55% 99.83% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::overflows 10 0.12% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 5700356716960 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 8292 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 2171478662469 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 49649496213031 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 51821531497 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 5700356989224 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 8236 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 5309324904433 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46511648342067 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 51821514544 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16350 # number of quiesce instructions executed -system.cpu0.committedInsts 446506838 # Number of instructions committed -system.cpu0.committedOps 524620955 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 481485743 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 439185 # Number of float alu accesses -system.cpu0.num_func_calls 26339620 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 68267650 # number of instructions that are conditional controls -system.cpu0.num_int_insts 481485743 # number of integer instructions -system.cpu0.num_fp_insts 439185 # number of float instructions -system.cpu0.num_int_register_reads 703915697 # number of times the integer registers were read -system.cpu0.num_int_register_writes 382127275 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 705229 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 378788 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 117675600 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 117367653 # number of times the CC registers were written -system.cpu0.num_mem_refs 159834987 # number of memory refs -system.cpu0.num_load_insts 83607531 # Number of load instructions -system.cpu0.num_store_insts 76227456 # Number of store instructions -system.cpu0.num_idle_cycles 50234015072.883141 # Number of idle cycles -system.cpu0.num_busy_cycles 1587516424.116865 # Number of busy cycles -system.cpu0.not_idle_fraction 0.030634 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.969366 # Percentage of idle cycles -system.cpu0.Branches 99742938 # Number of branches fetched +system.cpu0.kern.inst.quiesce 16340 # number of quiesce instructions executed +system.cpu0.committedInsts 447398457 # Number of instructions committed +system.cpu0.committedOps 525429864 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 482287917 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 434588 # Number of float alu accesses +system.cpu0.num_func_calls 26374142 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 68421724 # number of instructions that are conditional controls +system.cpu0.num_int_insts 482287917 # number of integer instructions +system.cpu0.num_fp_insts 434588 # number of float instructions +system.cpu0.num_int_register_reads 704372154 # number of times the integer registers were read +system.cpu0.num_int_register_writes 382730581 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 702801 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 363748 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 117948117 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 117634638 # number of times the CC registers were written +system.cpu0.num_mem_refs 160118732 # number of memory refs +system.cpu0.num_load_insts 83867967 # Number of load instructions +system.cpu0.num_store_insts 76250765 # Number of store instructions +system.cpu0.num_idle_cycles 50235171233.913414 # Number of idle cycles +system.cpu0.num_busy_cycles 1586343310.086583 # Number of busy cycles +system.cpu0.not_idle_fraction 0.030612 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.969388 # Percentage of idle cycles +system.cpu0.Branches 99895335 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 363863642 69.32% 69.32% # Class of executed instruction -system.cpu0.op_class::IntMult 1121256 0.21% 69.53% # Class of executed instruction -system.cpu0.op_class::IntDiv 48514 0.01% 69.54% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 55488 0.01% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::MemRead 83607531 15.93% 85.48% # Class of executed instruction -system.cpu0.op_class::MemWrite 76227456 14.52% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 364386062 69.31% 69.31% # Class of executed instruction +system.cpu0.op_class::IntMult 1119710 0.21% 69.52% # Class of executed instruction +system.cpu0.op_class::IntDiv 49931 0.01% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 52613 0.01% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::MemRead 83867967 15.95% 85.50% # Class of executed instruction +system.cpu0.op_class::MemWrite 76250765 14.50% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 524923888 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 10233133 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.965653 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 310246690 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10233645 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 30.316343 # Average number of references to valid blocks. +system.cpu0.op_class::total 525727049 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 10225430 # 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Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.487415 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.512518 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999933 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 415 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 404 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1292621561 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1292621561 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 78084246 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 78779688 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 156863934 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 72276585 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 72648252 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 144924837 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 197426 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 197729 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 395155 # 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number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 609834 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1232503 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 148976 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 158663 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 307639 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses +system.cpu0.dcache.tags.tag_accesses 1291585318 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1291585318 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 78353332 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 78391099 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 156744431 # 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number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3167232000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 83500 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 82000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 194000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 83824627500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 83511508500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 167336136000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94497005500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 93869843000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 188366848500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3111292000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3121623000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6232915000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3111292000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3121623000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6232915000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032408 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032912 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032661 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015201 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014759 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014980 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.770427 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.764355 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.767428 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.790800 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.781180 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.786011 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055880 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.062259 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059036 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 165500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 83875897000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 82658635000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 166534532000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94461351000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 93148138500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 187609489500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3103960000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3128821500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6232781500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3103960000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3128821500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6232781500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032531 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032873 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032702 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015030 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014688 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014859 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.769986 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.763295 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.766659 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.790927 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.781493 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.786254 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057635 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.061103 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059361 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028109 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028075 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028092 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032226 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.032032 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032129 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14891.233147 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14768.533951 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14829.122223 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29292.099692 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29445.127004 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29367.664885 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16037.209456 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16075.808226 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16056.197459 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 19577.024872 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 19449.279640 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 19513.817411 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13369.471753 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13390.566467 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13380.477640 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 56000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028117 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028003 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028060 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032175 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.031976 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032076 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14922.618038 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14809.895672 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14865.938017 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29284.847615 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28983.369456 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29135.678801 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16101.117067 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16273.216028 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16186.317369 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 19541.749222 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 19540.375112 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 19541.072748 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13413.052339 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13370.293370 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13391.138903 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 83500 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 82000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 64666.666667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19251.693732 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19067.777750 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19159.466454 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18825.533472 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18684.053461 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18754.762173 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186573.039098 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 183301.409278 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184920.043909 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 98250.292102 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 87320.568408 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92454.536015 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 13781825 # number of replacements +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 82750 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19217.148593 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18989.434569 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19103.445214 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18809.231206 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18639.088902 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18724.369023 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186648.226097 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 183239.912152 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184921.569500 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 96947.246775 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 88389.781909 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92453.927168 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 13794841 # number of replacements system.cpu0.icache.tags.tagsinuse 511.891071 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 881366045 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 13782337 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 63.948955 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 31614405500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 231.253269 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 280.637803 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.451667 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.548121 # Average percentage of cache occupancy +system.cpu0.icache.tags.total_refs 880461329 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 13795353 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 63.823037 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 31612122500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 239.271634 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 272.619438 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.467327 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.532460 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999787 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 217 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 908930729 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 908930729 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 439927744 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 441438301 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 881366045 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 439927744 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 441438301 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 881366045 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 439927744 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 441438301 # number of overall hits -system.cpu0.icache.overall_hits::total 881366045 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6856104 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 6926238 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 13782342 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6856104 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 6926238 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 13782342 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6856104 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 6926238 # number of overall misses -system.cpu0.icache.overall_misses::total 13782342 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 92096826500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 93000613500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 185097440000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 92096826500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 93000613500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 185097440000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 92096826500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 93000613500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 185097440000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 446783848 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 448364539 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 895148387 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 446783848 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 448364539 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 895148387 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 446783848 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 448364539 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 895148387 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015345 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015448 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.015397 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015345 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015448 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.015397 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015345 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015448 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.015397 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13432.822270 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13427.291049 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13430.042586 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13432.822270 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13427.291049 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13430.042586 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13432.822270 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13427.291049 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13430.042586 # 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number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 171611501500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 85104796500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 86506705000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 171611501500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 85104796500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 86506705000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 171611501500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1959551500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 1303928500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3263480000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1959551500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 1303928500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 3263480000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.015345 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015448 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.015397 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.015345 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015448 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.015397 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.015345 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015448 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.015397 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12432.822270 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12427.291049 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12430.042586 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12432.822270 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12427.291049 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12430.042586 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12432.822270 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12427.291049 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12430.042586 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.015283 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015571 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.015427 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.015283 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015571 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.015427 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.015283 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015571 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.015427 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12439.161022 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12440.429701 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12439.800511 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12439.161022 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12440.429701 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12439.800511 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12439.161022 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12440.429701 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12439.800511 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 75588.315846 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 75805.389222 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75674.898551 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75588.315846 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 75805.389222 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75674.898551 # average overall mshr uncacheable latency -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1108,70 +1097,76 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 131388 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 131388 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 20694 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94767 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 12 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 131376 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.304470 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 84.045560 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-2047 131374 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 132777 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 132777 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 20416 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 96210 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 132763 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.225967 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 59.372165 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-2047 132761 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 131376 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 115473 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 25989.651260 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 22881.227305 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 14446.882730 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 114392 99.06% 99.06% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 917 0.79% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 63 0.05% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 52 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 33 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 115473 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 5991401436 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 1.130704 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -783101296 -13.07% -13.07% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 6774502732 113.07% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 5991401436 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 94767 82.08% 82.08% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 20694 17.92% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 115461 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 131388 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::16384-18431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 132763 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 116640 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 24809.139232 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21505.913100 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 14394.407415 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 77454 66.40% 66.40% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 38152 32.71% 99.11% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 546 0.47% 99.58% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 345 0.30% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 7 0.01% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 46 0.04% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 7 0.01% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 32 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 26 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 11 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 116640 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -4577799504 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.827535 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.377784 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -789509296 17.25% 17.25% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 -3788290208 82.75% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -4577799504 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 96210 82.49% 82.49% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 20416 17.51% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 116626 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 132777 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 131388 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 115461 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 132777 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 116626 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 115461 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 246849 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 116626 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 249403 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 84308595 # DTB read hits -system.cpu1.dtb.read_misses 100203 # DTB read misses -system.cpu1.dtb.write_hits 76530288 # DTB write hits -system.cpu1.dtb.write_misses 31185 # DTB write misses +system.cpu1.dtb.read_hits 83913526 # DTB read hits +system.cpu1.dtb.read_misses 101272 # DTB read misses +system.cpu1.dtb.write_hits 76384029 # DTB write hits +system.cpu1.dtb.write_misses 31505 # DTB write misses system.cpu1.dtb.flush_tlb 51822 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 20910 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 530 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 73106 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 21568 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 527 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 72847 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4660 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4726 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 9685 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 84408798 # DTB read accesses -system.cpu1.dtb.write_accesses 76561473 # DTB write accesses +system.cpu1.dtb.perms_faults 10026 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 84014798 # DTB read accesses +system.cpu1.dtb.write_accesses 76415534 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 160838883 # DTB hits -system.cpu1.dtb.misses 131388 # DTB misses -system.cpu1.dtb.accesses 160970271 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 160297555 # DTB hits +system.cpu1.dtb.misses 132777 # DTB misses +system.cpu1.dtb.accesses 160430332 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1201,144 +1196,150 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 76510 # Table walker walks requested -system.cpu1.itb.walker.walksLong 76510 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4384 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 66713 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 76510 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 76510 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 76510 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 71097 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 29111.284583 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 26008.835767 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 16533.926039 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 69890 98.30% 98.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 1057 1.49% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 63 0.09% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 56 0.08% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 18 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 71097 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 78422 # Table walker walks requested +system.cpu1.itb.walker.walksLong 78422 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4294 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 68564 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 78422 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 78422 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 78422 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 72858 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 27889.977765 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 24544.855352 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 16997.530464 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 38730 53.16% 53.16% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 32903 45.16% 98.32% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 429 0.59% 98.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 642 0.88% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 9 0.01% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 58 0.08% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 14 0.02% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 33 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 12 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 3 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 3 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 72858 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples -850152296 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 -850152296 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total -850152296 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 66713 93.83% 93.83% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 4384 6.17% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 71097 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 68564 94.11% 94.11% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 4294 5.89% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 72858 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 76510 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 76510 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 78422 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 78422 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 71097 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 71097 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 147607 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 448364539 # ITB inst hits -system.cpu1.itb.inst_misses 76510 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 72858 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 72858 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 151280 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 446586968 # ITB inst hits +system.cpu1.itb.inst_misses 78422 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 51822 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 20910 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 530 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 52840 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 21568 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 527 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 53690 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 448441049 # ITB inst accesses -system.cpu1.itb.hits 448364539 # DTB hits -system.cpu1.itb.misses 76510 # DTB misses -system.cpu1.itb.accesses 448441049 # DTB accesses -system.cpu1.numPwrStateTransitions 16068 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 8034 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 6192978089.022779 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 118311828609.490631 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3509 43.68% 43.68% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 4459 55.50% 99.18% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 4 0.05% 99.23% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 45 0.56% 99.79% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.81% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 13 0.16% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 446665390 # ITB inst accesses +system.cpu1.itb.hits 446586968 # DTB hits +system.cpu1.itb.misses 78422 # DTB misses +system.cpu1.itb.accesses 446665390 # DTB accesses +system.cpu1.numPwrStateTransitions 16158 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 8079 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 6172474015.634856 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 126400173933.037643 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3542 43.84% 43.84% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 4472 55.35% 99.20% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 4 0.05% 99.24% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 45 0.56% 99.80% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.83% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 12 0.15% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 3977581604528 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 8034 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 2066588908291 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 49754385967209 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 51820418254 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 5966386038488 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 8079 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 1953555674186 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 49867417572314 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 51820431949 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 448088743 # Number of instructions committed -system.cpu1.committedOps 526628545 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 483582453 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 455004 # Number of float alu accesses -system.cpu1.num_func_calls 26546962 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 68480445 # number of instructions that are conditional controls -system.cpu1.num_int_insts 483582453 # number of integer instructions -system.cpu1.num_fp_insts 455004 # number of float instructions -system.cpu1.num_int_register_reads 705060671 # number of times the integer registers were read -system.cpu1.num_int_register_writes 383633333 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 735821 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 380160 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 117946404 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 117660346 # number of times the CC registers were written -system.cpu1.num_mem_refs 160831979 # number of memory refs -system.cpu1.num_load_insts 84305574 # Number of load instructions -system.cpu1.num_store_insts 76526405 # Number of store instructions -system.cpu1.num_idle_cycles 50231588268.978668 # Number of idle cycles -system.cpu1.num_busy_cycles 1588829985.021333 # Number of busy cycles -system.cpu1.not_idle_fraction 0.030660 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.969340 # Percentage of idle cycles -system.cpu1.Branches 100054364 # Number of branches fetched +system.cpu1.committedInsts 446306314 # Number of instructions committed +system.cpu1.committedOps 524758442 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 481884827 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 461371 # Number of float alu accesses +system.cpu1.num_func_calls 26537022 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 68126137 # number of instructions that are conditional controls +system.cpu1.num_int_insts 481884827 # number of integer instructions +system.cpu1.num_fp_insts 461371 # number of float instructions +system.cpu1.num_int_register_reads 702656955 # number of times the integer registers were read +system.cpu1.num_int_register_writes 382236658 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 740777 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 397264 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 117187848 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 116906080 # number of times the CC registers were written +system.cpu1.num_mem_refs 160291234 # number of memory refs +system.cpu1.num_load_insts 83910548 # Number of load instructions +system.cpu1.num_store_insts 76380686 # Number of store instructions +system.cpu1.num_idle_cycles 50237560488.814125 # Number of idle cycles +system.cpu1.num_busy_cycles 1582871460.185875 # Number of busy cycles +system.cpu1.not_idle_fraction 0.030545 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.969455 # Percentage of idle cycles +system.cpu1.Branches 99714086 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 364882138 69.25% 69.25% # Class of executed instruction -system.cpu1.op_class::IntMult 1103160 0.21% 69.46% # Class of executed instruction -system.cpu1.op_class::IntDiv 49288 0.01% 69.47% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 54935 0.01% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::MemRead 84305574 16.00% 85.48% # Class of executed instruction -system.cpu1.op_class::MemWrite 76526405 14.52% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 363557209 69.24% 69.24% # Class of executed instruction +system.cpu1.op_class::IntMult 1101804 0.21% 69.45% # Class of executed instruction +system.cpu1.op_class::IntDiv 48133 0.01% 69.46% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 57875 0.01% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::MemRead 83910548 15.98% 85.45% # Class of executed instruction +system.cpu1.op_class::MemWrite 76380686 14.55% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 526921542 # Class of executed instruction -system.iobus.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40309 # Transaction distribution -system.iobus.trans_dist::ReadResp 40309 # Transaction distribution +system.cpu1.op_class::total 525056297 # Class of executed instruction +system.iobus.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40314 # Transaction distribution +system.iobus.trans_dist::ReadResp 40314 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1355,11 +1356,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230976 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230976 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230986 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230986 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353760 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353770 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1374,16 +1375,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334336 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334336 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334376 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334376 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42146500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492296 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42149000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 323500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1401,75 +1402,75 @@ system.iobus.reqLayer16.occupancy 17000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25738000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25704500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38603500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38608500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 568948940 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 568719305 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147736000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147746000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115469 # number of replacements -system.iocache.tags.tagsinuse 10.457310 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115474 # number of replacements +system.iocache.tags.tagsinuse 10.457313 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115485 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115490 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13153887286000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.511180 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.946130 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219449 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.434133 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13153882422000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.510792 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.946521 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219424 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434158 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.653582 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039749 # Number of tag accesses -system.iocache.tags.data_accesses 1039749 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039794 # Number of tag accesses +system.iocache.tags.data_accesses 1039794 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8824 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8861 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8829 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8866 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115488 # number of demand (read+write) misses -system.iocache.demand_misses::total 115528 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115493 # number of demand (read+write) misses +system.iocache.demand_misses::total 115533 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115488 # number of overall misses -system.iocache.overall_misses::total 115528 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1592669163 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1597755163 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115493 # number of overall misses +system.iocache.overall_misses::total 115533 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5103000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1592841262 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1597944262 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12771081777 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12771081777 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14363750940 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14369187940 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14363750940 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14369187940 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12773360043 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12773360043 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5454000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14366201305 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14371655305 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5454000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14366201305 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14371655305 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8824 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8861 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8829 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8866 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115488 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115528 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115493 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115533 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115488 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115528 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115493 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115533 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1483,53 +1484,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 180492.878853 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 180313.188466 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137918.918919 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 180410.155397 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 180232.829010 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119731.884956 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 119731.884956 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124374.402016 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124378.401253 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124374.402016 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124378.401253 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 30368 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119753.244234 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 119753.244234 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 136350 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124390.234083 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124394.374811 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 136350 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124390.234083 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124394.374811 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 30355 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3349 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3247 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.067781 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.348630 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8824 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8861 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8829 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8866 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115488 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115528 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115493 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115533 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115488 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115528 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1151469163 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1154705163 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115493 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115533 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3253000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1151391262 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1154644262 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7431123166 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7431123166 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 8582592329 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8586029329 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 8582592329 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8586029329 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7433322678 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7433322678 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3454000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8584713940 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8588167940 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3454000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8584713940 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8588167940 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1543,591 +1544,594 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130492.878853 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 130313.188466 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87918.918919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130410.155397 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 130232.829010 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69668.521394 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69668.521394 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 74315.879823 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 74319.899323 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 74315.879823 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 74319.899323 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1307989 # number of replacements -system.l2c.tags.tagsinuse 65252.064264 # Cycle average of tags in use -system.l2c.tags.total_refs 44034643 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1371175 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 32.114532 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 6646395500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38392.380157 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 144.452542 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 212.975590 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3457.790228 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9508.612364 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 156.104056 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 224.227466 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2866.176081 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 10289.345780 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.585821 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002204 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003250 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.052762 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.145090 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002382 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003421 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.043734 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.157003 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995667 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 258 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62928 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 257 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 416 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2434 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5412 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54630 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003937 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.960205 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 395596143 # Number of tag accesses -system.l2c.tags.data_accesses 395596143 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.l2c.ReadReq_hits::cpu0.dtb.walker 248480 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 169318 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 245899 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 163828 # number of ReadReq hits -system.l2c.ReadReq_hits::total 827525 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 7895103 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 7895103 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 13780242 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 13780242 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 5072 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 4937 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 10009 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 827908 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 804935 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1632843 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 6817014 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 6887144 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 13704158 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 3253717 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 3311406 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 6565123 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 363022 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 359819 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 722841 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 248480 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 169318 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 6817014 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 4081625 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 245899 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 163828 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 6887144 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4116341 # number of demand (read+write) hits -system.l2c.demand_hits::total 22729649 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 248480 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 169318 # number of overall hits -system.l2c.overall_hits::cpu0.inst 6817014 # number of overall hits -system.l2c.overall_hits::cpu0.data 4081625 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 245899 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 163828 # number of overall hits -system.l2c.overall_hits::cpu1.inst 6887144 # number of overall hits -system.l2c.overall_hits::cpu1.data 4116341 # number of overall hits -system.l2c.overall_hits::total 22729649 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1916 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1908 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2340 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2129 # number of ReadReq misses -system.l2c.ReadReq_misses::total 8293 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 17934 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 17937 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 35871 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69689.142335 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69689.142335 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 86350 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 74331.032530 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 74335.193754 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 86350 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74331.032530 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74335.193754 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1313152 # number of replacements +system.l2c.tags.tagsinuse 65370.708254 # Cycle average of tags in use +system.l2c.tags.total_refs 46163144 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1376667 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 33.532542 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 6637701500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 10009.384485 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 223.831306 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 257.129416 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3503.499374 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 24340.454100 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 220.642740 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 259.400016 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2811.960142 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 23744.406675 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.152731 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003415 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003923 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.053459 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.371406 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003367 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003958 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.042907 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.362311 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.997478 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 266 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 63249 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 266 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 805 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5995 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56179 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.004059 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.965103 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 392950064 # Number of tag accesses +system.l2c.tags.data_accesses 392950064 # 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mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.242388 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.244614 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.243487 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.005701 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005644 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005673 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.041323 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.039844 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.040577 # mshr miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.416990 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.409972 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::total 0.413518 # mshr miss rate for InvalidateReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.007652 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011143 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005701 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.090294 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.009426 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.012829 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005644 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.088178 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.037667 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.007652 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011143 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005701 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.090294 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.009426 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.012829 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005644 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.088178 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.037667 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76887.787056 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78477.987421 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76587.179487 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76828.558008 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 77153.623538 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18916.583027 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18919.496014 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18918.039642 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 44500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.243909 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.240947 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.242443 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.005814 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005824 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005819 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.041701 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.040840 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.041269 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.415078 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.414965 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.415022 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.008517 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.013338 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005814 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.090665 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.009980 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.013460 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005824 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.088276 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.037904 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.008517 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.013338 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005814 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.090665 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.009980 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.013460 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005824 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.088276 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.037904 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 77271.268467 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78612.488084 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77433.134583 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77921.040409 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 77807.696800 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19077.824050 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19017.848037 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19047.527048 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 72000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 70500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 53166.666667 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 72001.797054 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71983.378667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 71992.661792 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72910.283960 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72683.762214 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72797.017293 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74403.995372 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74590.725350 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74496.407757 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 18670.722173 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18670.205788 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 18670.468860 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76887.787056 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78477.987421 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72910.283960 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72833.398851 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76587.179487 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76828.558008 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72683.762214 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72883.433794 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 72892.859506 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76887.787056 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78477.987421 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72910.283960 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72833.398851 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76587.179487 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76828.558008 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72683.762214 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72883.433794 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 72892.859506 # average overall mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71250 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 72113.209501 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71743.107550 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 71931.252668 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72597.259930 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72713.398523 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72655.847877 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74539.819731 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74507.090984 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74523.570805 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 18669.456913 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18671.128760 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 18670.279848 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77271.268467 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78612.488084 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72597.259930 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72959.051121 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77433.134583 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77921.040409 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72713.398523 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72718.716719 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 72871.496473 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77271.268467 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78612.488084 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72597.259930 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72959.051121 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77433.134583 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77921.040409 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72713.398523 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72718.716719 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 72871.496473 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63088.315846 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174050.071960 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174124.804570 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63305.389222 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170778.479154 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 111091.017948 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170717.481698 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 111090.901991 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63088.315846 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 91655.635204 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 90442.436830 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63305.389222 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81354.933005 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 77213.287378 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 2973114 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1487263 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3311 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 82349.313521 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 77212.900308 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 2952008 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1460758 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3777 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 76831 # Transaction distribution -system.membus.trans_dist::ReadResp 449832 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 76830 # Transaction distribution +system.membus.trans_dist::ReadResp 456752 # Transaction distribution system.membus.trans_dist::WriteReq 33710 # Transaction distribution system.membus.trans_dist::WriteResp 33710 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1230432 # Transaction distribution -system.membus.trans_dist::CleanEvict 191908 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36440 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1230888 # Transaction distribution +system.membus.trans_dist::CleanEvict 196616 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4451 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 524978 # Transaction distribution -system.membus.trans_dist::ReadExResp 524978 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 373001 # Transaction distribution -system.membus.trans_dist::InvalidateReq 616319 # Transaction distribution +system.membus.trans_dist::ReadExReq 521854 # Transaction distribution +system.membus.trans_dist::ReadExResp 521854 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 379922 # Transaction distribution +system.membus.trans_dist::InvalidateReq 618256 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3721926 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3851630 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237395 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237395 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4089025 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6940 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3704616 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3834318 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 236933 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 236933 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4071251 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 128978144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 129147994 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7233792 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7233792 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 136381786 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3125 # Total snoops (count) -system.membus.snoopTraffic 199488 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1661282 # Request fanout histogram -system.membus.snoop_fanout::mean 0.019128 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.136975 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 129250016 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 129419862 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7203584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7203584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 136623446 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3602 # Total snoops (count) +system.membus.snoopTraffic 230016 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1635025 # Request fanout histogram +system.membus.snoop_fanout::mean 0.019925 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.139743 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1629505 98.09% 98.09% # Request fanout histogram -system.membus.snoop_fanout::1 31777 1.91% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1602447 98.01% 98.01% # Request fanout histogram +system.membus.snoop_fanout::1 32578 1.99% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1661282 # Request fanout histogram -system.membus.reqLayer0.occupancy 106916500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1635025 # Request fanout histogram +system.membus.reqLayer0.occupancy 106891500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5690500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5673000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8079257005 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8054295189 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4924178426 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4944826036 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44658046 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44675477 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -2170,86 +2174,86 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 48659442 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 24643437 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1748 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2028 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2028 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 48651794 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 24630474 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1743 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2027 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 1290012 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 21916025 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51820973246500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 1286860 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 21921577 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 9018905 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 13781825 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2522217 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 45883 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 45886 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2158380 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2158380 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 13782342 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 6845459 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1260926 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1232503 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 41432759 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 30927957 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 796484 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1252515 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 74409715 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1764279188 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1081608326 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2697464 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3989080 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2852574058 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1717339 # Total snoops (count) -system.toL2Bus.snoopTraffic 74998872 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 26724704 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.021941 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.146492 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 9010476 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 13794841 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2528106 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 30086 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 30088 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2154783 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2154783 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 13795358 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 6841623 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1261461 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1232703 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 41471807 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 30873248 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 776442 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1216589 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 74338086 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1765945236 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1080533506 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2538024 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3725984 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2852742750 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1772959 # Total snoops (count) +system.toL2Bus.snoopTraffic 75424744 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 26717035 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021855 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.146208 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 26138332 97.81% 97.81% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 586372 2.19% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 26133147 97.81% 97.81% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 583888 2.19% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 26724704 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 46394070000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 26717035 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 46394041000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1633889 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1620386 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 20716638000 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 20736162000 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 14191518968 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 14171869470 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 459301000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 459189000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 753880000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 750841000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index ef2534218..2d36751f4 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.062409 # Number of seconds simulated -sim_ticks 62408957500 # Number of ticks simulated -final_tick 62408957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.062421 # Number of seconds simulated +sim_ticks 62420912500 # Number of ticks simulated +final_tick 62420912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 176281 # Simulator instruction rate (inst/s) -host_op_rate 177159 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 121425676 # Simulator tick rate (ticks/s) -host_mem_usage 399932 # Number of bytes of host memory used -host_seconds 513.97 # Real time elapsed on the host +host_inst_rate 255603 # Simulator instruction rate (inst/s) +host_op_rate 256876 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 176097831 # Simulator tick rate (ticks/s) +host_mem_usage 405340 # Number of bytes of host memory used +host_seconds 354.47 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 947264 # Number of bytes read from this memory system.physmem.bytes_read::total 996736 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 49472 # Nu system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14801 # Number of read requests responded to by this memory system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 792707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15178334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15971041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 792707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 792707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 792707 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15178334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15971041 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 792555 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15175427 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15967982 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 792555 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 792555 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 792555 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15175427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15967982 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15574 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 62408863500 # Total gap between requests +system.physmem.totGap 62420817500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 15459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 15458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 110 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1549 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 642.437702 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 437.017774 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 401.182344 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 251 16.20% 16.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 185 11.94% 28.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 90 5.81% 33.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 67 4.33% 38.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 77 4.97% 43.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 93 6.00% 49.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 42 2.71% 51.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 43 2.78% 54.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 701 45.26% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1549 # Bytes accessed per row activation -system.physmem.totQLat 75120250 # Total ticks spent queuing -system.physmem.totMemAccLat 367132750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 645.984416 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 440.038624 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 401.127365 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 251 16.30% 16.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 179 11.62% 27.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 84 5.45% 33.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 75 4.87% 38.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 76 4.94% 43.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 73 4.74% 47.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 57 3.70% 51.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 48 3.12% 54.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 697 45.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation +system.physmem.totQLat 72080000 # Total ticks spent queuing +system.physmem.totMemAccLat 364092500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4823.44 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4628.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23573.44 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23378.23 # Average memory access latency per DRAM burst system.physmem.avgRdBW 15.97 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.97 # Average system read bandwidth in MiByte/s @@ -217,48 +217,48 @@ system.physmem.busUtilRead 0.12 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14020 # Number of row buffer hits during reads +system.physmem.readRowHits 14024 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.02 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.05 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4007246.92 # Average gap between requests -system.physmem.pageHitRate 90.02 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6395760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3489750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 4008014.48 # Average gap between requests +system.physmem.pageHitRate 90.05 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6335280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3456750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 63648000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4076108400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2565881505 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 35193459000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41909107215 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.544396 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 58537353750 # Time in different power states -system.physmem_0.memoryStateTime::REF 2083900000 # Time in different power states +system.physmem_0.refreshEnergy 4076616960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2557911195 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 35205114000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41913082185 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.524455 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 58558754750 # Time in different power states +system.physmem_0.memoryStateTime::REF 2084160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1785901250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1773814250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5314680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2899875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 5292000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2887500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4076108400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2571480045 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 35188548000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41901860400 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.428274 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 58529558500 # Time in different power states -system.physmem_1.memoryStateTime::REF 2083900000 # Time in different power states +system.physmem_1.refreshEnergy 4076616960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2600892900 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 35167410750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41910562710 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.484088 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 58497118250 # Time in different power states +system.physmem_1.memoryStateTime::REF 2084160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1793609000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1836331750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 20808236 # Number of BP lookups -system.cpu.branchPred.condPredicted 17115622 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 20808241 # Number of BP lookups +system.cpu.branchPred.condPredicted 17115627 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8965652 # Number of BTB lookups -system.cpu.branchPred.BTBHits 8840815 # Number of BTB hits +system.cpu.branchPred.BTBLookups 8965661 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8840824 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.607608 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 98.607610 # BTB Hit Percentage system.cpu.branchPred.usedRAS 61995 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 26211 # Number of indirect predictor lookups. @@ -266,7 +266,7 @@ system.cpu.branchPred.indirectHits 24795 # Nu system.cpu.branchPred.indirectMisses 1416 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,16 +387,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 62408957500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 124817915 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 62420912500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 124841825 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602850 # Number of instructions committed system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2182474 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2182225 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.377638 # CPI: cycles per instruction -system.cpu.ipc 0.725880 # IPC: instructions per cycle +system.cpu.cpi 1.377902 # CPI: cycles per instruction +system.cpu.ipc 0.725741 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction @@ -432,60 +432,60 @@ system.cpu.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 91054081 # Class of committed instruction -system.cpu.tickCycles 110516717 # Number of cycles that the object actually ticked -system.cpu.idleCycles 14301198 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 110516273 # Number of cycles that the object actually ticked +system.cpu.idleCycles 14325552 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 946101 # number of replacements -system.cpu.dcache.tags.tagsinuse 3621.431844 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26274920 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3621.404220 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26274921 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 950197 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.652076 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20702462500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3621.431844 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.884139 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.884139 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 27.652077 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20706654500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3621.404220 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.884132 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.884132 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 242 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2203 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1651 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2205 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1649 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55461267 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55461267 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21605941 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21605941 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4660697 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4660697 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 55461265 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55461265 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 21605938 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21605938 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4660701 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4660701 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26266638 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26266638 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26267146 # number of overall hits -system.cpu.dcache.overall_hits::total 26267146 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 906327 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 906327 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 74284 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 74284 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 26266639 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26266639 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26267147 # number of overall hits +system.cpu.dcache.overall_hits::total 26267147 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 906329 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 906329 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 74280 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 74280 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 980611 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 980611 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 980615 # number of overall misses -system.cpu.dcache.overall_misses::total 980615 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11805097500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11805097500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2540928500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2540928500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14346026000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14346026000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14346026000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14346026000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22512268 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22512268 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 980609 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 980609 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 980613 # number of overall misses +system.cpu.dcache.overall_misses::total 980613 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11804222500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11804222500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2566012000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2566012000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14370234500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14370234500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14370234500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14370234500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22512267 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22512267 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) @@ -494,28 +494,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27247249 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27247249 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27247761 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27247761 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 27247248 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27247248 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27247760 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27247760 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040259 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.040259 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015688 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015688 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015687 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015687 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.035989 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.035989 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.035989 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.035989 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13025.207789 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13025.207789 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34205.596091 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34205.596091 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14629.680883 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14629.680883 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14629.621207 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14629.621207 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13024.213613 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13024.213613 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34545.126548 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34545.126548 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14654.397930 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14654.397930 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14654.338154 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14654.338154 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -524,14 +524,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 943282 # number of writebacks system.cpu.dcache.writebacks::total 943282 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2897 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2897 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27520 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 27520 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 30417 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 30417 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 30417 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 30417 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2899 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2899 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27516 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27516 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 30415 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 30415 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 30415 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 30415 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903430 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 903430 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses @@ -542,16 +542,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 950194 system.cpu.dcache.demand_mshr_misses::total 950194 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 950197 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950197 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10863020500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10863020500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1482579500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1482579500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12345600000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12345600000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12345756000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12345756000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10862380000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10862380000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1495373500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1495373500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 158000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 158000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12357753500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12357753500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12357911500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12357911500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040131 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040131 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses @@ -562,71 +562,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034873 system.cpu.dcache.demand_mshr_miss_rate::total 0.034873 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12024.197226 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12024.197226 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31703.436404 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31703.436404 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12992.715172 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12992.715172 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12992.838327 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12992.838327 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12023.488261 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12023.488261 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31977.022924 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31977.022924 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52666.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52666.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13005.505718 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13005.505718 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13005.630938 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13005.630938 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.tagsinuse 689.591924 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27835291 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 689.589449 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27835051 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34750.675406 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 34750.375780 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 689.591924 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.336715 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.336715 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 689.589449 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.336714 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.336714 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55672985 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55672985 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 27835291 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27835291 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27835291 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27835291 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27835291 # number of overall hits -system.cpu.icache.overall_hits::total 27835291 # number of overall hits +system.cpu.icache.tags.tag_accesses 55672505 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55672505 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 27835051 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27835051 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27835051 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27835051 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27835051 # number of overall hits +system.cpu.icache.overall_hits::total 27835051 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 801 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 801 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 801 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 801 # number of overall misses system.cpu.icache.overall_misses::total 801 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 60446000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 60446000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 60446000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 60446000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 60446000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 60446000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27836092 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27836092 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27836092 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27836092 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27836092 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27836092 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 60780500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 60780500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 60780500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 60780500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 60780500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 60780500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27835852 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27835852 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27835852 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27835852 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27835852 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27835852 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75463.171036 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75463.171036 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75463.171036 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75463.171036 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75463.171036 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75463.171036 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75880.774032 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75880.774032 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75880.774032 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75880.774032 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75880.774032 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75880.774032 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -641,48 +641,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 801 system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59645000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 59645000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59645000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 59645000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59645000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 59645000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59979500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 59979500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59979500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 59979500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59979500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 59979500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74463.171036 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74463.171036 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74463.171036 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74463.171036 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74463.171036 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74463.171036 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74880.774032 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74880.774032 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74880.774032 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74880.774032 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74880.774032 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74880.774032 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10294.680667 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1834001 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 117.889117 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 11312.672856 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1881373 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15574 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 120.802170 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9404.439964 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.596313 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 215.644390 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.287001 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.593915 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10638.078941 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020587 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.006581 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.314169 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::cpu.data 0.324648 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.345235 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15574 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15237953 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15237953 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15454 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475281 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 15191206 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15191206 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 943282 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 943282 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits @@ -711,18 +709,18 @@ system.cpu.l2cache.demand_misses::total 15581 # nu system.cpu.l2cache.overall_misses::cpu.inst 774 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14807 # number of overall misses system.cpu.l2cache.overall_misses::total 15581 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1068633000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1068633000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58136500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 58136500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22289000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 22289000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 58136500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1090922000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1149058500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 58136500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1090922000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1149058500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1081439500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1081439500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58471000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 58471000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21652500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 21652500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 58471000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1103092000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1161563000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 58471000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1103092000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1161563000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 943282 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 943282 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses) @@ -751,18 +749,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016384 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966292 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015583 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016384 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73475.866337 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73475.866337 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75111.757106 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75111.757106 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84749.049430 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84749.049430 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75111.757106 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73676.099142 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73747.416725 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75111.757106 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73676.099142 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73747.416725 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74356.401265 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74356.401265 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75543.927649 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75543.927649 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82328.897338 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82328.897338 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75543.927649 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74498.007699 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74549.964701 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75543.927649 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74498.007699 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74549.964701 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -791,18 +789,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15574 system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14801 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 923193000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 923193000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 50340000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 50340000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19328000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19328000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50340000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 942521000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 992861000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50340000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 942521000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 992861000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 935999500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 935999500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 50673500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 50673500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18685500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18685500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50673500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 954685000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1005358500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50673500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 954685000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1005358500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses @@ -815,25 +813,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63475.866337 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63475.866337 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65122.897801 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65122.897801 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75206.225681 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75206.225681 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65122.897801 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63679.548679 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63751.187877 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65122.897801 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63679.548679 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63751.187877 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64356.401265 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64356.401265 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65554.333765 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65554.333765 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72706.225681 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72706.225681 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65554.333765 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64501.385042 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64553.647104 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65554.333765 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64501.385042 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64553.647104 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1897104 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 946122 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 904234 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 943282 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution @@ -867,7 +865,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 1201999 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1425298494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 15574 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 62420912500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1030 # Transaction distribution system.membus.trans_dist::ReadExReq 14544 # Transaction distribution system.membus.trans_dist::ReadExResp 14544 # Transaction distribution @@ -888,9 +892,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15574 # Request fanout histogram -system.membus.reqLayer0.occupancy 21833000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 21795000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 82137750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 82138750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 0313fa682..a9bdce95d 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,117 +1,117 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058199 # Number of seconds simulated -sim_ticks 58199030500 # Number of ticks simulated -final_tick 58199030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058328 # Number of seconds simulated +sim_ticks 58328364500 # Number of ticks simulated +final_tick 58328364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122100 # Simulator instruction rate (inst/s) -host_op_rate 122709 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 78442850 # Simulator tick rate (ticks/s) -host_mem_usage 487108 # Number of bytes of host memory used -host_seconds 741.93 # Real time elapsed on the host +host_inst_rate 135523 # Simulator instruction rate (inst/s) +host_op_rate 136198 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 87259482 # Simulator tick rate (ticks/s) +host_mem_usage 492508 # Number of bytes of host memory used +host_seconds 668.45 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 44352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 87616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 925056 # Number of bytes read from this memory -system.physmem.bytes_read::total 1057024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 11200 # Number of bytes written to this memory -system.physmem.bytes_written::total 11200 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 693 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1369 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14454 # Number of read requests responded to by this memory -system.physmem.num_reads::total 16516 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 175 # Number of write requests responded to by this memory -system.physmem.num_writes::total 175 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 762075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1505455 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 15894698 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 18162227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 762075 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 762075 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 192443 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 192443 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 192443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 762075 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1505455 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 15894698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18354670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 16517 # Number of read requests accepted -system.physmem.writeReqs 175 # Number of write requests accepted -system.physmem.readBursts 16517 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 175 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1048320 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue -system.physmem.bytesWritten 9216 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1057088 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11200 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 218752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 921408 # Number of bytes read from this memory +system.physmem.bytes_read::total 1184896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5696 # Number of bytes written to this memory +system.physmem.bytes_written::total 5696 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3418 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14397 # Number of read requests responded to by this memory +system.physmem.num_reads::total 18514 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 89 # Number of write requests responded to by this memory +system.physmem.num_writes::total 89 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 766968 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3750354 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 15796911 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 20314233 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 766968 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 766968 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 97654 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 97654 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 97654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 766968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3750354 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 15796911 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 20411887 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 18515 # Number of read requests accepted +system.physmem.writeReqs 89 # Number of write requests accepted +system.physmem.readBursts 18515 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 89 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1179904 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5056 # Total number of bytes read from write queue +system.physmem.bytesWritten 4480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1184960 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5696 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 79 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1166 # Per bank write bursts -system.physmem.perBankRdBursts::1 920 # Per bank write bursts -system.physmem.perBankRdBursts::2 953 # Per bank write bursts +system.physmem.perBankRdBursts::0 3247 # Per bank write bursts +system.physmem.perBankRdBursts::1 921 # Per bank write bursts +system.physmem.perBankRdBursts::2 949 # Per bank write bursts system.physmem.perBankRdBursts::3 1031 # Per bank write bursts system.physmem.perBankRdBursts::4 1061 # Per bank write bursts -system.physmem.perBankRdBursts::5 1122 # Per bank write bursts -system.physmem.perBankRdBursts::6 1094 # Per bank write bursts -system.physmem.perBankRdBursts::7 1089 # Per bank write bursts -system.physmem.perBankRdBursts::8 1025 # Per bank write bursts +system.physmem.perBankRdBursts::5 1117 # Per bank write bursts +system.physmem.perBankRdBursts::6 1095 # Per bank write bursts +system.physmem.perBankRdBursts::7 1097 # Per bank write bursts +system.physmem.perBankRdBursts::8 1024 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts -system.physmem.perBankRdBursts::10 933 # Per bank write bursts -system.physmem.perBankRdBursts::11 900 # Per bank write bursts -system.physmem.perBankRdBursts::12 903 # Per bank write bursts -system.physmem.perBankRdBursts::13 900 # Per bank write bursts -system.physmem.perBankRdBursts::14 1411 # Per bank write bursts -system.physmem.perBankRdBursts::15 910 # Per bank write bursts -system.physmem.perBankWrBursts::0 2 # Per bank write bursts +system.physmem.perBankRdBursts::10 932 # Per bank write bursts +system.physmem.perBankRdBursts::11 899 # Per bank write bursts +system.physmem.perBankRdBursts::12 902 # Per bank write bursts +system.physmem.perBankRdBursts::13 896 # Per bank write bursts +system.physmem.perBankRdBursts::14 1399 # Per bank write bursts +system.physmem.perBankRdBursts::15 904 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 6 # Per bank write bursts +system.physmem.perBankWrBursts::2 2 # Per bank write bursts system.physmem.perBankWrBursts::3 1 # Per bank write bursts -system.physmem.perBankWrBursts::4 3 # Per bank write bursts -system.physmem.perBankWrBursts::5 16 # Per bank write bursts -system.physmem.perBankWrBursts::6 40 # Per bank write bursts -system.physmem.perBankWrBursts::7 7 # Per bank write bursts +system.physmem.perBankWrBursts::4 2 # Per bank write bursts +system.physmem.perBankWrBursts::5 9 # Per bank write bursts +system.physmem.perBankWrBursts::6 10 # Per bank write bursts +system.physmem.perBankWrBursts::7 8 # Per bank write bursts system.physmem.perBankWrBursts::8 2 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 2 # Per bank write bursts -system.physmem.perBankWrBursts::11 2 # Per bank write bursts +system.physmem.perBankWrBursts::10 3 # Per bank write bursts +system.physmem.perBankWrBursts::11 3 # Per bank write bursts system.physmem.perBankWrBursts::12 2 # Per bank write bursts -system.physmem.perBankWrBursts::13 17 # Per bank write bursts -system.physmem.perBankWrBursts::14 37 # Per bank write bursts -system.physmem.perBankWrBursts::15 7 # Per bank write bursts +system.physmem.perBankWrBursts::13 9 # Per bank write bursts +system.physmem.perBankWrBursts::14 13 # Per bank write bursts +system.physmem.perBankWrBursts::15 6 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58199022000 # Total gap between requests +system.physmem.totGap 58328356000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 16517 # Read request sizes (log2) +system.physmem.readPktSize::6 18515 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 175 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 11454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2521 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 462 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 316 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 292 # What read queue length does an incoming req see +system.physmem.writePktSize::6 89 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 13470 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2526 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 307 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 283 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 54 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -149,24 +149,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -198,98 +198,102 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1812 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 582.746137 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 353.648277 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 424.722034 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 448 24.72% 24.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 213 11.75% 36.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 96 5.30% 41.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 72 3.97% 45.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 56 3.09% 48.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 67 3.70% 52.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 61 3.37% 55.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 48 2.65% 58.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 751 41.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1812 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 8 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2016.250000 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 98.342741 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 5441.040729 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 7 87.50% 87.50% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-15871 1 12.50% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 8 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 8 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 8 100.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 8 # Writes before turning the bus around for reads -system.physmem.totQLat 175730624 # Total ticks spent queuing -system.physmem.totMemAccLat 482855624 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 81900000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10728.37 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 3107 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 380.704216 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 201.847183 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 402.867268 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1088 35.02% 35.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 865 27.84% 62.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 94 3.03% 65.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 72 2.32% 68.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 65 2.09% 70.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 68 2.19% 72.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 56 1.80% 74.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 51 1.64% 75.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 748 24.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 3107 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 4608 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 1496.681558 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 7484.705695 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 1 25.00% 25.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 1 25.00% 50.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 1 25.00% 75.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-15871 1 25.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.500000 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.477704 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 1 25.00% 25.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3 75.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4 # Writes before turning the bus around for reads +system.physmem.totQLat 204802662 # Total ticks spent queuing +system.physmem.totMemAccLat 550477662 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 92180000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11108.84 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29478.37 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 18.01 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 18.16 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.19 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29858.84 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 20.23 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.08 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 20.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.10 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.14 # Data bus utilization in percentage -system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.16 # Data bus utilization in percentage +system.physmem.busUtilRead 0.16 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.75 # Average write queue length when enqueuing -system.physmem.readRowHits 14651 # Number of row buffer hits during reads -system.physmem.writeRowHits 51 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.44 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 29.82 # Row buffer hit rate for writes -system.physmem.avgGap 3486641.62 # Average gap between requests -system.physmem.pageHitRate 88.83 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7658280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 4178625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 65512200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 486000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3800977440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2714701095 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32535498750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 39129012390 # Total energy per rank (pJ) -system.physmem_0.averagePower 672.381118 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 54114607553 # Time in different power states -system.physmem_0.memoryStateTime::REF 1943240000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.38 # Average write queue length when enqueuing +system.physmem.readRowHits 15382 # Number of row buffer hits during reads +system.physmem.writeRowHits 10 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 11.49 # Row buffer hit rate for writes +system.physmem.avgGap 3135258.87 # Average gap between requests +system.physmem.pageHitRate 83.10 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 17803800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 9714375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 81876600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 162000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3809622960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6575109030 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29228595750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 39722884515 # Total energy per rank (pJ) +system.physmem_0.averagePower 681.036990 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 48583441495 # Time in different power states +system.physmem_0.memoryStateTime::REF 1947660000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2137743447 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7795971005 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6017760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3283500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 61916400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 447120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3800977440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2480426820 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32741002500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 39094071540 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.780705 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 54458056984 # Time in different power states -system.physmem_1.memoryStateTime::REF 1943240000 # Time in different power states +system.physmem_1.actEnergy 5609520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3060750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 61760400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 187920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3809622960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2425538385 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32868570000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 39174349935 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.632528 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 54671634140 # Time in different power states +system.physmem_1.memoryStateTime::REF 1947660000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1793992016 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1708703360 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 28233538 # Number of BP lookups -system.cpu.branchPred.condPredicted 23266052 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 835390 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11829354 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11747655 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 28233990 # Number of BP lookups +system.cpu.branchPred.condPredicted 23266525 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 835401 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11829630 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11747896 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.309354 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 74541 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 92 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 27216 # Number of indirect predictor lookups. +system.cpu.branchPred.BTBHitPct 99.309074 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 74550 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 96 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 27225 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 25478 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1738 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 1747 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -319,7 +323,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -349,7 +353,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -379,7 +383,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -410,84 +414,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58199030500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 116398062 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 116656730 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 746143 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 134906479 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28233538 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11847674 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 114760827 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1674187 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 911 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 805 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32275055 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 562 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 116345779 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.164712 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.318875 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 746133 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134907690 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28233990 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11847924 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 115018036 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1674227 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 853 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 829 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32275439 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 555 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 116602964 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.162155 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.318550 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58810972 50.55% 50.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13933527 11.98% 62.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9228064 7.93% 70.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34373216 29.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 59067374 50.66% 50.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13933709 11.95% 62.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9228635 7.91% 70.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34373246 29.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 116345779 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.242560 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.159010 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8834252 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64111694 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33013656 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9560800 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 825377 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4097950 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11817 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114395383 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1985420 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 825377 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15270485 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 49952350 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 109536 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35410349 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14777682 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110872417 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1412237 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11132933 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1144918 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1526969 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 486977 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129945519 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483152587 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119447216 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 116602964 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.242026 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.156450 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8835100 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64368120 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33012562 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9561783 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 825399 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4097891 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11814 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 114395515 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1985251 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 825399 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15271601 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50089085 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 110009 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35409630 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14897240 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110872720 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1412183 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11133547 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1231881 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1645196 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 486344 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129945840 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483153679 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119447461 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 433 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22632600 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 22632921 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4409 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 4401 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21510749 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26805153 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5347343 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 519410 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 254099 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109667150 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 21513680 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26805319 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5347286 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 522469 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 256366 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109667529 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 8283 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101366848 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1074801 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18634403 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41667039 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 101366370 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1074686 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18634782 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41671490 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 65 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 116345779 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.871255 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.989200 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 116602964 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.869329 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.988911 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54714850 47.03% 47.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 31358235 26.95% 73.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22007860 18.92% 92.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7066756 6.07% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1197765 1.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54969091 47.14% 47.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31363076 26.90% 74.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22007447 18.87% 92.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7065313 6.06% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1197724 1.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -495,9 +499,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 116345779 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116602964 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9784213 48.67% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9783594 48.67% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 50 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.67% # attempts to use FU when none available @@ -526,13 +530,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.67% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9614548 47.83% 96.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 702998 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9615674 47.83% 96.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 702930 3.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71970791 71.00% 71.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10698 0.01% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71970691 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10697 0.01% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued @@ -556,86 +560,86 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 54 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 125 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24337715 24.01% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5047462 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24337594 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5047205 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101366848 # Type of FU issued -system.cpu.iq.rate 0.870864 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20101822 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.198308 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 340255638 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128310520 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99608490 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 101366370 # Type of FU issued +system.cpu.iq.rate 0.868929 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20102261 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.198313 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 340512191 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128311283 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99607990 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 624 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 115 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121468430 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 288068 # Number of loads that had data forwarded from stores +system.cpu.iq.fp_inst_queue_writes 628 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121468392 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 239 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 288047 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4329242 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1500 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1342 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 602499 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4329408 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1498 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1351 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 602442 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7579 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130663 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7583 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 130712 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 825377 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8119454 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 685980 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109688255 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 825399 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8206553 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 706266 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109688634 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26805153 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5347343 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 26805319 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5347286 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 4395 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 180270 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 342292 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1342 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 435059 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412404 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 847463 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100109842 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23803071 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1257006 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 180569 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 362078 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1351 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 435086 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412401 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 847487 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100109489 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23802993 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1256881 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 12822 # number of nop insts executed -system.cpu.iew.exec_refs 28718921 # number of memory reference insts executed -system.cpu.iew.exec_branches 20621209 # Number of branches executed -system.cpu.iew.exec_stores 4915850 # Number of stores executed -system.cpu.iew.exec_rate 0.860065 # Inst execution rate -system.cpu.iew.wb_sent 99693752 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99608605 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59691637 # num instructions producing a value -system.cpu.iew.wb_consumers 95527463 # num instructions consuming a value -system.cpu.iew.wb_rate 0.855758 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.624864 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 17362842 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 28718621 # number of memory reference insts executed +system.cpu.iew.exec_branches 20621294 # Number of branches executed +system.cpu.iew.exec_stores 4915628 # Number of stores executed +system.cpu.iew.exec_rate 0.858154 # Inst execution rate +system.cpu.iew.wb_sent 99693258 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99608103 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59691284 # num instructions producing a value +system.cpu.iew.wb_consumers 95529167 # num instructions consuming a value +system.cpu.iew.wb_rate 0.853856 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624849 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 17363279 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 823674 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 113658017 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.801119 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.737711 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 823687 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 113915056 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.799312 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.736114 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 77235221 67.95% 67.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18611593 16.38% 84.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7151823 6.29% 90.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3469408 3.05% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1644636 1.45% 95.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 541902 0.48% 95.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 703188 0.62% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 178974 0.16% 96.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4121272 3.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 77490817 68.03% 68.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18611366 16.34% 84.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7154135 6.28% 90.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3469454 3.05% 93.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1644903 1.44% 95.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 541342 0.48% 95.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 703110 0.62% 96.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 178773 0.16% 96.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4121156 3.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 113658017 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 113915056 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602408 # Number of instructions committed system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -681,80 +685,80 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction -system.cpu.commit.bw_lim_events 4121272 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 217947492 # The number of ROB reads -system.cpu.rob.rob_writes 219521309 # The number of ROB writes -system.cpu.timesIdled 570 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 52283 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 4121156 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 218205084 # The number of ROB reads +system.cpu.rob.rob_writes 219522331 # The number of ROB writes +system.cpu.timesIdled 576 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 53766 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589799 # Number of Instructions Simulated system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.284891 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.284891 # CPI: Total CPI of All Threads -system.cpu.ipc 0.778276 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.778276 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108097873 # number of integer regfile reads -system.cpu.int_regfile_writes 58692304 # number of integer regfile writes -system.cpu.fp_regfile_reads 59 # number of floating regfile reads -system.cpu.fp_regfile_writes 96 # number of floating regfile writes -system.cpu.cc_regfile_reads 369004699 # number of cc regfile reads -system.cpu.cc_regfile_writes 58686555 # number of cc regfile writes -system.cpu.misc_regfile_reads 28410105 # number of misc regfile reads +system.cpu.cpi 1.287747 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.287747 # CPI: Total CPI of All Threads +system.cpu.ipc 0.776550 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.776550 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108097252 # number of integer regfile reads +system.cpu.int_regfile_writes 58691902 # number of integer regfile writes +system.cpu.fp_regfile_reads 58 # number of floating regfile reads +system.cpu.fp_regfile_writes 93 # number of floating regfile writes +system.cpu.cc_regfile_reads 369002875 # number of cc regfile reads +system.cpu.cc_regfile_writes 58686679 # number of cc regfile writes +system.cpu.misc_regfile_reads 28409649 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 5470634 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.784091 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18249365 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5471146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.335565 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 35796500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.784091 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999578 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999578 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 5470636 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.779483 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18249262 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5471148 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.335545 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 36545500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.779483 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999569 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999569 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 344 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 335 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61906904 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61906904 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 13887331 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13887331 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4353747 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4353747 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61906894 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61906894 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 13887138 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13887138 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4353836 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4353836 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18241078 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18241078 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18241600 # number of overall hits -system.cpu.dcache.overall_hits::total 18241600 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9587264 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9587264 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 381234 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 381234 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 18240974 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18240974 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18241496 # number of overall hits +system.cpu.dcache.overall_hits::total 18241496 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9587451 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9587451 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 381145 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 381145 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9968498 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9968498 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9968505 # number of overall misses -system.cpu.dcache.overall_misses::total 9968505 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88773272500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88773272500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4000795875 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4000795875 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 291000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 291000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92774068375 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92774068375 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92774068375 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92774068375 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23474595 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23474595 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 9968596 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9968596 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9968603 # number of overall misses +system.cpu.dcache.overall_misses::total 9968603 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88929958000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88929958000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4000514273 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4000514273 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 284000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 284000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 92930472273 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92930472273 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92930472273 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92930472273 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23474589 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23474589 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) @@ -763,470 +767,474 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28209576 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28209576 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28210105 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28210105 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408410 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408410 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080514 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080514 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28209570 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28209570 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28210099 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28210099 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408418 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408418 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080496 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080496 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353373 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353373 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353366 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353366 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9259.500156 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9259.500156 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10494.331238 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10494.331238 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19400 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19400 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9306.724882 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9306.724882 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9306.718347 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9306.718347 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 329915 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 108865 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 121409 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.353376 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353376 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353370 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353370 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9275.662322 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9275.662322 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10496.042905 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10496.042905 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20285.714286 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20285.714286 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9322.323051 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9322.323051 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9322.316504 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9322.316504 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 330469 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 108734 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 121517 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.717385 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.479903 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 5470634 # number of writebacks -system.cpu.dcache.writebacks::total 5470634 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338603 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4338603 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158750 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158750 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4497353 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4497353 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4497353 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4497353 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248661 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5248661 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222484 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222484 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.719529 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8.469699 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 5470636 # number of writebacks +system.cpu.dcache.writebacks::total 5470636 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338792 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4338792 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158657 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158657 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 4497449 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4497449 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4497449 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4497449 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248659 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5248659 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222488 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 222488 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 5471145 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 5471145 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 5471149 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5471149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43288788000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43288788000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285573254 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285573254 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 214500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 214500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45574361254 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 45574361254 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45574575754 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45574575754 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 5471147 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5471147 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5471151 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5471151 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43429617000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43429617000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285050165 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285050165 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 217500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 217500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45714667165 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 45714667165 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45714884665 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 45714884665 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223589 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223589 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046987 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046987 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193946 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.193946 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193943 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.193943 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8247.586956 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8247.586956 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10272.978075 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10272.978075 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8329.949445 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8329.949445 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8329.982560 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8329.982560 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8274.421524 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8274.421524 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10270.442294 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10270.442294 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54375 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54375 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8355.591097 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8355.591097 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8355.624742 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8355.624742 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 447 # number of replacements -system.cpu.icache.tags.tagsinuse 427.448157 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32273898 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 427.481000 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32274286 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 904 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35701.214602 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 35701.643805 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 427.448157 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.834860 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.834860 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 427.481000 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.834924 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.834924 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 457 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64550990 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64550990 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 32273898 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32273898 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32273898 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32273898 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32273898 # number of overall hits -system.cpu.icache.overall_hits::total 32273898 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1145 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1145 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1145 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1145 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1145 # number of overall misses -system.cpu.icache.overall_misses::total 1145 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 60302481 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 60302481 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 60302481 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 60302481 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 60302481 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 60302481 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 32275043 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 32275043 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 32275043 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 32275043 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 32275043 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 32275043 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 64551760 # Number of tag accesses +system.cpu.icache.tags.data_accesses 64551760 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 32274286 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 32274286 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 32274286 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 32274286 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 32274286 # number of overall hits +system.cpu.icache.overall_hits::total 32274286 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1142 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1142 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1142 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1142 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1142 # number of overall misses +system.cpu.icache.overall_misses::total 1142 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 61976480 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 61976480 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 61976480 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 61976480 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 61976480 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 61976480 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 32275428 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 32275428 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 32275428 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 32275428 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 32275428 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 32275428 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000035 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000035 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000035 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000035 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000035 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000035 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52665.922271 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52665.922271 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52665.922271 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52665.922271 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52665.922271 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52665.922271 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 18953 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 107 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54270.122592 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54270.122592 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54270.122592 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54270.122592 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54270.122592 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54270.122592 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 19008 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 148 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 219 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 86.543379 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 21.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 86.794521 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 29.600000 # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 447 # number of writebacks system.cpu.icache.writebacks::total 447 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 240 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 240 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 240 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 240 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 240 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 240 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 237 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 237 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 237 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 237 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 237 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 237 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 905 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 905 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 905 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 905 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 905 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 905 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49734485 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 49734485 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49734485 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 49734485 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49734485 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 49734485 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50842984 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 50842984 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50842984 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 50842984 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50842984 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 50842984 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54955.232044 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54955.232044 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 4981065 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 5296247 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 274020 # number of redundant prefetches already in prefetch queue +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 56180.092818 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 56180.092818 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 56180.092818 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 56180.092818 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 56180.092818 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 56180.092818 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 4982437 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 5296601 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 273114 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 14074841 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 248 # number of replacements -system.cpu.l2cache.tags.tagsinuse 11235.818499 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5318374 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 14915 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 356.578880 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 14074231 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 123 # number of replacements +system.cpu.l2cache.tags.tagsinuse 11197.361342 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5291777 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 14677 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 360.548954 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 11061.516911 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 174.301588 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.675141 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.010639 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.685780 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 181 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 14486 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 168 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 469 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3489 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9544 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 100 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 884 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011047 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884155 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 180510207 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 180510207 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 5451171 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 5451171 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 17033 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 17033 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 226019 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 226019 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 210 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 210 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5243562 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 5243562 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 210 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 5469581 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 5469791 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 210 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 5469581 # number of overall hits -system.cpu.l2cache.overall_hits::total 5469791 # number of overall hits +system.cpu.l2cache.tags.occ_blocks::writebacks 11137.339599 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 60.021743 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.679769 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.003663 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.683433 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 61 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 14493 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 50 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 466 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3478 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9594 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 118 # 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number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 866631987 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 46500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 46500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32627500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32627500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44309000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44309000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 208942500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 208942500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44309000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 241570000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 285879000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44309000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 241570000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 866631987 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1152510987 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001510 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001510 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.766851 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000196 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000196 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000250 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000377 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000250 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001505 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001505 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.773481 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.773481 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000587 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000587 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.773481 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000625 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000753 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.773481 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000625 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.058141 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2697.430895 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13833.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13833.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95745.614035 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95745.614035 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62242.795389 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62242.795389 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61881.809339 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61881.809339 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67614.341085 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3118.582380 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 10943135 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471097 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.058605 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2737.542327 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2737.542327 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95681.818182 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95681.818182 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63298.571429 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63298.571429 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67882.553606 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67882.553606 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63298.571429 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70655.162328 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69404.952658 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63298.571429 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70655.162328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2737.542327 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3593.825187 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 10943139 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471099 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2877 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 303361 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302576 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.snoop_filter.tot_snoops 302176 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302175 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 5245531 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 5451346 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 19910 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1794 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 317966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 5457869 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13303 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 34 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 318447 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 226519 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 226519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 226521 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 226521 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 905 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244627 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2256 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16415192 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412942 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16415198 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 700360640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 319939 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 11456 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5791989 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.053010 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.224658 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 700360896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 318574 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5952 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5790626 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.052683 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.223400 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5485738 94.71% 94.71% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 305466 5.27% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 785 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5485560 94.73% 94.73% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 305065 5.27% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5791989 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10942648515 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5790626 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10942652515 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1357497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8206724991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 8206727492 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 16175 # Transaction distribution -system.membus.trans_dist::WritebackDirty 175 # Transaction distribution -system.membus.trans_dist::CleanEvict 63 # Transaction distribution +system.membus.snoop_filter.tot_requests 18642 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 3008 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 58328364500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 18174 # Transaction distribution +system.membus.trans_dist::WritebackDirty 89 # Transaction distribution +system.membus.trans_dist::CleanEvict 34 # Transaction distribution system.membus.trans_dist::UpgradeReq 4 # Transaction distribution -system.membus.trans_dist::ReadExReq 341 # Transaction distribution -system.membus.trans_dist::ReadExResp 341 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 16176 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 33275 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 33275 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1068224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1068224 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 340 # Transaction distribution +system.membus.trans_dist::ReadExResp 340 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 18175 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37156 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 37156 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1190592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1190592 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 16759 # Request fanout histogram +system.membus.snoop_fanout::samples 18519 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 16759 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 18519 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 16759 # Request fanout histogram -system.membus.reqLayer0.occupancy 27529285 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 86434816 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.snoop_fanout::total 18519 # Request fanout histogram +system.membus.reqLayer0.occupancy 29524488 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 97237655 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index b912f8d81..b27dfcb1b 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.361598 # Number of seconds simulated -sim_ticks 361597758500 # Number of ticks simulated -final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.361613 # Number of seconds simulated +sim_ticks 361613361500 # Number of ticks simulated +final_tick 361613361500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1165746 # Simulator instruction rate (inst/s) -host_op_rate 1165794 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1728825291 # Simulator tick rate (ticks/s) -host_mem_usage 381188 # Number of bytes of host memory used -host_seconds 209.16 # Real time elapsed on the host +host_inst_rate 1370596 # Simulator instruction rate (inst/s) +host_op_rate 1370653 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2032709522 # Simulator tick rate (ticks/s) +host_mem_usage 385816 # Number of bytes of host memory used +host_seconds 177.90 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory system.physmem.bytes_read::total 998592 # Number of bytes read from this memory @@ -22,19 +22,19 @@ system.physmem.bytes_inst_read::total 56256 # Nu system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 155576 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2606034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2761610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 155576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 155576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 155576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2606034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2761610 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 155569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2605921 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2761491 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 155569 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 155569 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 155569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2605921 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2761491 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 443 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 361597758500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 723195517 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 361613361500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 723226723 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 243825150 # Number of instructions committed @@ -53,7 +53,7 @@ system.cpu.num_mem_refs 105711441 # nu system.cpu.num_load_insts 82803521 # Number of load instructions system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 723195516.998000 # Number of busy cycles +system.cpu.num_busy_cycles 723226722.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 29302884 # Number of branches fetched @@ -92,25 +92,25 @@ system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 244431613 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 935475 # number of replacements -system.cpu.dcache.tags.tagsinuse 3562.412338 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3562.404243 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 134409733500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3562.412338 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.869730 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.869730 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 134415942500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3562.404243 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.869728 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.869728 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits @@ -131,16 +131,16 @@ system.cpu.dcache.demand_misses::cpu.data 939567 # n system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses system.cpu.dcache.overall_misses::total 939567 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614835000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11614835000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1320964000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1320964000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12935799000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12935799000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12935799000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12935799000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614992000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11614992000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1335530000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1335530000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 102000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 102000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12950522000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12950522000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12950522000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12950522000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) @@ -161,16 +161,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.617281 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.617281 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28280.111325 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28280.111325 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13767.830288 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13767.830288 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.793121 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.793121 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28591.950332 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28591.950332 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25500 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 25500 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13783.500272 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13783.500272 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13783.500272 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13783.500272 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -189,16 +189,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 939567 system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10721978000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10721978000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1274254000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1274254000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 97000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 97000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11996232000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11996232000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11996232000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11996232000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10722135000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10722135000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1288820000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1288820000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 98000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 98000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12010955000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12010955000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12010955000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12010955000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses @@ -209,26 +209,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.617281 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.617281 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27280.111325 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27280.111325 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24250 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24250 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.793121 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.793121 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27591.950332 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27591.950332 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24500 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24500 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12783.500272 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12783.500272 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12783.500272 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12783.500272 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 25 # number of replacements -system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 725.403723 # Cycle average of tags in use system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 725.404879 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.354202 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.354202 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 725.403723 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.354201 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.354201 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id @@ -237,7 +237,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 781 system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits @@ -250,12 +250,12 @@ system.cpu.icache.demand_misses::cpu.inst 882 # n system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses system.cpu.icache.overall_misses::total 882 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 54543500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 54543500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 54543500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 54543500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 54543500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 54543500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 55422500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 55422500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 55422500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 55422500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 55422500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 55422500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses @@ -268,12 +268,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61840.702948 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61840.702948 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61840.702948 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61840.702948 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62837.301587 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62837.301587 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62837.301587 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62837.301587 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62837.301587 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62837.301587 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -288,48 +288,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 882 system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53661500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 53661500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53661500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 53661500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53661500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 53661500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54540500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 54540500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54540500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 54540500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54540500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 54540500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60840.702948 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60840.702948 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61837.301587 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61837.301587 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61837.301587 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61837.301587 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61837.301587 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61837.301587 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 10855.563013 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1860349 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15603 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 119.230212 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8846.376929 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.627938 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 144.315582 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.269970 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.626846 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10116.936167 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.296915 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::cpu.data 0.308744 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.331285 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15603 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15465 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.476166 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 15023219 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15023219 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits @@ -358,18 +356,18 @@ system.cpu.l2cache.demand_misses::total 15603 # nu system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses system.cpu.l2cache.overall_misses::total 15603 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 866736500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 866736500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 52304000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 52304000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9341500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 9341500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 52304000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 876078000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 928382000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 52304000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 876078000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 928382000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 881303500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 881303500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 53183000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 53183000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9498500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 9498500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 53183000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 890802000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 943985000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 53183000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 890802000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 943985000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 935266 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 935266 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 25 # number of WritebackClean accesses(hits+misses) @@ -398,18 +396,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016591 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.981797 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.981797 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59500.224316 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59500.224316 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.981797 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.981797 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.981797 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60500.224316 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.981797 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60500.224316 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -428,18 +426,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15603 system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 721066500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 721066500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43514000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43514000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7771500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7771500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43514000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 728838000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 772352000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43514000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 728838000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 772352000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 735633500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 735633500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44393000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44393000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7928500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7928500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44393000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 743562000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 787955000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44393000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 743562000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 787955000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses @@ -452,25 +450,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.981797 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.981797 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.981797 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.981797 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.981797 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.224316 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.981797 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.224316 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution @@ -504,7 +502,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 1323000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 15603 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1036 # Transaction distribution system.membus.trans_dist::ReadExReq 14567 # Transaction distribution system.membus.trans_dist::ReadExResp 14567 # Transaction distribution diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 4b965d579..1e87ba0e2 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,78 +1,78 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.065987 # Number of seconds simulated -sim_ticks 65986743500 # Number of ticks simulated -final_tick 65986743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.065554 # Number of seconds simulated +sim_ticks 65553895500 # Number of ticks simulated +final_tick 65553895500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 86207 # Simulator instruction rate (inst/s) -host_op_rate 151797 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36005878 # Simulator tick rate (ticks/s) -host_mem_usage 411344 # Number of bytes of host memory used -host_seconds 1832.67 # Real time elapsed on the host +host_inst_rate 122580 # Simulator instruction rate (inst/s) +host_op_rate 215844 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50862026 # Simulator tick rate (ticks/s) +host_mem_usage 417260 # Number of bytes of host memory used +host_seconds 1288.86 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 69440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1890368 # Number of bytes read from this memory -system.physmem.bytes_read::total 1959808 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 69440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 69440 # Number of instructions bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 69632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1890944 # Number of bytes read from this memory +system.physmem.bytes_read::total 1960576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 69632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 69632 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 17920 # Number of bytes written to this memory system.physmem.bytes_written::total 17920 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1085 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29537 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30622 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1088 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29546 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30634 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 280 # Number of write requests responded to by this memory system.physmem.num_writes::total 280 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1052333 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28647693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29700026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1052333 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1052333 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 271570 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 271570 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 271570 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1052333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28647693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29971596 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30622 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 1062210 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28845639 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29907849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1062210 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1062210 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 273363 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 273363 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 273363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1062210 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28845639 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 30181212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30634 # Number of read requests accepted system.physmem.writeReqs 280 # Number of write requests accepted -system.physmem.readBursts 30622 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 30634 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 280 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1952768 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7040 # Total number of bytes read from write queue -system.physmem.bytesWritten 16064 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1959808 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 1951616 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8960 # Total number of bytes read from write queue +system.physmem.bytesWritten 16000 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1960576 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 17920 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 110 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 140 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1932 # Per bank write bursts -system.physmem.perBankRdBursts::1 2084 # Per bank write bursts -system.physmem.perBankRdBursts::2 2041 # Per bank write bursts -system.physmem.perBankRdBursts::3 1935 # Per bank write bursts -system.physmem.perBankRdBursts::4 2086 # Per bank write bursts -system.physmem.perBankRdBursts::5 1909 # Per bank write bursts -system.physmem.perBankRdBursts::6 1974 # Per bank write bursts -system.physmem.perBankRdBursts::7 1865 # Per bank write bursts -system.physmem.perBankRdBursts::8 1948 # Per bank write bursts +system.physmem.perBankRdBursts::0 1938 # Per bank write bursts +system.physmem.perBankRdBursts::1 2083 # Per bank write bursts +system.physmem.perBankRdBursts::2 2040 # Per bank write bursts +system.physmem.perBankRdBursts::3 1941 # Per bank write bursts +system.physmem.perBankRdBursts::4 2041 # Per bank write bursts +system.physmem.perBankRdBursts::5 1918 # Per bank write bursts +system.physmem.perBankRdBursts::6 1976 # Per bank write bursts +system.physmem.perBankRdBursts::7 1870 # Per bank write bursts +system.physmem.perBankRdBursts::8 1951 # Per bank write bursts system.physmem.perBankRdBursts::9 1940 # Per bank write bursts -system.physmem.perBankRdBursts::10 1806 # Per bank write bursts +system.physmem.perBankRdBursts::10 1805 # Per bank write bursts system.physmem.perBankRdBursts::11 1794 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts system.physmem.perBankRdBursts::13 1799 # Per bank write bursts -system.physmem.perBankRdBursts::14 1828 # Per bank write bursts +system.physmem.perBankRdBursts::14 1827 # Per bank write bursts system.physmem.perBankRdBursts::15 1779 # Per bank write bursts system.physmem.perBankWrBursts::0 10 # Per bank write bursts system.physmem.perBankWrBursts::1 107 # Per bank write bursts -system.physmem.perBankWrBursts::2 30 # Per bank write bursts -system.physmem.perBankWrBursts::3 12 # Per bank write bursts -system.physmem.perBankWrBursts::4 60 # Per bank write bursts -system.physmem.perBankWrBursts::5 8 # Per bank write bursts +system.physmem.perBankWrBursts::2 31 # Per bank write bursts +system.physmem.perBankWrBursts::3 25 # Per bank write bursts +system.physmem.perBankWrBursts::4 39 # Per bank write bursts +system.physmem.perBankWrBursts::5 13 # Per bank write bursts system.physmem.perBankWrBursts::6 16 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 1 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts system.physmem.perBankWrBursts::9 5 # Per bank write bursts system.physmem.perBankWrBursts::10 3 # Per bank write bursts @@ -83,14 +83,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 65986546500 # Total gap between requests +system.physmem.totGap 65553697500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 30622 # Read request sizes (log2) +system.physmem.readPktSize::6 30634 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,11 +98,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 280 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29999 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 29978 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 404 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -147,18 +147,18 @@ system.physmem.wrQLenPdf::13 1 # Wh system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see @@ -194,336 +194,335 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2831 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 694.731190 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 483.360902 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 396.952113 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 443 15.65% 15.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 258 9.11% 24.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 108 3.81% 28.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 115 4.06% 32.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 113 3.99% 36.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 115 4.06% 40.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 137 4.84% 45.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 80 2.83% 48.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1462 51.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2831 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 2859 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 687.860091 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 477.665686 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 399.129385 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 441 15.42% 15.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 263 9.20% 24.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 134 4.69% 29.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 136 4.76% 34.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 118 4.13% 38.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 116 4.06% 42.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 85 2.97% 45.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 96 3.36% 48.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1470 51.42% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2859 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 14 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2175.285714 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 28.380874 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 8064.070078 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2173.928571 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 21.222071 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 8074.812153 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 13 92.86% 92.86% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::29696-30719 1 7.14% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 14 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 14 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.928571 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.918266 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.615728 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.857143 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.849200 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.534522 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16 1 7.14% 7.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 12 85.71% 92.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 7.14% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 13 92.86% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 14 # Writes before turning the bus around for reads -system.physmem.totQLat 136557750 # Total ticks spent queuing -system.physmem.totMemAccLat 708657750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 152560000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4475.54 # Average queueing delay per DRAM burst +system.physmem.totQLat 136299000 # Total ticks spent queuing +system.physmem.totMemAccLat 708061500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 152470000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4469.70 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23225.54 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 29.59 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23219.70 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 29.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 29.70 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 29.91 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.27 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.53 # Average write queue length when enqueuing -system.physmem.readRowHits 27745 # Number of row buffer hits during reads -system.physmem.writeRowHits 178 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.93 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 63.57 # Row buffer hit rate for writes -system.physmem.avgGap 2135348.73 # Average gap between requests -system.physmem.pageHitRate 90.68 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 11551680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 6303000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 123130800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1574640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4309537440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3035388510 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 36925944000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 44413430070 # Total energy per rank (pJ) -system.physmem_0.averagePower 673.125124 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 61414409250 # Time in different power states -system.physmem_0.memoryStateTime::REF 2203240000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.62 # Average write queue length when enqueuing +system.physmem.readRowHits 27721 # Number of row buffer hits during reads +system.physmem.writeRowHits 161 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.91 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.50 # Row buffer hit rate for writes +system.physmem.avgGap 2120518.13 # Average gap between requests +system.physmem.pageHitRate 90.60 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 11740680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 6406125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 123169800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1568160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4281566640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3052855305 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 36653676000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 44130982710 # Total energy per rank (pJ) +system.physmem_0.averagePower 673.213820 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 60959756000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2188940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2364289750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2404016500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 9805320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 5350125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 114441600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 9873360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 5387250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 114558600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4309537440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3171429270 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 36806601750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 44417217345 # Total energy per rank (pJ) -system.physmem_1.averagePower 673.182663 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 61216839000 # Time in different power states -system.physmem_1.memoryStateTime::REF 2203240000 # Time in different power states +system.physmem_1.refreshEnergy 4281566640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3230070300 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 36498224250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 44139732240 # Total energy per rank (pJ) +system.physmem_1.averagePower 673.347293 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 60700713000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2188940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2563655500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2663059500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 40828848 # Number of BP lookups -system.cpu.branchPred.condPredicted 40828848 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1470674 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26813424 # Number of BTB lookups +system.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 40360668 # Number of BP lookups +system.cpu.branchPred.condPredicted 40360668 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1392637 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26664097 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6079027 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 92484 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 26813424 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 21202389 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5611035 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 566146 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 5988252 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 86625 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 26664097 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 21157452 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5506645 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 511906 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 65986743500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 131973488 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 131107792 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30825655 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 222121094 # Number of instructions fetch has processed -system.cpu.fetch.Branches 40828848 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 27281416 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 99433771 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3060135 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 329 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 6280 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 112427 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 56 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 115 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 29997924 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 374431 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 8 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 131908700 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.964131 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.412100 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30523578 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 219647427 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40360668 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 27145704 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 98945290 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2900833 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 518 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 6239 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 114030 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 50 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 29742559 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 352958 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 20 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 131040277 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.949675 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.407509 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 65727022 49.83% 49.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4068693 3.08% 52.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3626407 2.75% 55.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6133247 4.65% 60.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7782444 5.90% 66.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5574161 4.23% 70.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3387073 2.57% 73.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2926863 2.22% 75.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 32682790 24.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 65532629 50.01% 50.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4015050 3.06% 53.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3611452 2.76% 55.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6110552 4.66% 60.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7743592 5.91% 66.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5553299 4.24% 70.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3377797 2.58% 73.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2818268 2.15% 75.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 32277638 24.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 131908700 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.309372 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.683074 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15512553 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64273138 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 40712149 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9880793 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1530067 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 365468602 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1530067 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 21068463 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11448631 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17559 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 44736331 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53107649 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 355543189 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 24245 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 799476 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 46595900 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4792588 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 358065930 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 942303414 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 580264608 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 22491 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 131040277 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.307843 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.675319 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15257836 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64260169 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 40205069 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9866787 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1450416 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 361840570 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1450416 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 20789312 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11161609 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17754 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 44252475 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53368711 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 352352816 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 16475 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 802883 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 46797603 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4838735 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 354809982 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 933969547 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 575070468 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 25233 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 78853183 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 501 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 500 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 64461317 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 113156478 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 38725561 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 51813945 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9109294 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 346336448 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4423 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 319025181 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 175223 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 68148407 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 106206343 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3978 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 131908700 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.418530 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.165753 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 75597235 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 487 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 488 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 64661942 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 112312024 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 38476139 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 51587404 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9144280 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343861767 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4715 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 317818488 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 169830 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 65674018 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 101673382 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4270 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131040277 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.425350 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.164581 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 35712645 27.07% 27.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20185531 15.30% 42.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17171104 13.02% 55.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17670057 13.40% 68.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 15380757 11.66% 80.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12917935 9.79% 90.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6743014 5.11% 95.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4104772 3.11% 98.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2022885 1.53% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 35194225 26.86% 26.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20112862 15.35% 42.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17093441 13.04% 55.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17641161 13.46% 68.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15328111 11.70% 80.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12869587 9.82% 90.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6689257 5.10% 95.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4093724 3.12% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2017909 1.54% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 131908700 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131040277 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 364922 8.93% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3529438 86.37% 95.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 191983 4.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 366862 8.95% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3538662 86.29% 95.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 195200 4.76% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33340 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 182585704 57.23% 57.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11686 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 478 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 321 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101596397 31.85% 89.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34797255 10.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 181791277 57.20% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11724 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 408 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 305 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101272470 31.86% 89.08% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34708964 10.92% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 319025181 # Type of FU issued -system.cpu.iq.rate 2.417343 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4086343 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012809 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 774202119 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 414517759 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 314637932 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 18509 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 33754 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 4413 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 323069884 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8300 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57418928 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 317818488 # Type of FU issued +system.cpu.iq.rate 2.424101 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4100724 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012903 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 770927721 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 409562927 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 313648272 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 20086 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 38326 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 4607 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 321877132 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8740 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 57541030 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 22377093 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 67905 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 65034 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7285809 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 21532639 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 67356 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 63407 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7036387 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4034 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 140997 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3908 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 141249 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1530067 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8343953 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3020633 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 346340871 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 136261 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 113156478 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 38725561 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1825 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2944 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3026950 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 65034 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 548248 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1104057 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1652305 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 316487526 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100816589 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2537655 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1450416 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8045146 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3020269 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343866482 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 122594 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 112312024 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 38476139 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1910 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3213 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3025719 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 63407 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 529775 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1033204 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1562979 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 315414153 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100518036 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2404335 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 135188403 # number of memory reference insts executed -system.cpu.iew.exec_branches 32185799 # Number of branches executed -system.cpu.iew.exec_stores 34371814 # Number of stores executed -system.cpu.iew.exec_rate 2.398114 # Inst execution rate -system.cpu.iew.wb_sent 315304152 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 314642345 # cumulative count of insts written-back -system.cpu.iew.wb_producers 238446717 # num instructions producing a value -system.cpu.iew.wb_consumers 344411432 # num instructions consuming a value -system.cpu.iew.wb_rate 2.384133 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692331 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 68273083 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 134824639 # number of memory reference insts executed +system.cpu.iew.exec_branches 32104448 # Number of branches executed +system.cpu.iew.exec_stores 34306603 # Number of stores executed +system.cpu.iew.exec_rate 2.405762 # Inst execution rate +system.cpu.iew.wb_sent 314286106 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 313652879 # cumulative count of insts written-back +system.cpu.iew.wb_producers 237682188 # num instructions producing a value +system.cpu.iew.wb_consumers 343423954 # num instructions consuming a value +system.cpu.iew.wb_rate 2.392328 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692096 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 65797430 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1477187 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 122118176 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.278059 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.046851 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1399141 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 121633848 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.287130 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.051606 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 56957157 46.64% 46.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16546673 13.55% 60.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11180219 9.16% 69.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8765216 7.18% 76.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2116572 1.73% 78.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1764817 1.45% 79.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 934979 0.77% 80.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 730886 0.60% 81.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23121657 18.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 56556051 46.50% 46.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16464352 13.54% 60.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11233282 9.24% 69.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8748892 7.19% 76.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2045691 1.68% 78.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1756798 1.44% 79.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 927336 0.76% 80.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 727466 0.60% 80.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23173980 19.05% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 122118176 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 121633848 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -569,337 +568,336 @@ system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 23121657 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 445462066 # The number of ROB reads -system.cpu.rob.rob_writes 702797421 # The number of ROB writes -system.cpu.timesIdled 887 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 64788 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 23173980 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 442449762 # The number of ROB reads +system.cpu.rob.rob_writes 697455131 # The number of ROB writes +system.cpu.timesIdled 919 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 67515 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.835336 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.835336 # CPI: Total CPI of All Threads -system.cpu.ipc 1.197123 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.197123 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 504041942 # number of integer regfile reads -system.cpu.int_regfile_writes 248656420 # number of integer regfile writes -system.cpu.fp_regfile_reads 4180 # number of floating regfile reads -system.cpu.fp_regfile_writes 782 # number of floating regfile writes -system.cpu.cc_regfile_reads 109261684 # number of cc regfile reads -system.cpu.cc_regfile_writes 65602098 # number of cc regfile writes -system.cpu.misc_regfile_reads 202573497 # number of misc regfile reads +system.cpu.cpi 0.829856 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.829856 # CPI: Total CPI of All Threads +system.cpu.ipc 1.205028 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.205028 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 502814986 # number of integer regfile reads +system.cpu.int_regfile_writes 247784196 # number of integer regfile writes +system.cpu.fp_regfile_reads 4396 # number of floating regfile reads +system.cpu.fp_regfile_writes 732 # number of floating regfile writes +system.cpu.cc_regfile_reads 109093589 # number of cc regfile reads +system.cpu.cc_regfile_writes 65488596 # number of cc regfile writes +system.cpu.misc_regfile_reads 201890594 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2073508 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.413497 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 71894591 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2077604 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.604569 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 21372047500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.413497 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993265 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993265 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2073601 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.108072 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 71473739 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2077697 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.400463 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 21041764500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.108072 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993190 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993190 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 542 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3404 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 507 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3433 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 156 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 151442194 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 151442194 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 40548572 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40548572 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31346019 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31346019 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71894591 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71894591 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71894591 # number of overall hits -system.cpu.dcache.overall_hits::total 71894591 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2693971 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2693971 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93733 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93733 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2787704 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2787704 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2787704 # number of overall misses -system.cpu.dcache.overall_misses::total 2787704 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32332975500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32332975500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2952822993 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2952822993 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35285798493 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35285798493 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35285798493 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35285798493 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 43242543 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 43242543 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 150601371 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 150601371 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 40127755 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40127755 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31345984 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31345984 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71473739 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71473739 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71473739 # number of overall hits +system.cpu.dcache.overall_hits::total 71473739 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2694330 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2694330 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 93768 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 93768 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2788098 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2788098 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2788098 # number of overall misses +system.cpu.dcache.overall_misses::total 2788098 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32345718500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32345718500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2982305493 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2982305493 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35328023993 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35328023993 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35328023993 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35328023993 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 42822085 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 42822085 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74682295 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74682295 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74682295 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74682295 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062299 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.062299 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002981 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002981 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037328 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037328 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037328 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037328 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12001.976079 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12001.976079 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31502.491044 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31502.491044 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12657.656083 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12657.656083 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12657.656083 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12657.656083 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 219202 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 497 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 43207 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 74261837 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74261837 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74261837 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74261837 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062919 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.062919 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002982 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002982 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037544 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037544 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037544 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037544 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12005.106464 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12005.106464 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31805.152003 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31805.152003 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12671.012279 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12671.012279 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12671.012279 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12671.012279 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 218790 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 393 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 43059 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.073298 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 124.250000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2066969 # number of writebacks -system.cpu.dcache.writebacks::total 2066969 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 698217 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 698217 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11883 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11883 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 710100 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 710100 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 710100 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 710100 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995754 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1995754 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81850 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 81850 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2077604 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2077604 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2077604 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2077604 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24221413500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24221413500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2795777993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2795777993 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27017191493 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27017191493 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27017191493 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27017191493 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046153 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046153 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002603 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002603 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027819 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027819 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027819 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027819 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12136.472481 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12136.472481 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34157.336506 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34157.336506 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 93 # number of replacements -system.cpu.icache.tags.tagsinuse 870.928206 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 29996478 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1113 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26951.013477 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.081168 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 98.250000 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2067196 # number of writebacks +system.cpu.dcache.writebacks::total 2067196 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 698496 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 698496 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11905 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11905 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 710401 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 710401 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 710401 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 710401 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995834 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1995834 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81863 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 81863 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2077697 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2077697 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2077697 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2077697 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24223051500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24223051500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2825101993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2825101993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27048153493 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27048153493 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27048153493 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27048153493 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046608 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046608 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002604 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002604 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027978 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027978 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027978 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027978 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12136.806718 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12136.806718 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34510.120482 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34510.120482 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13018.333998 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13018.333998 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13018.333998 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13018.333998 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 91 # number of replacements +system.cpu.icache.tags.tagsinuse 875.979350 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 29741086 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1117 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26625.860340 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 870.928206 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.425258 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.425258 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1020 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 34 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 906 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 59996959 # Number of tag accesses -system.cpu.icache.tags.data_accesses 59996959 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 29996478 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 29996478 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 29996478 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 29996478 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 29996478 # number of overall hits -system.cpu.icache.overall_hits::total 29996478 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1445 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1445 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1445 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1445 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1445 # number of overall misses -system.cpu.icache.overall_misses::total 1445 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 106088999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 106088999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 106088999 # 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Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29988 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 166 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29650 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.915161 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 33250579 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 33250579 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 2067196 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2067196 # 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average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78090.073529 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75660.682226 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75660.682226 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78090.073529 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74072.277127 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74214.973559 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78090.073529 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74072.277127 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74214.973559 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -908,122 +906,128 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.writebacks::writebacks 280 # number of writebacks system.cpu.l2cache.writebacks::total 280 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28982 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 28982 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1085 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1085 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 555 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 555 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1085 # 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mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.974843 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000278 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.974843 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014217 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014731 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.974843 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014217 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014731 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63047.391484 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63047.391484 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66228.110599 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66228.110599 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68210.810811 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68210.810811 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66228.110599 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63144.412093 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63253.673829 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66228.110599 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63144.412093 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63253.673829 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4152318 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073604 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 20 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 325 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 325 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28989 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28989 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1856506500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74082000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74082000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 36573000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 36573000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74082000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1893079500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1967161500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74082000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1893079500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1967161500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.354004 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.354004 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.974038 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.974038 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000279 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000279 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.974038 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014736 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.974038 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014736 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64041.757218 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64041.757218 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68090.073529 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68090.073529 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65660.682226 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65660.682226 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68090.073529 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64072.277127 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64214.973559 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68090.073529 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64072.277127 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64214.973559 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4152506 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073696 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 331 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 331 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1996829 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2067249 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 93 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6909 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 81888 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 81888 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1113 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995716 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2319 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228716 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6231035 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265252672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265329856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 650 # Total snoops (count) +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1996925 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2067476 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 91 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6788 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 81889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 81889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1117 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995808 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2325 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228995 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6231320 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265273152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265350464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 663 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 17920 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2079367 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.012936 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 2079477 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000168 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.012972 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2079019 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 348 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2079127 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 350 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2079367 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4143221000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2079477 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4143540000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1670997 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1675999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3116406000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1640 # Transaction distribution +system.cpu.toL2Bus.respLayer1.occupancy 3116545500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 30966 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 332 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 65553895500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1645 # Transaction distribution system.membus.trans_dist::WritebackDirty 280 # Transaction distribution -system.membus.trans_dist::CleanEvict 45 # Transaction distribution -system.membus.trans_dist::ReadExReq 28982 # Transaction distribution -system.membus.trans_dist::ReadExResp 28982 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1640 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61569 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61569 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61569 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1977728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1977728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1977728 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::CleanEvict 52 # Transaction distribution +system.membus.trans_dist::ReadExReq 28989 # Transaction distribution +system.membus.trans_dist::ReadExResp 28989 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1645 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61600 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61600 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61600 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1978496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1978496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1978496 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 30947 # Request fanout histogram +system.membus.snoop_fanout::samples 30634 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30947 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 30634 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30947 # Request fanout histogram -system.membus.reqLayer0.occupancy 43483000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 30634 # Request fanout histogram +system.membus.reqLayer0.occupancy 43502500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 161384500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 161439750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index 8197faf7d..683cfaa02 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,51 +1,51 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.366199 # Number of seconds simulated -sim_ticks 366199170500 # Number of ticks simulated -final_tick 366199170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.366229 # Number of seconds simulated +sim_ticks 366229314500 # Number of ticks simulated +final_tick 366229314500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 454673 # Simulator instruction rate (inst/s) -host_op_rate 800606 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1053878980 # Simulator tick rate (ticks/s) -host_mem_usage 406480 # Number of bytes of host memory used -host_seconds 347.48 # Real time elapsed on the host +host_inst_rate 561124 # Simulator instruction rate (inst/s) +host_op_rate 988050 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1300728257 # Simulator tick rate (ticks/s) +host_mem_usage 412916 # Number of bytes of host memory used +host_seconds 281.56 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1871424 # Number of bytes read from this memory -system.physmem.bytes_read::total 1922816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1871552 # Number of bytes read from this memory +system.physmem.bytes_read::total 1922944 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6528 # Number of bytes written to this memory -system.physmem.bytes_written::total 6528 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 6656 # Number of bytes written to this memory +system.physmem.bytes_written::total 6656 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29241 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30044 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 102 # Number of write requests responded to by this memory -system.physmem.num_writes::total 102 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 140339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5110399 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5250738 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 140339 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 140339 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 17826 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 17826 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 17826 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 140339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5110399 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5268565 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.physmem.num_reads::cpu.data 29243 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30046 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 104 # Number of write requests responded to by this memory +system.physmem.num_writes::total 104 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 140327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5110328 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5250656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 140327 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 140327 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 18174 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 18174 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 18174 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 140327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5110328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5268830 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 366199170500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 732398341 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 366229314500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 732458629 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 157988548 # Number of instructions committed @@ -66,7 +66,7 @@ system.cpu.num_mem_refs 122219137 # nu system.cpu.num_load_insts 90779385 # Number of load instructions system.cpu.num_store_insts 31439752 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 732398340.998000 # Number of busy cycles +system.cpu.num_busy_cycles 732458628.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 29309705 # Number of branches fetched @@ -105,25 +105,25 @@ system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 278192465 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2062733 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.299825 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4076.272883 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 126122344500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.299825 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995190 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995190 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 126128435500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.272883 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995184 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995184 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1779 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2195 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1776 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2198 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits @@ -140,14 +140,14 @@ system.cpu.dcache.demand_misses::cpu.data 2066829 # n system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses system.cpu.dcache.overall_misses::total 2066829 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 25499993500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 25499993500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2801625000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2801625000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28301618500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28301618500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28301618500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28301618500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25500310500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25500310500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2830649000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2830649000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28330959500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28330959500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28330959500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28330959500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) @@ -164,14 +164,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13005.423263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13005.423263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26403.273992 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26403.273992 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13693.255949 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13693.255949 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13005.584938 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13005.584938 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26676.804041 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26676.804041 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13707.452092 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13707.452092 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13707.452092 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13707.452092 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -188,14 +188,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23539273500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23539273500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2695516000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2695516000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26234789500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26234789500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26234789500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26234789500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23539590500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23539590500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2724540000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2724540000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26264130500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26264130500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26264130500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26264130500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses @@ -204,22 +204,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12005.423263 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12005.423263 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25403.273992 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25403.273992 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12005.584938 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12005.584938 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25676.804041 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25676.804041 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12707.452092 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12707.452092 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12707.452092 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12707.452092 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 24 # number of replacements -system.cpu.icache.tags.tagsinuse 665.627299 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 665.626582 # Cycle average of tags in use system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 665.627299 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 665.626582 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.325013 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.325013 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id @@ -229,7 +229,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 715 system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 435393136 # Number of tag accesses system.cpu.icache.tags.data_accesses 435393136 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 217695356 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 217695356 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 217695356 # number of demand (read+write) hits @@ -242,12 +242,12 @@ system.cpu.icache.demand_misses::cpu.inst 808 # n system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses system.cpu.icache.overall_misses::total 808 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 49857000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 49857000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 49857000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 49857000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 49857000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 49857000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 50660000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 50660000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 50660000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 50660000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 50660000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 50660000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses @@ -260,12 +260,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61704.207921 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61704.207921 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61704.207921 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61704.207921 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62698.019802 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62698.019802 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62698.019802 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62698.019802 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62698.019802 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62698.019802 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -280,48 +280,48 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 808 system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49049000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 49049000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49049000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 49049000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49049000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 49049000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49852000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 49852000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49852000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 49852000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49852000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 49852000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60704.207921 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60704.207921 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 313 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20037.622351 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3992697 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 30021 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 132.996802 # Average number of references to valid blocks. +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61698.019802 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61698.019802 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61698.019802 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61698.019802 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61698.019802 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61698.019802 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 315 # number of replacements +system.cpu.l2cache.tags.tagsinuse 21080.806353 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4100347 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30047 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 136.464439 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 19324.712224 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.457266 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 156.452862 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.589743 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016982 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.004775 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.611500 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1692 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27876 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 33179282 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 33179282 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::writebacks 0.624695 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.051540 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 20524.130118 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000019 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016969 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.626347 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.643335 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29732 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 45 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29568 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.907349 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 33073199 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 33073199 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 2062482 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2062482 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 24 # number of WritebackClean hits @@ -330,38 +330,38 @@ system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 5 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1960503 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1960503 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1960501 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1960501 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2037588 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2037593 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2037586 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2037591 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2037588 # number of overall hits -system.cpu.l2cache.overall_hits::total 2037593 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2037586 # number of overall hits +system.cpu.l2cache.overall_hits::total 2037591 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 803 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 803 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 217 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 217 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 219 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 219 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 29241 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 30044 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 29243 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 30046 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 29241 # number of overall misses -system.cpu.l2cache.overall_misses::total 30044 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1726959000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1726959000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47782000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 47782000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12911500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 12911500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 47782000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1739870500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1787652500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 47782000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1739870500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1787652500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 29243 # number of overall misses +system.cpu.l2cache.overall_misses::total 30046 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1755983000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1755983000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 48585000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 48585000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13249500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 13249500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 48585000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1769232500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1817817500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 48585000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1769232500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1817817500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 2062482 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 2062482 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 24 # number of WritebackClean accesses(hits+misses) @@ -382,91 +382,91 @@ system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993812 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000111 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000111 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000112 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000112 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014148 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014531 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014149 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014532 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014148 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014531 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.068082 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.068082 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59504.358655 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59504.358655 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59501.148316 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59501.148316 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014149 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014532 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60501.068082 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60501.068082 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60504.358655 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60504.358655 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60504.358655 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.060083 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60501.148239 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60504.358655 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.060083 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60501.148239 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 102 # number of writebacks -system.cpu.l2cache.writebacks::total 102 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 104 # number of writebacks +system.cpu.l2cache.writebacks::total 104 # number of writebacks system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 803 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 803 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 217 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 217 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 219 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 219 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29241 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30044 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29243 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30046 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29241 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30044 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1436719000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1436719000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 39752000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 39752000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10741500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10741500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39752000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1447460500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1487212500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39752000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1447460500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1487212500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 29243 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30046 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1465743000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1465743000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 40555000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 40555000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11059500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11059500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40555000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1476802500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1517357500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40555000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1476802500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1517357500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993812 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000111 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000112 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014531 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014149 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014532 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014531 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.068082 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.068082 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49504.358655 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49504.358655 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014149 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014532 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50501.068082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50501.068082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50504.358655 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50504.358655 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50504.358655 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.060083 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.148239 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50504.358655 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.060083 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.148239 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 4130394 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 197 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2062584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2062586 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 24 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 462 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution @@ -479,53 +479,59 @@ system.cpu.toL2Bus.pkt_count::total 6198031 # Pa system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53248 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264275904 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 264329152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 313 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6528 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2067950 # Request fanout histogram +system.cpu.toL2Bus.snoops 315 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6656 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2067952 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000095 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.009760 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2067753 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2067755 99.99% 99.99% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 197 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2067950 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2067952 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4127703000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1020 # Transaction distribution -system.membus.trans_dist::WritebackDirty 102 # Transaction distribution +system.membus.snoop_filter.tot_requests 30164 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 118 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1022 # Transaction distribution +system.membus.trans_dist::WritebackDirty 104 # Transaction distribution system.membus.trans_dist::CleanEvict 14 # Transaction distribution system.membus.trans_dist::ReadExReq 29024 # Transaction distribution system.membus.trans_dist::ReadExResp 29024 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1020 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60204 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60204 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 60204 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1929344 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 1022 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60210 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60210 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 60210 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1929600 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 30160 # Request fanout histogram +system.membus.snoop_fanout::samples 30046 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30160 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 30046 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30160 # Request fanout histogram -system.membus.reqLayer0.occupancy 30602500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 30046 # Request fanout histogram +system.membus.reqLayer0.occupancy 30614500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 150220000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 150230000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index 2a8feed05..eadbc59cf 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.417310 # Number of seconds simulated -sim_ticks 417309765500 # Number of ticks simulated -final_tick 417309765500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.417806 # Number of seconds simulated +sim_ticks 417805983500 # Number of ticks simulated +final_tick 417805983500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 274693 # Simulator instruction rate (inst/s) -host_op_rate 274693 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 187337647 # Simulator tick rate (ticks/s) -host_mem_usage 252076 # Number of bytes of host memory used -host_seconds 2227.58 # Real time elapsed on the host +host_inst_rate 243916 # Simulator instruction rate (inst/s) +host_op_rate 243916 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 166545939 # Simulator tick rate (ticks/s) +host_mem_usage 257728 # Number of bytes of host memory used +host_seconds 2508.65 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 156544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24144128 # Number of bytes read from this memory -system.physmem.bytes_read::total 24300672 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 156544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 156544 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18790848 # Number of bytes written to this memory -system.physmem.bytes_written::total 18790848 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2446 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 377252 # Number of read requests responded to by this memory -system.physmem.num_reads::total 379698 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293607 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293607 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 375127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 57856609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 58231736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 375127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 375127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45028536 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45028536 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45028536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 375127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 57856609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 103260272 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 379698 # Number of read requests accepted -system.physmem.writeReqs 293607 # Number of write requests accepted -system.physmem.readBursts 379698 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 293607 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24277632 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 23040 # Total number of bytes read from write queue -system.physmem.bytesWritten 18789440 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24300672 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18790848 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 360 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 156672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24196352 # Number of bytes read from this memory +system.physmem.bytes_read::total 24353024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 156672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 156672 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18839232 # Number of bytes written to this memory +system.physmem.bytes_written::total 18839232 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2448 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 378068 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380516 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 294363 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294363 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 374987 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 57912890 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 58287878 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 374987 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 374987 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45090862 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45090862 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45090862 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 374987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 57912890 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 103378740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 380516 # Number of read requests accepted +system.physmem.writeReqs 294363 # Number of write requests accepted +system.physmem.readBursts 380516 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 294363 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24332224 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20800 # Total number of bytes read from write queue +system.physmem.bytesWritten 18837888 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24353024 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18839232 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 325 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 23694 # Per bank write bursts -system.physmem.perBankRdBursts::1 23158 # Per bank write bursts -system.physmem.perBankRdBursts::2 23444 # Per bank write bursts -system.physmem.perBankRdBursts::3 24500 # Per bank write bursts -system.physmem.perBankRdBursts::4 25443 # Per bank write bursts -system.physmem.perBankRdBursts::5 23576 # Per bank write bursts -system.physmem.perBankRdBursts::6 23654 # Per bank write bursts -system.physmem.perBankRdBursts::7 23908 # Per bank write bursts -system.physmem.perBankRdBursts::8 23181 # Per bank write bursts -system.physmem.perBankRdBursts::9 23984 # Per bank write bursts -system.physmem.perBankRdBursts::10 24716 # Per bank write bursts -system.physmem.perBankRdBursts::11 22779 # Per bank write bursts -system.physmem.perBankRdBursts::12 23723 # Per bank write bursts -system.physmem.perBankRdBursts::13 24392 # Per bank write bursts -system.physmem.perBankRdBursts::14 22740 # Per bank write bursts -system.physmem.perBankRdBursts::15 22446 # Per bank write bursts -system.physmem.perBankWrBursts::0 17782 # Per bank write bursts -system.physmem.perBankWrBursts::1 17457 # Per bank write bursts -system.physmem.perBankWrBursts::2 17944 # Per bank write bursts -system.physmem.perBankWrBursts::3 18853 # Per bank write bursts -system.physmem.perBankWrBursts::4 19512 # Per bank write bursts -system.physmem.perBankWrBursts::5 18592 # Per bank write bursts -system.physmem.perBankWrBursts::6 18778 # Per bank write bursts -system.physmem.perBankWrBursts::7 18657 # Per bank write bursts -system.physmem.perBankWrBursts::8 18440 # Per bank write bursts -system.physmem.perBankWrBursts::9 18940 # Per bank write bursts -system.physmem.perBankWrBursts::10 19258 # Per bank write bursts -system.physmem.perBankWrBursts::11 18049 # Per bank write bursts -system.physmem.perBankWrBursts::12 18265 # Per bank write bursts -system.physmem.perBankWrBursts::13 18732 # Per bank write bursts -system.physmem.perBankWrBursts::14 17195 # Per bank write bursts -system.physmem.perBankWrBursts::15 17131 # Per bank write bursts +system.physmem.perBankRdBursts::0 23763 # Per bank write bursts +system.physmem.perBankRdBursts::1 23178 # Per bank write bursts +system.physmem.perBankRdBursts::2 23498 # Per bank write bursts +system.physmem.perBankRdBursts::3 24610 # Per bank write bursts +system.physmem.perBankRdBursts::4 25501 # Per bank write bursts +system.physmem.perBankRdBursts::5 23627 # Per bank write bursts +system.physmem.perBankRdBursts::6 23703 # Per bank write bursts +system.physmem.perBankRdBursts::7 23985 # Per bank write bursts +system.physmem.perBankRdBursts::8 23235 # Per bank write bursts +system.physmem.perBankRdBursts::9 24022 # Per bank write bursts +system.physmem.perBankRdBursts::10 24757 # Per bank write bursts +system.physmem.perBankRdBursts::11 22829 # Per bank write bursts +system.physmem.perBankRdBursts::12 23792 # Per bank write bursts +system.physmem.perBankRdBursts::13 24451 # Per bank write bursts +system.physmem.perBankRdBursts::14 22759 # Per bank write bursts +system.physmem.perBankRdBursts::15 22481 # Per bank write bursts +system.physmem.perBankWrBursts::0 17837 # Per bank write bursts +system.physmem.perBankWrBursts::1 17476 # Per bank write bursts +system.physmem.perBankWrBursts::2 17996 # Per bank write bursts +system.physmem.perBankWrBursts::3 18950 # Per bank write bursts +system.physmem.perBankWrBursts::4 19553 # Per bank write bursts +system.physmem.perBankWrBursts::5 18644 # Per bank write bursts +system.physmem.perBankWrBursts::6 18825 # Per bank write bursts +system.physmem.perBankWrBursts::7 18731 # Per bank write bursts +system.physmem.perBankWrBursts::8 18487 # Per bank write bursts +system.physmem.perBankWrBursts::9 18977 # Per bank write bursts +system.physmem.perBankWrBursts::10 19289 # Per bank write bursts +system.physmem.perBankWrBursts::11 18103 # Per bank write bursts +system.physmem.perBankWrBursts::12 18331 # Per bank write bursts +system.physmem.perBankWrBursts::13 18779 # Per bank write bursts +system.physmem.perBankWrBursts::14 17209 # Per bank write bursts +system.physmem.perBankWrBursts::15 17155 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 417309678500 # Total gap between requests +system.physmem.totGap 417805895500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 379698 # Read request sizes (log2) +system.physmem.readPktSize::6 380516 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 293607 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 378264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1069 # What read queue length does an incoming req see +system.physmem.writePktSize::6 294363 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 379108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1078 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,37 +145,37 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see @@ -194,102 +194,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 142524 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 302.166540 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.513789 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.994907 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50939 35.74% 35.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38821 27.24% 62.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13298 9.33% 72.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8416 5.90% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5517 3.87% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3864 2.71% 84.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2991 2.10% 86.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2664 1.87% 88.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16014 11.24% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 142524 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17328 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.890986 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 236.476851 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17319 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 138680 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 311.287453 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 185.207223 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.580337 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47172 34.01% 34.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38791 27.97% 61.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13255 9.56% 71.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8020 5.78% 77.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5116 3.69% 81.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3846 2.77% 83.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3216 2.32% 86.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2646 1.91% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16618 11.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 138680 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17507 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.716228 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 18.015056 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 232.517715 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17502 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 2 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7168-8191 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17328 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17328 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.942809 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.869717 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.235744 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 17276 99.70% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 34 0.20% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 12 0.07% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 2 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::328-335 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17328 # Writes before turning the bus around for reads -system.physmem.totQLat 4040781000 # Total ticks spent queuing -system.physmem.totMemAccLat 11153368500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1896690000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10652.19 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17507 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17507 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.812818 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.784450 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.984212 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 10318 58.94% 58.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 249 1.42% 60.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 6843 39.09% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 94 0.54% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17507 # Writes before turning the bus around for reads +system.physmem.totQLat 4112094750 # Total ticks spent queuing +system.physmem.totMemAccLat 11240676000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1900955000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10815.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29402.19 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 58.18 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 45.03 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 58.23 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 45.03 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29565.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 58.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 45.09 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 58.29 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 45.09 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.81 # Data bus utilization in percentage system.physmem.busUtilRead 0.45 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.54 # Average write queue length when enqueuing -system.physmem.readRowHits 314151 # Number of row buffer hits during reads -system.physmem.writeRowHits 216242 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.65 # Row buffer hit rate for writes -system.physmem.avgGap 619792.93 # Average gap between requests -system.physmem.pageHitRate 78.82 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 548954280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 299528625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1492608000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 956117520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 27256273200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 62660545740 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 195417206250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 288631233615 # Total energy per rank (pJ) -system.physmem_0.averagePower 691.656457 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 324545157250 # Time in different power states -system.physmem_0.memoryStateTime::REF 13934700000 # Time in different power states +system.physmem.avgWrQLen 21.26 # Average write queue length when enqueuing +system.physmem.readRowHits 314275 # Number of row buffer hits during reads +system.physmem.writeRowHits 221571 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.66 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.27 # Row buffer hit rate for writes +system.physmem.avgGap 619082.67 # Average gap between requests +system.physmem.pageHitRate 79.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 534363480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 291567375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1496445600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 959027040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 27288821040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 62100331785 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 196207614000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 288878170320 # Total energy per rank (pJ) +system.physmem_0.averagePower 691.422544 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 325857976500 # Time in different power states +system.physmem_0.memoryStateTime::REF 13951340000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 78824485250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 77993346000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 528194520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 288201375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1465682400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 946002240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 27256273200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 59613271875 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 198090253500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 288187879110 # Total energy per rank (pJ) -system.physmem_1.averagePower 690.594032 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 329008482750 # Time in different power states -system.physmem_1.memoryStateTime::REF 13934700000 # Time in different power states +system.physmem_1.actEnergy 513853200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 280376250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1468724400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 948101760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 27288821040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 59269027500 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 198691214250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 288460118400 # Total energy per rank (pJ) +system.physmem_1.averagePower 690.421947 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 330008811500 # Time in different power states +system.physmem_1.memoryStateTime::REF 13951340000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 74361159750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 73843223000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 124433672 # Number of BP lookups +system.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 124433678 # Number of BP lookups system.cpu.branchPred.condPredicted 87996740 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 6213240 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 71713354 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67453022 # Number of BTB hits +system.cpu.branchPred.BTBLookups 71713362 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67453030 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 94.059221 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15161941 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 15161942 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1121063 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 7034 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 4431 # Number of indirect target hits. @@ -300,22 +298,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 149830728 # DTB read hits +system.cpu.dtb.read_hits 149830726 # DTB read hits system.cpu.dtb.read_misses 559355 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 150390083 # DTB read accesses +system.cpu.dtb.read_accesses 150390081 # DTB read accesses system.cpu.dtb.write_hits 57603616 # DTB write hits system.cpu.dtb.write_misses 71398 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 57675014 # DTB write accesses -system.cpu.dtb.data_hits 207434344 # DTB hits +system.cpu.dtb.data_hits 207434342 # DTB hits system.cpu.dtb.data_misses 630753 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 208065097 # DTB accesses -system.cpu.itb.fetch_hits 227957182 # ITB hits +system.cpu.dtb.data_accesses 208065095 # DTB accesses +system.cpu.itb.fetch_hits 227957240 # ITB hits system.cpu.itb.fetch_misses 48 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 227957230 # ITB accesses +system.cpu.itb.fetch_accesses 227957288 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -329,16 +327,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 417309765500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 834619531 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 417805983500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 835611967 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 611901617 # Number of instructions committed system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed -system.cpu.discardedOps 14840405 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 14840404 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.363977 # CPI: cycles per instruction -system.cpu.ipc 0.733150 # IPC: instructions per cycle +system.cpu.cpi 1.365599 # CPI: cycles per instruction +system.cpu.ipc 0.732280 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 52179272 8.53% 8.53% # Class of committed instruction system.cpu.op_class_0::IntAlu 355264620 58.06% 66.59% # Class of committed instruction system.cpu.op_class_0::IntMult 152833 0.02% 66.61% # Class of committed instruction @@ -374,59 +372,59 @@ system.cpu.op_class_0::MemWrite 57220983 9.35% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 611901617 # Class of committed instruction -system.cpu.tickCycles 746834256 # Number of cycles that the object actually ticked -system.cpu.idleCycles 87785275 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 746834854 # Number of cycles that the object actually ticked +system.cpu.idleCycles 88777113 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2535509 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.685849 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 203187427 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4087.671717 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 203187431 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2539605 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 80.007492 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1653740500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.685849 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997970 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997970 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 80.007494 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1657773500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.671717 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997967 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997967 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 75 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 828 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3147 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 415624619 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 415624619 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tag_accesses 415624617 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 415624617 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 147521260 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 147521260 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 55666167 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 55666167 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 203187427 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 203187427 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 203187427 # number of overall hits -system.cpu.dcache.overall_hits::total 203187427 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1811213 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1811213 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1543867 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1543867 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3355080 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3355080 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3355080 # number of overall misses -system.cpu.dcache.overall_misses::total 3355080 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36182187000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36182187000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 47720909500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 47720909500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83903096500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83903096500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83903096500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83903096500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 149332473 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 149332473 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits::cpu.data 55666171 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 55666171 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 203187431 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 203187431 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 203187431 # number of overall hits +system.cpu.dcache.overall_hits::total 203187431 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1811212 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1811212 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1543863 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1543863 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3355075 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3355075 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3355075 # number of overall misses +system.cpu.dcache.overall_misses::total 3355075 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36424837000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36424837000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 48227162000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 48227162000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 84651999000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 84651999000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 84651999000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 84651999000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 149332472 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 149332472 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 57210034 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 206542507 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 206542507 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 206542507 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 206542507 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 206542506 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 206542506 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 206542506 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 206542506 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012129 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012129 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026986 # miss rate for WriteReq accesses @@ -435,30 +433,30 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016244 system.cpu.dcache.demand_miss_rate::total 0.016244 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016244 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016244 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19976.770816 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19976.770816 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30909.987389 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30909.987389 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25007.778205 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25007.778205 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25007.778205 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25007.778205 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20110.752910 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20110.752910 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31237.980313 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31237.980313 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25231.030305 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25231.030305 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25231.030305 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25231.030305 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2339608 # number of writebacks -system.cpu.dcache.writebacks::total 2339608 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 46417 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 46417 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769058 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 769058 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 815475 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 815475 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 815475 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 815475 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 2339290 # number of writebacks +system.cpu.dcache.writebacks::total 2339290 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 46416 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 46416 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769054 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 769054 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 815470 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 815470 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 815470 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 815470 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764796 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1764796 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774809 # number of WriteReq MSHR misses @@ -467,14 +465,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2539605 system.cpu.dcache.demand_mshr_misses::total 2539605 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2539605 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2539605 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33173534500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33173534500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23341678000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 23341678000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56515212500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 56515212500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56515212500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 56515212500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33407226500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33407226500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23596131500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 23596131500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 57003358000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 57003358000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 57003358000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 57003358000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.011818 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011818 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013543 # mshr miss rate for WriteReq accesses @@ -483,24 +481,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012296 system.cpu.dcache.demand_mshr_miss_rate::total 0.012296 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012296 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012296 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18797.376297 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18797.376297 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30125.718726 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30125.718726 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22253.544350 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22253.544350 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22253.544350 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22253.544350 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18929.795002 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18929.795002 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30454.126759 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30454.126759 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22445.757510 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22445.757510 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22445.757510 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22445.757510 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 3176 # number of replacements -system.cpu.icache.tags.tagsinuse 1116.866766 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 227952177 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1116.932847 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 227952235 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 5005 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 45544.890509 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 45544.902098 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1116.866766 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.545345 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.545345 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1116.932847 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.545377 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.545377 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 80 # Occupied blocks per task id @@ -508,45 +506,45 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 17 system.cpu.icache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1592 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 455919369 # Number of tag accesses -system.cpu.icache.tags.data_accesses 455919369 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 227952177 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 227952177 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 227952177 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 227952177 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 227952177 # number of overall hits -system.cpu.icache.overall_hits::total 227952177 # number of overall hits +system.cpu.icache.tags.tag_accesses 455919485 # Number of tag accesses +system.cpu.icache.tags.data_accesses 455919485 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 227952235 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 227952235 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 227952235 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 227952235 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 227952235 # number of overall hits +system.cpu.icache.overall_hits::total 227952235 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 5005 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 5005 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 5005 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 5005 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5005 # number of overall misses system.cpu.icache.overall_misses::total 5005 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 230776000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 230776000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 230776000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 230776000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 230776000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 230776000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 227957182 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 227957182 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 227957182 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 227957182 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 227957182 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 227957182 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 240293500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 240293500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 240293500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 240293500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 240293500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 240293500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 227957240 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 227957240 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 227957240 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 227957240 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 227957240 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 227957240 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46109.090909 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46109.090909 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46109.090909 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46109.090909 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46109.090909 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46109.090909 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48010.689311 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48010.689311 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48010.689311 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48010.689311 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48010.689311 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48010.689311 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -561,90 +559,90 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5005 system.cpu.icache.demand_mshr_misses::total 5005 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 5005 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 5005 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 225771000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 225771000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 225771000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 225771000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 225771000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 225771000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 235288500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 235288500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 235288500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 235288500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 235288500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 235288500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45109.090909 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45109.090909 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45109.090909 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 45109.090909 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45109.090909 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 45109.090909 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 347716 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29508.447379 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3909297 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 380147 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.283646 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 191524989500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21334.159610 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.927719 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8013.360050 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.651067 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004911 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.244548 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.900526 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32431 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13172 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18759 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989716 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41824659 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41824659 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2339608 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2339608 # number of WritebackDirty hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47010.689311 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47010.689311 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47010.689311 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47010.689311 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47010.689311 # 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number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12292449000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12292449000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176434000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26702568500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26879002500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176434000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26702568500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26879002500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265122 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265122 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.488711 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.488711 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.097049 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.097049 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.488711 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148548 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.149217 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.488711 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148548 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.149217 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68611.667192 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68611.667192 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68240.188062 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68240.188062 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70542.753017 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70542.753017 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68240.188062 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69486.714451 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69478.684375 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68240.188062 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69486.714451 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69478.684375 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265318 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265318 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.489111 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.489111 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.097425 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.097425 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.489111 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148869 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.149538 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.489111 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148869 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.149538 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69796.856988 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69796.856988 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72072.712418 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72072.712418 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71630.143931 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71630.143931 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72072.712418 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70629.009861 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70638.297733 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72072.712418 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70629.009861 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70638.297733 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 5083295 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2538685 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2395 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2395 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2446 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2446 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1766458 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2633215 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2633653 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3176 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 250010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 250480 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 778152 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 778152 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 5005 # Transaction distribution @@ -762,53 +760,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7614719 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 7627905 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 523584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312269632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312793216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 347716 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18790848 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2892326 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000828 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.028764 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312249280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312772864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 348624 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 18839232 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2893234 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000845 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.029064 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2889931 99.92% 99.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2395 0.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2890788 99.92% 99.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2446 0.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2892326 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4884431500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2893234 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4884113500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 7507500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3809407500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 173393 # Transaction distribution -system.membus.trans_dist::WritebackDirty 293607 # Transaction distribution -system.membus.trans_dist::CleanEvict 51719 # Transaction distribution -system.membus.trans_dist::ReadExReq 206305 # Transaction distribution -system.membus.trans_dist::ReadExResp 206305 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 173393 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1104722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1104722 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43091520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43091520 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 726699 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 346183 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 174058 # Transaction distribution +system.membus.trans_dist::WritebackDirty 294363 # Transaction distribution +system.membus.trans_dist::CleanEvict 51820 # Transaction distribution +system.membus.trans_dist::ReadExReq 206458 # Transaction distribution +system.membus.trans_dist::ReadExResp 206458 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 174058 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1107215 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1107215 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43192256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43192256 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 725024 # Request fanout histogram +system.membus.snoop_fanout::samples 380516 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 725024 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 380516 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 725024 # Request fanout histogram -system.membus.reqLayer0.occupancy 2021857500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 380516 # Request fanout histogram +system.membus.reqLayer0.occupancy 2021728500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2009466000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2014027500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 55f9db9e0..3a2939b58 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.366439 # Number of seconds simulated -sim_ticks 366439129500 # Number of ticks simulated -final_tick 366439129500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.366632 # Number of seconds simulated +sim_ticks 366631719500 # Number of ticks simulated +final_tick 366631719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 188596 # Simulator instruction rate (inst/s) -host_op_rate 204275 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 136422977 # Simulator tick rate (ticks/s) -host_mem_usage 271112 # Number of bytes of host memory used -host_seconds 2686.05 # Real time elapsed on the host +host_inst_rate 211005 # Simulator instruction rate (inst/s) +host_op_rate 228546 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 152712719 # Simulator tick rate (ticks/s) +host_mem_usage 277288 # Number of bytes of host memory used +host_seconds 2400.79 # Real time elapsed on the host sim_insts 506579366 # Number of instructions simulated sim_ops 548692589 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 179840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9028544 # Number of bytes read from this memory -system.physmem.bytes_read::total 9208384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9053376 # Number of bytes read from this memory +system.physmem.bytes_read::total 9233216 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 179840 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 179840 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6219648 # Number of bytes written to this memory -system.physmem.bytes_written::total 6219648 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 6241792 # Number of bytes written to this memory +system.physmem.bytes_written::total 6241792 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2810 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141071 # Number of read requests responded to by this memory -system.physmem.num_reads::total 143881 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97182 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97182 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 490777 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24638591 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25129369 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 490777 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 490777 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 16973209 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 16973209 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 16973209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 490777 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24638591 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42102578 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 143881 # Number of read requests accepted -system.physmem.writeReqs 97182 # Number of write requests accepted -system.physmem.readBursts 143881 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97182 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9201344 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7040 # Total number of bytes read from write queue -system.physmem.bytesWritten 6217600 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9208384 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6219648 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 110 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu.data 141459 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144269 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97528 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97528 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 490519 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24693379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25183898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 490519 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 490519 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17024692 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17024692 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17024692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 490519 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24693379 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42208590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144269 # Number of read requests accepted +system.physmem.writeReqs 97528 # Number of write requests accepted +system.physmem.readBursts 144269 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97528 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9226688 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue +system.physmem.bytesWritten 6240064 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9233216 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6241792 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9364 # Per bank write bursts -system.physmem.perBankRdBursts::1 8912 # Per bank write bursts -system.physmem.perBankRdBursts::2 8949 # Per bank write bursts -system.physmem.perBankRdBursts::3 8655 # Per bank write bursts -system.physmem.perBankRdBursts::4 9392 # Per bank write bursts -system.physmem.perBankRdBursts::5 9355 # Per bank write bursts -system.physmem.perBankRdBursts::6 8959 # Per bank write bursts -system.physmem.perBankRdBursts::7 8100 # Per bank write bursts -system.physmem.perBankRdBursts::8 8596 # Per bank write bursts -system.physmem.perBankRdBursts::9 8629 # Per bank write bursts -system.physmem.perBankRdBursts::10 8739 # Per bank write bursts -system.physmem.perBankRdBursts::11 9451 # Per bank write bursts -system.physmem.perBankRdBursts::12 9334 # Per bank write bursts -system.physmem.perBankRdBursts::13 9512 # Per bank write bursts -system.physmem.perBankRdBursts::14 8707 # Per bank write bursts -system.physmem.perBankRdBursts::15 9117 # Per bank write bursts -system.physmem.perBankWrBursts::0 6231 # Per bank write bursts -system.physmem.perBankWrBursts::1 6102 # Per bank write bursts -system.physmem.perBankWrBursts::2 6028 # Per bank write bursts -system.physmem.perBankWrBursts::3 5879 # Per bank write bursts -system.physmem.perBankWrBursts::4 6243 # Per bank write bursts -system.physmem.perBankWrBursts::5 6239 # Per bank write bursts -system.physmem.perBankWrBursts::6 6050 # Per bank write bursts -system.physmem.perBankWrBursts::7 5507 # Per bank write bursts -system.physmem.perBankWrBursts::8 5786 # Per bank write bursts -system.physmem.perBankWrBursts::9 5859 # Per bank write bursts -system.physmem.perBankWrBursts::10 5978 # Per bank write bursts -system.physmem.perBankWrBursts::11 6493 # Per bank write bursts -system.physmem.perBankWrBursts::12 6351 # Per bank write bursts -system.physmem.perBankWrBursts::13 6319 # Per bank write bursts -system.physmem.perBankWrBursts::14 5995 # Per bank write bursts -system.physmem.perBankWrBursts::15 6090 # Per bank write bursts +system.physmem.perBankRdBursts::0 9376 # Per bank write bursts +system.physmem.perBankRdBursts::1 8929 # Per bank write bursts +system.physmem.perBankRdBursts::2 8964 # Per bank write bursts +system.physmem.perBankRdBursts::3 8666 # Per bank write bursts +system.physmem.perBankRdBursts::4 9423 # Per bank write bursts +system.physmem.perBankRdBursts::5 9371 # Per bank write bursts +system.physmem.perBankRdBursts::6 8974 # Per bank write bursts +system.physmem.perBankRdBursts::7 8126 # Per bank write bursts +system.physmem.perBankRdBursts::8 8634 # Per bank write bursts +system.physmem.perBankRdBursts::9 8697 # Per bank write bursts +system.physmem.perBankRdBursts::10 8760 # Per bank write bursts +system.physmem.perBankRdBursts::11 9487 # Per bank write bursts +system.physmem.perBankRdBursts::12 9347 # Per bank write bursts +system.physmem.perBankRdBursts::13 9550 # Per bank write bursts +system.physmem.perBankRdBursts::14 8728 # Per bank write bursts +system.physmem.perBankRdBursts::15 9135 # Per bank write bursts +system.physmem.perBankWrBursts::0 6252 # Per bank write bursts +system.physmem.perBankWrBursts::1 6118 # Per bank write bursts +system.physmem.perBankWrBursts::2 6042 # Per bank write bursts +system.physmem.perBankWrBursts::3 5901 # Per bank write bursts +system.physmem.perBankWrBursts::4 6273 # Per bank write bursts +system.physmem.perBankWrBursts::5 6263 # Per bank write bursts +system.physmem.perBankWrBursts::6 6069 # Per bank write bursts +system.physmem.perBankWrBursts::7 5534 # Per bank write bursts +system.physmem.perBankWrBursts::8 5815 # Per bank write bursts +system.physmem.perBankWrBursts::9 5920 # Per bank write bursts +system.physmem.perBankWrBursts::10 5985 # Per bank write bursts +system.physmem.perBankWrBursts::11 6510 # Per bank write bursts +system.physmem.perBankWrBursts::12 6360 # Per bank write bursts +system.physmem.perBankWrBursts::13 6344 # Per bank write bursts +system.physmem.perBankWrBursts::14 6013 # Per bank write bursts +system.physmem.perBankWrBursts::15 6102 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 366439104000 # Total gap between requests +system.physmem.totGap 366631694000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 143881 # Read request sizes (log2) +system.physmem.readPktSize::6 144269 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97182 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143447 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 307 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97528 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -145,34 +145,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5629 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -194,118 +194,106 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65604 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 235.015914 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.088937 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.071665 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24900 37.96% 37.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18453 28.13% 66.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7121 10.85% 76.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7867 11.99% 88.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1977 3.01% 91.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1093 1.67% 93.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 809 1.23% 94.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 630 0.96% 95.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2754 4.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65604 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5611 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.620745 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 380.610137 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5609 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 63306 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 244.314283 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.017060 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 244.594379 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22538 35.60% 35.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17961 28.37% 63.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7327 11.57% 75.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7996 12.63% 88.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2051 3.24% 91.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1180 1.86% 93.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 835 1.32% 94.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 660 1.04% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2758 4.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63306 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5727 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.172342 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 18.597400 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 376.088417 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5724 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5611 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5611 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.314204 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.219748 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.335766 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2654 47.30% 47.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2805 49.99% 97.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 62 1.10% 98.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 24 0.43% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 17 0.30% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 10 0.18% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 10 0.18% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 10 0.18% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 2 0.04% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 4 0.07% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 2 0.04% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 2 0.04% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::62-63 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::98-99 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5611 # Writes before turning the bus around for reads -system.physmem.totQLat 1554447250 # Total ticks spent queuing -system.physmem.totMemAccLat 4250153500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 718855000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10811.97 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5727 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5727 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.024795 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.995243 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.004050 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2743 47.90% 47.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 142 2.48% 50.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 2814 49.14% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 20 0.35% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 6 0.10% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5727 # Writes before turning the bus around for reads +system.physmem.totQLat 1581653750 # Total ticks spent queuing +system.physmem.totMemAccLat 4284785000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 720835000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10970.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29561.97 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.11 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 16.97 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.13 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 16.97 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29720.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 17.02 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.18 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 17.02 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.60 # Average write queue length when enqueuing -system.physmem.readRowHits 110522 # Number of row buffer hits during reads -system.physmem.writeRowHits 64789 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.87 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.67 # Row buffer hit rate for writes -system.physmem.avgGap 1520096.84 # Average gap between requests -system.physmem.pageHitRate 72.76 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 249842880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 136323000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 559080600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 312783120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 23933850720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47987220420 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 177768013500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 250947114240 # Total energy per rank (pJ) -system.physmem_0.averagePower 684.830589 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 295423376000 # Time in different power states -system.physmem_0.memoryStateTime::REF 12236120000 # Time in different power states +system.physmem.avgWrQLen 20.20 # Average write queue length when enqueuing +system.physmem.readRowHits 110439 # Number of row buffer hits during reads +system.physmem.writeRowHits 67921 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 69.64 # Row buffer hit rate for writes +system.physmem.avgGap 1516278.92 # Average gap between requests +system.physmem.pageHitRate 73.80 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 239652000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 130762500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 560266200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 313968960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23946564720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47282173740 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 178503263250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 250976651370 # Total energy per rank (pJ) +system.physmem_0.averagePower 684.547573 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 296644648000 # Time in different power states +system.physmem_0.memoryStateTime::REF 12242620000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 58777294250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 57744168750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 246017520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 134235750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 562114800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 316645200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 23933850720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 47395195335 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 178287321750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 250875381075 # Total energy per rank (pJ) -system.physmem_1.averagePower 684.634868 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 296291389000 # Time in different power states -system.physmem_1.memoryStateTime::REF 12236120000 # Time in different power states +system.physmem_1.actEnergy 238941360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 130374750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 564213000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 317837520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 23946564720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 47121480765 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 178644216000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 250963628115 # Total energy per rank (pJ) +system.physmem_1.averagePower 684.512070 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 296880094250 # Time in different power states +system.physmem_1.memoryStateTime::REF 12242620000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 57909758500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 57508713250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 132103761 # Number of BP lookups -system.cpu.branchPred.condPredicted 98193255 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5910050 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68601566 # Number of BTB lookups -system.cpu.branchPred.BTBHits 60590451 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 132103795 # Number of BP lookups +system.cpu.branchPred.condPredicted 98193288 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5910048 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68601542 # Number of BTB lookups +system.cpu.branchPred.BTBHits 60590460 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.322256 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 88.322300 # BTB Hit Percentage system.cpu.branchPred.usedRAS 10017120 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 18743 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3891572 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 3891574 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 3883027 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 8545 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 8547 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 54138 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -335,7 +323,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -365,7 +353,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -395,7 +383,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -426,16 +414,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 366439129500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 732878259 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 733263439 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506579366 # Number of instructions committed system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed -system.cpu.discardedOps 12939743 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 12939754 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.446720 # CPI: cycles per instruction -system.cpu.ipc 0.691219 # IPC: instructions per cycle +system.cpu.cpi 1.447480 # CPI: cycles per instruction +system.cpu.ipc 0.690856 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction system.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction @@ -471,29 +459,29 @@ system.cpu.op_class_0::MemWrite 56860222 10.36% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 548692589 # Class of committed instruction -system.cpu.tickCycles 694071941 # Number of cycles that the object actually ticked -system.cpu.idleCycles 38806318 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 694072576 # Number of cycles that the object actually ticked +system.cpu.idleCycles 39190863 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1141337 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.313641 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171083825 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4070.301946 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171083822 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1145433 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.361704 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5033914500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.313641 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993729 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993729 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 149.361702 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5036525500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.301946 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993726 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993726 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 549 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3501 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346338115 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346338115 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 114566020 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114566020 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 346338109 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346338109 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 114566017 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114566017 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53537929 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 53537929 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 2794 # number of SoftPFReq hits @@ -502,10 +490,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168103949 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168103949 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168106743 # number of overall hits -system.cpu.dcache.overall_hits::total 168106743 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168103946 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168103946 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168106740 # number of overall hits +system.cpu.dcache.overall_hits::total 168106740 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 811381 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 811381 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 701120 # number of WriteReq misses @@ -516,16 +504,16 @@ system.cpu.dcache.demand_misses::cpu.data 1512501 # n system.cpu.dcache.demand_misses::total 1512501 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1512516 # number of overall misses system.cpu.dcache.overall_misses::total 1512516 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13462011000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13462011000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21943272000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21943272000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35405283000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35405283000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35405283000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35405283000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115377401 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115377401 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13515584500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13515584500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22200332500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22200332500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35715917000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35715917000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35715917000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35715917000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115377398 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115377398 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2809 # number of SoftPFReq accesses(hits+misses) @@ -534,10 +522,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169616450 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169616450 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169619259 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169619259 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 169616447 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169616447 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169619256 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169619256 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007032 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007032 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012926 # miss rate for WriteReq accesses @@ -548,22 +536,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008917 system.cpu.dcache.demand_miss_rate::total 0.008917 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008917 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.008917 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16591.479219 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16591.479219 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31297.455500 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31297.455500 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23408.436094 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23408.436094 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23408.203946 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23408.203946 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16657.506769 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16657.506769 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31664.098157 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31664.098157 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23613.813809 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23613.813809 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23613.579625 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23613.579625 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1069267 # number of writebacks -system.cpu.dcache.writebacks::total 1069267 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1068942 # number of writebacks +system.cpu.dcache.writebacks::total 1068942 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22348 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 22348 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344732 # number of WriteReq MSHR hits @@ -582,16 +570,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1145421 system.cpu.dcache.demand_mshr_misses::total 1145421 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1145433 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1145433 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12369658000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12369658000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11145800500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11145800500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1093500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1093500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23515458500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23515458500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23516552000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23516552000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12423186500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12423186500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11274063500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11274063500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 942500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 942500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23697250000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23697250000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23698192500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23698192500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006839 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006839 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006571 # mshr miss rate for WriteReq accesses @@ -602,26 +590,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006753 system.cpu.dcache.demand_mshr_miss_rate::total 0.006753 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006753 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15676.984359 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15676.984359 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31274.342851 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31274.342851 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 91125 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 91125 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20529.969767 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20529.969767 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20530.709347 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20530.709347 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15744.824995 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15744.824995 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31634.239930 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31634.239930 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78541.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78541.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20688.681280 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20688.681280 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20689.287370 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20689.287370 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 18175 # number of replacements -system.cpu.icache.tags.tagsinuse 1187.153068 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 199148908 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1187.102530 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 199148962 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 20047 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 9934.100264 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 9934.102958 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1187.153068 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.579665 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.579665 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1187.102530 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.579640 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.579640 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id @@ -629,45 +617,45 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 57 system.cpu.icache.tags.age_task_id_blocks_1024::3 311 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1400 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 398357957 # Number of tag accesses -system.cpu.icache.tags.data_accesses 398357957 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 199148908 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 199148908 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 199148908 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 199148908 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 199148908 # number of overall hits -system.cpu.icache.overall_hits::total 199148908 # number of overall hits +system.cpu.icache.tags.tag_accesses 398358065 # Number of tag accesses +system.cpu.icache.tags.data_accesses 398358065 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 199148962 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 199148962 # 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miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000101 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000101 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22739.387440 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22739.387440 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22739.387440 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22739.387440 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22739.387440 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22739.387440 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23337.008031 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23337.008031 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23337.008031 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23337.008031 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23337.008031 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23337.008031 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -682,89 +670,89 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 20047 system.cpu.icache.demand_mshr_misses::total 20047 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 20047 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 20047 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 435809500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 435809500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 435809500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 435809500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 435809500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 435809500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 447790000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 447790000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 447790000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 447790000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 447790000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 447790000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000101 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21739.387440 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21739.387440 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21739.387440 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21739.387440 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21739.387440 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21739.387440 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 112318 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27616.037174 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1771878 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 143528 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.345173 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 165163715500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23489.264935 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 308.326790 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3818.445449 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.716835 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009409 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.116530 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.842775 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31210 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 318 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4934 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25858 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952454 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 19060134 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 19060134 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 1069267 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 1069267 # number of WritebackDirty hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22337.008031 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22337.008031 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22337.008031 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22337.008031 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22337.008031 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22337.008031 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 112761 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29068.883602 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2174452 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 145529 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.941709 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 101788000000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 134.067060 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.855024 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28626.961519 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.004091 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009395 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.873626 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.887112 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 981 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31589 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 18705497 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18705497 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 1068942 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 1068942 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 17938 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 17938 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 255711 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255711 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17236 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 17236 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 748638 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 748638 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 17236 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1004349 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1021585 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 17236 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1004349 # number of overall hits -system.cpu.l2cache.overall_hits::total 1021585 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 100927 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 100927 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2811 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2811 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 40157 # 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number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 236084500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 236084500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3363607000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3363607000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 236084500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11421132500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11657217000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 236084500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11421132500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11657217000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 1068942 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 1068942 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 17938 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 17938 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 356638 # number of ReadExReq accesses(hits+misses) @@ -779,107 +767,107 @@ system.cpu.l2cache.demand_accesses::total 1165480 # n system.cpu.l2cache.overall_accesses::cpu.inst 20047 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1145433 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 1165480 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282996 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.282996 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140220 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140220 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050909 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050909 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.140220 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.123171 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123464 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140220 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.123171 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123464 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78559.032766 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78559.032766 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79720.028460 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79720.028460 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82343.651169 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82343.651169 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79720.028460 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79636.255706 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79637.892213 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79720.028460 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79636.255706 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79637.892213 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283139 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.283139 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140270 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140270 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.051337 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.051337 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.140270 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.123510 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123798 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140270 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.123510 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123798 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79794.861257 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79794.861257 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83956.081081 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83956.081081 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83064.330518 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83064.330518 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83956.081081 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80730.692292 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80793.552993 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83956.081081 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80730.692292 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80793.552993 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 97182 # number of writebacks -system.cpu.l2cache.writebacks::total 97182 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 97528 # number of writebacks +system.cpu.l2cache.writebacks::total 97528 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 13 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 13 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100927 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100927 # number of ReadExReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100978 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100978 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2810 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2810 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40144 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40144 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40481 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40481 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2810 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 141071 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 143881 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 141459 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 144269 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2810 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 141071 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 143881 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6919457500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6919457500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 195753000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 195753000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2904162000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2904162000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195753000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9823619500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10019372500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195753000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9823619500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10019372500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282996 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282996 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141459 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 144269 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7047745500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7047745500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 207624000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 207624000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2957433000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2957433000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 207624000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10005178500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10212802500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 207624000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10005178500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10212802500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283139 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283139 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140171 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050893 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050893 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.051320 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.051320 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123160 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123452 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123785 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123160 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123452 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68559.032766 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68559.032766 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69662.989324 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69662.989324 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72343.612993 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72343.612993 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69662.989324 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69635.995350 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69636.522543 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69662.989324 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69635.995350 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69636.522543 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123785 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69794.861257 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69794.861257 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73887.544484 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73887.544484 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73057.310837 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73057.310837 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73887.544484 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70728.469026 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70789.999931 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73887.544484 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70728.469026 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70789.999931 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 2324992 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159582 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4996 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2610 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2607 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2618 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2615 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 808842 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1166449 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1166470 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 18175 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 87206 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 87628 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 356638 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 356638 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 20047 # Transaction distribution @@ -888,53 +876,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432203 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 3490472 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2446208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141740800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 144187008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 112318 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6219648 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1277798 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.006010 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.077318 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141720000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 144166208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 112761 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6241792 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1278241 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.006014 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.077345 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1270122 99.40% 99.40% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 7673 0.60% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1270557 99.40% 99.40% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 7681 0.60% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1277798 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2249938000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1278241 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2249613000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 30093953 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 30094452 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1718157484 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1718157983 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 42954 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97182 # Transaction distribution -system.membus.trans_dist::CleanEvict 12526 # Transaction distribution -system.membus.trans_dist::ReadExReq 100927 # Transaction distribution -system.membus.trans_dist::ReadExResp 100927 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 42954 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397470 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 397470 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15428032 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15428032 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 254412 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 110315 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 43291 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97528 # Transaction distribution +system.membus.trans_dist::CleanEvict 12615 # Transaction distribution +system.membus.trans_dist::ReadExReq 100978 # Transaction distribution +system.membus.trans_dist::ReadExResp 100978 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 43291 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398681 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 398681 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15475008 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15475008 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 253589 # Request fanout histogram +system.membus.snoop_fanout::samples 144269 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 253589 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 144269 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 253589 # Request fanout histogram -system.membus.reqLayer0.occupancy 685523500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 144269 # Request fanout histogram +system.membus.reqLayer0.occupancy 685129000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 763755750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 765930250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index d31d95a5e..f10b69af3 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.232865 # Number of seconds simulated -sim_ticks 232864525000 # Number of ticks simulated -final_tick 232864525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233363 # Number of seconds simulated +sim_ticks 233363457000 # Number of ticks simulated +final_tick 233363457000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 208842 # Simulator instruction rate (inst/s) -host_op_rate 226249 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 96255881 # Simulator tick rate (ticks/s) -host_mem_usage 295820 # Number of bytes of host memory used -host_seconds 2419.22 # Real time elapsed on the host +host_inst_rate 153279 # Simulator instruction rate (inst/s) +host_op_rate 166055 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 70798116 # Simulator tick rate (ticks/s) +host_mem_usage 302508 # Number of bytes of host memory used +host_seconds 3296.18 # Real time elapsed on the host sim_insts 505234934 # Number of instructions simulated sim_ops 547348155 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 523840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10146304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16460800 # Number of bytes read from this memory -system.physmem.bytes_read::total 27130944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 523840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 523840 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18710656 # Number of bytes written to this memory -system.physmem.bytes_written::total 18710656 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8185 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158536 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 257200 # Number of read requests responded to by this memory -system.physmem.num_reads::total 423921 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292354 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292354 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2249548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 43571703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 70688311 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 116509563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2249548 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2249548 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 80349963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 80349963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 80349963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2249548 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 43571703 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 70688311 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 196859526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 423921 # Number of read requests accepted -system.physmem.writeReqs 292354 # Number of write requests accepted -system.physmem.readBursts 423921 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292354 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26979136 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 151808 # Total number of bytes read from write queue -system.physmem.bytesWritten 18708352 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 27130944 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18710656 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2372 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 641792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10513600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16409344 # Number of bytes read from this memory +system.physmem.bytes_read::total 27564736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 641792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 641792 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18651328 # Number of bytes written to this memory +system.physmem.bytes_written::total 18651328 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10028 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 164275 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 256396 # Number of read requests responded to by this memory +system.physmem.num_reads::total 430699 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 291427 # Number of write requests responded to by this memory +system.physmem.num_writes::total 291427 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2750182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 45052469 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 70316682 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 118119333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2750182 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2750182 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 79923945 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 79923945 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 79923945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2750182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 45052469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 70316682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 198043278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 430699 # Number of read requests accepted +system.physmem.writeReqs 291427 # Number of write requests accepted +system.physmem.readBursts 430699 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 291427 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27407296 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 157440 # Total number of bytes read from write queue +system.physmem.bytesWritten 18649728 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27564736 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18651328 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2460 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26585 # Per bank write bursts -system.physmem.perBankRdBursts::1 25966 # Per bank write bursts -system.physmem.perBankRdBursts::2 25309 # Per bank write bursts -system.physmem.perBankRdBursts::3 32108 # Per bank write bursts -system.physmem.perBankRdBursts::4 27451 # Per bank write bursts -system.physmem.perBankRdBursts::5 28247 # Per bank write bursts -system.physmem.perBankRdBursts::6 25115 # Per bank write bursts -system.physmem.perBankRdBursts::7 24228 # Per bank write bursts -system.physmem.perBankRdBursts::8 25496 # Per bank write bursts -system.physmem.perBankRdBursts::9 25694 # Per bank write bursts -system.physmem.perBankRdBursts::10 25307 # Per bank write bursts -system.physmem.perBankRdBursts::11 26044 # Per bank write bursts -system.physmem.perBankRdBursts::12 27396 # Per bank write bursts -system.physmem.perBankRdBursts::13 26024 # Per bank write bursts -system.physmem.perBankRdBursts::14 24983 # Per bank write bursts -system.physmem.perBankRdBursts::15 25596 # Per bank write bursts -system.physmem.perBankWrBursts::0 18605 # Per bank write bursts -system.physmem.perBankWrBursts::1 18353 # Per bank write bursts -system.physmem.perBankWrBursts::2 18036 # Per bank write bursts -system.physmem.perBankWrBursts::3 17927 # Per bank write bursts -system.physmem.perBankWrBursts::4 18566 # Per bank write bursts -system.physmem.perBankWrBursts::5 18339 # Per bank write bursts -system.physmem.perBankWrBursts::6 17904 # Per bank write bursts -system.physmem.perBankWrBursts::7 17705 # Per bank write bursts -system.physmem.perBankWrBursts::8 17878 # Per bank write bursts -system.physmem.perBankWrBursts::9 17947 # Per bank write bursts -system.physmem.perBankWrBursts::10 18182 # Per bank write bursts -system.physmem.perBankWrBursts::11 18731 # Per bank write bursts -system.physmem.perBankWrBursts::12 18803 # Per bank write bursts -system.physmem.perBankWrBursts::13 18363 # Per bank write bursts -system.physmem.perBankWrBursts::14 18474 # Per bank write bursts -system.physmem.perBankWrBursts::15 18505 # Per bank write bursts +system.physmem.perBankRdBursts::0 27205 # Per bank write bursts +system.physmem.perBankRdBursts::1 26463 # Per bank write bursts +system.physmem.perBankRdBursts::2 25602 # Per bank write bursts +system.physmem.perBankRdBursts::3 32969 # Per bank write bursts +system.physmem.perBankRdBursts::4 28037 # Per bank write bursts +system.physmem.perBankRdBursts::5 29890 # Per bank write bursts +system.physmem.perBankRdBursts::6 25340 # Per bank write bursts +system.physmem.perBankRdBursts::7 24398 # Per bank write bursts +system.physmem.perBankRdBursts::8 25649 # Per bank write bursts +system.physmem.perBankRdBursts::9 25581 # Per bank write bursts +system.physmem.perBankRdBursts::10 25884 # Per bank write bursts +system.physmem.perBankRdBursts::11 26303 # Per bank write bursts +system.physmem.perBankRdBursts::12 27555 # Per bank write bursts +system.physmem.perBankRdBursts::13 26148 # Per bank write bursts +system.physmem.perBankRdBursts::14 24908 # Per bank write bursts +system.physmem.perBankRdBursts::15 26307 # Per bank write bursts +system.physmem.perBankWrBursts::0 18644 # Per bank write bursts +system.physmem.perBankWrBursts::1 18139 # Per bank write bursts +system.physmem.perBankWrBursts::2 17950 # Per bank write bursts +system.physmem.perBankWrBursts::3 17944 # Per bank write bursts +system.physmem.perBankWrBursts::4 18581 # Per bank write bursts +system.physmem.perBankWrBursts::5 18235 # Per bank write bursts +system.physmem.perBankWrBursts::6 17841 # Per bank write bursts +system.physmem.perBankWrBursts::7 17708 # Per bank write bursts +system.physmem.perBankWrBursts::8 18005 # Per bank write bursts +system.physmem.perBankWrBursts::9 17734 # Per bank write bursts +system.physmem.perBankWrBursts::10 18244 # Per bank write bursts +system.physmem.perBankWrBursts::11 18783 # Per bank write bursts +system.physmem.perBankWrBursts::12 18680 # Per bank write bursts +system.physmem.perBankWrBursts::13 18156 # Per bank write bursts +system.physmem.perBankWrBursts::14 18369 # Per bank write bursts +system.physmem.perBankWrBursts::15 18389 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 232864472500 # Total gap between requests +system.physmem.totGap 233363404500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 423921 # Read request sizes (log2) +system.physmem.readPktSize::6 430699 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292354 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 324214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 49387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8884 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3284 # What read queue length does an incoming req see +system.physmem.writePktSize::6 291427 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 330391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 50226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12856 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8880 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6027 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4235 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3274 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 56 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -149,41 +149,41 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 7265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 15014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 18097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 19016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 7280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16901 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see @@ -198,118 +198,117 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 322606 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 141.616907 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 99.575706 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 179.865264 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 203481 63.07% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 79249 24.57% 87.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15283 4.74% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7278 2.26% 94.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4895 1.52% 96.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2519 0.78% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1928 0.60% 97.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1485 0.46% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6488 2.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 322606 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17068 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.693051 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 142.945620 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17066 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 328347 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 140.266048 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 98.833830 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 178.808988 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 208753 63.58% 63.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 80037 24.38% 87.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14980 4.56% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7256 2.21% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4857 1.48% 96.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2521 0.77% 96.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1858 0.57% 97.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1524 0.46% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6561 2.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 328347 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 16970 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.230642 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 145.328941 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 16968 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17068 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17068 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.126670 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.068877 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.479655 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 9203 53.92% 53.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 342 2.00% 55.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5412 31.71% 87.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1340 7.85% 95.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 381 2.23% 97.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 185 1.08% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 84 0.49% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 48 0.28% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 28 0.16% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 13 0.08% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 9 0.05% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 6 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 6 0.04% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 3 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17068 # Writes before turning the bus around for reads -system.physmem.totQLat 8669198966 # Total ticks spent queuing -system.physmem.totMemAccLat 16573242716 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2107745000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20565.10 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 16970 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 16970 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.171597 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.099419 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.840930 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 9436 55.60% 55.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 6694 39.45% 95.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 588 3.46% 98.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 150 0.88% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 55 0.32% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 20 0.12% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 4 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 8 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 2 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 4 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62-63 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-73 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-77 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::94-95 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 16970 # Writes before turning the bus around for reads +system.physmem.totQLat 8687632010 # Total ticks spent queuing +system.physmem.totMemAccLat 16717113260 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2141195000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20286.88 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39315.10 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 115.86 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 80.34 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 116.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 80.35 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39036.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 117.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 79.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 118.12 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 79.92 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.53 # Data bus utilization in percentage -system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes +system.physmem.busUtil 1.54 # Data bus utilization in percentage +system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.62 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.66 # Average write queue length when enqueuing -system.physmem.readRowHits 306141 # Number of row buffer hits during reads -system.physmem.writeRowHits 85116 # Number of row buffer hits during writes -system.physmem.readRowHitRate 72.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 29.11 # Row buffer hit rate for writes -system.physmem.avgGap 325104.84 # Average gap between requests -system.physmem.pageHitRate 54.81 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1231478640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 671937750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1677023400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 942418800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15209503920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 82038252060 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 67754804250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 169525418820 # Total energy per rank (pJ) -system.physmem_0.averagePower 728.002962 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 112181922825 # Time in different power states -system.physmem_0.memoryStateTime::REF 7775820000 # Time in different power states +system.physmem.avgWrQLen 21.52 # Average write queue length when enqueuing +system.physmem.readRowHits 308039 # Number of row buffer hits during reads +system.physmem.writeRowHits 83248 # Number of row buffer hits during writes +system.physmem.readRowHitRate 71.93 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 28.57 # Row buffer hit rate for writes +system.physmem.avgGap 323161.62 # Average gap between requests +system.physmem.pageHitRate 54.37 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1261242360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 688177875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1715142000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 939872160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15242051760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 86511761685 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 64129665000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 170487912840 # Total energy per rank (pJ) +system.physmem_0.averagePower 730.572857 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 106127593352 # Time in different power states +system.physmem_0.memoryStateTime::REF 7792460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 112906030175 # Time in different power states +system.physmem_0.memoryStateTime::ACT 119441919148 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1207422720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 658812000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1610934000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 951801840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15209503920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 78953270130 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 70460943000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 169052687610 # Total energy per rank (pJ) -system.physmem_1.averagePower 725.972811 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 116702858630 # Time in different power states -system.physmem_1.memoryStateTime::REF 7775820000 # Time in different power states +system.physmem_1.actEnergy 1221045840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 666245250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1624857000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 948412800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15242051760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 81485025165 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 68539083000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 169726720815 # Total energy per rank (pJ) +system.physmem_1.averagePower 727.311005 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 113492657633 # Time in different power states +system.physmem_1.memoryStateTime::REF 7792460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 108384997620 # Time in different power states +system.physmem_1.memoryStateTime::ACT 112077139867 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 174583649 # Number of BP lookups -system.cpu.branchPred.condPredicted 131051926 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7234327 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90400017 # Number of BTB lookups -system.cpu.branchPred.BTBHits 79003628 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 174594135 # Number of BP lookups +system.cpu.branchPred.condPredicted 131061438 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7233022 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90315091 # Number of BTB lookups +system.cpu.branchPred.BTBHits 79002409 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.393377 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12104831 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104507 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 4687804 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 4673781 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 14023 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 53864 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 87.474206 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12105110 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104499 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 4687937 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 4674274 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 13663 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 53871 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -339,7 +338,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -369,7 +368,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -399,7 +398,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -430,233 +429,233 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 465729051 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 466726915 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7627967 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 727492581 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174583649 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95782240 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 450186491 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14522705 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 4278 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 141 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 13015 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 235271545 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 36405 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 465093244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.693494 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.182412 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7649319 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 727510991 # Number of instructions fetch has processed +system.cpu.fetch.Branches 174594135 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95781793 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 451018276 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14520177 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5415 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 146 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 13360 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 235275678 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 36827 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 465946604 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.690437 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.183518 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95400849 20.51% 20.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132044062 28.39% 48.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57356261 12.33% 61.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 180292072 38.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 96241342 20.66% 20.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132050994 28.34% 49.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57360477 12.31% 61.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 180293791 38.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 465093244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.374861 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.562051 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32522816 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 120066297 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 282921194 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22809829 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6773108 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 23856996 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 495879 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 710982293 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29095211 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6773108 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63338503 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 55962062 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40377047 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 273519607 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 25122917 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 682713266 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 12851705 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 9930975 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2510705 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1794472 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1920747 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 827509638 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3000483792 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 718633951 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 465946604 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.374082 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.558751 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32536552 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 120918293 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 282902203 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22817634 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6771922 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 23855471 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 495849 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 710960604 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29091371 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6771922 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63349282 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 56784032 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40401553 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 273510163 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 25129652 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 682692967 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 12844145 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9945202 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2511648 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1805093 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1905777 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 827472920 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3000392013 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 718609980 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 96 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654095674 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 173413964 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1545834 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1536299 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 43818789 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 142365669 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67523427 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12892964 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11349045 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 664768510 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2979350 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608926727 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5749477 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 120399705 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 306541324 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1718 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 465093244 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.309257 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.101839 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 173377246 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1545812 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1536134 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 43839802 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 142358029 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67522859 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12902461 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11335768 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 664750936 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2979334 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608926553 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5748894 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 120382115 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 306467952 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1702 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 465946604 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.306859 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.102130 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 148683316 31.97% 31.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 100887288 21.69% 53.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 145497620 31.28% 84.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63056493 13.56% 98.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6967915 1.50% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 612 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 149520607 32.09% 32.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 100880237 21.65% 53.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145552540 31.24% 84.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63032249 13.53% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6960366 1.49% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 605 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 465093244 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 465946604 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71909518 53.13% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44304480 32.74% 85.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19119642 14.13% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71896734 53.12% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44291867 32.73% 85.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19147796 14.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 412592470 67.76% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 352106 0.06% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 133579374 21.94% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62402774 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 412590919 67.76% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 352109 0.06% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 133574983 21.94% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62408539 10.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608926727 # Type of FU issued -system.cpu.iq.rate 1.307470 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135333670 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.222250 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1824029756 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 788176792 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594203276 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 89 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 608926553 # Type of FU issued +system.cpu.iq.rate 1.304674 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135336427 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222254 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1824884935 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 788141663 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594200588 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 96 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 76 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 744260342 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 55 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7285470 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 744262920 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 60 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 7284479 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 26482386 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24610 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29757 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10663207 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 26474746 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24624 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29798 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10662639 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 225824 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 22615 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 225013 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 22508 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6773108 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22711376 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 916891 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 669240779 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6771922 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22843049 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 918168 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 669223084 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 142365669 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67523427 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1490808 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 256518 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 523375 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29757 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3591194 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3743418 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7334612 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 598426944 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129087025 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10499783 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 142358029 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67522859 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1490792 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 256633 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 523882 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29798 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3590923 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3742651 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7333574 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 598420503 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129081054 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10506050 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1492919 # number of nop insts executed -system.cpu.iew.exec_refs 190006687 # number of memory reference insts executed -system.cpu.iew.exec_branches 131263664 # Number of branches executed -system.cpu.iew.exec_stores 60919662 # Number of stores executed -system.cpu.iew.exec_rate 1.284925 # Inst execution rate -system.cpu.iew.wb_sent 595449226 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594203292 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349565798 # num instructions producing a value -system.cpu.iew.wb_consumers 571378084 # num instructions consuming a value -system.cpu.iew.wb_rate 1.275856 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611794 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 107129246 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1492814 # number of nop insts executed +system.cpu.iew.exec_refs 190002009 # number of memory reference insts executed +system.cpu.iew.exec_branches 131263961 # Number of branches executed +system.cpu.iew.exec_stores 60920955 # Number of stores executed +system.cpu.iew.exec_rate 1.282164 # Inst execution rate +system.cpu.iew.wb_sent 595445456 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594200604 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349565575 # num instructions producing a value +system.cpu.iew.wb_consumers 571385188 # num instructions consuming a value +system.cpu.iew.wb_rate 1.273123 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611786 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 107116116 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6746083 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 448430808 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.223582 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.891618 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6744856 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 449285999 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.221253 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.890713 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 219662042 48.98% 48.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116371870 25.95% 74.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43476650 9.70% 84.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23164070 5.17% 89.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11528126 2.57% 92.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7755918 1.73% 94.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8275201 1.85% 95.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4244089 0.95% 96.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13952842 3.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 220514428 49.08% 49.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116376748 25.90% 74.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43480691 9.68% 84.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23177999 5.16% 89.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11514242 2.56% 92.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7755129 1.73% 94.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8259802 1.84% 95.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4227193 0.94% 96.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13979767 3.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 448430808 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 449285999 # Number of insts commited each cycle system.cpu.commit.committedInsts 506578818 # Number of instructions committed system.cpu.commit.committedOps 548692039 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -702,555 +701,560 @@ system.cpu.commit.op_class_0::MemWrite 56860220 10.36% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction -system.cpu.commit.bw_lim_events 13952842 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1090292113 # The number of ROB reads -system.cpu.rob.rob_writes 1328334369 # The number of ROB writes -system.cpu.timesIdled 12786 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 635807 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 13979767 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1091107249 # The number of ROB reads +system.cpu.rob.rob_writes 1328306301 # The number of ROB writes +system.cpu.timesIdled 14326 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 780311 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505234934 # Number of Instructions Simulated system.cpu.committedOps 547348155 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.921807 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.921807 # CPI: Total CPI of All Threads -system.cpu.ipc 1.084826 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.084826 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 610135542 # number of integer regfile reads -system.cpu.int_regfile_writes 327337405 # number of integer regfile writes +system.cpu.cpi 0.923782 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.923782 # CPI: Total CPI of All Threads +system.cpu.ipc 1.082507 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.082507 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 610129735 # number of integer regfile reads +system.cpu.int_regfile_writes 327331512 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2166261838 # number of cc regfile reads -system.cpu.cc_regfile_writes 376539611 # number of cc regfile writes -system.cpu.misc_regfile_reads 217603179 # number of misc regfile reads +system.cpu.cc_regfile_reads 2166233884 # number of cc regfile reads +system.cpu.cc_regfile_writes 376536291 # number of cc regfile writes +system.cpu.misc_regfile_reads 217601523 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2817145 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.627957 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168870791 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2817657 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 59.933055 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 500883000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.627957 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999273 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999273 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2817306 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.628303 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168866082 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2817818 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 59.927959 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 501259000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.628303 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999274 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999274 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 280 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 355267161 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 355267161 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 114168570 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114168570 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51722271 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51722271 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2788 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2788 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 355259202 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 355259202 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 114162091 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114162091 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51724043 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51724043 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2789 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2789 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 165890841 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 165890841 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 165893629 # number of overall hits -system.cpu.dcache.overall_hits::total 165893629 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4837166 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4837166 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2516778 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2516778 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 165886134 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 165886134 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 165888923 # number of overall hits +system.cpu.dcache.overall_hits::total 165888923 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4839586 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4839586 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2515006 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2515006 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 10 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 10 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7353944 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7353944 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7353956 # number of overall misses -system.cpu.dcache.overall_misses::total 7353956 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57478265500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57478265500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18947607428 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18947607428 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1052500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1052500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 76425872928 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 76425872928 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 76425872928 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 76425872928 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119005736 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119005736 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7354592 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7354592 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7354602 # number of overall misses +system.cpu.dcache.overall_misses::total 7354602 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58596122500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58596122500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18922626430 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18922626430 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1155000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1155000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 77518748930 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 77518748930 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 77518748930 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 77518748930 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119001677 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119001677 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2800 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2800 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2799 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2799 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173244785 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173244785 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173247585 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173247585 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040646 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040646 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046402 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046402 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004286 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.004286 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 173240726 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173240726 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173243525 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173243525 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040668 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040668 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046369 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046369 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003573 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.003573 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.042448 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.042448 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042448 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042448 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11882.632413 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11882.632413 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7528.517584 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7528.517584 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15946.969697 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15946.969697 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10392.501347 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10392.501347 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10392.484389 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10392.484389 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 916660 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 221191 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.200000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 4.144201 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2817145 # number of writebacks -system.cpu.dcache.writebacks::total 2817145 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2539309 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2539309 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996958 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1996958 # number of WriteReq MSHR hits +system.cpu.dcache.demand_miss_rate::cpu.data 0.042453 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042453 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042452 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042452 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12107.672536 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12107.672536 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7523.889180 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7523.889180 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10540.183457 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10540.183457 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10540.169125 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10540.169125 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 907373 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 221320 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.099824 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2817306 # number of writebacks +system.cpu.dcache.writebacks::total 2817306 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2541564 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2541564 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1995189 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1995189 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4536267 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4536267 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4536267 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4536267 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2297857 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2297857 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519820 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519820 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2817677 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2817677 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2817687 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2817687 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29541351500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29541351500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4603156994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4603156994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 669500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 669500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34144508494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 34144508494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34145177994 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 34145177994 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019309 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019309 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 4536753 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4536753 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4536753 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4536753 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2298022 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2298022 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519817 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519817 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 9 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 9 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2817839 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2817839 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2817848 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2817848 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30115234500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30115234500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4603448995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4603448995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 602500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 602500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34718683495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 34718683495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34719285995 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 34719285995 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019311 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019311 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009584 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009584 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003571 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003571 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016264 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016264 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12856.044349 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12856.044349 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8855.290281 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8855.290281 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 66950 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 66950 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12117.964016 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12117.964016 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12118.158615 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12118.158615 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 76528 # number of replacements -system.cpu.icache.tags.tagsinuse 466.435319 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 235186472 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 77040 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3052.783904 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 115558244500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 466.435319 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.911006 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.911006 # Average percentage of cache occupancy +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003215 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003215 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016265 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016265 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016265 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016265 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13104.850389 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13104.850389 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8855.903126 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8855.903126 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 66944.444444 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 66944.444444 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12321.031647 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12321.031647 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12321.206110 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12321.206110 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 76636 # number of replacements +system.cpu.icache.tags.tagsinuse 466.486924 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 235189788 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 77148 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3048.553274 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 115712400500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 466.486924 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.911107 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.911107 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 470619957 # Number of tag accesses -system.cpu.icache.tags.data_accesses 470619957 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 235186472 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 235186472 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 235186472 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 235186472 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 235186472 # number of overall hits -system.cpu.icache.overall_hits::total 235186472 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 84972 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 84972 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 84972 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 84972 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 84972 # number of overall misses -system.cpu.icache.overall_misses::total 84972 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1359599197 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1359599197 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1359599197 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1359599197 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1359599197 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1359599197 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 235271444 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 235271444 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 235271444 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 235271444 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 235271444 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 235271444 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000361 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000361 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000361 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000361 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000361 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000361 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16000.555442 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16000.555442 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16000.555442 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16000.555442 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16000.555442 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16000.555442 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 161540 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 362 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6762 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 23.889382 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 60.333333 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 76528 # number of writebacks -system.cpu.icache.writebacks::total 76528 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7901 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 7901 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 7901 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 7901 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 7901 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 7901 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77071 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 77071 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 77071 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 77071 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 77071 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 77071 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1127867788 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1127867788 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1127867788 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1127867788 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1127867788 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1127867788 # number of overall MSHR miss cycles +system.cpu.icache.tags.tag_accesses 470628332 # Number of tag accesses +system.cpu.icache.tags.data_accesses 470628332 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 235189788 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 235189788 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 235189788 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 235189788 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 235189788 # number of overall hits +system.cpu.icache.overall_hits::total 235189788 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 85789 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 85789 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 85789 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 85789 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 85789 # number of overall misses +system.cpu.icache.overall_misses::total 85789 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1556704687 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1556704687 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1556704687 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1556704687 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1556704687 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1556704687 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 235275577 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 235275577 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 235275577 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 235275577 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 235275577 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 235275577 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000365 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000365 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000365 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000365 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000365 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000365 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18145.737647 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18145.737647 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18145.737647 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18145.737647 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18145.737647 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18145.737647 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 171831 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 200 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6857 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 25.059210 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 50 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 76636 # number of writebacks +system.cpu.icache.writebacks::total 76636 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8610 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 8610 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 8610 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 8610 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 8610 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 8610 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77179 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 77179 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 77179 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 77179 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 77179 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 77179 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1268632793 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1268632793 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1268632793 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1268632793 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1268632793 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1268632793 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000328 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000328 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000328 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14634.139793 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14634.139793 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 8513492 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 8514887 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 402 # number of redundant prefetches already in prefetch queue +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16437.538618 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16437.538618 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16437.538618 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16437.538618 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16437.538618 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16437.538618 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 8513734 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 8515093 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 374 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 743841 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 395630 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15127.357564 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3184940 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 411561 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.738683 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 169696310500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 13778.300526 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 0.000101 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1349.056936 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.840961 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.082340 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.923301 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 1053 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 14878 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 34 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 239 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 778 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4895 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6342 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3283 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.064270 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908081 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 94885258 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 94885258 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2350571 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2350571 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 519224 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 519224 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 516915 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 516915 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 68843 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 68843 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2136682 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 2136682 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 68843 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2653597 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2722440 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 68843 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2653597 # number of overall hits -system.cpu.l2cache.overall_hits::total 2722440 # number of overall hits +system.cpu.l2cache.prefetcher.pfSpanPage 743899 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 390403 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15000.108571 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2699085 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 406018 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.647698 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14926.062493 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 74.046079 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.911015 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004519 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.915534 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 114 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15501 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30384071193 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3662 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3662 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10028 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10028 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 160616 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 160616 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10028 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 164278 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 174306 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10028 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 164278 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 356222 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 530528 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18747915458 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18747915458 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 462000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 462000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 336888000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 336888000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 689794500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 689794500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11439165000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11439165000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 689794500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11776053000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12465847500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 689794500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11776053000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18747915458 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31213762958 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007088 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007088 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.106248 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.106248 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.067449 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.067449 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.106248 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056266 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.057596 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.106248 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056266 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007015 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007015 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.129991 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.129991 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069961 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069961 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.129991 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058300 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060210 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.129991 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058300 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.178797 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53136.776573 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14650 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14650 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89883.243243 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89883.243243 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66851.130116 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66851.130116 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70149.575686 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70149.575686 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66851.130116 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70610.125017 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70425.583153 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66851.130116 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70610.125017 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58706.034228 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5788431 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893715 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 261080 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244791 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16289 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2372715 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2642925 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 543102 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 266298 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 392168 # Transaction distribution +system.cpu.l2cache.overall_mshr_miss_rate::total 0.183259 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 52629.864124 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 52629.864124 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15400 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15400 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91995.630803 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91995.630803 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68786.846829 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68786.846829 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71220.582009 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71220.582009 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68786.846829 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71683.688625 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71517.030395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68786.846829 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71683.688625 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 52629.864124 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58835.279114 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5788969 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893984 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23717 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 99826 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99825 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 2372984 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2645368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 540001 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 98976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 397627 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 30 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 30 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 522011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 522011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 77071 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295646 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230634 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8452520 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8683154 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9828032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360627392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 370455424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 950855 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18712896 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3845578 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.078356 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.284056 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 522012 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 522012 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 77179 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295806 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230958 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8453003 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8683961 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9841856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360648000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 370489856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 788066 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 18653632 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 3683057 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.033555 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.180083 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3560544 92.59% 92.59% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 268745 6.99% 99.58% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 16289 0.42% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3559472 96.64% 96.64% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 123584 3.36% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3845578 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5787888505 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3683057 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5788426505 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 115689827 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 115796940 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4226522955 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4226763956 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 420223 # Transaction distribution -system.membus.trans_dist::WritebackDirty 292354 # Transaction distribution -system.membus.trans_dist::CleanEvict 98859 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33 # Transaction distribution -system.membus.trans_dist::ReadExReq 3697 # Transaction distribution -system.membus.trans_dist::ReadExResp 3697 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 420224 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1239087 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1239087 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45841536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45841536 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 821136 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 414105 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 427040 # Transaction distribution +system.membus.trans_dist::WritebackDirty 291427 # Transaction distribution +system.membus.trans_dist::CleanEvict 98976 # Transaction distribution +system.membus.trans_dist::UpgradeReq 34 # Transaction distribution +system.membus.trans_dist::ReadExReq 3658 # Transaction distribution +system.membus.trans_dist::ReadExResp 3658 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 427041 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1251834 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1251834 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46216000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 46216000 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 815167 # Request fanout histogram +system.membus.snoop_fanout::samples 430733 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 815167 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 430733 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 815167 # Request fanout histogram -system.membus.reqLayer0.occupancy 2211611288 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2242842427 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 430733 # Request fanout histogram +system.membus.reqLayer0.occupancy 2217216132 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 2280002282 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index e8a891fe8..6a67fce1b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.279361 # Nu sim_ticks 279360903000 # Number of ticks simulated final_tick 279360903000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1100009 # Simulator instruction rate (inst/s) -host_op_rate 1191455 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 606617028 # Simulator tick rate (ticks/s) -host_mem_usage 259840 # Number of bytes of host memory used -host_seconds 460.52 # Real time elapsed on the host +host_inst_rate 1206466 # Simulator instruction rate (inst/s) +host_op_rate 1306763 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 665324846 # Simulator tick rate (ticks/s) +host_mem_usage 263448 # Number of bytes of host memory used +host_seconds 419.89 # Real time elapsed on the host sim_insts 506578818 # Number of instructions simulated sim_ops 548692039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,6 +220,12 @@ system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548692589 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 630707528 # Transaction distribution system.membus.trans_dist::ReadResp 632196069 # Transaction distribution @@ -239,14 +245,14 @@ system.membus.pkt_size::total 2705349287 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 687926230 # Request fanout histogram -system.membus.snoop_fanout::mean 0.750965 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.432454 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 171317644 24.90% 24.90% # Request fanout histogram -system.membus.snoop_fanout::1 516608586 75.10% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 687926230 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 687926230 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index a77764c75..9780dac13 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.708539 # Number of seconds simulated -sim_ticks 708539449500 # Number of ticks simulated -final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.708700 # Number of seconds simulated +sim_ticks 708700329500 # Number of ticks simulated +final_tick 708700329500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 665557 # Simulator instruction rate (inst/s) -host_op_rate 720769 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 933837970 # Simulator tick rate (ticks/s) -host_mem_usage 269828 # Number of bytes of host memory used -host_seconds 758.74 # Real time elapsed on the host +host_inst_rate 820539 # Simulator instruction rate (inst/s) +host_op_rate 888607 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1151553403 # Simulator tick rate (ticks/s) +host_mem_usage 275232 # Number of bytes of host memory used +host_seconds 615.43 # Real time elapsed on the host sim_insts 504984064 # Number of instructions simulated sim_ops 546875315 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8963904 # Number of bytes read from this memory -system.physmem.bytes_read::total 9111296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8988096 # Number of bytes read from this memory +system.physmem.bytes_read::total 9135488 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 147392 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 147392 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6165120 # Number of bytes written to this memory -system.physmem.bytes_written::total 6165120 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 6185472 # Number of bytes written to this memory +system.physmem.bytes_written::total 6185472 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2303 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140061 # Number of read requests responded to by this memory -system.physmem.num_reads::total 142364 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96330 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96330 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 208022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12651242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12859264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 208022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 208022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8701167 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8701167 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8701167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 208022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12651242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21560431 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.physmem.num_reads::cpu.data 140439 # Number of read requests responded to by this memory +system.physmem.num_reads::total 142742 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96648 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96648 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 207975 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12682506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12890481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 207975 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 207975 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8727909 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8727909 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8727909 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 207975 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12682506 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21618390 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -69,7 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -99,7 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -129,7 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -160,8 +160,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 708539449500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1417078899 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 708700329500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1417400659 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 504984064 # Number of instructions committed @@ -182,7 +182,7 @@ system.cpu.num_mem_refs 172743505 # nu system.cpu.num_load_insts 115883283 # Number of load instructions system.cpu.num_store_insts 56860222 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1417078898.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1417400658.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 121552863 # Number of branches fetched @@ -221,16 +221,16 @@ system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548692589 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1136276 # number of replacements -system.cpu.dcache.tags.tagsinuse 4065.261181 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4065.253828 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 170177272 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1140372 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 149.229613 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 11750119500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.261181 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992495 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992495 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 11754931500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.253828 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992494 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992494 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id @@ -240,7 +240,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 343775660 # Number of tag accesses system.cpu.dcache.tags.data_accesses 343775660 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 113315079 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 113315079 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53882541 # number of WriteReq hits @@ -265,14 +265,14 @@ system.cpu.dcache.demand_misses::cpu.data 1140371 # n system.cpu.dcache.demand_misses::total 1140371 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1140372 # number of overall misses system.cpu.dcache.overall_misses::total 1140372 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12120585500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12120585500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9577302500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9577302500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 21697888000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 21697888000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 21697888000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 21697888000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12176129500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12176129500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9680337500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9680337500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 21856467000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 21856467000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 21856467000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 21856467000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114098942 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114098942 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) @@ -297,22 +297,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006774 system.cpu.dcache.demand_miss_rate::total 0.006774 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006774 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006774 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15462.632501 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15462.632501 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26864.200803 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26864.200803 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19027.042954 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19027.042954 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19027.026269 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19027.026269 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15533.491822 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15533.491822 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27153.212551 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27153.212551 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19166.102084 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19166.102084 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19166.085277 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19166.085277 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1065708 # number of writebacks -system.cpu.dcache.writebacks::total 1065708 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1065429 # number of writebacks +system.cpu.dcache.writebacks::total 1065429 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783863 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 783863 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356508 # number of WriteReq MSHR misses @@ -323,16 +323,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1140371 system.cpu.dcache.demand_mshr_misses::total 1140371 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1140372 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1140372 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11336722500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11336722500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9220794500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9220794500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20557517000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 20557517000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20557578000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20557578000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11392266500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11392266500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9323829500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9323829500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20716096000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20716096000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20716158000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20716158000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006870 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006870 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006573 # mshr miss rate for WriteReq accesses @@ -343,26 +343,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006774 system.cpu.dcache.demand_mshr_miss_rate::total 0.006774 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006774 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006774 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14462.632501 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14462.632501 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25864.200803 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25864.200803 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14533.491822 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14533.491822 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26153.212551 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26153.212551 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18166.102084 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18166.102084 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18166.140523 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18166.140523 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 9788 # number of replacements -system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 983.167360 # Cycle average of tags in use system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 44839.602986 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 983.198764 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.480078 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.480078 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 983.167360 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.480062 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.480062 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id @@ -372,7 +372,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1033228695 # Number of tag accesses system.cpu.icache.tags.data_accesses 1033228695 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 516597066 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 516597066 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 516597066 # number of demand (read+write) hits @@ -385,12 +385,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 263211000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 263211000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 263211000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 263211000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 263211000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 263211000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 265513000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 265513000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 265513000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 265513000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 265513000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 265513000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 516608587 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 516608587 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 516608587 # number of demand (read+write) accesses @@ -403,12 +403,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22846.193907 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22846.193907 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22846.193907 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22846.193907 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23046.002951 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23046.002951 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23046.002951 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23046.002951 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23046.002951 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23046.002951 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -423,89 +423,89 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521 system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 251690000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 251690000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 251690000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 251690000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 251690000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 251690000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253992000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 253992000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253992000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 253992000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253992000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 253992000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21846.193907 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21846.193907 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 110394 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 141582 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.339245 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 339115608000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23375.830047 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.203585 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3636.053019 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.713374 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007330 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.110964 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.831668 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3657 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27176 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18853226 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18853226 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 1065708 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 1065708 # number of WritebackDirty hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22046.002951 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22046.002951 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22046.002951 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22046.002951 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22046.002951 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22046.002951 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 110813 # number of replacements +system.cpu.l2cache.tags.tagsinuse 28700.010798 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2150809 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 143581 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.979761 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 210357436000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 80.467975 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 239.840136 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28379.702687 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.002456 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007319 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.866080 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.875855 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 661 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31936 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 18498717 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18498717 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 1065429 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 1065429 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 9751 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 9751 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 255720 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255720 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 255675 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 255675 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9218 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 9218 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 744591 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 744591 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 744258 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 744258 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 9218 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1000311 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1009529 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 999933 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1009151 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 9218 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1000311 # number of overall hits -system.cpu.l2cache.overall_hits::total 1009529 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 100788 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 100788 # number of ReadExReq misses +system.cpu.l2cache.overall_hits::cpu.data 999933 # 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number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 140439 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 142742 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2303 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 140061 # number of overall misses -system.cpu.l2cache.overall_misses::total 142364 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6000939500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6000939500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137232000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 137232000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2339459000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2339459000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 137232000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8340398500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8477630500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 137232000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8340398500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8477630500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 1065708 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 1065708 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 140439 # number of overall misses +system.cpu.l2cache.overall_misses::total 142742 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6104447000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6104447000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 139534000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 139534000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2398500500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2398500500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 139534000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8502947500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8642481500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 139534000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8502947500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8642481500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 1065429 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 1065429 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 9751 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 9751 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 356508 # number of ReadExReq accesses(hits+misses) @@ -520,101 +520,101 @@ system.cpu.l2cache.demand_accesses::total 1151893 # n system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1140372 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 1151893 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282709 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.282709 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282835 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.282835 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.199896 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.199896 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050102 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050102 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050527 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050527 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.199896 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.122820 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123591 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.123152 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123919 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.199896 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.122820 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123591 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59540.218082 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59540.218082 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59588.363005 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59588.363005 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59569.144196 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59569.144196 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59548.976567 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59548.976567 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.123152 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123919 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60540.170381 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60540.170381 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60587.928789 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60587.928789 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60559.018836 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60559.018836 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60587.928789 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60545.485941 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60546.170714 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60587.928789 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60545.485941 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60546.170714 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 96330 # number of writebacks -system.cpu.l2cache.writebacks::total 96330 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 96648 # number of writebacks +system.cpu.l2cache.writebacks::total 96648 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100788 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100788 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100833 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100833 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2303 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2303 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39273 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39273 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39606 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39606 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2303 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 140061 # 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number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1946729000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114202000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6939788500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7053990500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114202000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6939788500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7053990500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 140439 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 142742 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5096117000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5096117000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 116504000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 116504000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2002440500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2002440500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116504000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7098557500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7215061500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116504000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7098557500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7215061500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282709 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282709 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282835 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282835 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.199896 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050102 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050102 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050527 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050527 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123591 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123152 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123919 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123591 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49540.218082 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49540.218082 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49588.363005 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49588.363005 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49569.144196 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49569.144196 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123152 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123919 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50540.170381 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50540.170381 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50587.928789 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50587.928789 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50559.018836 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50559.018836 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50587.928789 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50545.485941 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50546.170714 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50587.928789 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50545.485941 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50546.170714 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 2297957 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2153 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2152 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 795385 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1162038 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1162077 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 84632 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 85012 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 356508 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 356508 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution @@ -623,53 +623,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3417020 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 3449850 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1363776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141189120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142552896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 110394 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6165120 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1262287 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004566 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.067432 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141171264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142535040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 110813 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6185472 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1262706 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004570 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.067461 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1256524 99.54% 99.54% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5762 0.46% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1256936 99.54% 99.54% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5769 0.46% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1262287 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2224474500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1262706 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2224195500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1710558000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 41576 # Transaction distribution -system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution -system.membus.trans_dist::CleanEvict 11920 # Transaction distribution -system.membus.trans_dist::ReadExReq 100788 # Transaction distribution -system.membus.trans_dist::ReadExResp 100788 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 41576 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392978 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 392978 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15276416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15276416 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 251405 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 108784 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 41909 # Transaction distribution +system.membus.trans_dist::WritebackDirty 96648 # Transaction distribution +system.membus.trans_dist::CleanEvict 12014 # Transaction distribution +system.membus.trans_dist::ReadExReq 100833 # Transaction distribution +system.membus.trans_dist::ReadExResp 100833 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 41909 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394146 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 394146 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15320960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15320960 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 250615 # Request fanout histogram +system.membus.snoop_fanout::samples 142743 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 250615 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 142743 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 250615 # Request fanout histogram -system.membus.reqLayer0.occupancy 644476328 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 142743 # Request fanout histogram +system.membus.reqLayer0.occupancy 644372828 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 711820000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 713710000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 4e13e1bff..bc9a5d8a0 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.481958 # Number of seconds simulated -sim_ticks 481957625500 # Number of ticks simulated -final_tick 481957625500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.482382 # Number of seconds simulated +sim_ticks 482382057000 # Number of ticks simulated +final_tick 482382057000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109870 # Simulator instruction rate (inst/s) -host_op_rate 203315 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64041688 # Simulator tick rate (ticks/s) -host_mem_usage 315224 # Number of bytes of host memory used -host_seconds 7525.69 # Real time elapsed on the host +host_inst_rate 90853 # Simulator instruction rate (inst/s) +host_op_rate 168124 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53003549 # Simulator tick rate (ticks/s) +host_mem_usage 321140 # Number of bytes of host memory used +host_seconds 9100.94 # Real time elapsed on the host sim_insts 826847303 # Number of instructions simulated sim_ops 1530082520 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 154624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24604096 # Number of bytes read from this memory -system.physmem.bytes_read::total 24758720 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 154624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 154624 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18874880 # Number of bytes written to this memory -system.physmem.bytes_written::total 18874880 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2416 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 384439 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386855 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 294920 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294920 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 320825 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 51050330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51371155 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 320825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 320825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 39162945 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 39162945 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 39162945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 320825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 51050330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 90534100 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386855 # Number of read requests accepted -system.physmem.writeReqs 294920 # Number of write requests accepted -system.physmem.readBursts 386855 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 294920 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24737792 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20928 # Total number of bytes read from write queue -system.physmem.bytesWritten 18873280 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24758720 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18874880 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 327 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 155136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24650752 # Number of bytes read from this memory +system.physmem.bytes_read::total 24805888 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 155136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 155136 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18911424 # Number of bytes written to this memory +system.physmem.bytes_written::total 18911424 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2424 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 385168 # Number of read requests responded to by this memory +system.physmem.num_reads::total 387592 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 295491 # Number of write requests responded to by this memory +system.physmem.num_writes::total 295491 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 321604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 51102133 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51423737 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 321604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 321604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 39204244 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 39204244 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 39204244 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 321604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 51102133 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 90627981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 387592 # Number of read requests accepted +system.physmem.writeReqs 295491 # Number of write requests accepted +system.physmem.readBursts 387592 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 295491 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24786816 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19072 # Total number of bytes read from write queue +system.physmem.bytesWritten 18910464 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24805888 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18911424 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 298 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24516 # Per bank write bursts -system.physmem.perBankRdBursts::1 26460 # Per bank write bursts -system.physmem.perBankRdBursts::2 24685 # Per bank write bursts -system.physmem.perBankRdBursts::3 24442 # Per bank write bursts -system.physmem.perBankRdBursts::4 23203 # Per bank write bursts -system.physmem.perBankRdBursts::5 23588 # Per bank write bursts -system.physmem.perBankRdBursts::6 24636 # Per bank write bursts -system.physmem.perBankRdBursts::7 24397 # Per bank write bursts -system.physmem.perBankRdBursts::8 23786 # Per bank write bursts -system.physmem.perBankRdBursts::9 23509 # Per bank write bursts -system.physmem.perBankRdBursts::10 24817 # Per bank write bursts -system.physmem.perBankRdBursts::11 23975 # Per bank write bursts -system.physmem.perBankRdBursts::12 23290 # Per bank write bursts -system.physmem.perBankRdBursts::13 22963 # Per bank write bursts -system.physmem.perBankRdBursts::14 23965 # Per bank write bursts -system.physmem.perBankRdBursts::15 24296 # Per bank write bursts -system.physmem.perBankWrBursts::0 18881 # Per bank write bursts -system.physmem.perBankWrBursts::1 19925 # Per bank write bursts -system.physmem.perBankWrBursts::2 19022 # Per bank write bursts -system.physmem.perBankWrBursts::3 18969 # Per bank write bursts -system.physmem.perBankWrBursts::4 18086 # Per bank write bursts -system.physmem.perBankWrBursts::5 18421 # Per bank write bursts -system.physmem.perBankWrBursts::6 19142 # Per bank write bursts -system.physmem.perBankWrBursts::7 19085 # Per bank write bursts -system.physmem.perBankWrBursts::8 18675 # Per bank write bursts -system.physmem.perBankWrBursts::9 17903 # Per bank write bursts -system.physmem.perBankWrBursts::10 18899 # Per bank write bursts -system.physmem.perBankWrBursts::11 17761 # Per bank write bursts -system.physmem.perBankWrBursts::12 17398 # Per bank write bursts -system.physmem.perBankWrBursts::13 16983 # Per bank write bursts -system.physmem.perBankWrBursts::14 17797 # Per bank write bursts -system.physmem.perBankWrBursts::15 17948 # Per bank write bursts +system.physmem.perBankRdBursts::0 24694 # Per bank write bursts +system.physmem.perBankRdBursts::1 26457 # Per bank write bursts +system.physmem.perBankRdBursts::2 24696 # Per bank write bursts +system.physmem.perBankRdBursts::3 24495 # Per bank write bursts +system.physmem.perBankRdBursts::4 23285 # Per bank write bursts +system.physmem.perBankRdBursts::5 23614 # Per bank write bursts +system.physmem.perBankRdBursts::6 24693 # Per bank write bursts +system.physmem.perBankRdBursts::7 24448 # Per bank write bursts +system.physmem.perBankRdBursts::8 23844 # Per bank write bursts +system.physmem.perBankRdBursts::9 23582 # Per bank write bursts +system.physmem.perBankRdBursts::10 24812 # Per bank write bursts +system.physmem.perBankRdBursts::11 24004 # Per bank write bursts +system.physmem.perBankRdBursts::12 23312 # Per bank write bursts +system.physmem.perBankRdBursts::13 22998 # Per bank write bursts +system.physmem.perBankRdBursts::14 24024 # Per bank write bursts +system.physmem.perBankRdBursts::15 24336 # Per bank write bursts +system.physmem.perBankWrBursts::0 19003 # Per bank write bursts +system.physmem.perBankWrBursts::1 19960 # Per bank write bursts +system.physmem.perBankWrBursts::2 19024 # Per bank write bursts +system.physmem.perBankWrBursts::3 18975 # Per bank write bursts +system.physmem.perBankWrBursts::4 18152 # Per bank write bursts +system.physmem.perBankWrBursts::5 18441 # Per bank write bursts +system.physmem.perBankWrBursts::6 19161 # Per bank write bursts +system.physmem.perBankWrBursts::7 19119 # Per bank write bursts +system.physmem.perBankWrBursts::8 18726 # Per bank write bursts +system.physmem.perBankWrBursts::9 17970 # Per bank write bursts +system.physmem.perBankWrBursts::10 18928 # Per bank write bursts +system.physmem.perBankWrBursts::11 17785 # Per bank write bursts +system.physmem.perBankWrBursts::12 17418 # Per bank write bursts +system.physmem.perBankWrBursts::13 16994 # Per bank write bursts +system.physmem.perBankWrBursts::14 17838 # Per bank write bursts +system.physmem.perBankWrBursts::15 17982 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 481957508500 # Total gap between requests +system.physmem.totGap 482381969500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386855 # Read request sizes (log2) +system.physmem.readPktSize::6 387592 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 294920 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381052 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 5169 # What read queue length does an incoming req see +system.physmem.writePktSize::6 295491 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 5176 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -145,33 +145,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -194,247 +194,242 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 150272 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 290.205707 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 171.657717 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 319.431199 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 56562 37.64% 37.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 41303 27.49% 65.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13716 9.13% 74.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7600 5.06% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5568 3.71% 83.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3790 2.52% 85.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2987 1.99% 87.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2640 1.76% 89.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16106 10.72% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 150272 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17470 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.124900 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 243.906372 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17461 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 146280 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 298.722669 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 176.940489 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.258352 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 52888 36.16% 36.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40462 27.66% 63.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14063 9.61% 73.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7664 5.24% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5102 3.49% 82.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3857 2.64% 84.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2918 1.99% 86.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2773 1.90% 88.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16553 11.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 146280 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17634 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.962913 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 18.199318 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 216.461189 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17628 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::29696-30719 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17470 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17470 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.880080 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.823698 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.084974 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17271 98.86% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 152 0.87% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 24 0.14% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 6 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 3 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 4 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 4 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17470 # Writes before turning the bus around for reads -system.physmem.totQLat 4249579000 # Total ticks spent queuing -system.physmem.totMemAccLat 11496979000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1932640000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10994.23 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 17634 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17633 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.755969 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.728033 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.977832 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 10918 61.92% 61.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 278 1.58% 63.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 6268 35.55% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 161 0.91% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 7 0.04% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17633 # Writes before turning the bus around for reads +system.physmem.totQLat 4311135000 # Total ticks spent queuing +system.physmem.totMemAccLat 11572897500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1936470000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11131.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29744.23 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 51.33 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 39.16 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.37 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 39.16 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29881.43 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 51.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 39.20 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.42 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 39.20 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.71 # Data bus utilization in percentage system.physmem.busUtilRead 0.40 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.31 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.94 # Average write queue length when enqueuing -system.physmem.readRowHits 315674 # Number of row buffer hits during reads -system.physmem.writeRowHits 215465 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.06 # Row buffer hit rate for writes -system.physmem.avgGap 706915.78 # Average gap between requests -system.physmem.pageHitRate 77.94 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 581999040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 317559000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1528152600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 981784800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 31478846880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 70268579415 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 227533024500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 332689946235 # Total energy per rank (pJ) -system.physmem_0.averagePower 690.294629 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 377929772750 # Time in different power states -system.physmem_0.memoryStateTime::REF 16093480000 # Time in different power states +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.28 # Average write queue length when enqueuing +system.physmem.readRowHits 315765 # Number of row buffer hits during reads +system.physmem.writeRowHits 220723 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes +system.physmem.avgGap 706183.54 # Average gap between requests +system.physmem.pageHitRate 78.57 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 566682480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 309201750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1531779600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 983877840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 31506817680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 69780771990 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 228217880250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 332897011590 # Total energy per rank (pJ) +system.physmem_0.averagePower 690.111043 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 379065618250 # Time in different power states +system.physmem_0.memoryStateTime::REF 16107780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 87930818250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 87208649000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 553777560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 302160375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1486375800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 928823760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 31478846880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 68021430795 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 229504207500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 332275622670 # Total energy per rank (pJ) -system.physmem_1.averagePower 689.434954 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 381228600750 # Time in different power states -system.physmem_1.memoryStateTime::REF 16093480000 # Time in different power states +system.physmem_1.actEnergy 539164080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 294186750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1489098000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 930690000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 31506817680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 67080778605 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 230586295500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 332427030615 # Total energy per rank (pJ) +system.physmem_1.averagePower 689.136751 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 383030551000 # Time in different power states +system.physmem_1.memoryStateTime::REF 16107780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 84631916750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 83243489000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 297786504 # Number of BP lookups -system.cpu.branchPred.condPredicted 297786504 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 23596621 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 229702188 # Number of BTB lookups +system.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 297919436 # Number of BP lookups +system.cpu.branchPred.condPredicted 297919436 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 23611614 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 229854393 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 40293529 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4405587 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 229702188 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 119907455 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 109794733 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 11576014 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 40311454 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4410387 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 229854393 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 119921311 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 109933082 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 11586406 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 481957625500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 963915252 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 964764115 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 229572933 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1587362959 # Number of instructions fetch has processed -system.cpu.fetch.Branches 297786504 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 160200984 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 709710694 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 48100941 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1387 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 31814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 398605 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 6640 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 216353847 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6306355 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 229640733 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1587519909 # Number of instructions fetch has processed +system.cpu.fetch.Branches 297919436 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 160232765 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 710474501 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 48125197 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1838 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 31961 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 395431 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 7638 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 34 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 216406816 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6303131 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 963772561 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.083618 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.495232 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 964614734 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.081549 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.494827 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 472321182 49.01% 49.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 36440853 3.78% 52.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 36199829 3.76% 56.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33073350 3.43% 59.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28557183 2.96% 62.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 29987754 3.11% 66.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40189317 4.17% 70.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 37482048 3.89% 74.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 249521045 25.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 473031835 49.04% 49.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 36413294 3.77% 52.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 36207947 3.75% 56.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33239258 3.45% 60.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28476947 2.95% 62.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 30017172 3.11% 66.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40187194 4.17% 70.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 37484755 3.89% 74.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 249556332 25.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 963772561 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.308934 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.646787 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 165558629 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 380809572 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 312283336 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 81070554 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 24050470 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2743818074 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 24050470 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 201592178 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 193949048 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12373 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 351358358 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 192810134 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2626442761 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 758361 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 120779385 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 21914925 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 41340162 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2707324732 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6591643908 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4206582921 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2532048 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 964614734 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.308800 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.645501 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 165560291 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 381637451 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 312327895 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 81026499 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 24062598 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2744008679 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 24062598 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 201558349 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 194036216 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13250 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 351418098 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 193526223 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2626516746 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 906315 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 120859920 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 22304361 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 41770089 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2707207684 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6591914084 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4206827635 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2574467 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1616961572 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1090363160 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 921 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 827 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 369363812 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 608309859 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 244105032 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 253215291 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 76456984 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2419527437 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 123521 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1999245990 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3630215 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 889568438 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1509945066 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 122969 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 963772561 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.074396 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.106547 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1090246112 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1066 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 982 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 368286677 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 608256588 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 244134978 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 253265740 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 76368619 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2419508786 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 132419 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1999186857 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3656712 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 889558685 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1510180986 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 131867 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 964614734 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.072524 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.106121 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 335335755 34.79% 34.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 135420425 14.05% 48.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 129949182 13.48% 62.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 118520110 12.30% 74.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 97996233 10.17% 84.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 67311922 6.98% 91.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 45709014 4.74% 96.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 22671115 2.35% 98.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10858805 1.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 336173556 34.85% 34.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 135262022 14.02% 48.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 129832579 13.46% 62.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119015920 12.34% 74.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 98090682 10.17% 84.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 67084509 6.95% 91.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 45576707 4.72% 96.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 22663670 2.35% 98.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10915089 1.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 963772561 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 964614734 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11256438 43.50% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11830784 45.72% 89.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2789302 10.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11249182 43.29% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11894821 45.77% 89.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2844033 10.94% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2910372 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1333563815 66.70% 66.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 358658 0.02% 66.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 4798558 0.24% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 10 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2910415 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1333514799 66.70% 66.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 358060 0.02% 66.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 4798571 0.24% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.11% # Type of FU issued @@ -460,82 +455,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 471264290 23.57% 90.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186350287 9.32% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 471222917 23.57% 90.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186382093 9.32% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1999245990 # Type of FU issued -system.cpu.iq.rate 2.074089 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25876524 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012943 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4990508159 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3305732748 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1923901013 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1263121 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4059650 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 238029 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2021668252 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 543890 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 179792885 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1999186857 # Type of FU issued +system.cpu.iq.rate 2.072203 # Inst issue rate +system.cpu.iq.fu_busy_cnt 25988036 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012999 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4991322155 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3305635589 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1923777377 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1311041 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4133688 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 240317 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2021708405 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 556073 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 179295064 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 224226629 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 339387 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 641597 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94946837 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 224173511 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 339017 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 636964 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94976783 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 32049 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 734 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 31958 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 747 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 24050470 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 144665099 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6487735 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2419650958 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1303031 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 608309942 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 244105032 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 42573 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1493780 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4140484 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 641597 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8724662 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 20631512 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 29356174 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1945805936 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 456837338 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 53440054 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 24062598 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 144797851 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6250562 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2419641205 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1306710 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 608256824 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 244134978 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 45669 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1454928 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3966770 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 636964 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8731316 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 20649413 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 29380729 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1945668790 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 456756594 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 53518067 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 635668777 # number of memory reference insts executed -system.cpu.iew.exec_branches 185171662 # Number of branches executed -system.cpu.iew.exec_stores 178831439 # Number of stores executed -system.cpu.iew.exec_rate 2.018648 # Inst execution rate -system.cpu.iew.wb_sent 1934669445 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1924139042 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1457092334 # num instructions producing a value -system.cpu.iew.wb_consumers 2203939353 # num instructions consuming a value -system.cpu.iew.wb_rate 1.996170 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.661131 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 889643735 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 635598570 # number of memory reference insts executed +system.cpu.iew.exec_branches 185172751 # Number of branches executed +system.cpu.iew.exec_stores 178841976 # Number of stores executed +system.cpu.iew.exec_rate 2.016730 # Inst execution rate +system.cpu.iew.wb_sent 1934534562 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1924017694 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1456930726 # num instructions producing a value +system.cpu.iew.wb_consumers 2203703226 # num instructions consuming a value +system.cpu.iew.wb_rate 1.994288 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.661128 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 889633438 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 23627115 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 831081217 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.841075 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.465971 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 23642184 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 831915086 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.839229 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.465352 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 351390819 42.28% 42.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 184611364 22.21% 64.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57978208 6.98% 71.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 87188862 10.49% 81.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 30418140 3.66% 85.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26591078 3.20% 88.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10434720 1.26% 90.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9032324 1.09% 91.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 73435702 8.84% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 352165945 42.33% 42.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 184695932 22.20% 64.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57945588 6.97% 71.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 87210863 10.48% 81.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 30437769 3.66% 85.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26536432 3.19% 88.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10472867 1.26% 90.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9005135 1.08% 91.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 73444555 8.83% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 831081217 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 831915086 # Number of insts commited each cycle system.cpu.commit.committedInsts 826847303 # Number of instructions committed system.cpu.commit.committedOps 1530082520 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -581,489 +576,496 @@ system.cpu.commit.op_class_0::MemWrite 149158195 9.75% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction -system.cpu.commit.bw_lim_events 73435702 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3177371770 # The number of ROB reads -system.cpu.rob.rob_writes 4973814894 # The number of ROB writes -system.cpu.timesIdled 2014 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 142691 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 73444555 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3178186489 # The number of ROB reads +system.cpu.rob.rob_writes 4973800859 # The number of ROB writes +system.cpu.timesIdled 2058 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 149381 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826847303 # Number of Instructions Simulated system.cpu.committedOps 1530082520 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.165772 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.165772 # CPI: Total CPI of All Threads -system.cpu.ipc 0.857801 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.857801 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2928585667 # number of integer regfile reads -system.cpu.int_regfile_writes 1576867903 # number of integer regfile writes -system.cpu.fp_regfile_reads 239177 # number of floating regfile reads -system.cpu.fp_regfile_writes 8 # number of floating regfile writes -system.cpu.cc_regfile_reads 617820038 # number of cc regfile reads -system.cpu.cc_regfile_writes 419954937 # number of cc regfile writes -system.cpu.misc_regfile_reads 1064369445 # number of misc regfile reads +system.cpu.cpi 1.166798 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.166798 # CPI: Total CPI of All Threads +system.cpu.ipc 0.857046 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.857046 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2928420991 # number of integer regfile reads +system.cpu.int_regfile_writes 1576721018 # number of integer regfile writes +system.cpu.fp_regfile_reads 241306 # number of floating regfile reads +system.cpu.fp_regfile_writes 1 # number of floating regfile writes +system.cpu.cc_regfile_reads 617864492 # number of cc regfile reads +system.cpu.cc_regfile_writes 419924545 # number of cc regfile writes +system.cpu.misc_regfile_reads 1064270268 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2545945 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.303608 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 421067815 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2550041 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.121978 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1812560500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.303608 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998121 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998121 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2546182 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.922606 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 421485651 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2550278 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.270473 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1898151500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.922606 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998028 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998028 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 634 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3418 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 599 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3454 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 851394195 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 851394195 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 272697526 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 272697526 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148366944 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148366944 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 421064470 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 421064470 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 421064470 # number of overall hits -system.cpu.dcache.overall_hits::total 421064470 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2566340 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2566340 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791267 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791267 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3357607 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3357607 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3357607 # number of overall misses -system.cpu.dcache.overall_misses::total 3357607 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57037182000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57037182000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24501570500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24501570500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 81538752500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 81538752500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 81538752500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 81538752500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 275263866 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 275263866 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 852234240 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 852234240 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 273116230 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 273116230 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148366946 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148366946 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 421483176 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 421483176 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 421483176 # number of overall hits +system.cpu.dcache.overall_hits::total 421483176 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2567540 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2567540 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 791265 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 791265 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3358805 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3358805 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3358805 # number of overall misses +system.cpu.dcache.overall_misses::total 3358805 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57574934000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57574934000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24743790498 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24743790498 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 82318724498 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 82318724498 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 82318724498 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 82318724498 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 275683770 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 275683770 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 424422077 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 424422077 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 424422077 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 424422077 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009323 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009323 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 424841981 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 424841981 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 424841981 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 424841981 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009313 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009313 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005305 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.005305 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007911 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007911 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007911 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007911 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22225.107351 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22225.107351 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30964.984639 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30964.984639 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24284.781542 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24284.781542 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24284.781542 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24284.781542 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 8528 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1295 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 875 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.746286 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 92.500000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2337968 # number of writebacks -system.cpu.dcache.writebacks::total 2337968 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 800154 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 800154 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5753 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 5753 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 805907 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 805907 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 805907 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 805907 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766186 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1766186 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785514 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 785514 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2551700 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2551700 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2551700 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2551700 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33673145000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33673145000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23618473500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 23618473500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 57291618500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 57291618500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 57291618500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 57291618500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006416 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006416 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.007906 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007906 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007906 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007906 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22424.162428 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22424.162428 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31271.180323 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31271.180323 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24508.336893 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24508.336893 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24508.336893 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24508.336893 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 8828 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1268 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 857 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12 # 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Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1543 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.832031 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 432820961 # Number of tag accesses +system.cpu.icache.tags.data_accesses 432820961 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 216397172 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 216397172 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 216397172 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 216397172 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 216397172 # number of overall hits +system.cpu.icache.overall_hits::total 216397172 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9643 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36772.944001 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36772.944001 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 690 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 43.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 76.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 4014 # number of writebacks -system.cpu.icache.writebacks::total 4014 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2282 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2282 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2282 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2282 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2282 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2282 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7390 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7390 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7390 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7390 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7390 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7390 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243725000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 243725000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243725000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 243725000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243725000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 243725000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 4041 # number of writebacks +system.cpu.icache.writebacks::total 4041 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2312 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2312 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2312 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2312 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2312 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2312 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7331 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7331 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7331 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7331 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7331 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7331 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 251236999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 251236999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 251236999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 251236999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 251236999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 251236999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32980.378890 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26967067000 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 295491 # number of writebacks +system.cpu.l2cache.writebacks::total 295491 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206802 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206802 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2424 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2424 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 178367 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 178367 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2424 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 385169 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 387593 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2424 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 385169 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 387593 # number of overall MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 102500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 102500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14535147500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14535147500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 179310000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 179310000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12743139000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12743139000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 179310000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 27278286500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27457596500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 179310000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 27278286500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27457596500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808921 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808921 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263602 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263602 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.426253 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.426253 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100661 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100661 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.426253 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150762 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151373 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.426253 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150762 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151373 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19041.728018 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19041.728018 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69047.647156 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69047.647156 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70933.567881 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70933.567881 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70456.222611 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70456.222611 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70933.567881 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69698.949666 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69706.659946 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70933.567881 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69698.949666 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69706.659946 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5109049 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551690 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 8246 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2834 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2829 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 5 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1773348 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2632888 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4014 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 268218 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 1659 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 1659 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 784083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 784083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 7390 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1765958 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17072 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649345 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7666417 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 619648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312832576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 313452224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 356883 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18985088 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2914251 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004390 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.066139 # Request fanout histogram +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.003171 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.003171 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263749 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263749 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.428571 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.428571 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100990 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100990 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.428571 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151030 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151644 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.428571 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151030 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151644 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70285.333314 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70285.333314 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73972.772277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73972.772277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71443.366766 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71443.366766 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73972.772277 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70821.604283 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70841.311634 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73972.772277 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70821.604283 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70841.311634 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5109409 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551871 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7932 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2949 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2946 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1773523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2633350 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4041 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 268853 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1577 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1577 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 784086 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 784086 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 7331 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1766192 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17028 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649892 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7666920 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 620608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312840768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 313461376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 357696 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 19018624 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2915207 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004295 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.065414 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2901462 99.56% 99.56% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12784 0.44% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 5 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2902688 99.57% 99.57% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12516 0.43% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2914251 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4896549913 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2915207 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4896659390 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 11087994 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10998496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3825891006 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3826206608 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 180179 # Transaction distribution -system.membus.trans_dist::WritebackDirty 294920 # Transaction distribution -system.membus.trans_dist::CleanEvict 57436 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1352 # Transaction distribution -system.membus.trans_dist::ReadExReq 206676 # Transaction distribution -system.membus.trans_dist::ReadExResp 206676 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 180179 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1127418 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1127418 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1127418 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43633600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43633600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43633600 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 740700 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 353605 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 180791 # Transaction distribution +system.membus.trans_dist::WritebackDirty 295491 # Transaction distribution +system.membus.trans_dist::CleanEvict 57611 # Transaction distribution +system.membus.trans_dist::UpgradeReq 6 # Transaction distribution +system.membus.trans_dist::ReadExReq 206801 # Transaction distribution +system.membus.trans_dist::ReadExResp 206801 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 180791 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1128292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1128292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1128292 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43717312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43717312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43717312 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 740563 # Request fanout histogram +system.membus.snoop_fanout::samples 387598 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 740563 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 387598 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 740563 # Request fanout histogram -system.membus.reqLayer0.occupancy 1999132580 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 387598 # Request fanout histogram +system.membus.reqLayer0.occupancy 1995849000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 2047220500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2051150500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index ff2284b45..76b9b35da 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.885773 # Nu sim_ticks 885772926000 # Number of ticks simulated final_tick 885772926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 771975 # Simulator instruction rate (inst/s) -host_op_rate 1428542 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 826990545 # Simulator tick rate (ticks/s) -host_mem_usage 269652 # Number of bytes of host memory used -host_seconds 1071.08 # Real time elapsed on the host +host_inst_rate 861241 # Simulator instruction rate (inst/s) +host_op_rate 1593729 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 922618164 # Simulator tick rate (ticks/s) +host_mem_usage 273768 # Number of bytes of host memory used +host_seconds 960.06 # Real time elapsed on the host sim_insts 826847304 # Number of instructions simulated sim_ops 1530082521 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -104,6 +104,12 @@ system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1530082521 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 1452393978 # Transaction distribution system.membus.trans_dist::ReadResp 1452393978 # Transaction distribution @@ -122,14 +128,14 @@ system.membus.pkt_size::total 11823849838 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 1601552189 # Request fanout histogram -system.membus.snoop_fanout::mean 0.667047 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.471270 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 533241553 33.30% 33.30% # Request fanout histogram -system.membus.snoop_fanout::1 1068310636 66.70% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1601552189 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 1601552189 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index b7bd8e61b..9b8e6bb2d 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,51 +1,51 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.650501 # Number of seconds simulated -sim_ticks 1650501252500 # Number of ticks simulated -final_tick 1650501252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.650924 # Number of seconds simulated +sim_ticks 1650923912500 # Number of ticks simulated +final_tick 1650923912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 516047 # Simulator instruction rate (inst/s) -host_op_rate 954946 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1030101248 # Simulator tick rate (ticks/s) -host_mem_usage 278616 # Number of bytes of host memory used -host_seconds 1602.27 # Real time elapsed on the host +host_inst_rate 598809 # Simulator instruction rate (inst/s) +host_op_rate 1108098 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1195612149 # Simulator tick rate (ticks/s) +host_mem_usage 285816 # Number of bytes of host memory used +host_seconds 1380.82 # Real time elapsed on the host sim_insts 826847304 # Number of instructions simulated sim_ops 1530082521 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory -system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 115776 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18765248 # Number of bytes written to this memory -system.physmem.bytes_written::total 18765248 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1809 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 379046 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380855 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293207 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293207 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 70146 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14697925 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14768071 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 70146 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 70146 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11369424 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11369424 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11369424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 70146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14697925 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 26137495 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 115968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24312256 # Number of bytes read from this memory +system.physmem.bytes_read::total 24428224 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 115968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 115968 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18812864 # Number of bytes written to this memory +system.physmem.bytes_written::total 18812864 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1812 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 379879 # Number of read requests responded to by this memory +system.physmem.num_reads::total 381691 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293951 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293951 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 70244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14726455 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14796699 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 70244 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 70244 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 11395355 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11395355 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11395355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 70244 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14726455 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 26192054 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1650501252500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 3301002505 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1650923912500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 3301847825 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826847304 # Number of instructions committed @@ -66,7 +66,7 @@ system.cpu.num_mem_refs 533241508 # nu system.cpu.num_load_insts 384083313 # Number of load instructions system.cpu.num_store_insts 149158195 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 3301002504.998000 # Number of busy cycles +system.cpu.num_busy_cycles 3301847824.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 149981740 # Number of branches fetched @@ -105,16 +105,16 @@ system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1530082521 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2517016 # number of replacements -system.cpu.dcache.tags.tagsinuse 4086.386474 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4086.382570 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2521112 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 210.510458 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 8246025500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4086.386474 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997653 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997653 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 8250925500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4086.382570 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997652 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997652 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id @@ -124,7 +124,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits @@ -141,14 +141,14 @@ system.cpu.dcache.demand_misses::cpu.data 2521112 # n system.cpu.dcache.demand_misses::total 2521112 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2521112 # number of overall misses system.cpu.dcache.overall_misses::total 2521112 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 30948499500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 30948499500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20399257500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20399257500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 51347757000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 51347757000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 51347757000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 51347757000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31154171500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31154171500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20614263500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20614263500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 51768435000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 51768435000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 51768435000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 51768435000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 384083342 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 384083342 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) @@ -165,22 +165,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004728 system.cpu.dcache.demand_miss_rate::total 0.004728 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004728 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004728 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17891.974352 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17891.974352 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25777.142803 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 25777.142803 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20367.106658 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20367.106658 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18010.877634 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18010.877634 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26048.831141 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26048.831141 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20533.968741 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20533.968741 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20533.968741 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20533.968741 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2325221 # number of writebacks -system.cpu.dcache.writebacks::total 2325221 # number of writebacks +system.cpu.dcache.writebacks::writebacks 2324919 # number of writebacks +system.cpu.dcache.writebacks::total 2324919 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1729742 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1729742 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791370 # number of WriteReq MSHR misses @@ -189,14 +189,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2521112 system.cpu.dcache.demand_mshr_misses::total 2521112 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2521112 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2521112 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29218757500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29218757500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19607887500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19607887500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48826645000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 48826645000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48826645000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 48826645000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29424429500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29424429500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19822893500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19822893500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49247323000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 49247323000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49247323000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 49247323000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004504 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004504 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005306 # mshr miss rate for WriteReq accesses @@ -205,22 +205,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004728 system.cpu.dcache.demand_mshr_miss_rate::total 0.004728 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.004728 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16891.974352 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16891.974352 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24777.142803 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24777.142803 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17010.877634 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17010.877634 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25048.831141 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25048.831141 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19533.968741 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19533.968741 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19533.968741 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19533.968741 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1253 # number of replacements -system.cpu.icache.tags.tagsinuse 881.361687 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 881.361666 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 379640.306326 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 881.361687 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 881.361666 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id @@ -232,7 +232,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits @@ -245,12 +245,12 @@ system.cpu.icache.demand_misses::cpu.inst 2814 # n system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses system.cpu.icache.overall_misses::total 2814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 125255000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 125255000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 125255000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 125255000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 125255000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 125255000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 127237000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 127237000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 127237000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 127237000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 127237000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 127237000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1068310636 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1068310636 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1068310636 # number of demand (read+write) accesses @@ -263,12 +263,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44511.371713 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44511.371713 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44511.371713 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44511.371713 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45215.707178 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 45215.707178 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 45215.707178 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 45215.707178 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 45215.707178 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 45215.707178 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -283,89 +283,88 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814 system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122441000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 122441000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122441000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 122441000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122441000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 122441000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 124423000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 124423000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 124423000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 124423000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 124423000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 124423000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43511.371713 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43511.371713 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 348438 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29288.734166 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3851952 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 380798 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.115473 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 756996028500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 20940.857984 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.259734 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.616448 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.639064 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004006 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.250751 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.893821 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41509728 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41509728 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2325221 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2325221 # number of WritebackDirty hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44215.707178 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44215.707178 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44215.707178 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 44215.707178 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44215.707178 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 44215.707178 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 349420 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30439.047290 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4660001 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 382188 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.192955 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 287867097000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 31.679459 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.475071 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30276.892760 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000967 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003982 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.923977 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.928926 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 346 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 32344 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 40719748 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40719748 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 2324919 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2324919 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 585014 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 585014 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1005 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1005 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1557052 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1557052 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1005 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2142066 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2143071 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1005 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2142066 # number of overall hits -system.cpu.l2cache.overall_hits::total 2143071 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 206356 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206356 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1809 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1809 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 172690 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 172690 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1809 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 379046 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 380855 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1809 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 379046 # number of overall misses -system.cpu.l2cache.overall_misses::total 380855 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12278185500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12278185500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 107656000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 107656000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10275095500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 10275095500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 107656000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22553281000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22660937000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 107656000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22553281000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22660937000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2325221 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2325221 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits::cpu.data 584841 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 584841 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1002 # 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number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 173350 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 173350 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1812 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 379879 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 381691 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1812 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 379879 # number of overall misses +system.cpu.l2cache.overall_misses::total 381691 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12495008000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12495008000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 109669500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 109669500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10487697500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 10487697500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 109669500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22982705500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23092375000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 109669500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22982705500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23092375000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2324919 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2324919 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 1253 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 1253 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 791370 # number of ReadExReq accesses(hits+misses) @@ -380,101 +379,101 @@ system.cpu.l2cache.demand_accesses::total 2523926 # n system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2521112 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2523926 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260758 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.260758 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.642857 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.642857 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099836 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099836 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.642857 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150349 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.150898 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.642857 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.150349 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.150898 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.016961 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.016961 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.332228 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.332228 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.234524 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.234524 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59500.169356 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59500.169356 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260977 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.260977 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.643923 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.643923 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100217 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100217 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.643923 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150679 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151229 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.643923 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150679 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151229 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.016947 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.016947 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60524.006623 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60524.006623 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.129795 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.129795 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60524.006623 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.068443 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60500.182084 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60524.006623 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.068443 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60500.182084 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 293208 # number of writebacks -system.cpu.l2cache.writebacks::total 293208 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 293952 # number of writebacks +system.cpu.l2cache.writebacks::total 293952 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206356 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206356 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1809 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1809 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172690 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172690 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1809 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 379046 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 380855 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1809 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 379046 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 380855 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10214625500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10214625500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 89566000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 89566000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8548195500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8548195500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 89566000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18762821000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18852387000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89566000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762821000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18852387000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206529 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206529 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1812 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1812 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 173350 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 173350 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1812 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 379879 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 381691 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1812 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 379879 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 381691 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10429718000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10429718000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 91549500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 91549500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8754197500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8754197500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91549500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19183915500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19275465000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91549500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19183915500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19275465000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260758 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260758 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.642857 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099836 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099836 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.150898 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.150898 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.016961 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.016961 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.332228 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.332228 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234524 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234524 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260977 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260977 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.643923 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100217 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100217 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150679 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151229 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150679 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151229 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.016947 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.016947 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50524.006623 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50524.006623 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.129795 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.129795 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50524.006623 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.068443 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.182084 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50524.006623 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.068443 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.182084 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1866 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1866 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2618429 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2618871 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 247025 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 247565 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 791370 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 791370 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution @@ -483,55 +482,61 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7559240 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 7566121 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310165312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 310425600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 348438 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18765312 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2872364 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000602 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.024527 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310145984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 310406272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 349420 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 18812928 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2873346 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000649 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.025475 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2870635 99.94% 99.94% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1729 0.06% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2871480 99.94% 99.94% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1866 0.06% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2872364 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4847571500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2873346 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4847269500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 174499 # Transaction distribution -system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution -system.membus.trans_dist::CleanEvict 53507 # Transaction distribution -system.membus.trans_dist::ReadExReq 206356 # Transaction distribution -system.membus.trans_dist::ReadExResp 206356 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 174499 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1108424 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43139968 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 729250 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 347559 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 175162 # Transaction distribution +system.membus.trans_dist::WritebackDirty 293951 # Transaction distribution +system.membus.trans_dist::CleanEvict 53608 # Transaction distribution +system.membus.trans_dist::ReadExReq 206529 # Transaction distribution +system.membus.trans_dist::ReadExResp 206529 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 175162 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1110941 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1110941 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1110941 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43241088 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43241088 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43241088 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 727569 # Request fanout histogram +system.membus.snoop_fanout::samples 381691 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 727569 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 381691 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 727569 # Request fanout histogram -system.membus.reqLayer0.occupancy 1900428000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 381691 # Request fanout histogram +system.membus.reqLayer0.occupancy 1905079500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1904275000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1908455000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index b65c3962a..6b30c3cf1 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.233526 # Number of seconds simulated -sim_ticks 233525789500 # Number of ticks simulated -final_tick 233525789500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233534 # Number of seconds simulated +sim_ticks 233533887500 # Number of ticks simulated +final_tick 233533887500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 279317 # Simulator instruction rate (inst/s) -host_op_rate 279317 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 163615265 # Simulator tick rate (ticks/s) -host_mem_usage 255720 # Number of bytes of host memory used -host_seconds 1427.29 # Real time elapsed on the host +host_inst_rate 225573 # Simulator instruction rate (inst/s) +host_op_rate 225573 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 132138421 # Simulator tick rate (ticks/s) +host_mem_usage 260868 # Number of bytes of host memory used +host_seconds 1767.34 # Real time elapsed on the host sim_insts 398664651 # Number of instructions simulated sim_ops 398664651 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 249280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory system.physmem.bytes_read::total 503872 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 249280 # Nu system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1067462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1090209 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2157672 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1067462 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1067462 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1067462 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1090209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2157672 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1067425 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1090172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2157597 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1067425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1067425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1067425 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1090172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2157597 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7873 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 233525688500 # Total gap between requests +system.physmem.totGap 233533785500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6853 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 951 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 69 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1541 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 326.852693 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 195.480715 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 331.694198 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 535 34.72% 34.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 344 22.32% 57.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 186 12.07% 69.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 104 6.75% 75.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 66 4.28% 80.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 53 3.44% 83.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 28 1.82% 85.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 39 2.53% 87.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 186 12.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1541 # Bytes accessed per row activation -system.physmem.totQLat 52273750 # Total ticks spent queuing -system.physmem.totMemAccLat 199892500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 326.051813 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 195.846863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.937998 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 532 34.46% 34.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 344 22.28% 56.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 193 12.50% 69.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 103 6.67% 75.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 73 4.73% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 45 2.91% 83.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 32 2.07% 85.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 36 2.33% 87.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 186 12.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation +system.physmem.totQLat 53440000 # Total ticks spent queuing +system.physmem.totMemAccLat 201058750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6639.62 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6787.76 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25389.62 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25537.76 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s @@ -217,75 +217,75 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6330 # Number of row buffer hits during reads +system.physmem.readRowHits 6327 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.40 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.36 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 29661588.78 # Average gap between requests -system.physmem.pageHitRate 80.40 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6804000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3712500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 34327800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 29662617.24 # Average gap between requests +system.physmem.pageHitRate 80.36 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6758640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3687750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 34296600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15252731520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5982776145 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 134867232750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 156147584715 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.653337 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 224361889750 # Time in different power states -system.physmem_0.memoryStateTime::REF 7797920000 # Time in different power states +system.physmem_0.refreshEnergy 15253240080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6038642700 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 134822908500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 156159534270 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.682165 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 224288059000 # Time in different power states +system.physmem_0.memoryStateTime::REF 7798180000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1365674000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1447046250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4845960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2644125 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 4914000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2681250 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 27058200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15252731520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5743132470 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 135077446500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 156107858775 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.483223 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 224713608000 # Time in different power states -system.physmem_1.memoryStateTime::REF 7797920000 # Time in different power states +system.physmem_1.refreshEnergy 15253240080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5739994620 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 135084870750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 156112758900 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.481917 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 224725904750 # Time in different power states +system.physmem_1.memoryStateTime::REF 7798180000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1013955750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1009185250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 45912937 # Number of BP lookups -system.cpu.branchPred.condPredicted 26702744 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 45912940 # Number of BP lookups +system.cpu.branchPred.condPredicted 26702743 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 565787 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25186730 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 25186733 # Number of BTB lookups system.cpu.branchPred.BTBHits 18811780 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 74.689251 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 74.689242 # BTB Hit Percentage system.cpu.branchPred.usedRAS 8285572 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2249877 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 2249880 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 2235903 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 13974 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 13977 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 111495 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 95338457 # DTB read hits +system.cpu.dtb.read_hits 95338456 # DTB read hits system.cpu.dtb.read_misses 116 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 95338573 # DTB read accesses +system.cpu.dtb.read_accesses 95338572 # DTB read accesses system.cpu.dtb.write_hits 73578378 # DTB write hits system.cpu.dtb.write_misses 849 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 73579227 # DTB write accesses -system.cpu.dtb.data_hits 168916835 # DTB hits +system.cpu.dtb.data_hits 168916834 # DTB hits system.cpu.dtb.data_misses 965 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168917800 # DTB accesses -system.cpu.itb.fetch_hits 96959231 # ITB hits +system.cpu.dtb.data_accesses 168917799 # DTB accesses +system.cpu.itb.fetch_hits 96959232 # ITB hits system.cpu.itb.fetch_misses 1239 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 96960470 # ITB accesses +system.cpu.itb.fetch_accesses 96960471 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,16 +299,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 233525789500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 467051579 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 233533887500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 467067775 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664651 # Number of instructions committed system.cpu.committedOps 398664651 # Number of ops (including micro ops) committed system.cpu.discardedOps 2289293 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.171540 # CPI: cycles per instruction -system.cpu.ipc 0.853577 # IPC: instructions per cycle +system.cpu.cpi 1.171581 # CPI: cycles per instruction +system.cpu.ipc 0.853548 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction system.cpu.op_class_0::IntAlu 141652555 35.53% 41.33% # Class of committed instruction system.cpu.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction @@ -344,18 +344,18 @@ system.cpu.op_class_0::MemWrite 73520764 18.44% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 398664651 # Class of committed instruction -system.cpu.tickCycles 455740556 # Number of cycles that the object actually ticked -system.cpu.idleCycles 11311023 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 455740572 # Number of cycles that the object actually ticked +system.cpu.idleCycles 11327203 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.966637 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 167817023 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3291.924590 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 167817024 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40292.202401 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40292.202641 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3291.966637 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803703 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803703 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.924590 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803693 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803693 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id @@ -365,31 +365,31 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 3113 system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 335652191 # Number of tag accesses system.cpu.dcache.tags.data_accesses 335652191 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 94302223 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94302223 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73514800 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73514800 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 167817023 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 167817023 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 167817023 # number of overall hits -system.cpu.dcache.overall_hits::total 167817023 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 73514801 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514801 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 167817024 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 167817024 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 167817024 # number of overall hits +system.cpu.dcache.overall_hits::total 167817024 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1061 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1061 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5929 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5929 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 6990 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6990 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6990 # number of overall misses -system.cpu.dcache.overall_misses::total 6990 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 77930500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 77930500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 429190000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 429190000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 507120500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 507120500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 507120500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 507120500 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 5928 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5928 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 6989 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6989 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6989 # number of overall misses +system.cpu.dcache.overall_misses::total 6989 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 80682500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 80682500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 434084500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 434084500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 514767000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 514767000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 514767000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 514767000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94303284 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94303284 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -406,14 +406,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73450.047125 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73450.047125 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72388.261090 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72388.261090 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72549.427754 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72549.427754 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72549.427754 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72549.427754 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76043.826579 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76043.826579 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73226.130229 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73226.130229 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73653.884676 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73653.884676 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73653.884676 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73653.884676 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -424,12 +424,12 @@ system.cpu.dcache.writebacks::writebacks 654 # nu system.cpu.dcache.writebacks::total 654 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 92 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2733 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2733 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2825 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2825 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2825 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2825 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2732 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2732 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2824 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2824 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2824 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2824 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses @@ -438,14 +438,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4165 system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70280500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 70280500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 239912500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 239912500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 310193000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 310193000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 310193000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 310193000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 72936500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 72936500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 242391000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 242391000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 315327500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 315327500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 315327500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 315327500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -454,69 +454,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72528.895769 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72528.895769 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75066.489362 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75066.489362 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74476.110444 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74476.110444 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74476.110444 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74476.110444 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75269.865841 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75269.865841 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75841.989987 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75841.989987 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75708.883553 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75708.883553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75708.883553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75708.883553 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 3193 # number of replacements -system.cpu.icache.tags.tagsinuse 1919.750364 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 96954060 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1919.733373 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 96954061 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 5171 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18749.576484 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 18749.576678 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1919.750364 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.937378 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.937378 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1919.733373 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.937370 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.937370 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1287 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 193923633 # Number of tag accesses -system.cpu.icache.tags.data_accesses 193923633 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 96954060 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 96954060 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 96954060 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 96954060 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 96954060 # number of overall hits -system.cpu.icache.overall_hits::total 96954060 # number of overall hits +system.cpu.icache.tags.tag_accesses 193923635 # Number of tag accesses +system.cpu.icache.tags.data_accesses 193923635 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 96954061 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 96954061 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 96954061 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 96954061 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 96954061 # number of overall hits +system.cpu.icache.overall_hits::total 96954061 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 5171 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 5171 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 5171 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 5171 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5171 # number of overall misses system.cpu.icache.overall_misses::total 5171 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 318040500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 318040500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 318040500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 318040500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 318040500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 318040500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 96959231 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 96959231 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 96959231 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 96959231 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 96959231 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 96959231 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 321948500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 321948500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 321948500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 321948500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 321948500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 321948500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 96959232 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 96959232 # 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average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -531,47 +531,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5171 system.cpu.icache.demand_mshr_misses::total 5171 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 5171 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 5171 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312869500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 312869500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312869500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 312869500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312869500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 312869500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 316777500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 316777500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 316777500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 316777500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 316777500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 316777500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60504.641269 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60504.641269 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60504.641269 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60504.641269 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60504.641269 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60504.641269 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61260.394508 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61260.394508 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61260.394508 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61260.394508 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61260.394508 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61260.394508 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4425.384656 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4801 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5273 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.910487 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 7128.160045 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5427 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 7873 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.689318 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 372.164909 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.179805 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 642.039942 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011358 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104101 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.019594 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.135052 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5273 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 613 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4442 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160919 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 114871 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 114871 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.137560 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3717.022485 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104100 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.113435 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.217534 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 7873 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7185 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.240265 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 114273 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 114273 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 654 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 654 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 3193 # number of WritebackClean hits @@ -600,18 +599,18 @@ system.cpu.l2cache.demand_misses::total 7873 # nu system.cpu.l2cache.overall_misses::cpu.inst 3895 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses system.cpu.l2cache.overall_misses::total 7873 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 234589500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 234589500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 291713500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 291713500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 67354500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 67354500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 291713500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 301944000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 593657500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 291713500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 301944000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 593657500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 237071000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 237071000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 295621500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 295621500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 70008000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 70008000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 295621500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 307079000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 602700500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 295621500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 307079000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 602700500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 654 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 654 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 3193 # number of WritebackClean accesses(hits+misses) @@ -640,18 +639,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.843295 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.753239 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.843295 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74781.479120 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74781.479120 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74894.351733 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74894.351733 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80088.585018 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80088.585018 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74894.351733 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75903.469080 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75404.229646 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74894.351733 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75903.469080 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75404.229646 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75572.521517 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75572.521517 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75897.689345 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75897.689345 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83243.757432 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83243.757432 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75897.689345 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77194.318753 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76552.838816 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75897.689345 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77194.318753 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76552.838816 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -670,18 +669,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7873 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3895 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 203219500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 203219500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 252763500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 252763500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 58944500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 58944500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 252763500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 262164000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 514927500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 252763500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 262164000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 514927500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 205701000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 205701000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 256671500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 256671500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 61598000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 61598000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 256671500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 267299000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 523970500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 256671500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 267299000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 523970500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.753239 # mshr miss rate for ReadCleanReq accesses @@ -694,25 +693,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.843295 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.753239 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.843295 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64781.479120 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64781.479120 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64894.351733 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64894.351733 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70088.585018 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70088.585018 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64894.351733 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65903.469080 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65404.229646 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64894.351733 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65903.469080 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65404.229646 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65572.521517 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65572.521517 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65897.689345 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65897.689345 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73243.757432 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73243.757432 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65897.689345 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67194.318753 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66552.838816 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65897.689345 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67194.318753 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66552.838816 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 13300 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 3964 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 6138 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3193 # Transaction distribution @@ -744,9 +743,15 @@ system.cpu.toL2Bus.reqLayer0.occupancy 10497000 # La system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 7756500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6247999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6247500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 233525789500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 7873 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 233533887500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4736 # Transaction distribution system.membus.trans_dist::ReadExReq 3137 # Transaction distribution system.membus.trans_dist::ReadExResp 3137 # Transaction distribution @@ -767,9 +772,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7873 # Request fanout histogram -system.membus.reqLayer0.occupancy 9219000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9223000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 41801750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 41799750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 81cd1b880..71e9e3432 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.064189 # Number of seconds simulated -sim_ticks 64188759000 # Number of ticks simulated -final_tick 64188759000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.064159 # Number of seconds simulated +sim_ticks 64159445000 # Number of ticks simulated +final_tick 64159445000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 260398 # Simulator instruction rate (inst/s) -host_op_rate 260398 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44504184 # Simulator tick rate (ticks/s) -host_mem_usage 257256 # Number of bytes of host memory used -host_seconds 1442.31 # Real time elapsed on the host +host_inst_rate 223776 # Simulator instruction rate (inst/s) +host_op_rate 223776 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38227708 # Simulator tick rate (ticks/s) +host_mem_usage 261380 # Number of bytes of host memory used +host_seconds 1678.35 # Real time elapsed on the host sim_insts 375574794 # Number of instructions simulated sim_ops 375574794 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 220736 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 255360 # Number of bytes read from this memory -system.physmem.bytes_read::total 476160 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220800 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3450 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 476096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220736 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3449 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3990 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7440 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3439855 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3978267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7418121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3439855 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3439855 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3439855 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3978267 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7418121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7440 # Number of read requests accepted +system.physmem.num_reads::total 7439 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3440429 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3980084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7420513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3440429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3440429 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3440429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3980084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7420513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7439 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7440 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7439 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 476160 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 476096 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 476160 # Total read bytes from the system interface side +system.physmem.bytesReadSys 476096 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -56,7 +56,7 @@ system.physmem.perBankRdBursts::10 339 # Pe system.physmem.perBankRdBursts::11 305 # Per bank write bursts system.physmem.perBankRdBursts::12 414 # Per bank write bursts system.physmem.perBankRdBursts::13 540 # Per bank write bursts -system.physmem.perBankRdBursts::14 454 # Per bank write bursts +system.physmem.perBankRdBursts::14 453 # Per bank write bursts system.physmem.perBankRdBursts::15 380 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 64188663500 # Total gap between requests +system.physmem.totGap 64159334500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7440 # Read request sizes (log2) +system.physmem.readPktSize::6 7439 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,11 +91,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1868 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 921 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1861 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1358 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 347.287187 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 206.380841 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 346.777138 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 443 32.62% 32.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 304 22.39% 55.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 160 11.78% 66.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 96 7.07% 73.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 54 3.98% 77.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 38 2.80% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 38 2.80% 83.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 25 1.84% 85.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 200 14.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1358 # Bytes accessed per row activation -system.physmem.totQLat 65294500 # Total ticks spent queuing -system.physmem.totMemAccLat 204794500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37200000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8776.14 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1349 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 352.640474 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 209.024877 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 349.175025 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 440 32.62% 32.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 302 22.39% 55.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 154 11.42% 66.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 83 6.15% 72.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 53 3.93% 76.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 50 3.71% 80.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 36 2.67% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 35 2.59% 85.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 196 14.53% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1349 # Bytes accessed per row activation +system.physmem.totQLat 63577500 # Total ticks spent queuing +system.physmem.totMemAccLat 203058750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37195000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8546.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27526.14 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27296.51 # Average memory access latency per DRAM burst system.physmem.avgRdBW 7.42 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 7.42 # Average system read bandwidth in MiByte/s @@ -217,75 +217,75 @@ system.physmem.busUtilRead 0.06 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6069 # Number of row buffer hits during reads +system.physmem.readRowHits 6088 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.84 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8627508.53 # Average gap between requests -system.physmem.pageHitRate 81.57 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5843880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3188625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 32221800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 8624725.70 # Average gap between requests +system.physmem.pageHitRate 81.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5821200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3176250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 32416800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4192060080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1996054785 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 36758466000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 42987835170 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.776911 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 61149211250 # Time in different power states -system.physmem_0.memoryStateTime::REF 2143180000 # Time in different power states +system.physmem_0.refreshEnergy 4190534400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1995176700 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 36745221000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 42972346350 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.779347 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 61126318750 # Time in different power states +system.physmem_0.memoryStateTime::REF 2142400000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 890802750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 890255000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4399920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2400750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 25217400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 4377240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2388375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 25560600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4192060080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1854861795 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 36882319500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 42961259445 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.362844 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 61355238000 # Time in different power states -system.physmem_1.memoryStateTime::REF 2143180000 # Time in different power states +system.physmem_1.refreshEnergy 4190534400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1859740425 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 36864024750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 42946625790 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.378459 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 61324552000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2142400000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 684265000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 692021750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 47858697 # Number of BP lookups -system.cpu.branchPred.condPredicted 27887013 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 573168 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 23334340 # Number of BTB lookups -system.cpu.branchPred.BTBHits 19575055 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 47856205 # Number of BP lookups +system.cpu.branchPred.condPredicted 27886274 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 572784 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 23348714 # Number of BTB lookups +system.cpu.branchPred.BTBHits 19574502 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.889474 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 8688210 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1446 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2339152 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2308305 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 30847 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 111425 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 83.835461 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 8687459 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1418 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 2338624 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2308001 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 30623 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 111239 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 98833092 # DTB read hits -system.cpu.dtb.read_misses 28443 # DTB read misses -system.cpu.dtb.read_acv 867 # DTB read access violations -system.cpu.dtb.read_accesses 98861535 # DTB read accesses -system.cpu.dtb.write_hits 75500788 # DTB write hits +system.cpu.dtb.read_hits 98829712 # DTB read hits +system.cpu.dtb.read_misses 28367 # DTB read misses +system.cpu.dtb.read_acv 845 # DTB read access violations +system.cpu.dtb.read_accesses 98858079 # DTB read accesses +system.cpu.dtb.write_hits 75499203 # DTB write hits system.cpu.dtb.write_misses 1454 # DTB write misses system.cpu.dtb.write_acv 3 # DTB write access violations -system.cpu.dtb.write_accesses 75502242 # DTB write accesses -system.cpu.dtb.data_hits 174333880 # DTB hits -system.cpu.dtb.data_misses 29897 # DTB misses -system.cpu.dtb.data_acv 870 # DTB access violations -system.cpu.dtb.data_accesses 174363777 # DTB accesses -system.cpu.itb.fetch_hits 46960311 # ITB hits -system.cpu.itb.fetch_misses 430 # ITB misses -system.cpu.itb.fetch_acv 5 # ITB acv -system.cpu.itb.fetch_accesses 46960741 # ITB accesses +system.cpu.dtb.write_accesses 75500657 # DTB write accesses +system.cpu.dtb.data_hits 174328915 # DTB hits +system.cpu.dtb.data_misses 29821 # DTB misses +system.cpu.dtb.data_acv 848 # DTB access violations +system.cpu.dtb.data_accesses 174358736 # DTB accesses +system.cpu.itb.fetch_hits 46955913 # ITB hits +system.cpu.itb.fetch_misses 420 # ITB misses +system.cpu.itb.fetch_acv 7 # ITB acv +system.cpu.itb.fetch_accesses 46956333 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,141 +299,141 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 128377521 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 128318893 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 47431154 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 424848239 # Number of instructions fetch has processed -system.cpu.fetch.Branches 47858697 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 30571570 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80009353 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1247564 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 47425719 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 424811206 # Number of instructions fetch has processed +system.cpu.fetch.Branches 47856205 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 30569962 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 79950349 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1246202 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 13 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 284 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 13513 # Number of stall cycles due to pending traps +system.cpu.fetch.MiscStallCycles 270 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 13187 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 60 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 46960311 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 225671 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 128078159 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.317101 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.349648 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 46955913 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 225768 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 128012699 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.318508 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.349839 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 53091522 41.45% 41.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4331488 3.38% 44.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6713646 5.24% 50.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5106781 3.99% 54.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 10967794 8.56% 62.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7526071 5.88% 68.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5305239 4.14% 72.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1848793 1.44% 74.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 33186825 25.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 53041219 41.43% 41.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4325218 3.38% 44.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6711253 5.24% 50.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5104898 3.99% 54.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 10968142 8.57% 62.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7524114 5.88% 68.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5300788 4.14% 72.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1845614 1.44% 74.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 33191453 25.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 128078159 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.372797 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.309366 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 42083889 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 13603478 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 67893810 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3877357 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 619625 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 8883159 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4198 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 421926458 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 13804 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 619625 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 43653235 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3048927 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 516546 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70101215 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10138611 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 419911173 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 439346 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2543427 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2848893 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3543199 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 273983157 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 552185759 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 393726185 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 158459573 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 128012699 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.372947 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.310590 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 42125446 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 13481218 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 67948873 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3838220 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 618942 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 8882912 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4201 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 421902807 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 13825 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 618942 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 43678343 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3058028 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 517106 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70134710 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10005570 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 419884966 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 437260 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2526892 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2765017 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 3520699 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 273968908 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 552151473 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 393698766 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 158452706 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14450838 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 14436589 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 37562 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 298 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 15867681 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 99739292 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 76524203 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 11895065 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9302116 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 392194254 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 15635470 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 99735139 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 76519296 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 11859955 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9294086 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 392181792 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 290 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 389210938 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 196221 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 16619749 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7681566 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 389203558 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 195886 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 16607287 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7664931 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 75 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 128078159 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.038855 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.181056 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 128012699 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.040351 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.180919 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17247166 13.47% 13.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19402738 15.15% 28.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22008781 17.18% 45.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17964276 14.03% 59.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 19060613 14.88% 74.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 13269746 10.36% 85.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8793023 6.87% 91.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6106038 4.77% 96.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4225778 3.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17224377 13.46% 13.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19358192 15.12% 28.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22001472 17.19% 45.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17955910 14.03% 59.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19066405 14.89% 74.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 13282652 10.38% 85.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8794829 6.87% 91.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6104058 4.77% 96.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4224804 3.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 128078159 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 128012699 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 255592 1.41% 1.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 138975 0.77% 2.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 79489 0.44% 2.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 3727 0.02% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 3445589 19.00% 21.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1648341 9.09% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 30.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8051616 44.40% 75.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4508979 24.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 256922 1.42% 1.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 1.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 138470 0.76% 2.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 78848 0.44% 2.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 3339 0.02% 2.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 3443164 19.01% 21.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1648895 9.10% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 30.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8039924 44.38% 75.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4505956 24.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 146987981 37.77% 37.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2128295 0.55% 38.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 146986421 37.77% 37.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2128250 0.55% 38.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 36418632 9.36% 47.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7354909 1.89% 49.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2800462 0.72% 50.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16556521 4.25% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1584140 0.41% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 36418938 9.36% 47.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7355017 1.89% 49.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2800646 0.72% 50.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16556809 4.25% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1584153 0.41% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.95% # Type of FU issued @@ -455,82 +455,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.95% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 99505104 25.57% 80.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 75841313 19.49% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 99502900 25.57% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 75836843 19.49% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 389210938 # Type of FU issued -system.cpu.iq.rate 3.031769 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18132308 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.046587 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 592570653 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 242193331 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 227932630 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 332257911 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 166691582 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 158290719 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 234731368 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 172578297 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19373689 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 389203558 # Type of FU issued +system.cpu.iq.rate 3.033096 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18115520 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.046545 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 592493180 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 242176639 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 227925873 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 332238041 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 166682962 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 158291544 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 234723560 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172561937 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19352464 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4984806 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 93159 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 70985 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3003475 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4980653 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 92349 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 70589 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2998568 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 382536 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3859 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 383293 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3853 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 619625 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1856570 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 132026 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 415917767 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 108843 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 99739292 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 76524203 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 618942 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1854909 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 149633 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 415904338 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 108226 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 99735139 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 76519296 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 290 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8227 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 123512 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 70985 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 411741 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 230567 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 642308 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 387626106 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 98862428 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1584832 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 7462 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 141873 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 70589 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 411438 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 230495 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 641933 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 387616397 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 98858950 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1587161 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 23723223 # number of nop insts executed -system.cpu.iew.exec_refs 174364706 # number of memory reference insts executed -system.cpu.iew.exec_branches 45864043 # Number of branches executed -system.cpu.iew.exec_stores 75502278 # Number of stores executed -system.cpu.iew.exec_rate 3.019424 # Inst execution rate -system.cpu.iew.wb_sent 386487511 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 386223349 # cumulative count of insts written-back -system.cpu.iew.wb_producers 192322376 # num instructions producing a value -system.cpu.iew.wb_consumers 273878502 # num instructions consuming a value -system.cpu.iew.wb_rate 3.008497 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.702218 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 17254297 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 23722256 # number of nop insts executed +system.cpu.iew.exec_refs 174359643 # number of memory reference insts executed +system.cpu.iew.exec_branches 45862472 # Number of branches executed +system.cpu.iew.exec_stores 75500693 # Number of stores executed +system.cpu.iew.exec_rate 3.020727 # Inst execution rate +system.cpu.iew.wb_sent 386480663 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 386217417 # cumulative count of insts written-back +system.cpu.iew.wb_producers 192328787 # num instructions producing a value +system.cpu.iew.wb_consumers 273868663 # num instructions consuming a value +system.cpu.iew.wb_rate 3.009825 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.702266 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 17240745 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 569011 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 125612042 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.173777 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.248518 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 568625 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 125549188 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.175366 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.248155 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 42074654 33.50% 33.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 17552788 13.97% 47.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 8725383 6.95% 54.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9055727 7.21% 61.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6223211 4.95% 66.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4119483 3.28% 69.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4738198 3.77% 73.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2406397 1.92% 75.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 30716201 24.45% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 42020703 33.47% 33.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 17522364 13.96% 47.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 8729636 6.95% 54.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9062074 7.22% 61.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6240745 4.97% 66.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4112376 3.28% 69.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4753795 3.79% 73.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2410879 1.92% 75.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 30696616 24.45% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 125612042 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 125549188 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664569 # Number of instructions committed system.cpu.commit.committedOps 398664569 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -576,33 +576,33 @@ system.cpu.commit.op_class_0::MemWrite 73520728 18.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 398664569 # Class of committed instruction -system.cpu.commit.bw_lim_events 30716201 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 510811730 # The number of ROB reads -system.cpu.rob.rob_writes 834310252 # The number of ROB writes -system.cpu.timesIdled 3164 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 299362 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 30696616 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 510754909 # The number of ROB reads +system.cpu.rob.rob_writes 834280363 # The number of ROB writes +system.cpu.timesIdled 3150 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 306194 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574794 # Number of Instructions Simulated system.cpu.committedOps 375574794 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.341816 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.341816 # CPI: Total CPI of All Threads -system.cpu.ipc 2.925550 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.925550 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 385452871 # number of integer regfile reads -system.cpu.int_regfile_writes 165252221 # number of integer regfile writes -system.cpu.fp_regfile_reads 154536644 # number of floating regfile reads -system.cpu.fp_regfile_writes 102074619 # number of floating regfile writes +system.cpu.cpi 0.341660 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.341660 # CPI: Total CPI of All Threads +system.cpu.ipc 2.926886 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.926886 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 385442521 # number of integer regfile reads +system.cpu.int_regfile_writes 165246956 # number of integer regfile writes +system.cpu.fp_regfile_reads 154535424 # number of floating regfile reads +system.cpu.fp_regfile_writes 102076666 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 776 # number of replacements -system.cpu.dcache.tags.tagsinuse 3292.009184 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 152572889 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4176 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 36535.653496 # Average number of references to valid blocks. +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 779 # number of replacements +system.cpu.dcache.tags.tagsinuse 3291.925722 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 152589979 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4179 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 36513.514956 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3292.009184 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803713 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803713 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.925722 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803693 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803693 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3400 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id @@ -610,45 +610,45 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 211 system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.830078 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 305192990 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 305192990 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 79071847 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 79071847 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501036 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501036 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 305227185 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 305227185 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 79088959 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 79088959 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501014 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501014 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 152572883 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 152572883 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 152572883 # number of overall hits -system.cpu.dcache.overall_hits::total 152572883 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1826 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1826 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19692 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19692 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21518 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21518 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21518 # number of overall misses -system.cpu.dcache.overall_misses::total 21518 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 128481000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 128481000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1201737956 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1201737956 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1330218956 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1330218956 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1330218956 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1330218956 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 79073673 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 79073673 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 152589973 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 152589973 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 152589973 # number of overall hits +system.cpu.dcache.overall_hits::total 152589973 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1810 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1810 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19714 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19714 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21524 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21524 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21524 # number of overall misses +system.cpu.dcache.overall_misses::total 21524 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 128203000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 128203000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1194602455 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1194602455 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1322805455 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1322805455 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1322805455 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1322805455 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 79090769 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 79090769 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520728 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520728 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 152594401 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 152594401 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 152594401 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 152594401 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 152611497 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 152611497 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 152611497 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 152611497 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000268 # miss rate for WriteReq accesses @@ -657,258 +657,257 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000141 system.cpu.dcache.demand_miss_rate::total 0.000141 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000141 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000141 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70361.993428 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70361.993428 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61026.709120 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61026.709120 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61818.893763 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61818.893763 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61818.893763 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61818.893763 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 50592 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 80 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 740 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70830.386740 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70830.386740 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60596.654915 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60596.654915 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61457.231695 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61457.231695 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61457.231695 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61457.231695 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 49869 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 82 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 741 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.367568 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 80 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 655 # number of writebacks -system.cpu.dcache.writebacks::total 655 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 838 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 838 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16504 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16504 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17342 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17342 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17342 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17342 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 988 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 988 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3188 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3188 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4176 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4176 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4176 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4176 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 74762500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 74762500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 249321500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 249321500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 324084000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 324084000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 324084000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 324084000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 67.299595 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 82 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 658 # 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number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4179 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4179 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4179 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4179 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76039500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 76039500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 251163000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 251163000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 327202500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 327202500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 327202500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 327202500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000013 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000013 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75670.546559 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75670.546559 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78206.242158 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78206.242158 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77606.321839 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77606.321839 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77606.321839 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77606.321839 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 2132 # number of replacements -system.cpu.icache.tags.tagsinuse 1831.246133 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 46954666 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4060 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11565.188670 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76885.237614 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76885.237614 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78734.482759 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78734.482759 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78296.841350 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78296.841350 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78296.841350 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78296.841350 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 2131 # number of replacements +system.cpu.icache.tags.tagsinuse 1829.791655 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 46950265 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4058 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11569.804091 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1831.246133 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894163 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894163 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1928 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1346 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 93924682 # Number of tag accesses -system.cpu.icache.tags.data_accesses 93924682 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 46954666 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 46954666 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 46954666 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 46954666 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 46954666 # number of overall hits -system.cpu.icache.overall_hits::total 46954666 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5645 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5645 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5645 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5645 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5645 # number of overall misses -system.cpu.icache.overall_misses::total 5645 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 370489499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 370489499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 370489499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 370489499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 370489499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 370489499 # 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Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 297 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1343 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.940918 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 93915884 # Number of tag accesses +system.cpu.icache.tags.data_accesses 93915884 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 46950265 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 46950265 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 46950265 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 46950265 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 46950265 # 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number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 373323999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 46955913 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 46955913 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 46955913 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 46955913 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 46955913 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 46955913 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000120 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000120 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000120 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000120 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 66098.441749 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 66098.441749 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 66098.441749 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 66098.441749 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 575 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 62 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63.888889 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.849926 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.954774 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.903120 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.849926 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.954774 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.903120 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78525.575448 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78525.575448 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76940.852421 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76940.852421 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84840.487239 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84840.487239 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76940.852421 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79889.849624 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78522.583681 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76940.852421 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79889.849624 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78522.583681 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -917,116 +916,122 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3128 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3128 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3450 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3450 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3449 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3449 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 862 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 862 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3450 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3449 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 3990 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7440 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3450 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7439 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3449 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3990 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7440 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 212530500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 212530500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 228307000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 228307000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 63243500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 63243500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 228307000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 275774000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 504081000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 228307000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 275774000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 504081000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981179 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981179 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.849754 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.849754 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.872470 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.872470 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.849754 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955460 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.903351 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.849754 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955460 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.903351 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67944.533248 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67944.533248 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66175.942029 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66175.942029 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73368.329466 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73368.329466 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66175.942029 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69116.290727 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67752.822581 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66175.942029 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69116.290727 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67752.822581 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 11144 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2908 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_misses::total 7439 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 214348000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 214348000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 230879000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 230879000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 64512500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 64512500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 230879000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 278860500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 509739500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 230879000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 278860500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 509739500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980564 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980564 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.849926 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.849926 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.871587 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.871587 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.849926 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.954774 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.903120 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.849926 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.954774 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.903120 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68525.575448 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68525.575448 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66940.852421 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66940.852421 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74840.487239 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74840.487239 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66940.852421 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69889.849624 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68522.583681 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66940.852421 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69889.849624 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68522.583681 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 11147 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2910 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 5048 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 655 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2132 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 5047 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 658 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2131 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 121 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3188 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3188 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4060 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 988 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10252 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9128 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 19380 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 396288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 705472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 3190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4058 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 989 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10247 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9137 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 19384 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 396096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 705664 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 8236 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 8237 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 8236 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 8237 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8236 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 8359000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 8237 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 8362500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6090499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6087499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6264000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6268500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4312 # Transaction distribution +system.membus.snoop_filter.tot_requests 7439 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 64159445000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 4311 # Transaction distribution system.membus.trans_dist::ReadExReq 3128 # Transaction distribution system.membus.trans_dist::ReadExResp 3128 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4312 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14880 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14880 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476160 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 476160 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 4311 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14878 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14878 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 476096 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 7440 # Request fanout histogram +system.membus.snoop_fanout::samples 7439 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7440 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7439 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7440 # Request fanout histogram -system.membus.reqLayer0.occupancy 9246500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7439 # Request fanout histogram +system.membus.reqLayer0.occupancy 9245500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 39238750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 39234750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 9532c68be..33645e09f 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.567385 # Number of seconds simulated -sim_ticks 567385356500 # Number of ticks simulated -final_tick 567385356500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.567393 # Number of seconds simulated +sim_ticks 567392530500 # Number of ticks simulated +final_tick 567392530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1154582 # Simulator instruction rate (inst/s) -host_op_rate 1154582 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1643217424 # Simulator tick rate (ticks/s) -host_mem_usage 254440 # Number of bytes of host memory used -host_seconds 345.29 # Real time elapsed on the host +host_inst_rate 646502 # Simulator instruction rate (inst/s) +host_op_rate 646502 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 920122456 # Simulator tick rate (ticks/s) +host_mem_usage 259072 # Number of bytes of host memory used +host_seconds 616.65 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory system.physmem.bytes_read::total 459136 # Number of bytes read from this memory @@ -22,15 +22,15 @@ system.physmem.bytes_inst_read::total 205120 # Nu system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 361518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 447696 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 809214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 361518 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 361518 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 361518 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 447696 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 809214 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 361513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 447690 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 809203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 361513 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 361513 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 361513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 447690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 809203 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -65,8 +65,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 567385356500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1134770713 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 567392530500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1134785061 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664609 # Number of instructions committed @@ -85,7 +85,7 @@ system.cpu.num_mem_refs 168275276 # nu system.cpu.num_load_insts 94754511 # Number of load instructions system.cpu.num_store_insts 73520765 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1134770713 # Number of busy cycles +system.cpu.num_busy_cycles 1134785061 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 44587535 # Number of branches fetched @@ -124,16 +124,16 @@ system.cpu.op_class::MemWrite 73520765 18.44% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 398664665 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 764 # number of replacements -system.cpu.dcache.tags.tagsinuse 3288.807028 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3288.789389 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3288.807028 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.802931 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.802931 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3288.789389 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.802927 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.802927 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id @@ -143,7 +143,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 3112 system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 336554592 # Number of tag accesses system.cpu.dcache.tags.data_accesses 336554592 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 4152 # n system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses system.cpu.dcache.overall_misses::total 4152 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 52888500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 52888500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 195593000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 195593000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 248481500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 248481500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 248481500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 248481500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 53715500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 53715500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 198735000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 198735000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 252450500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 252450500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 252450500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 252450500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55672.105263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55672.105263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61084.634603 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61084.634603 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59846.218690 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59846.218690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59846.218690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59846.218690 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56542.631579 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56542.631579 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62065.896315 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62065.896315 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60802.143545 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60802.143545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60802.143545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60802.143545 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -208,14 +208,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51938500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 51938500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 192391000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 192391000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 244329500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 244329500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 244329500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 244329500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52765500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 52765500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 195533000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 195533000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 248298500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 248298500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 248298500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 248298500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -224,34 +224,34 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54672.105263 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54672.105263 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60084.634603 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60084.634603 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55542.631579 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55542.631579 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61065.896315 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61065.896315 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59802.143545 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 59802.143545 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59802.143545 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 59802.143545 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1769 # number of replacements -system.cpu.icache.tags.tagsinuse 1795.084430 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1795.076643 # Cycle average of tags in use system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1795.084430 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.876506 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.876506 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1795.076643 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.876502 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.876502 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1904 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 251 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1375 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.929688 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 797333005 # Number of tag accesses system.cpu.icache.tags.data_accesses 797333005 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits @@ -264,12 +264,12 @@ system.cpu.icache.demand_misses::cpu.inst 3673 # n system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses system.cpu.icache.overall_misses::total 3673 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 204815000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 204815000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 204815000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 204815000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 204815000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 204815000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 208020000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 208020000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 208020000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 208020000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 208020000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 208020000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses @@ -282,12 +282,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55762.319630 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55762.319630 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55762.319630 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55762.319630 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55762.319630 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55762.319630 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56634.903349 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56634.903349 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56634.903349 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56634.903349 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56634.903349 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56634.903349 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -302,48 +302,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3673 system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 201142000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 201142000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 201142000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 201142000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 201142000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 201142000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 204347000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 204347000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 204347000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 204347000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 204347000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 204347000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54762.319630 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54762.319630 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55634.903349 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55634.903349 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55634.903349 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 55634.903349 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55634.903349 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 55634.903349 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3772.330397 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2561 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.560885 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 6481.659208 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3184 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 7174 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.443825 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 371.516873 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.363420 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 630.450105 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011338 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084545 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.019240 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.115122 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4566 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 497 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3787 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.139343 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 90632 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 90632 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.348214 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3711.310994 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084544 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.113260 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.197805 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 7174 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 392 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6535 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.218933 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 90038 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 90038 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 649 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 649 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1769 # number of WritebackClean hits @@ -372,18 +370,18 @@ system.cpu.l2cache.demand_misses::total 7174 # nu system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7174 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 186953000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 186953000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 190709000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 190709000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49213500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 49213500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 190709000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 236166500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 426875500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 190709000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 236166500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 426875500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 190095000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 190095000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 193914000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 193914000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50040500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 50040500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 193914000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 240135500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 434049500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 193914000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 240135500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 434049500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 649 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 649 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 1769 # number of WritebackClean accesses(hits+misses) @@ -412,18 +410,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.916805 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.273074 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.273074 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.588144 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.588144 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59508.464329 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59508.464329 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.588144 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59502.771479 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59503.136326 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.588144 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59502.771479 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59503.136326 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60501.273074 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60501.273074 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.588144 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.588144 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60508.464329 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60508.464329 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.588144 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60502.771479 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60503.136326 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.588144 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60502.771479 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60503.136326 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -442,18 +440,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7174 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 155533000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 155533000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 158659000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 158659000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 40943500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 40943500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 158659000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 196476500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 355135500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 158659000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 196476500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 355135500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 158675000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158675000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 161864000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 161864000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 41770500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 41770500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 161864000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 200445500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 362309500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 161864000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 200445500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 362309500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadCleanReq accesses @@ -466,25 +464,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.273074 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.273074 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.588144 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.588144 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49508.464329 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49508.464329 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.588144 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49502.771479 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.136326 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.588144 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49502.771479 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.136326 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50501.273074 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50501.273074 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.588144 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.588144 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50508.464329 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50508.464329 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.588144 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50502.771479 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50503.136326 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.588144 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50502.771479 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50503.136326 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 10358 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2533 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 649 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1769 # Transaction distribution @@ -518,7 +516,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 5509500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 7174 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4032 # Transaction distribution system.membus.trans_dist::ReadExReq 3142 # Transaction distribution system.membus.trans_dist::ReadExResp 3142 # Transaction distribution diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 0b49d498f..a1a985a56 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.225030 # Number of seconds simulated -sim_ticks 225030243000 # Number of ticks simulated -final_tick 225030243000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.225041 # Number of seconds simulated +sim_ticks 225040911000 # Number of ticks simulated +final_tick 225040911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131394 # Simulator instruction rate (inst/s) -host_op_rate 157754 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 108291606 # Simulator tick rate (ticks/s) -host_mem_usage 275248 # Number of bytes of host memory used -host_seconds 2078.00 # Real time elapsed on the host +host_inst_rate 161529 # Simulator instruction rate (inst/s) +host_op_rate 193933 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 133133968 # Simulator tick rate (ticks/s) +host_mem_usage 280148 # Number of bytes of host memory used +host_seconds 1690.33 # Real time elapsed on the host sim_insts 273037855 # Number of instructions simulated sim_ops 327812212 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory system.physmem.bytes_read::total 485568 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 219136 # Nu system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4163 # Number of read requests responded to by this memory system.physmem.num_reads::total 7587 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 973807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1183983 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2157790 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 973807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 973807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 973807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1183983 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2157790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 973761 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1183927 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2157688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 973761 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 973761 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 973761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1183927 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2157688 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7587 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7587 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 225029996000 # Total gap between requests +system.physmem.totGap 225040663000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1511 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 320.084712 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.611752 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 331.049486 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 552 36.53% 36.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 328 21.71% 58.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 178 11.78% 70.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 86 5.69% 75.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 72 4.77% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 49 3.24% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 32 2.12% 85.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 31 2.05% 87.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 183 12.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1511 # Bytes accessed per row activation -system.physmem.totQLat 51456750 # Total ticks spent queuing -system.physmem.totMemAccLat 193713000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1537 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 314.836695 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 187.294672 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.034747 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 563 36.63% 36.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 357 23.23% 59.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 158 10.28% 70.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 85 5.53% 75.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 84 5.47% 81.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 48 3.12% 84.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 39 2.54% 86.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 28 1.82% 88.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 175 11.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1537 # Bytes accessed per row activation +system.physmem.totQLat 55497500 # Total ticks spent queuing +system.physmem.totMemAccLat 197753750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37935000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6782.23 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7314.81 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25532.23 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26064.81 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s @@ -217,48 +217,48 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6068 # Number of row buffer hits during reads +system.physmem.readRowHits 6044 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.98 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.66 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 29659944.11 # Average gap between requests -system.physmem.pageHitRate 79.98 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 29881800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 29661350.07 # Average gap between requests +system.physmem.pageHitRate 79.66 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5110560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2788500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29967600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14697384000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5831471925 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 129898404750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 150464889630 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.664832 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 216095628500 # Time in different power states -system.physmem_0.memoryStateTime::REF 7514000000 # Time in different power states +system.physmem_0.refreshEnergy 14698401120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5878157490 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 129866796000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 150481221270 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.691134 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 216043617250 # Time in different power states +system.physmem_0.memoryStateTime::REF 7514520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1413270250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1481090250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6380640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3481500 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 6501600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3547500 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 29000400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14697384000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6004643625 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 129746499750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 150487389915 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.764823 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 215845139250 # Time in different power states -system.physmem_1.memoryStateTime::REF 7514000000 # Time in different power states +system.physmem_1.refreshEnergy 14698401120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6069721950 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 129698757000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 150505929570 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.800930 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 215760799500 # Time in different power states +system.physmem_1.memoryStateTime::REF 7514520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1668675750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1763151750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 32430290 # Number of BP lookups +system.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 32430292 # Number of BP lookups system.cpu.branchPred.condPredicted 16924100 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 738493 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17494980 # Number of BTB lookups -system.cpu.branchPred.BTBHits 12858502 # Number of BTB hits +system.cpu.branchPred.BTBLookups 17494982 # Number of BTB lookups +system.cpu.branchPred.BTBHits 12858504 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 73.498238 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 73.498241 # BTB Hit Percentage system.cpu.branchPred.usedRAS 6523127 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 2303930 # Number of indirect predictor lookups. @@ -266,7 +266,7 @@ system.cpu.branchPred.indirectHits 2264813 # Nu system.cpu.branchPred.indirectMisses 39117 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 128237 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,16 +387,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 225030243000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 450060486 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 450081822 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037855 # Number of instructions committed system.cpu.committedOps 327812212 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2063972 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2063975 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.648345 # CPI: cycles per instruction -system.cpu.ipc 0.606669 # IPC: instructions per cycle +system.cpu.cpi 1.648423 # CPI: cycles per instruction +system.cpu.ipc 0.606640 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 104312542 31.82% 31.82% # Class of committed instruction system.cpu.op_class_0::IntMult 2145905 0.65% 32.48% # Class of committed instruction @@ -432,18 +432,18 @@ system.cpu.op_class_0::MemWrite 82375599 25.13% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 327812212 # Class of committed instruction -system.cpu.tickCycles 434886518 # Number of cycles that the object actually ticked -system.cpu.idleCycles 15173968 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 434887274 # Number of cycles that the object actually ticked +system.cpu.idleCycles 15194548 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1355 # number of replacements -system.cpu.dcache.tags.tagsinuse 3086.261687 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168654217 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3086.207714 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168654219 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37379.037456 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37379.037899 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3086.261687 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.753482 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.753482 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3086.207714 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.753469 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753469 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id @@ -451,43 +451,43 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 7 system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337326818 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337326818 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 86521433 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86521433 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82047456 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047456 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 337326820 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337326820 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 86521434 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86521434 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047457 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047457 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 63538 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 63538 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168568889 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168568889 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168632427 # number of overall hits -system.cpu.dcache.overall_hits::total 168632427 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168568891 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168568891 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168632429 # number of overall hits +system.cpu.dcache.overall_hits::total 168632429 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1710 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1710 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5221 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5221 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5220 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5220 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 6931 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6931 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6936 # number of overall misses -system.cpu.dcache.overall_misses::total 6936 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 114932500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 114932500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 393586500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 393586500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 508519000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 508519000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 508519000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 508519000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86523143 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86523143 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 6930 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6930 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 6935 # number of overall misses +system.cpu.dcache.overall_misses::total 6935 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 116252000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 116252000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 401349000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 401349000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 517601000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 517601000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 517601000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 517601000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86523144 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86523144 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 63543 # number of SoftPFReq accesses(hits+misses) @@ -496,10 +496,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168575820 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168575820 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168639363 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168639363 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168575821 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168575821 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168639364 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168639364 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses @@ -510,14 +510,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000041 system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000041 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67211.988304 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67211.988304 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75385.271021 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75385.271021 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73368.777954 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73368.777954 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73315.888120 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73315.888120 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67983.625731 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67983.625731 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76886.781609 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76886.781609 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74689.898990 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74689.898990 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74636.049027 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74636.049027 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -528,12 +528,12 @@ system.cpu.dcache.writebacks::writebacks 1010 # nu system.cpu.dcache.writebacks::total 1010 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 71 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2351 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2351 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2422 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2422 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2422 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2422 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2350 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2350 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2421 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2421 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2421 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2421 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1639 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1639 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses @@ -544,16 +544,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4509 system.cpu.dcache.demand_mshr_misses::total 4509 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4512 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4512 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 110662500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 110662500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219478500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 219478500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 238000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 238000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 330141000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 330141000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 330379000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 330379000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 111802000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 111802000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 223602000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 223602000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 241000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 241000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 335404000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 335404000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 335645000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 335645000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -564,72 +564,72 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67518.303844 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67518.303844 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76473.344948 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76473.344948 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73218.230206 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73218.230206 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73222.296099 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73222.296099 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68213.544844 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68213.544844 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77910.104530 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77910.104530 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74385.451320 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74385.451320 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74389.406028 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74389.406028 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 38188 # number of replacements -system.cpu.icache.tags.tagsinuse 1925.010528 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 69819783 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1924.983594 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 69819782 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 40125 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1740.056897 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1740.056872 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1925.010528 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939947 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939947 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.983594 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939933 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939933 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 277 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 139759943 # Number of tag accesses -system.cpu.icache.tags.data_accesses 139759943 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 69819783 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 69819783 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 69819783 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 69819783 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 69819783 # number of overall hits -system.cpu.icache.overall_hits::total 69819783 # number of overall hits +system.cpu.icache.tags.tag_accesses 139759941 # Number of tag accesses +system.cpu.icache.tags.data_accesses 139759941 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 69819782 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 69819782 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 69819782 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 69819782 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 69819782 # number of overall hits +system.cpu.icache.overall_hits::total 69819782 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 40126 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 40126 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 40126 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 40126 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 40126 # number of overall misses system.cpu.icache.overall_misses::total 40126 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 756662500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 756662500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 756662500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 756662500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 756662500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 756662500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 69859909 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 69859909 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 69859909 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 69859909 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 69859909 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 69859909 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 763080000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 763080000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 763080000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 763080000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 763080000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 763080000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 69859908 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 69859908 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 69859908 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 69859908 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 69859908 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 69859908 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000574 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000574 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000574 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000574 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000574 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000574 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18857.162438 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18857.162438 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18857.162438 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18857.162438 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18857.162438 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18857.162438 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19017.096147 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19017.096147 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19017.096147 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19017.096147 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19017.096147 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19017.096147 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -644,48 +644,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 40126 system.cpu.icache.demand_mshr_misses::total 40126 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 40126 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 40126 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 716537500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 716537500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 716537500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 716537500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 716537500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 716537500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 722955000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 722955000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 722955000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 722955000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 722955000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 722955000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000574 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000574 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000574 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17857.187360 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17857.187360 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17857.187360 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17857.187360 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17857.187360 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17857.187360 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18017.121069 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18017.121069 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18017.121069 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18017.121069 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18017.121069 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18017.121069 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4201.230054 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 60569 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5649 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.722075 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 6597.313111 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 61516 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 7587 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 8.108080 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 354.127692 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3168.434045 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 678.668317 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.010807 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096693 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.020711 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.128211 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5649 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3168.373403 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.939708 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096691 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.104643 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.201334 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 7587 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1257 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4262 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172394 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 561687 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 561687 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 789 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6671 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.231537 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 560755 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 560755 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 1010 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 1010 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 23270 # number of WritebackClean hits @@ -714,18 +712,18 @@ system.cpu.l2cache.demand_misses::total 7630 # nu system.cpu.l2cache.overall_misses::cpu.inst 3426 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses system.cpu.l2cache.overall_misses::total 7630 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214976500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 214976500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 256075000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 256075000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 105174500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 105174500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 256075000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 320151000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 576226000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 256075000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 320151000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 576226000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 219100000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 219100000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 262492500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 262492500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106317000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 106317000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 262492500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 325417000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 587909500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 262492500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 325417000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 587909500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 1010 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 1010 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 23270 # number of WritebackClean accesses(hits+misses) @@ -754,18 +752,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.170931 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085381 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.931738 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.170931 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75324.632095 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75324.632095 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74744.600117 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74744.600117 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77907.037037 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77907.037037 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74744.600117 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76153.901047 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75521.100917 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74744.600117 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76153.901047 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75521.100917 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76769.446391 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76769.446391 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76617.775832 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76617.775832 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78753.333333 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78753.333333 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76617.775832 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77406.517602 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77052.359109 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76617.775832 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77406.517602 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77052.359109 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -794,18 +792,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7587 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3424 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4163 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7587 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 186436500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 186436500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 221700500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 221700500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 89390500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 89390500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 221700500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 275827000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 497527500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 221700500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 275827000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 497527500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 190560000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 190560000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 228116000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 228116000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90492000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90492000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 228116000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 281052000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 509168000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 228116000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 281052000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 509168000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for ReadCleanReq accesses @@ -818,25 +816,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.169967 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.169967 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65324.632095 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65324.632095 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64748.977804 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64748.977804 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68289.152024 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68289.152024 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64748.977804 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66256.785972 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65576.314749 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64748.977804 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66256.785972 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65576.314749 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66769.446391 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66769.446391 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66622.663551 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66622.663551 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69130.634072 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69130.634072 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66622.663551 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67511.890464 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67110.583894 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66622.663551 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67511.890464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67110.583894 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 84181 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 39645 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15035 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 41767 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 38188 # Transaction distribution @@ -870,7 +868,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 60188498 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6789457 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 225030243000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 7587 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 225040911000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4733 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution @@ -891,9 +895,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7587 # Request fanout histogram -system.membus.reqLayer0.occupancy 9083500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9083000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40284000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40294250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 01e70293e..3bab29953 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.111754 # Number of seconds simulated -sim_ticks 111753553500 # Number of ticks simulated -final_tick 111753553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.120480 # Number of seconds simulated +sim_ticks 120480458500 # Number of ticks simulated +final_tick 120480458500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 142273 # Simulator instruction rate (inst/s) -host_op_rate 170814 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58231903 # Simulator tick rate (ticks/s) -host_mem_usage 288696 # Number of bytes of host memory used -host_seconds 1919.11 # Real time elapsed on the host -sim_insts 273037220 # Number of instructions simulated -sim_ops 327811602 # Number of ops (including micro ops) simulated +host_inst_rate 129515 # Simulator instruction rate (inst/s) +host_op_rate 155497 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57149813 # Simulator tick rate (ticks/s) +host_mem_usage 293332 # Number of bytes of host memory used +host_seconds 2108.15 # Real time elapsed on the host +sim_insts 273037218 # Number of instructions simulated +sim_ops 327811600 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 620544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 4626112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 168832 # Number of bytes read from this memory -system.physmem.bytes_read::total 5415488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 620544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 620544 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 9696 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 72283 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2638 # Number of read requests responded to by this memory -system.physmem.num_reads::total 84617 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 5552790 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 41395659 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1510753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48459202 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5552790 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5552790 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5552790 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 41395659 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1510753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 48459202 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 84617 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1888064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 14651392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 167808 # Number of bytes read from this memory +system.physmem.bytes_read::total 16707264 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1888064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1888064 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 29501 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 228928 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2622 # Number of read requests responded to by this memory +system.physmem.num_reads::total 261051 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 15671122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 121608037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1392823 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 138671982 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 15671122 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 15671122 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 15671122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 121608037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1392823 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 138671982 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 261052 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 84617 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 261052 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5415488 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 16707328 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5415488 # Total read bytes from the system interface side +system.physmem.bytesReadSys 16707328 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 956 # Per bank write bursts -system.physmem.perBankRdBursts::1 811 # Per bank write bursts -system.physmem.perBankRdBursts::2 834 # Per bank write bursts -system.physmem.perBankRdBursts::3 2907 # Per bank write bursts -system.physmem.perBankRdBursts::4 10637 # Per bank write bursts -system.physmem.perBankRdBursts::5 59817 # Per bank write bursts -system.physmem.perBankRdBursts::6 152 # Per bank write bursts -system.physmem.perBankRdBursts::7 259 # Per bank write bursts -system.physmem.perBankRdBursts::8 225 # Per bank write bursts -system.physmem.perBankRdBursts::9 303 # Per bank write bursts -system.physmem.perBankRdBursts::10 3870 # Per bank write bursts -system.physmem.perBankRdBursts::11 811 # Per bank write bursts -system.physmem.perBankRdBursts::12 1141 # Per bank write bursts -system.physmem.perBankRdBursts::13 693 # Per bank write bursts -system.physmem.perBankRdBursts::14 638 # Per bank write bursts -system.physmem.perBankRdBursts::15 563 # Per bank write bursts +system.physmem.perBankRdBursts::0 1258 # Per bank write bursts +system.physmem.perBankRdBursts::1 69992 # Per bank write bursts +system.physmem.perBankRdBursts::2 1296 # Per bank write bursts +system.physmem.perBankRdBursts::3 10757 # Per bank write bursts +system.physmem.perBankRdBursts::4 42908 # Per bank write bursts +system.physmem.perBankRdBursts::5 121820 # Per bank write bursts +system.physmem.perBankRdBursts::6 160 # Per bank write bursts +system.physmem.perBankRdBursts::7 266 # Per bank write bursts +system.physmem.perBankRdBursts::8 224 # Per bank write bursts +system.physmem.perBankRdBursts::9 562 # Per bank write bursts +system.physmem.perBankRdBursts::10 7776 # Per bank write bursts +system.physmem.perBankRdBursts::11 812 # Per bank write bursts +system.physmem.perBankRdBursts::12 1213 # Per bank write bursts +system.physmem.perBankRdBursts::13 743 # Per bank write bursts +system.physmem.perBankRdBursts::14 656 # Per bank write bursts +system.physmem.perBankRdBursts::15 609 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 111753395000 # Total gap between requests +system.physmem.totGap 120480449000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 84617 # Read request sizes (log2) +system.physmem.readPktSize::6 261052 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,19 +95,19 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 64967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 17796 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 204297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 43283 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12075 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 234 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 53 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 216 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 21 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see @@ -191,86 +191,86 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 21291 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 254.217463 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 213.921670 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 155.515771 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 2572 12.08% 12.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 7102 33.36% 45.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8141 38.24% 83.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1445 6.79% 90.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1060 4.98% 95.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 699 3.28% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 33 0.15% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 27 0.13% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 212 1.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 21291 # Bytes accessed per row activation -system.physmem.totQLat 818886094 # Total ticks spent queuing -system.physmem.totMemAccLat 2405454844 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 423085000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9677.56 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 67045 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 249.160415 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.717328 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 205.520754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18369 27.40% 27.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 21159 31.56% 58.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11457 17.09% 76.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6629 9.89% 85.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4618 6.89% 92.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2220 3.31% 96.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1372 2.05% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 491 0.73% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 730 1.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67045 # Bytes accessed per row activation +system.physmem.totQLat 2500931533 # Total ticks spent queuing +system.physmem.totMemAccLat 7395656533 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1305260000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9580.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28427.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 48.46 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28330.20 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 138.67 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 48.46 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 138.67 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.38 # Data bus utilization in percentage -system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.08 # Data bus utilization in percentage +system.physmem.busUtilRead 1.08 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 63316 # Number of row buffer hits during reads +system.physmem.readRowHits 193998 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.83 # Row buffer hit rate for reads +system.physmem.readRowHitRate 74.31 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1320696.73 # Average gap between requests -system.physmem.pageHitRate 74.83 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 137093040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 74802750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 595467600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 461518.97 # Average gap between requests +system.physmem.pageHitRate 74.31 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 469687680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 256278000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1937777400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 7298853120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 61580578995 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 13031079750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 82717875255 # Total energy per rank (pJ) -system.physmem_0.averagePower 740.214288 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 21327892271 # Time in different power states -system.physmem_0.memoryStateTime::REF 3731520000 # Time in different power states +system.physmem_0.refreshEnergy 7868948880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 73664414550 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 7668236250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 91865342760 # Total energy per rank (pJ) +system.physmem_0.averagePower 762.514125 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12350213739 # Time in different power states +system.physmem_0.memoryStateTime::REF 4022980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 86689152979 # Time in different power states +system.physmem_0.memoryStateTime::ACT 104104852261 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 23821560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 12997875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 64092600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 37134720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 20262000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 98069400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 7298853120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10878672015 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 57506417250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 75784854420 # Total energy per rank (pJ) -system.physmem_1.averagePower 678.173227 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 95612479879 # Time in different power states -system.physmem_1.memoryStateTime::REF 3731520000 # Time in different power states +system.physmem_1.refreshEnergy 7868948880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 16939770435 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 57426696000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 82390881435 # Total energy per rank (pJ) +system.physmem_1.averagePower 683.872818 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 95444315624 # Time in different power states +system.physmem_1.memoryStateTime::REF 4022980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 12405217621 # Time in different power states +system.physmem_1.memoryStateTime::ACT 21009739880 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 35971731 # Number of BP lookups -system.cpu.branchPred.condPredicted 19265386 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 984189 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17894968 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13923402 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 35971487 # Number of BP lookups +system.cpu.branchPred.condPredicted 19266966 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 984300 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17894295 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13923321 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 77.806241 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6951964 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4431 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2517343 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2473442 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 43901 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 128855 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 77.808715 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6951891 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4417 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 2517210 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2473355 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 43855 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 128902 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -300,7 +300,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +330,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +360,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -391,131 +391,131 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 223507108 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 240960918 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12083599 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 309381854 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35971731 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23348808 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 209499863 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1989645 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1258 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 12852393 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 309387545 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35971487 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23348567 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 224289895 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1990323 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1871 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 93 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 2666 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 82203342 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 33398 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 222582301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.671920 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.267628 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3026 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 82204082 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34266 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 238142439 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.562665 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.293284 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 62373241 28.02% 28.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 40203334 18.06% 46.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 28080746 12.62% 58.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 91924980 41.30% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 77933727 32.73% 32.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 40203358 16.88% 49.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28082672 11.79% 61.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 91922682 38.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 222582301 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.160942 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.384215 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 26238985 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 73050782 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 98117127 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 24314460 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 860947 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6686817 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 134221 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 348541423 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3410145 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 860947 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42548430 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 23450678 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 285531 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 105165670 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 50271045 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 344601348 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1453656 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7084396 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 85832 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7483674 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 23725025 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 3279176 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 394880845 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2218133140 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 335914250 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 192916662 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22650794 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11588 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11554 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 57533645 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89989968 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 84391268 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1975718 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1902358 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343283622 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22608 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 339469619 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 966789 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 15494628 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 37288530 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 488 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 222582301 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.525142 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.109331 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 238142439 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.149283 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.283974 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 26809492 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 87975457 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 98235303 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 24260898 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 861289 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6686645 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 134215 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 348536073 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3411178 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 861289 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 43087679 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 34729777 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 287359 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 105264108 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53912227 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 344595535 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1451317 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7117459 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 85486 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7456793 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 27429966 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 3277218 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 394867605 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2218081796 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 335910446 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 192911530 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 372230048 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 22637557 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11606 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11573 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 57394706 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89984018 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 84392471 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1976841 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1898355 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343274386 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22623 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 339465004 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 967637 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 15485409 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 37250778 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 503 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 238142439 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.425470 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.136916 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 42440680 19.07% 19.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 76122495 34.20% 53.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 59389973 26.68% 79.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34692267 15.59% 95.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9226095 4.15% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 678749 0.30% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 32042 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 57979720 24.35% 24.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 76155774 31.98% 56.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 59457503 24.97% 81.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34550396 14.51% 95.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9286722 3.90% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 677796 0.28% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34528 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 222582301 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 238142439 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9228112 7.75% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7358 0.01% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 237798 0.20% 7.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 147681 0.12% 8.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 70485 0.06% 8.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 67886 0.06% 8.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 638269 0.54% 8.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 297789 0.25% 8.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 542439 0.46% 9.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 51542568 43.28% 52.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 56315471 47.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9217758 7.75% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7319 0.01% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 238781 0.20% 7.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 138932 0.12% 8.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 70694 0.06% 8.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 68373 0.06% 8.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 637081 0.54% 8.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 296736 0.25% 8.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 541785 0.46% 9.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 51510154 43.32% 52.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 56187310 47.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 108184507 31.87% 31.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148145 0.63% 32.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 108183295 31.87% 31.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148337 0.63% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.50% # Type of FU issued @@ -534,103 +534,103 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.50% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6792731 2.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6792696 2.00% 34.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8635726 2.54% 37.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3210403 0.95% 37.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592905 0.47% 38.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20864008 6.15% 44.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7178651 2.11% 46.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7141492 2.10% 48.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175295 0.05% 48.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 90027492 26.52% 75.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 83518264 24.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8634939 2.54% 37.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3210556 0.95% 37.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592986 0.47% 38.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20863290 6.15% 44.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7179112 2.11% 46.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7141893 2.10% 48.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175297 0.05% 48.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 90024001 26.52% 75.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 83518602 24.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 339469619 # Type of FU issued -system.cpu.iq.rate 1.518831 # Inst issue rate -system.cpu.iq.fu_busy_cnt 119095856 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.350829 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 738018306 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 235153924 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 219171367 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 283565878 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 123658767 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 116921576 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 293614389 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 164951086 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5389138 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 339465004 # Type of FU issued +system.cpu.iq.rate 1.408797 # Inst issue rate +system.cpu.iq.fu_busy_cnt 118914923 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.350301 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 753593457 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 235149136 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 219170609 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 283361550 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 123645361 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 116917491 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 293630516 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 164749411 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5409371 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4257693 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7295 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11836 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2015651 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4251743 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7382 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12082 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2016854 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 126905 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 613909 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 126951 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 613385 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 860947 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1344821 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 736472 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343307622 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 861289 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1346418 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1223561 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343298428 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89989968 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 84391268 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11575 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7371 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 729404 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11836 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 437891 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 454375 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 892266 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 337441545 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 89439870 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2028074 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 89984018 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 84392471 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11590 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 7654 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1216581 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12082 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 438027 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 454511 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 892538 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 337435973 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 89435470 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2029031 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1392 # number of nop insts executed -system.cpu.iew.exec_refs 172567373 # number of memory reference insts executed -system.cpu.iew.exec_branches 31555849 # Number of branches executed -system.cpu.iew.exec_stores 83127503 # Number of stores executed -system.cpu.iew.exec_rate 1.509758 # Inst execution rate -system.cpu.iew.wb_sent 336239137 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 336092943 # cumulative count of insts written-back -system.cpu.iew.wb_producers 151867680 # num instructions producing a value -system.cpu.iew.wb_consumers 263704827 # num instructions consuming a value -system.cpu.iew.wb_rate 1.503724 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.575900 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 14172678 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1419 # number of nop insts executed +system.cpu.iew.exec_refs 172563167 # number of memory reference insts executed +system.cpu.iew.exec_branches 31555788 # Number of branches executed +system.cpu.iew.exec_stores 83127697 # Number of stores executed +system.cpu.iew.exec_rate 1.400376 # Inst execution rate +system.cpu.iew.wb_sent 336234414 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 336088100 # cumulative count of insts written-back +system.cpu.iew.wb_producers 151781597 # num instructions producing a value +system.cpu.iew.wb_consumers 263546089 # num instructions consuming a value +system.cpu.iew.wb_rate 1.394783 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.575921 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 14163176 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 850314 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 220392023 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.487405 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.078236 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 850428 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 235953046 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.389311 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.042233 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 89247998 40.50% 40.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 67546822 30.65% 71.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20918501 9.49% 80.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13253983 6.01% 86.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8642695 3.92% 90.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4496391 2.04% 92.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3033426 1.38% 93.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2604506 1.18% 95.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10647701 4.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 104793604 44.41% 44.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 67594704 28.65% 73.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20883417 8.85% 81.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13239055 5.61% 87.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8655759 3.67% 91.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4517031 1.91% 93.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3019754 1.28% 94.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2590982 1.10% 95.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10658740 4.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 220392023 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273037832 # Number of instructions committed -system.cpu.commit.committedOps 327812214 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 235953046 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273037830 # Number of instructions committed +system.cpu.commit.committedOps 327812212 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 168107892 # Number of memory references committed system.cpu.commit.loads 85732275 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 30563526 # Number of branches committed +system.cpu.commit.branches 30563525 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 258331704 # Number of committed integer instructions. +system.cpu.commit.int_insts 258331703 # Number of committed integer instructions. system.cpu.commit.function_calls 6225114 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 104312487 31.82% 31.82% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 104312485 31.82% 31.82% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction @@ -663,157 +663,157 @@ system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Cl system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 327812214 # Class of committed instruction -system.cpu.commit.bw_lim_events 10647701 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 551726691 # The number of ROB reads -system.cpu.rob.rob_writes 686162246 # The number of ROB writes -system.cpu.timesIdled 18335 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 924807 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273037220 # Number of Instructions Simulated -system.cpu.committedOps 327811602 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.818596 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.818596 # CPI: Total CPI of All Threads -system.cpu.ipc 1.221604 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.221604 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 325161919 # number of integer regfile reads -system.cpu.int_regfile_writes 134094717 # number of integer regfile writes -system.cpu.fp_regfile_reads 186641875 # number of floating regfile reads -system.cpu.fp_regfile_writes 131668024 # number of floating regfile writes -system.cpu.cc_regfile_reads 1279432977 # number of cc regfile reads -system.cpu.cc_regfile_writes 80060950 # number of cc regfile writes -system.cpu.misc_regfile_reads 1056766062 # number of misc regfile reads +system.cpu.commit.op_class_0::total 327812212 # Class of committed instruction +system.cpu.commit.bw_lim_events 10658740 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 567267171 # The number of ROB reads +system.cpu.rob.rob_writes 686142351 # The number of ROB writes +system.cpu.timesIdled 39413 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2818479 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273037218 # Number of Instructions Simulated +system.cpu.committedOps 327811600 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.882520 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.882520 # CPI: Total CPI of All Threads +system.cpu.ipc 1.133118 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.133118 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 325162337 # number of integer regfile reads +system.cpu.int_regfile_writes 134093699 # number of integer regfile writes +system.cpu.fp_regfile_reads 186638060 # number of floating regfile reads +system.cpu.fp_regfile_writes 131662989 # number of floating regfile writes +system.cpu.cc_regfile_reads 1279404689 # number of cc regfile reads +system.cpu.cc_regfile_writes 80058303 # number of cc regfile writes +system.cpu.misc_regfile_reads 1056730531 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1542955 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.836799 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 162076726 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1543467 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 105.008222 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 85416000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.836799 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999681 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999681 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1542807 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.846983 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 162052499 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1543319 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 105.002594 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 87321000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.846983 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999701 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999701 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 333528119 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 333528119 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 81065236 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 81065236 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80920030 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80920030 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 69611 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 69611 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10906 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10906 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 333478959 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 333478959 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 81039652 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 81039652 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80921351 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80921351 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 69633 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 69633 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10908 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10908 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 161985266 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 161985266 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 162054877 # number of overall hits -system.cpu.dcache.overall_hits::total 162054877 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2782957 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2782957 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1132669 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1132669 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 161961003 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161961003 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 162030636 # number of overall hits +system.cpu.dcache.overall_hits::total 162030636 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2784011 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2784011 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1131348 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1131348 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3915626 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3915626 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3915644 # number of overall misses -system.cpu.dcache.overall_misses::total 3915644 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31092984500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31092984500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9127104911 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9127104911 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 182000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 182000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 40220089411 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 40220089411 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 40220089411 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 40220089411 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 83848193 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 83848193 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3915359 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3915359 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3915377 # number of overall misses +system.cpu.dcache.overall_misses::total 3915377 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 45256653500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 45256653500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9138834402 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9138834402 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 184000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 54395487902 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 54395487902 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 54395487902 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 54395487902 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83823663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83823663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 69629 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 69629 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10910 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10910 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 69651 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 69651 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10912 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10912 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 165900892 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 165900892 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 165970521 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 165970521 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033190 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.033190 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013804 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013804 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000259 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.000259 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 165876362 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 165876362 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 165946013 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 165946013 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033213 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.033213 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013788 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013788 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000258 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000258 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000367 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000367 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023602 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023602 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023592 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023592 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11172.642804 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11172.642804 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8058.051303 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8058.051303 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 45500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 45500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10271.688208 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10271.688208 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10271.640990 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10271.640990 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023604 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023604 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023594 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023594 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16255.917631 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16255.917631 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8077.827867 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8077.827867 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 46000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 46000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13892.848115 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13892.848115 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13892.784246 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13892.784246 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1079488 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1086145 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 136770 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 136219 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7.892725 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1542955 # number of writebacks -system.cpu.dcache.writebacks::total 1542955 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1460236 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1460236 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911920 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 911920 # number of WriteReq MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_targets 7.973521 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 1542807 # number of writebacks +system.cpu.dcache.writebacks::total 1542807 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1461430 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1461430 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910604 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 910604 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2372156 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2372156 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2372156 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2372156 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322721 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1322721 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220749 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 220749 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2372034 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2372034 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2372034 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2372034 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322581 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1322581 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220744 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 220744 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1543470 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1543470 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1543481 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1543481 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15298451500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15298451500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1831859691 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1831859691 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 695500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 695500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17130311191 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17130311191 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17131006691 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17131006691 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015775 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015775 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1543325 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1543325 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1543336 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1543336 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25407816000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 25407816000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1834277181 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1834277181 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 705000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 705000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27242093181 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27242093181 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27242798181 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27242798181 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015778 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015778 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002690 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002690 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000158 # mshr miss rate for SoftPFReq accesses @@ -822,392 +822,396 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009304 system.cpu.dcache.demand_mshr_miss_rate::total 0.009304 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009300 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.009300 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11565.894471 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11565.894471 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8298.382738 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8298.382738 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 63227.272727 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 63227.272727 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11098.570877 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11098.570877 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11098.942385 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11098.942385 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 726201 # number of replacements -system.cpu.icache.tags.tagsinuse 511.803602 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 81470529 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 726713 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 112.108259 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 331355500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.803602 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999616 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999616 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19210.782553 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19210.782553 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8309.522257 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8309.522257 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 64090.909091 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 64090.909091 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17651.559575 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17651.559575 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17651.890568 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17651.890568 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 725593 # number of replacements +system.cpu.icache.tags.tagsinuse 511.815316 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 81471161 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 726105 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 112.203002 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 334835500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.815316 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999639 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999639 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 242 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 243 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 70 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 165133375 # Number of tag accesses -system.cpu.icache.tags.data_accesses 165133375 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 81470529 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 81470529 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 81470529 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 81470529 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 81470529 # number of overall hits -system.cpu.icache.overall_hits::total 81470529 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 732796 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 732796 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 732796 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 732796 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 732796 # number of overall misses -system.cpu.icache.overall_misses::total 732796 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 6565806949 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 6565806949 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 6565806949 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 6565806949 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 6565806949 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 6565806949 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 82203325 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 82203325 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 82203325 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 82203325 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 82203325 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 82203325 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008914 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008914 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008914 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008914 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008914 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008914 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8959.938303 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8959.938303 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8959.938303 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8959.938303 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8959.938303 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8959.938303 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 64284 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3051 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 165134244 # Number of tag accesses +system.cpu.icache.tags.data_accesses 165134244 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 81471161 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 81471161 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 81471161 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 81471161 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 81471161 # number of overall hits +system.cpu.icache.overall_hits::total 81471161 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 732901 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 732901 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 732901 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 732901 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 732901 # number of overall misses +system.cpu.icache.overall_misses::total 732901 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8031652441 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8031652441 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8031652441 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8031652441 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8031652441 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8031652441 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 82204062 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 82204062 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 82204062 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 82204062 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 82204062 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 82204062 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008916 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008916 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008916 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008916 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008916 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008916 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10958.713989 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10958.713989 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10958.713989 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10958.713989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10958.713989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10958.713989 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 128534 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 100 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4274 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.069813 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 31.333333 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 726201 # number of writebacks -system.cpu.icache.writebacks::total 726201 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 6071 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 6071 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 6071 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 6071 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 6071 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 6071 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726725 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 726725 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 726725 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 726725 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 726725 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 726725 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6109081458 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 6109081458 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6109081458 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 6109081458 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6109081458 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 6109081458 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008841 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008841 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008841 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8406.318013 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8406.318013 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 402434 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 402547 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 102 # number of redundant prefetches already in prefetch queue +system.cpu.icache.avg_blocked_cycles::no_mshrs 30.073467 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 33.333333 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 725593 # number of writebacks +system.cpu.icache.writebacks::total 725593 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 6780 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 6780 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 6780 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 6780 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 6780 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 6780 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726121 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 726121 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 726121 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 726121 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 726121 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 726121 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7527879949 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 7527879949 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7527879949 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 7527879949 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7527879949 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 7527879949 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008833 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.008833 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008833 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.008833 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10367.252771 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10367.252771 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10367.252771 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 10367.252771 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10367.252771 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 10367.252771 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 402848 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 402975 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 113 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 28085 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.pfSpanPage 27937 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 5603.177963 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3041133 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 6750 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 450.538222 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 5253.562311 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1811987 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 6314 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 286.979252 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 5495.535708 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 107.642255 # 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number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 187753381 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 187753381 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 251000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 251000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53315000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53315000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2084473500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2084473500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 14900259000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 14900259000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2084473500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14953574000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17038047500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2084473500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14953574000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 187753381 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17225800881 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.928571 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.928571 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003307 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003307 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013343 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013343 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.054095 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.054095 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013343 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.046832 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.036112 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013343 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.046832 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.941176 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.941176 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003429 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003429 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040634 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040634 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172520 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172520 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040634 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148335 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.113878 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040634 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148335 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.058865 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3448.748330 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3448.748330 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14384.615385 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14384.615385 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68908.904110 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68908.904110 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64966.016914 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64966.016914 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64708.293153 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64708.293153 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64966.016914 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64750.715936 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64776.180485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64966.016914 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64750.715936 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3448.748330 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41071.748859 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4539362 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2269187 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254586 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 130262 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 52910 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 77352 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2049447 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 968360 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1300796 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 81249 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 53022 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 220745 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 220745 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 726725 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322722 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2179572 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629917 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6809489 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92982208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197531008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 290513216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 134350 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5056 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2404477 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.192237 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.468638 # Request fanout histogram +system.cpu.l2cache.overall_mshr_miss_rate::total 0.137742 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3466.834961 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3466.834961 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15687.500000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15687.500000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70429.326288 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70429.326288 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70655.328452 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70655.328452 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65303.035881 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65303.035881 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70655.328452 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65319.987070 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65929.062028 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70655.328452 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65319.987070 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3466.834961 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55107.220969 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4537857 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268434 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254467 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 51535 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51534 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 2048700 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 968253 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1300147 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 55525 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 220739 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 220739 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 726121 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322580 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2177753 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629479 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6807232 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92904448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197512064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 290416512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 55606 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5184 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2324982 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.131629 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.338088 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2019600 83.99% 83.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 307525 12.79% 96.78% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 77352 3.22% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2018948 86.84% 86.84% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 306033 13.16% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2404477 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4538837000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 4.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1090392888 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2315538337 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 83887 # Transaction distribution -system.membus.trans_dist::UpgradeReq 13 # Transaction distribution -system.membus.trans_dist::ReadExReq 730 # Transaction distribution -system.membus.trans_dist::ReadExResp 730 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 83887 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 169247 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 169247 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 5415488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 5415488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoop_fanout::total 2324982 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4537328500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 3.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1089458442 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2315007958 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 261068 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 253748 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 120480458500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 260294 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16 # Transaction distribution +system.membus.trans_dist::ReadExReq 757 # Transaction distribution +system.membus.trans_dist::ReadExResp 757 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 260295 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522119 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 522119 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16707264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 16707264 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 84630 # Request fanout histogram +system.membus.snoop_fanout::samples 261068 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 84630 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 261068 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 84630 # Request fanout histogram -system.membus.reqLayer0.occupancy 108151910 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 445724357 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.snoop_fanout::total 261068 # Request fanout histogram +system.membus.reqLayer0.occupancy 329929457 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1377865586 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index e42324626..ec456bd8f 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.201717 # Nu sim_ticks 201717314000 # Number of ticks simulated final_tick 201717314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 732440 # Simulator instruction rate (inst/s) -host_op_rate 879375 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 541118678 # Simulator tick rate (ticks/s) -host_mem_usage 263976 # Number of bytes of host memory used -host_seconds 372.78 # Real time elapsed on the host +host_inst_rate 781022 # Simulator instruction rate (inst/s) +host_op_rate 937704 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 577011080 # Simulator tick rate (ticks/s) +host_mem_usage 268872 # Number of bytes of host memory used +host_seconds 349.59 # Real time elapsed on the host sim_insts 273037595 # Number of instructions simulated sim_ops 327811950 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,6 +220,12 @@ system.cpu.op_class::MemWrite 82375594 25.13% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812145 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 434895828 # Transaction distribution system.membus.trans_dist::ReadResp 434906723 # Transaction distribution @@ -239,14 +245,14 @@ system.membus.pkt_size::total 2275398075 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 517024352 # Request fanout histogram -system.membus.snoop_fanout::mean 0.674359 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 168364078 32.56% 32.56% # Request fanout histogram -system.membus.snoop_fanout::1 348660274 67.44% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 517024352 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 517024352 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index fd046e3e7..81799693e 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.517291 # Number of seconds simulated -sim_ticks 517291025500 # Number of ticks simulated -final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.517298 # Number of seconds simulated +sim_ticks 517297855500 # Number of ticks simulated +final_tick 517297855500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 451771 # Simulator instruction rate (inst/s) -host_op_rate 542368 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 856851233 # Simulator tick rate (ticks/s) -host_mem_usage 273716 # Number of bytes of host memory used -host_seconds 603.71 # Real time elapsed on the host +host_inst_rate 565388 # Simulator instruction rate (inst/s) +host_op_rate 678769 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1072356714 # Simulator tick rate (ticks/s) +host_mem_usage 278352 # Number of bytes of host memory used +host_seconds 482.39 # Real time elapsed on the host sim_insts 272739286 # Number of instructions simulated sim_ops 327433744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory system.physmem.bytes_read::total 437248 # Number of bytes read from this memory @@ -22,17 +22,17 @@ system.physmem.bytes_inst_read::total 166912 # Nu system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 322661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 522593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 845254 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 322661 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 322661 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 322661 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 522593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 845254 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -62,7 +62,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -92,7 +92,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -122,7 +122,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -153,8 +153,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 517291025500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1034582051 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 517297855500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1034595711 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 272739286 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 168107847 # nu system.cpu.num_load_insts 85732248 # Number of load instructions system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1034582050.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1034595710.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 30563503 # Number of branches fetched @@ -214,16 +214,16 @@ system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812214 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1332 # number of replacements -system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3078.320204 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.320204 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.751543 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.751543 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id @@ -233,7 +233,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits @@ -258,14 +258,14 @@ system.cpu.dcache.demand_misses::cpu.data 4476 # n system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses system.cpu.dcache.overall_misses::total 4479 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88052000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88052000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 177422500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 177422500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 265474500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 265474500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 265474500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 265474500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 89418000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 89418000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 180278500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 180278500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 269696500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 269696500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 269696500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 269696500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) @@ -290,14 +290,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54895.261845 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61776.636490 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59310.656836 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59310.656836 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55746.882793 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55746.882793 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62771.065460 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62771.065460 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60253.909741 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60253.909741 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60213.552132 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60213.552132 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -322,16 +322,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4475 system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86402000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 86402000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 174550500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 174550500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 183000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 183000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260952500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 260952500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 261135500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 261135500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 87767000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 87767000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 177406500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 177406500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 186000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 186000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 265173500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 265173500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 265359500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 265359500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -342,26 +342,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53900.187149 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53900.187149 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54751.715533 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54751.715533 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61771.065460 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61771.065460 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59256.648045 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 59256.648045 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59258.485931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 59258.485931 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 13796 # number of replacements -system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1765.939670 # Cycle average of tags in use system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1765.939670 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.862275 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.862275 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id @@ -371,7 +371,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits @@ -384,12 +384,12 @@ system.cpu.icache.demand_misses::cpu.inst 15603 # n system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses system.cpu.icache.overall_misses::total 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 338446000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 338446000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 338446000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 338446000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 338446000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 338446000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 341054000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 341054000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 341054000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 341054000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 341054000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 341054000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses @@ -402,12 +402,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21691.085048 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21691.085048 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21691.085048 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21691.085048 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21858.232391 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21858.232391 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21858.232391 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21858.232391 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21858.232391 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21858.232391 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,48 +422,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603 system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322843000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 322843000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322843000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 322843000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322843000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 322843000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 325451000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 325451000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 325451000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 325451000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 325451000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 325451000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20858.232391 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20858.232391 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20858.232391 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20858.232391 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20858.232391 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20858.232391 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 5901.352793 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 20712 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 6832 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.031616 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 738.688437 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073466 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.022543 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.106434 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.314356 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3494.038437 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073465 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.106630 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.180095 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 6832 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 758 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5967 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.208496 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 227184 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 227184 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits @@ -492,18 +490,18 @@ system.cpu.l2cache.demand_misses::total 6832 # nu system.cpu.l2cache.overall_misses::cpu.inst 2608 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4224 # number of overall misses system.cpu.l2cache.overall_misses::total 6832 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 170070500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 170070500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155292000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 155292000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 81591000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 81591000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 155292000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 251661500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 406953500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 155292000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 251661500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 406953500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 172926500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 172926500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 157900000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 157900000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 82959000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 82959000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 157900000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 255885500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 413785500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 157900000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 255885500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 413785500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 998 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 998 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 6212 # number of WritebackClean accesses(hits+misses) @@ -532,18 +530,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.340222 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167147 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.943278 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.494398 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.494398 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.478528 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.478528 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59642.543860 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59642.543860 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59565.793326 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60548.494398 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60548.494398 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60544.478528 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60544.478528 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60642.543860 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60642.543860 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60544.478528 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60578.953598 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60565.793326 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60544.478528 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60578.953598 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60565.793326 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -562,18 +560,18 @@ system.cpu.l2cache.demand_mshr_misses::total 6832 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141510500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141510500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129212000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129212000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 67911000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 67911000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129212000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 209421500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 338633500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129212000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 209421500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 338633500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 144366500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 144366500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 131820000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 131820000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 69279000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 69279000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 131820000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 213645500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 345465500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 131820000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 213645500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 345465500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadCleanReq accesses @@ -586,25 +584,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50548.494398 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50548.494398 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50544.478528 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50544.478528 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50642.543860 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50642.543860 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50544.478528 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50578.953598 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50565.793326 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50544.478528 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50578.953598 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50565.793326 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution @@ -638,7 +636,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 23404500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 6833 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3976 # Transaction distribution system.membus.trans_dist::ReadExReq 2856 # Transaction distribution system.membus.trans_dist::ReadExResp 2856 # Transaction distribution diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index f21f0115d..cfec5db38 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,70 +1,70 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.508216 # Number of seconds simulated -sim_ticks 508215534000 # Number of ticks simulated -final_tick 508215534000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.508441 # Number of seconds simulated +sim_ticks 508441445000 # Number of ticks simulated +final_tick 508441445000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 266071 # Simulator instruction rate (inst/s) -host_op_rate 266071 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 145588775 # Simulator tick rate (ticks/s) -host_mem_usage 258712 # Number of bytes of host memory used -host_seconds 3490.76 # Real time elapsed on the host +host_inst_rate 272638 # Simulator instruction rate (inst/s) +host_op_rate 272638 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 149248503 # Simulator tick rate (ticks/s) +host_mem_usage 263860 # Number of bytes of host memory used +host_seconds 3406.68 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 185920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18520192 # Number of bytes read from this memory -system.physmem.bytes_read::total 18706112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 185920 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 185920 # Number of instructions bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 185856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18520896 # Number of bytes read from this memory +system.physmem.bytes_read::total 18706752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 185856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 185856 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2905 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289378 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292283 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2904 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289389 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292293 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 365829 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36441609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36807438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 365829 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 365829 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8397445 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8397445 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8397445 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 365829 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36441609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 45204883 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292283 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 365541 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36426802 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36792343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 365541 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 365541 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8393714 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8393714 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8393714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 365541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36426802 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 45186057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292293 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 292283 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 292293 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18687040 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19072 # Total number of bytes read from write queue -system.physmem.bytesWritten 4265984 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18706112 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18685888 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20864 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266496 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18706752 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 298 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 326 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18032 # Per bank write bursts -system.physmem.perBankRdBursts::1 18362 # Per bank write bursts -system.physmem.perBankRdBursts::2 18398 # Per bank write bursts -system.physmem.perBankRdBursts::3 18335 # Per bank write bursts -system.physmem.perBankRdBursts::4 18250 # Per bank write bursts -system.physmem.perBankRdBursts::5 18255 # Per bank write bursts -system.physmem.perBankRdBursts::6 18321 # Per bank write bursts -system.physmem.perBankRdBursts::7 18295 # Per bank write bursts -system.physmem.perBankRdBursts::8 18232 # Per bank write bursts -system.physmem.perBankRdBursts::9 18236 # Per bank write bursts -system.physmem.perBankRdBursts::10 18232 # Per bank write bursts -system.physmem.perBankRdBursts::11 18379 # Per bank write bursts -system.physmem.perBankRdBursts::12 18271 # Per bank write bursts -system.physmem.perBankRdBursts::13 18134 # Per bank write bursts -system.physmem.perBankRdBursts::14 18060 # Per bank write bursts -system.physmem.perBankRdBursts::15 18193 # Per bank write bursts +system.physmem.perBankRdBursts::0 18028 # Per bank write bursts +system.physmem.perBankRdBursts::1 18361 # Per bank write bursts +system.physmem.perBankRdBursts::2 18399 # Per bank write bursts +system.physmem.perBankRdBursts::3 18347 # Per bank write bursts +system.physmem.perBankRdBursts::4 18249 # Per bank write bursts +system.physmem.perBankRdBursts::5 18247 # Per bank write bursts +system.physmem.perBankRdBursts::6 18319 # Per bank write bursts +system.physmem.perBankRdBursts::7 18291 # Per bank write bursts +system.physmem.perBankRdBursts::8 18230 # Per bank write bursts +system.physmem.perBankRdBursts::9 18239 # Per bank write bursts +system.physmem.perBankRdBursts::10 18229 # Per bank write bursts +system.physmem.perBankRdBursts::11 18377 # Per bank write bursts +system.physmem.perBankRdBursts::12 18268 # Per bank write bursts +system.physmem.perBankRdBursts::13 18136 # Per bank write bursts +system.physmem.perBankRdBursts::14 18057 # Per bank write bursts +system.physmem.perBankRdBursts::15 18190 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -74,7 +74,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4180 # Per bank write bursts +system.physmem.perBankWrBursts::9 4188 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -83,14 +83,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 508215452500 # Total gap between requests +system.physmem.totGap 508441362500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292283 # Read request sizes (log2) +system.physmem.readPktSize::6 292293 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,8 +98,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 291508 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 291491 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 464 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,25 +145,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -194,97 +194,97 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 103603 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 221.521925 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 143.541969 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 268.372247 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 37864 36.55% 36.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43808 42.28% 78.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9097 8.78% 87.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 745 0.72% 88.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1395 1.35% 89.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1153 1.11% 90.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 627 0.61% 91.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 610 0.59% 91.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8304 8.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 103603 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4049 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 69.361324 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.573478 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 739.455375 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4041 99.80% 99.80% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 103424 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 221.899134 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 143.895688 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 268.440022 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 37597 36.35% 36.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43798 42.35% 78.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9078 8.78% 87.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 804 0.78% 88.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1585 1.53% 89.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1026 0.99% 90.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 543 0.53% 91.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 660 0.64% 91.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8333 8.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 103424 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4053 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.164816 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.696519 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 767.230213 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4045 99.80% 99.80% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 4 0.10% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-16383 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 4 0.10% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-16383 2 0.05% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4049 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4049 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.462336 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.441628 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.843264 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3113 76.88% 76.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 936 23.12% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4049 # Writes before turning the bus around for reads -system.physmem.totQLat 2518388500 # Total ticks spent queuing -system.physmem.totMemAccLat 7993107250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1459925000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8625.06 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4053 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4053 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.448063 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.427763 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.835172 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3146 77.62% 77.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 906 22.35% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4053 # Writes before turning the bus around for reads +system.physmem.totQLat 2452616250 # Total ticks spent queuing +system.physmem.totMemAccLat 7926997500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1459835000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8400.32 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27375.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 36.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27150.32 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 36.75 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 8.39 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 36.81 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 8.40 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 36.79 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 8.39 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.35 # Data bus utilization in percentage system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing -system.physmem.readRowHits 203026 # Number of row buffer hits during reads -system.physmem.writeRowHits 52001 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.98 # Row buffer hit rate for writes -system.physmem.avgGap 1415776.01 # Average gap between requests -system.physmem.pageHitRate 71.10 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 390708360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 213184125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1140250800 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 24.39 # Average write queue length when enqueuing +system.physmem.readRowHits 203097 # Number of row buffer hits during reads +system.physmem.writeRowHits 52099 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.56 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.13 # Row buffer hit rate for writes +system.physmem.avgGap 1416365.89 # Average gap between requests +system.physmem.pageHitRate 71.15 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 390353040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 212990250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1140196200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 33193711200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 103572972045 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 214071794250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 352799059260 # Total energy per rank (pJ) -system.physmem_0.averagePower 694.201008 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 355459552750 # Time in different power states -system.physmem_0.memoryStateTime::REF 16970200000 # Time in different power states +system.physmem_0.refreshEnergy 33208459440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 103170345705 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 214560479250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 352899262365 # Total energy per rank (pJ) +system.physmem_0.averagePower 694.089734 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 356274409500 # Time in different power states +system.physmem_0.memoryStateTime::REF 16977740000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 135779058500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 135182501000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 392424480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 214120500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1136545800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215492400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 33193711200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 103467236760 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 214164544500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 352784075640 # Total energy per rank (pJ) -system.physmem_1.averagePower 694.171524 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 355611467750 # Time in different power states -system.physmem_1.memoryStateTime::REF 16970200000 # Time in different power states +system.physmem_1.actEnergy 391426560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 213576000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1136460000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215544240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 33208459440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 103438175310 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 214325517750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 352929159300 # Total energy per rank (pJ) +system.physmem_1.averagePower 694.148589 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 355878371250 # Time in different power states +system.physmem_1.memoryStateTime::REF 16977740000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 135627775750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 135579179250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 123851653 # Number of BP lookups +system.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 123851654 # Number of BP lookups system.cpu.branchPred.condPredicted 79872946 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 686743 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 102066131 # Number of BTB lookups -system.cpu.branchPred.BTBHits 68190141 # Number of BTB hits +system.cpu.branchPred.BTBLookups 102066133 # Number of BTB lookups +system.cpu.branchPred.BTBHits 68190143 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 66.809764 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18697400 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 18697398 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 11224 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 14052177 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 14048616 # Number of indirect target hits. @@ -299,18 +299,18 @@ system.cpu.dtb.read_hits 237539296 # DT system.cpu.dtb.read_misses 195211 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 237734507 # DTB read accesses -system.cpu.dtb.write_hits 98305020 # DTB write hits +system.cpu.dtb.write_hits 98305021 # DTB write hits system.cpu.dtb.write_misses 7170 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98312190 # DTB write accesses -system.cpu.dtb.data_hits 335844316 # DTB hits +system.cpu.dtb.write_accesses 98312191 # DTB write accesses +system.cpu.dtb.data_hits 335844317 # DTB hits system.cpu.dtb.data_misses 202381 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336046697 # DTB accesses -system.cpu.itb.fetch_hits 286584409 # ITB hits +system.cpu.dtb.data_accesses 336046698 # DTB accesses +system.cpu.itb.fetch_hits 286584411 # ITB hits system.cpu.itb.fetch_misses 119 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 286584528 # ITB accesses +system.cpu.itb.fetch_accesses 286584530 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -324,16 +324,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1016431068 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1016882890 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 319592 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 319599 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.094361 # CPI: cycles per instruction -system.cpu.ipc 0.913775 # IPC: instructions per cycle +system.cpu.cpi 1.094848 # CPI: cycles per instruction +system.cpu.ipc 0.913369 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction system.cpu.op_class_0::IntAlu 486529511 52.38% 61.66% # Class of committed instruction system.cpu.op_class_0::IntMult 7040 0.00% 61.67% # Class of committed instruction @@ -369,36 +369,36 @@ system.cpu.op_class_0::MemWrite 98308071 10.58% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 928789150 # Class of committed instruction -system.cpu.tickCycles 962815750 # Number of cycles that the object actually ticked -system.cpu.idleCycles 53615318 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 962815783 # Number of cycles that the object actually ticked +system.cpu.idleCycles 54067107 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 776559 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.348104 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 320318733 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4092.323693 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 320318732 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780655 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 410.320478 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 905242500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.348104 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999108 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999108 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 410.320477 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 911974500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.323693 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999102 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999102 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 955 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 956 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1381 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1491 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 643115729 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 643115729 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 222154684 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 222154684 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 643115727 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 643115727 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 222154683 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 222154683 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 98164049 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 98164049 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 320318733 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 320318733 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 320318733 # number of overall hits -system.cpu.dcache.overall_hits::total 320318733 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 320318732 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 320318732 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 320318732 # number of overall hits +system.cpu.dcache.overall_hits::total 320318732 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 711653 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 711653 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 137151 # number of WriteReq misses @@ -407,22 +407,22 @@ system.cpu.dcache.demand_misses::cpu.data 848804 # n system.cpu.dcache.demand_misses::total 848804 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 848804 # number of overall misses system.cpu.dcache.overall_misses::total 848804 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24412597000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24412597000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10105115500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10105115500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34517712500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34517712500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34517712500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34517712500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 222866337 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 222866337 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24607511500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24607511500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10163393500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10163393500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34770905000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34770905000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34770905000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34770905000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 222866336 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 222866336 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 321167537 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 321167537 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 321167537 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 321167537 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 321167536 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 321167536 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 321167536 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 321167536 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003193 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003193 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses @@ -431,22 +431,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002643 system.cpu.dcache.demand_miss_rate::total 0.002643 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002643 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002643 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34304.073755 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34304.073755 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73678.759178 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73678.759178 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40666.293396 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40666.293396 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40666.293396 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40666.293396 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34577.963558 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34577.963558 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74103.677698 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74103.677698 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40964.586642 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40964.586642 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40964.586642 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40964.586642 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88481 # number of writebacks -system.cpu.dcache.writebacks::total 88481 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88440 # number of writebacks +system.cpu.dcache.writebacks::total 88440 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68140 # number of WriteReq MSHR hits @@ -463,14 +463,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780655 system.cpu.dcache.demand_mshr_misses::total 780655 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 780655 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780655 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23700262500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23700262500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5068010000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5068010000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28768272500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28768272500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28768272500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28768272500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23895183000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23895183000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5097981500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5097981500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28993164500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28993164500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28993164500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28993164500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003193 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses @@ -479,24 +479,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002431 system.cpu.dcache.demand_mshr_miss_rate::total 0.002431 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002431 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002431 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33303.537302 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33303.537302 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73437.712828 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73437.712828 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36851.454868 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36851.454868 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36851.454868 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36851.454868 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 10580 # number of replacements -system.cpu.icache.tags.tagsinuse 1690.197843 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 286572082 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12326 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 23249.398183 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33577.439000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33577.439000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73872.013157 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73872.013157 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37139.536031 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 37139.536031 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37139.536031 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37139.536031 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 10578 # number of replacements +system.cpu.icache.tags.tagsinuse 1690.178313 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 286572086 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12324 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 23253.171535 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1690.197843 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.825292 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.825292 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1690.178313 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.825282 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.825282 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1746 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id @@ -504,181 +504,181 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 2 system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1576 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.852539 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 573181144 # Number of tag accesses -system.cpu.icache.tags.data_accesses 573181144 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 286572082 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 286572082 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 286572082 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 286572082 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 286572082 # number of overall hits -system.cpu.icache.overall_hits::total 286572082 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12327 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12327 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12327 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12327 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12327 # number of overall misses -system.cpu.icache.overall_misses::total 12327 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 353123500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 353123500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 353123500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 353123500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 353123500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 353123500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 286584409 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 286584409 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 286584409 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 286584409 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 286584409 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 286584409 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 573181146 # Number of tag accesses +system.cpu.icache.tags.data_accesses 573181146 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 286572086 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 286572086 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 286572086 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 286572086 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 286572086 # number of overall hits +system.cpu.icache.overall_hits::total 286572086 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12325 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12325 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12325 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12325 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12325 # number of overall misses +system.cpu.icache.overall_misses::total 12325 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 354631500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 354631500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 354631500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 354631500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 354631500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 354631500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 286584411 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 286584411 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 286584411 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 286584411 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 286584411 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 286584411 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28646.345421 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28773.346856 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28773.346856 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28773.346856 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28773.346856 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28773.346856 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28773.346856 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # 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number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 12325 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 780655 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 792982 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 792980 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965716 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.965716 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.235743 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.235743 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312984 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312984 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.235743 # 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miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.370700 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.368602 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.235700 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.370700 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.368602 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74568.159652 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74568.159652 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77422.203098 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77422.203098 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79437.632439 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79437.632439 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77422.203098 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78316.214507 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78307.329264 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77422.203098 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78316.214507 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78307.329264 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -691,120 +691,126 @@ system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66645 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66645 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2906 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2906 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222733 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222733 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2906 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 289378 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 292284 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2906 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 289378 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 292284 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4273173000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4273173000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 194338000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 194338000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15271890000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15271890000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 194338000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19545063000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19739401000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 194338000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19545063000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19739401000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2905 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2905 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222744 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222744 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2905 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 289389 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 292294 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2905 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 289389 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 292294 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4303145000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4303145000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 195871500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 195871500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15466816000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15466816000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195871500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19769961000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19965832500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195871500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19769961000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19965832500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.235743 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.235743 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312984 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312984 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.235743 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370686 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.368588 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.235743 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370686 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.368588 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64118.433491 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64118.433491 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66874.741913 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66874.741913 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68565.906264 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68565.906264 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66874.741913 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67541.634126 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67535.003627 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66874.741913 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67541.634126 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67535.003627 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1580121 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 787139 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.235700 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.235700 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312999 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312999 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.235700 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370700 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.368602 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.235700 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370700 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.368602 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64568.159652 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64568.159652 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67425.645439 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67425.645439 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69437.632439 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69437.632439 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67425.645439 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68316.214507 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68307.363476 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67425.645439 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68316.214507 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68307.363476 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1580117 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 787137 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2087 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2087 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2095 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2095 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 723970 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155164 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 10580 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 881355 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 723968 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155123 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 10578 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 881417 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 12327 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 12325 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 711644 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35233 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35227 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337869 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2373102 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1465984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55624704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 57090688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259960 # Total snoops (count) +system.cpu.toL2Bus.pkt_count::total 2373096 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1465728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55622080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 57087808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259981 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 4267712 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1052942 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001982 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.044476 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1052961 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001990 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.044561 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1050855 99.80% 99.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2087 0.20% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1050866 99.80% 99.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2095 0.20% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1052942 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 889121500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1052961 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 889076500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 18489000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 18486000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1170982999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 225638 # Transaction distribution +system.membus.snoop_filter.tot_requests 550179 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 257886 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 508441445000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 225648 # Transaction distribution system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 191190 # Transaction distribution +system.membus.trans_dist::CleanEvict 191203 # Transaction distribution system.membus.trans_dist::ReadExReq 66645 # Transaction distribution system.membus.trans_dist::ReadExResp 66645 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225638 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842439 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842439 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22973824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22973824 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225648 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842472 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842472 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22974464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22974464 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 550156 # Request fanout histogram +system.membus.snoop_fanout::samples 292293 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 550156 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 292293 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 550156 # Request fanout histogram -system.membus.reqLayer0.occupancy 925402000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 292293 # Request fanout histogram +system.membus.reqLayer0.occupancy 925378500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1556718500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1556878500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 577d97331..c74410070 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,70 +1,70 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.174766 # Number of seconds simulated -sim_ticks 174766258500 # Number of ticks simulated -final_tick 174766258500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.175004 # Number of seconds simulated +sim_ticks 175004412500 # Number of ticks simulated +final_tick 175004412500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 215097 # Simulator instruction rate (inst/s) -host_op_rate 215097 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44625570 # Simulator tick rate (ticks/s) -host_mem_usage 260248 # Number of bytes of host memory used -host_seconds 3916.28 # Real time elapsed on the host +host_inst_rate 244500 # Simulator instruction rate (inst/s) +host_op_rate 244500 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50794673 # Simulator tick rate (ticks/s) +host_mem_usage 265392 # Number of bytes of host memory used +host_seconds 3445.33 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 174016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18524608 # Number of bytes read from this memory -system.physmem.bytes_read::total 18698624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 174016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 174016 # Number of instructions bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 173952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18525120 # Number of bytes read from this memory +system.physmem.bytes_read::total 18699072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 173952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 173952 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267648 # Number of bytes written to this memory system.physmem.bytes_written::total 4267648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2719 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289447 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292166 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2718 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289455 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292173 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66682 # Number of write requests responded to by this memory system.physmem.num_writes::total 66682 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 995707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 105996479 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 106992186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 995707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 995707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 24419176 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 24419176 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 24419176 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 995707 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 105996479 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 131411362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292166 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 993986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 105855160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 106849146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 993986 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 993986 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 24385945 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 24385945 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 24385945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 993986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 105855160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 131235091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292173 # Number of read requests accepted system.physmem.writeReqs 66682 # Number of write requests accepted -system.physmem.readBursts 292166 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 292173 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66682 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18677824 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20800 # Total number of bytes read from write queue -system.physmem.bytesWritten 4265792 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18698624 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18679488 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19584 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266624 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18699072 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267648 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 325 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 306 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18006 # Per bank write bursts -system.physmem.perBankRdBursts::1 18334 # Per bank write bursts -system.physmem.perBankRdBursts::2 18382 # Per bank write bursts -system.physmem.perBankRdBursts::3 18340 # Per bank write bursts -system.physmem.perBankRdBursts::4 18235 # Per bank write bursts -system.physmem.perBankRdBursts::5 18233 # Per bank write bursts -system.physmem.perBankRdBursts::6 18311 # Per bank write bursts -system.physmem.perBankRdBursts::7 18302 # Per bank write bursts -system.physmem.perBankRdBursts::8 18233 # Per bank write bursts -system.physmem.perBankRdBursts::9 18227 # Per bank write bursts +system.physmem.perBankRdBursts::0 18012 # Per bank write bursts +system.physmem.perBankRdBursts::1 18337 # Per bank write bursts +system.physmem.perBankRdBursts::2 18383 # Per bank write bursts +system.physmem.perBankRdBursts::3 18348 # Per bank write bursts +system.physmem.perBankRdBursts::4 18239 # Per bank write bursts +system.physmem.perBankRdBursts::5 18237 # Per bank write bursts +system.physmem.perBankRdBursts::6 18320 # Per bank write bursts +system.physmem.perBankRdBursts::7 18308 # Per bank write bursts +system.physmem.perBankRdBursts::8 18229 # Per bank write bursts +system.physmem.perBankRdBursts::9 18225 # Per bank write bursts system.physmem.perBankRdBursts::10 18220 # Per bank write bursts -system.physmem.perBankRdBursts::11 18388 # Per bank write bursts -system.physmem.perBankRdBursts::12 18256 # Per bank write bursts -system.physmem.perBankRdBursts::13 18125 # Per bank write bursts -system.physmem.perBankRdBursts::14 18057 # Per bank write bursts -system.physmem.perBankRdBursts::15 18192 # Per bank write bursts +system.physmem.perBankRdBursts::11 18382 # Per bank write bursts +system.physmem.perBankRdBursts::12 18250 # Per bank write bursts +system.physmem.perBankRdBursts::13 18123 # Per bank write bursts +system.physmem.perBankRdBursts::14 18058 # Per bank write bursts +system.physmem.perBankRdBursts::15 18196 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -74,8 +74,8 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4261 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4180 # Per bank write bursts -system.physmem.perBankWrBursts::10 4148 # Per bank write bursts +system.physmem.perBankWrBursts::9 4191 # Per bank write bursts +system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4100 # Per bank write bursts @@ -83,14 +83,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 174766169000 # Total gap between requests +system.physmem.totGap 175004322000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292166 # Read request sizes (log2) +system.physmem.readPktSize::6 292173 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,12 +98,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66682 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 215310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 46521 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29810 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 215232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 46701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29729 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 174 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -146,24 +146,24 @@ system.physmem.wrQLenPdf::12 1 # Wh system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4144 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 4061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -194,125 +194,126 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 96628 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 237.414911 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 153.615169 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 282.362382 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 31544 32.64% 32.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 41851 43.31% 75.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11279 11.67% 87.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 407 0.42% 88.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 349 0.36% 88.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 422 0.44% 88.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 656 0.68% 89.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1511 1.56% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8609 8.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 96628 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4053 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 68.731557 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.520071 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 729.773377 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4045 99.80% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7168-8191 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 5 0.12% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 96708 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 237.268147 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 153.455294 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 282.430006 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 31632 32.71% 32.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 41779 43.20% 75.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11320 11.71% 87.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 443 0.46% 88.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 357 0.37% 88.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 304 0.31% 88.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 669 0.69% 89.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1569 1.62% 91.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8635 8.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 96708 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4054 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.658609 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.711074 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 765.890247 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4045 99.78% 99.78% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 3 0.07% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-16383 2 0.05% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4053 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4053 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.445349 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.425120 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.833815 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3151 77.74% 77.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 3 0.07% 77.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 896 22.11% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4053 # Writes before turning the bus around for reads -system.physmem.totQLat 3659606000 # Total ticks spent queuing -system.physmem.totMemAccLat 9131624750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1459205000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12539.73 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4054 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4054 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.444499 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.424176 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.836057 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3157 77.87% 77.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 892 22.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2 0.05% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 3 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4054 # Writes before turning the bus around for reads +system.physmem.totQLat 3688779750 # Total ticks spent queuing +system.physmem.totMemAccLat 9161286000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1459335000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12638.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31289.73 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 106.87 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 24.41 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 106.99 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 24.42 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31388.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 106.74 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 24.38 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 106.85 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 24.39 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.03 # Data bus utilization in percentage +system.physmem.busUtil 1.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.83 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.19 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.34 # Average write queue length when enqueuing -system.physmem.readRowHits 209802 # Number of row buffer hits during reads -system.physmem.writeRowHits 52054 # Number of row buffer hits during writes -system.physmem.readRowHitRate 71.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.06 # Row buffer hit rate for writes -system.physmem.avgGap 487020.04 # Average gap between requests -system.physmem.pageHitRate 73.04 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 364626360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 198952875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1139346000 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing +system.physmem.readRowHits 209722 # Number of row buffer hits during reads +system.physmem.writeRowHits 52099 # Number of row buffer hits during writes +system.physmem.readRowHitRate 71.86 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.13 # Row buffer hit rate for writes +system.physmem.avgGap 487674.19 # Average gap between requests +system.physmem.pageHitRate 73.02 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 365095080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 199208625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1140180600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216432000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 11414629200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 63677219400 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 49000374750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 126011580585 # Total energy per rank (pJ) -system.physmem_0.averagePower 721.044153 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 81102514500 # Time in different power states -system.physmem_0.memoryStateTime::REF 5835700000 # Time in different power states +system.physmem_0.refreshEnergy 11430394560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 63710720865 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 49115814750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 126177846480 # Total energy per rank (pJ) +system.physmem_0.averagePower 720.999703 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 81290875500 # Time in different power states +system.physmem_0.memoryStateTime::REF 5843760000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 87824440500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 87869398250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 365752800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 199567500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1136265000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215479440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 11414629200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 63630052470 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 49041749250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 126003495660 # Total energy per rank (pJ) -system.physmem_1.averagePower 720.997890 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 81165303250 # Time in different power states -system.physmem_1.memoryStateTime::REF 5835700000 # Time in different power states +system.physmem_1.actEnergy 366002280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 199703625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1136311800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215563680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 11430394560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 64026816075 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 48838535250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 126213327270 # Total energy per rank (pJ) +system.physmem_1.averagePower 721.202467 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 80826473000 # Time in different power states +system.physmem_1.memoryStateTime::REF 5843760000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 87762226750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 88334018000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 129267026 # Number of BP lookups -system.cpu.branchPred.condPredicted 83048450 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 145225 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 93510959 # Number of BTB lookups -system.cpu.branchPred.BTBHits 70602364 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 129267773 # Number of BP lookups +system.cpu.branchPred.condPredicted 83048997 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 145228 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 93512308 # Number of BTB lookups +system.cpu.branchPred.BTBHits 70602709 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 75.501700 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19428078 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1137 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 14846480 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 14819636 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 26844 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 4929 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 75.500980 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19428222 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1139 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 14846516 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 14819690 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 26826 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 4927 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 243602185 # DTB read hits -system.cpu.dtb.read_misses 267667 # DTB read misses +system.cpu.dtb.read_hits 243602594 # DTB read hits +system.cpu.dtb.read_misses 267810 # DTB read misses system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 243869852 # DTB read accesses -system.cpu.dtb.write_hits 101634527 # DTB write hits -system.cpu.dtb.write_misses 39608 # DTB write misses +system.cpu.dtb.read_accesses 243870404 # DTB read accesses +system.cpu.dtb.write_hits 101634629 # DTB write hits +system.cpu.dtb.write_misses 39603 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 101674135 # DTB write accesses -system.cpu.dtb.data_hits 345236712 # DTB hits -system.cpu.dtb.data_misses 307275 # DTB misses +system.cpu.dtb.write_accesses 101674232 # DTB write accesses +system.cpu.dtb.data_hits 345237223 # DTB hits +system.cpu.dtb.data_misses 307413 # DTB misses system.cpu.dtb.data_acv 2 # DTB access violations -system.cpu.dtb.data_accesses 345543987 # DTB accesses -system.cpu.itb.fetch_hits 116217608 # ITB hits -system.cpu.itb.fetch_misses 1594 # ITB misses +system.cpu.dtb.data_accesses 345544636 # DTB accesses +system.cpu.itb.fetch_hits 116218491 # ITB hits +system.cpu.itb.fetch_misses 1583 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 116219202 # ITB accesses +system.cpu.itb.fetch_accesses 116220074 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -326,138 +327,138 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 174766258500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 349532518 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 175004412500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 350008826 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 116536228 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 973715519 # Number of instructions fetch has processed -system.cpu.fetch.Branches 129267026 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 104850078 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 232359516 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 756618 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 832 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 13025 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 116537595 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 973721565 # Number of instructions fetch has processed +system.cpu.fetch.Branches 129267773 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 104850621 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 232833162 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 756818 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 12983 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 116217608 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 170932 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 349287938 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.787716 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.090069 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 116218491 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 171000 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 349762998 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.783947 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.089679 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 152570668 43.68% 43.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 21852908 6.26% 49.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15618674 4.47% 54.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 24569577 7.03% 61.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 38589117 11.05% 72.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15690770 4.49% 76.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 12536709 3.59% 80.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3990160 1.14% 81.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 63869355 18.29% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 153044218 43.76% 43.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 21853200 6.25% 50.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15619262 4.47% 54.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 24569789 7.02% 61.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 38589030 11.03% 72.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 15690779 4.49% 77.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 12536762 3.58% 80.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3989777 1.14% 81.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 63870181 18.26% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 349287938 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.369828 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.785765 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 85729217 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 85771889 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158922951 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18492364 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 371517 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11932000 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 7014 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 968678626 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 25475 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 371517 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 93246352 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12124008 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14162 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 169252951 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 74278948 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 966798475 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 812 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 25198716 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 40147884 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 7202949 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 666569389 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1151537527 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1114498375 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 37039151 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 349762998 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.369327 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.781991 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 85730052 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 86245168 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158924333 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18491829 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 371616 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11931982 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 7013 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 968682189 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 25467 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 371616 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 93247100 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12146615 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14284 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 169253997 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 74729386 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 966801753 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1559 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 25162616 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 40511587 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7290496 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 666571567 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1151541399 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1114502328 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 37039070 # Number of floating rename lookups system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27602231 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1366 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 86 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 87958062 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 245057270 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 102624029 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 35348443 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4751860 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 877942600 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 76 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 871652294 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 10599 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 35560646 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 10943510 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 349287938 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.495512 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.135180 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27604409 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1367 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 87953522 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 245057905 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 102624371 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 35358842 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4732178 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 877945283 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 77 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 871653931 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 10631 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 35563330 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 10945081 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 349762998 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.492127 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.135671 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 75519507 21.62% 21.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 61352705 17.57% 39.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 57497159 16.46% 55.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 51075272 14.62% 70.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 45041028 12.90% 83.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20641156 5.91% 89.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 18147367 5.20% 94.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10284591 2.94% 97.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 9729153 2.79% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 75990310 21.73% 21.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 61353138 17.54% 39.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 57501132 16.44% 55.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 51071612 14.60% 70.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 45054201 12.88% 83.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20633149 5.90% 89.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 18143842 5.19% 94.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10286820 2.94% 97.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 9728794 2.78% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 349287938 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 349762998 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3589516 19.40% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11788826 63.72% 83.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3123532 16.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3589530 19.39% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11797020 63.73% 83.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3124042 16.88% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 505111201 57.95% 57.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 505112247 57.95% 57.95% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 7850 0.00% 57.95% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 13300877 1.53% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 3826560 0.44% 59.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 3339807 0.38% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 13300875 1.53% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 3826555 0.44% 59.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 3339806 0.38% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 4 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.30% # Type of FU issued @@ -481,82 +482,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.30% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 244259904 28.02% 88.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 101804815 11.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 244260355 28.02% 88.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 101804963 11.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 871652294 # Type of FU issued -system.cpu.iq.rate 2.493766 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18501874 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021226 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2041816444 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 876761594 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 835992532 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 69288555 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 36778587 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 34169821 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 855051836 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 35101056 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 65597329 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 871653931 # Type of FU issued +system.cpu.iq.rate 2.490377 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18510592 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021236 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2042303381 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 876767032 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 835994185 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 69288702 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 36778589 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 34169846 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 855062076 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 35101171 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 65597395 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7546673 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5138 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 37094 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4322829 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7547308 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5161 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 37165 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4323171 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2714 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4439 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 4324 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 371517 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4003286 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 617757 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 966013425 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 16652 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 245057270 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 102624029 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 76 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 538427 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 92920 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 37094 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 128203 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 15937 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 144140 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 871030251 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 243869972 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 622043 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 371616 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4020858 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 620837 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 966016228 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 16689 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 245057905 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 102624371 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 77 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 538553 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 95932 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 37165 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 128220 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 15953 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 144173 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 871032011 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 243870521 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 621920 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 88070749 # number of nop insts executed -system.cpu.iew.exec_refs 345544428 # number of memory reference insts executed -system.cpu.iew.exec_branches 127159642 # Number of branches executed -system.cpu.iew.exec_stores 101674456 # Number of stores executed -system.cpu.iew.exec_rate 2.491986 # Inst execution rate -system.cpu.iew.wb_sent 870623887 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 870162353 # cumulative count of insts written-back -system.cpu.iew.wb_producers 525000957 # num instructions producing a value -system.cpu.iew.wb_consumers 821946847 # num instructions consuming a value -system.cpu.iew.wb_rate 2.489503 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.638729 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 31811556 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 88070868 # number of nop insts executed +system.cpu.iew.exec_refs 345545074 # number of memory reference insts executed +system.cpu.iew.exec_branches 127159833 # Number of branches executed +system.cpu.iew.exec_stores 101674553 # Number of stores executed +system.cpu.iew.exec_rate 2.488600 # Inst execution rate +system.cpu.iew.wb_sent 870625746 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 870164031 # cumulative count of insts written-back +system.cpu.iew.wb_producers 525002727 # num instructions producing a value +system.cpu.iew.wb_consumers 821961915 # num instructions consuming a value +system.cpu.iew.wb_rate 2.486120 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.638719 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 31814193 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 138434 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 345159794 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.690312 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.060061 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 138436 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 345634386 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.686618 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.059575 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 109423104 31.70% 31.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 81928646 23.74% 55.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 29947333 8.68% 64.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 19779535 5.73% 69.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 17819278 5.16% 75.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7961935 2.31% 77.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3040960 0.88% 78.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3978860 1.15% 79.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 71280143 20.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 109896722 31.80% 31.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 81929003 23.70% 55.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 29947850 8.66% 64.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 19779542 5.72% 69.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 17820096 5.16% 75.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7961930 2.30% 77.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3040428 0.88% 78.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3978823 1.15% 79.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 71279992 20.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 345159794 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 345634386 # Number of insts commited each cycle system.cpu.commit.committedInsts 928587628 # Number of instructions committed system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -602,127 +603,127 @@ system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction -system.cpu.commit.bw_lim_events 71280143 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1231657697 # The number of ROB reads -system.cpu.rob.rob_writes 1924928764 # The number of ROB writes -system.cpu.timesIdled 3152 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 244580 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 71279992 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1232135077 # The number of ROB reads +system.cpu.rob.rob_writes 1924934508 # The number of ROB writes +system.cpu.timesIdled 3150 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 245828 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 842382029 # Number of Instructions Simulated system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.414933 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.414933 # CPI: Total CPI of All Threads -system.cpu.ipc 2.410025 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.410025 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1104176449 # number of integer regfile reads -system.cpu.int_regfile_writes 635594518 # number of integer regfile writes -system.cpu.fp_regfile_reads 36406853 # number of floating regfile reads -system.cpu.fp_regfile_writes 24680531 # number of floating regfile writes +system.cpu.cpi 0.415499 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.415499 # CPI: Total CPI of All Threads +system.cpu.ipc 2.406745 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.406745 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1104178752 # number of integer regfile reads +system.cpu.int_regfile_writes 635595888 # number of integer regfile writes +system.cpu.fp_regfile_reads 36406844 # number of floating regfile reads +system.cpu.fp_regfile_writes 24680552 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 776668 # number of replacements -system.cpu.dcache.tags.tagsinuse 4091.068449 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 273851879 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 780764 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 350.748599 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 371412500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4091.068449 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998796 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998796 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 776667 # number of replacements +system.cpu.dcache.tags.tagsinuse 4091.035125 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 273851714 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 780763 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 350.748837 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 374790500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4091.035125 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998788 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998788 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 421 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1011 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1013 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 62 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 553379090 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 553379090 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 176443243 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 176443243 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 97408623 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 97408623 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 553380005 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 553380005 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 176443372 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 176443372 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 97408329 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 97408329 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 273851866 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 273851866 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 273851866 # number of overall hits -system.cpu.dcache.overall_hits::total 273851866 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1554707 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1554707 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 892577 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 892577 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2447284 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2447284 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2447284 # number of overall misses -system.cpu.dcache.overall_misses::total 2447284 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 83708553000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 83708553000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 61914869831 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 61914869831 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 145623422831 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 145623422831 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 145623422831 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 145623422831 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 177997950 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 177997950 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 273851701 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 273851701 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 273851701 # number of overall hits +system.cpu.dcache.overall_hits::total 273851701 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1555036 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1555036 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 892871 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 892871 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2447907 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2447907 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2447907 # number of overall misses +system.cpu.dcache.overall_misses::total 2447907 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 84877374000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 84877374000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 62367572330 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 62367572330 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 147244946330 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 147244946330 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 147244946330 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 147244946330 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 177998408 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 177998408 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 276299150 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 276299150 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 276299150 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 276299150 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008734 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008734 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009080 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009080 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008857 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008857 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008857 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53842.012032 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53842.012032 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69366.418618 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69366.418618 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59504.096309 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59504.096309 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59504.096309 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59504.096309 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 22333 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 68716 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 347 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 519 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 64.360231 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 132.400771 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88604 # number of writebacks -system.cpu.dcache.writebacks::total 88604 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 842561 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 842561 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 823959 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 823959 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1666520 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1666520 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1666520 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1666520 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712146 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712146 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68618 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 68618 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 780764 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 780764 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 780764 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 780764 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24226479500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24226479500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5661245497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5661245497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29887724997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29887724997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29887724997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29887724997 # number of overall MSHR miss cycles +system.cpu.dcache.demand_accesses::cpu.data 276299608 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 276299608 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 276299608 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 276299608 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008736 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008736 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009083 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009083 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008860 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008860 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008860 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008860 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54582.256617 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54582.256617 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69850.596928 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69850.596928 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60151.364545 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60151.364545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60151.364545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60151.364545 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24555 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 63758 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 349 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 520 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 70.358166 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 122.611538 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 88567 # number of writebacks +system.cpu.dcache.writebacks::total 88567 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 842892 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 842892 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 824252 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 824252 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1667144 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1667144 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1667144 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1667144 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712144 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712144 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68619 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 68619 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 780763 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 780763 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 780763 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 780763 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24487996000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24487996000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5721430497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5721430497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30209426497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 30209426497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30209426497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 30209426497 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004001 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004001 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000698 # mshr miss rate for WriteReq accesses @@ -731,24 +732,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002826 system.cpu.dcache.demand_mshr_miss_rate::total 0.002826 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002826 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002826 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34018.978552 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34018.978552 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82503.796336 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82503.796336 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38280.101282 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 38280.101282 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38280.101282 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 38280.101282 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 4617 # number of replacements -system.cpu.icache.tags.tagsinuse 1647.904441 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 116209358 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6322 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18381.739639 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34386.298277 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34386.298277 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83379.683426 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83379.683426 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38692.185077 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 38692.185077 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38692.185077 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 38692.185077 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 4616 # number of replacements +system.cpu.icache.tags.tagsinuse 1647.876124 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 116210243 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6321 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18384.787692 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1647.904441 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.804641 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.804641 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1647.876124 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.804627 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.804627 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1705 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id @@ -756,187 +757,187 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 1 system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1541 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.832520 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 232441538 # Number of tag accesses -system.cpu.icache.tags.data_accesses 232441538 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -949,120 +950,126 @@ system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66625 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66625 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2720 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2720 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222822 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222822 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2720 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 289447 # 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Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 718468 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155286 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4617 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 881176 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 68618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 68618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 6323 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 712146 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17262 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2338196 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2355458 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 700096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55639552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56339648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259794 # Total snoops (count) +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 718465 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155249 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4616 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 881227 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 68619 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 68619 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 6322 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 712144 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17259 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2338193 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2355452 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55637120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56337088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259809 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 4267648 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1046881 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001913 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.043699 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1046894 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001918 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.043754 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1044878 99.81% 99.81% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2003 0.19% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1044886 99.81% 99.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2008 0.19% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1046881 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 877407000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1046894 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 877367000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 9483000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 9481500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1171146499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1171144500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 225541 # Transaction distribution +system.membus.snoop_filter.tot_requests 549975 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 257802 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 175004412500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 225548 # Transaction distribution system.membus.trans_dist::WritebackDirty 66682 # Transaction distribution -system.membus.trans_dist::CleanEvict 191110 # Transaction distribution +system.membus.trans_dist::CleanEvict 191120 # Transaction distribution system.membus.trans_dist::ReadExReq 66625 # Transaction distribution system.membus.trans_dist::ReadExResp 66625 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225541 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842124 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842124 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22966272 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22966272 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225548 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842148 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842148 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22966720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22966720 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 549958 # Request fanout histogram +system.membus.snoop_fanout::samples 292173 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 549958 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 292173 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 549958 # Request fanout histogram -system.membus.reqLayer0.occupancy 877671500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 292173 # Request fanout histogram +system.membus.reqLayer0.occupancy 877549500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1551270000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1551106000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index b6b81e33b..efcf10ec9 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.464395 # Nu sim_ticks 464394627000 # Number of ticks simulated final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2033284 # Simulator instruction rate (inst/s) -host_op_rate 2033284 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1016862727 # Simulator tick rate (ticks/s) -host_mem_usage 248468 # Number of bytes of host memory used -host_seconds 456.69 # Real time elapsed on the host +host_inst_rate 1533629 # Simulator instruction rate (inst/s) +host_op_rate 1533629 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 766980884 # Simulator tick rate (ticks/s) +host_mem_usage 251816 # Number of bytes of host memory used +host_seconds 605.48 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -130,6 +130,12 @@ system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 928789150 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 464394627000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 1166299747 # Transaction distribution system.membus.trans_dist::ReadResp 1166299747 # Transaction distribution @@ -144,14 +150,14 @@ system.membus.pkt_size::total 6109961839 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 1264600947 # Request fanout histogram -system.membus.snoop_fanout::mean 0.734452 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.441624 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 335811797 26.55% 26.55% # Request fanout histogram -system.membus.snoop_fanout::1 928789150 73.45% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1264600947 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 1264600947 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index f13a4ce2b..7031d8335 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.288319 # Number of seconds simulated -sim_ticks 1288319411500 # Number of ticks simulated -final_tick 1288319411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.288611 # Number of seconds simulated +sim_ticks 1288611150500 # Number of ticks simulated +final_tick 1288611150500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1112167 # Simulator instruction rate (inst/s) -host_op_rate 1112167 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1543016447 # Simulator tick rate (ticks/s) -host_mem_usage 257436 # Number of bytes of host memory used -host_seconds 834.94 # Real time elapsed on the host +host_inst_rate 1122029 # Simulator instruction rate (inst/s) +host_op_rate 1122029 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1557051854 # Simulator tick rate (ticks/s) +host_mem_usage 262324 # Number of bytes of host memory used +host_seconds 827.60 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 137024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18511872 # Number of bytes read from this memory -system.physmem.bytes_read::total 18648896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18512320 # Number of bytes read from this memory +system.physmem.bytes_read::total 18649344 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 137024 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 137024 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2141 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289248 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291389 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289255 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291396 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 106359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14369008 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14475367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 106359 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 106359 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3312619 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3312619 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3312619 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 106359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14369008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17787986 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 106335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14366103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14472437 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 106335 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 106335 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3311870 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3311870 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3311870 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 106335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14366103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17784307 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -72,8 +72,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1288319411500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2576638823 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1288611150500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2577222301 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928587629 # Number of instructions committed @@ -92,7 +92,7 @@ system.cpu.num_mem_refs 336013318 # nu system.cpu.num_load_insts 237705247 # Number of load instructions system.cpu.num_store_insts 98308071 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2576638823 # Number of busy cycles +system.cpu.num_busy_cycles 2577222301 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 123111018 # Number of branches fetched @@ -131,16 +131,16 @@ system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 928789150 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 776432 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.180330 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4094.168779 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1104319500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.180330 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999556 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999556 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 1112572500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.168779 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999553 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999553 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id @@ -150,7 +150,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits @@ -167,14 +167,14 @@ system.cpu.dcache.demand_misses::cpu.data 780528 # n system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses system.cpu.dcache.overall_misses::total 780528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 20157098000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 20157098000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4162936000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4162936000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24320034000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24320034000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24320034000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24320034000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 20380048000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 20380048000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4229584000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4229584000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24609632000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24609632000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24609632000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24609632000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) @@ -191,22 +191,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28329.868421 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28329.868421 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60320.166923 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60320.166923 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31158.438903 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31158.438903 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31158.438903 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31158.438903 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28643.214329 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28643.214329 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61285.884024 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61285.884024 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31529.467232 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31529.467232 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31529.467232 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31529.467232 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88866 # number of writebacks -system.cpu.dcache.writebacks::total 88866 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88841 # number of writebacks +system.cpu.dcache.writebacks::total 88841 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses @@ -215,14 +215,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780528 system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19445584000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 19445584000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4093922000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4093922000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23539506000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23539506000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23539506000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23539506000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19668534000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 19668534000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4160570000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4160570000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23829104000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23829104000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23829104000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23829104000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses @@ -231,24 +231,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27329.868421 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27329.868421 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59320.166923 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59320.166923 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27643.214329 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27643.214329 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60285.884024 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60285.884024 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30529.467232 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30529.467232 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30529.467232 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30529.467232 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 4618 # number of replacements -system.cpu.icache.tags.tagsinuse 1474.418872 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1474.409268 # Cycle average of tags in use system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1474.418872 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.719931 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.719931 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1474.409268 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.719926 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.719926 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id @@ -257,7 +257,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1428 system.cpu.icache.tags.occ_task_id_percent::1024 0.756836 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1857584470 # Number of tag accesses system.cpu.icache.tags.data_accesses 1857584470 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 928782983 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 928782983 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 928782983 # number of demand (read+write) hits @@ -270,12 +270,12 @@ system.cpu.icache.demand_misses::cpu.inst 6168 # n system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses system.cpu.icache.overall_misses::total 6168 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 185126500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 185126500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 185126500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 185126500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 185126500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 185126500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 187267500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 187267500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 187267500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 187267500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 187267500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 187267500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses @@ -288,12 +288,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30014.023995 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 30014.023995 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 30014.023995 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 30014.023995 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 30014.023995 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 30014.023995 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30361.138132 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 30361.138132 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 30361.138132 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 30361.138132 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 30361.138132 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 30361.138132 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -308,90 +308,90 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 6168 system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 178958500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 178958500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 178958500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 178958500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 178958500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 178958500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 181099500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 181099500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 181099500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 181099500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 181099500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 181099500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29014.023995 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29014.023995 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 258847 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32654.651136 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1207020 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 291581 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.139570 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2500.518191 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 47.895472 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30106.237473 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.076310 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001462 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.918769 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996541 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32734 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1142 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31154 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998962 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12902563 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12902563 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 88866 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88866 # number of WritebackDirty hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29361.138132 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29361.138132 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29361.138132 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 29361.138132 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29361.138132 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 29361.138132 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 258865 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32717.214949 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1276112 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 291633 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.375746 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 4209362000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 27.944200 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 47.856544 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 32641.414205 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000853 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001460 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.996137 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998450 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1143 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31170 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 12833601 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 12833601 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 88841 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 88841 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 4618 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 4618 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4027 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 4027 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488914 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 488914 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488907 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 488907 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 4027 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 491280 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 495307 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 491273 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 495300 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 4027 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 491280 # number of overall hits -system.cpu.l2cache.overall_hits::total 495307 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 491273 # number of overall hits +system.cpu.l2cache.overall_hits::total 495300 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 66648 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66648 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2141 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 2141 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222600 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222600 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222607 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 222607 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 2141 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 289248 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 291389 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 289255 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 291396 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2141 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 289248 # number of overall misses -system.cpu.l2cache.overall_misses::total 291389 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3965557000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3965557000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 127415500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 127415500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13244711500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 13244711500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 127415500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 17210268500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 17337684000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 127415500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 17210268500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 17337684000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88866 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88866 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 289255 # number of overall misses +system.cpu.l2cache.overall_misses::total 291396 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4032205000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4032205000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 129556500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 129556500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13467735000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 13467735000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 129556500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 17499940000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17629496500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 129556500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 17499940000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17629496500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 88841 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 88841 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 4618 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 4618 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69014 # number of ReadExReq accesses(hits+misses) @@ -410,26 +410,26 @@ system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965717 system.cpu.l2cache.ReadExReq_miss_rate::total 0.965717 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.347114 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.347114 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312854 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312854 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312864 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312864 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.347114 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.370580 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.370396 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.370589 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.370405 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.347114 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.370580 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.370396 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.015004 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.015004 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59512.143858 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59512.143858 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.051662 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.051662 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59512.143858 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.043216 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59500.132126 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59512.143858 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.043216 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59500.132126 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.370589 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.370405 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.015004 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.015004 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60512.143858 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60512.143858 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.051661 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.051661 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60512.143858 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.043214 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60500.132123 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60512.143858 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.043214 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60500.132123 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -444,63 +444,63 @@ system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66648 system.cpu.l2cache.ReadExReq_mshr_misses::total 66648 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2141 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2141 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222600 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222600 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222607 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222607 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2141 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 289248 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291389 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 289255 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291396 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2141 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 289248 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291389 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3299077000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3299077000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 106005500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 106005500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11018711500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11018711500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106005500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14317788500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14423794000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106005500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14317788500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14423794000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 289255 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 291396 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3365725000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3365725000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 108146500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 108146500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11241665000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11241665000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 108146500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14607390000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14715536500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 108146500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14607390000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14715536500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965717 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965717 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.347114 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312854 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312854 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312864 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312864 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.370396 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370589 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.370405 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.370396 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.015004 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.015004 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49512.143858 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49512.143858 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.051662 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.051662 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49512.143858 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.043216 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.132126 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49512.143858 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.043216 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.132126 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370589 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.370405 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.015004 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.015004 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50512.143858 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50512.143858 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.051661 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.051661 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50512.143858 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.043214 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.132123 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50512.143858 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.043214 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.132123 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1567746 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 781050 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1718 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1718 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1726 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1726 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155549 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155524 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 4618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 879730 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 879773 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69014 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 6168 # Transaction distribution @@ -509,53 +509,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337488 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2354442 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 690304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55641216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56331520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 258847 # Total snoops (count) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55639616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56329920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 258865 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 4267712 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1045543 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001643 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.040503 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1045561 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001651 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.040596 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1043825 99.84% 99.84% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1718 0.16% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1043835 99.83% 99.83% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1726 0.17% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1045543 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 877357000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1045561 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 877332000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 224741 # Transaction distribution +system.membus.snoop_filter.tot_requests 548536 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 257140 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 224748 # Transaction distribution system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 190447 # Transaction distribution +system.membus.trans_dist::CleanEvict 190457 # Transaction distribution system.membus.trans_dist::ReadExReq 66648 # Transaction distribution system.membus.trans_dist::ReadExResp 66648 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 224741 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 839908 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22916608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22916608 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 224748 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839932 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 839932 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22917056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22917056 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 548519 # Request fanout histogram +system.membus.snoop_fanout::samples 291396 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 548519 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 291396 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 548519 # Request fanout histogram -system.membus.reqLayer0.occupancy 815264000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 291396 # Request fanout histogram +system.membus.reqLayer0.occupancy 815280500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1456945000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1456980000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 031a11fd6..228ad0113 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,96 +1,96 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.512589 # Number of seconds simulated -sim_ticks 512588680500 # Number of ticks simulated -final_tick 512588680500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.512877 # Number of seconds simulated +sim_ticks 512876814500 # Number of ticks simulated +final_tick 512876814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 180394 # Simulator instruction rate (inst/s) -host_op_rate 222088 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 144333179 # Simulator tick rate (ticks/s) -host_mem_usage 275860 # Number of bytes of host memory used -host_seconds 3551.43 # Real time elapsed on the host +host_inst_rate 169706 # Simulator instruction rate (inst/s) +host_op_rate 208931 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 135858559 # Simulator tick rate (ticks/s) +host_mem_usage 281524 # Number of bytes of host memory used +host_seconds 3775.08 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 164160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18474048 # Number of bytes read from this memory -system.physmem.bytes_read::total 18638208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18474496 # Number of bytes read from this memory +system.physmem.bytes_read::total 18638656 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 164160 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 164160 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2565 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288657 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291222 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288664 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291229 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 320257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36040687 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36360943 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 320257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 320257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8252761 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8252761 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8252761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 320257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36040687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 44613705 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291222 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 320077 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36021312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36341389 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 320077 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 320077 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8248125 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8248125 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8248125 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 320077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36021312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 44589514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291229 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 291222 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 291229 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18617600 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20608 # Total number of bytes read from write queue -system.physmem.bytesWritten 4228864 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18638208 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18616640 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 22016 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228352 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18638656 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 322 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 344 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18288 # Per bank write bursts -system.physmem.perBankRdBursts::1 18133 # Per bank write bursts -system.physmem.perBankRdBursts::2 18220 # Per bank write bursts -system.physmem.perBankRdBursts::3 18178 # Per bank write bursts -system.physmem.perBankRdBursts::4 18281 # Per bank write bursts -system.physmem.perBankRdBursts::5 18410 # Per bank write bursts -system.physmem.perBankRdBursts::6 18174 # Per bank write bursts -system.physmem.perBankRdBursts::7 17993 # Per bank write bursts -system.physmem.perBankRdBursts::8 18029 # Per bank write bursts -system.physmem.perBankRdBursts::9 18057 # Per bank write bursts -system.physmem.perBankRdBursts::10 18103 # Per bank write bursts -system.physmem.perBankRdBursts::11 18205 # Per bank write bursts -system.physmem.perBankRdBursts::12 18223 # Per bank write bursts -system.physmem.perBankRdBursts::13 18272 # Per bank write bursts -system.physmem.perBankRdBursts::14 18077 # Per bank write bursts -system.physmem.perBankRdBursts::15 18257 # Per bank write bursts +system.physmem.perBankRdBursts::0 18285 # Per bank write bursts +system.physmem.perBankRdBursts::1 18130 # Per bank write bursts +system.physmem.perBankRdBursts::2 18219 # Per bank write bursts +system.physmem.perBankRdBursts::3 18177 # Per bank write bursts +system.physmem.perBankRdBursts::4 18285 # Per bank write bursts +system.physmem.perBankRdBursts::5 18413 # Per bank write bursts +system.physmem.perBankRdBursts::6 18173 # Per bank write bursts +system.physmem.perBankRdBursts::7 17985 # Per bank write bursts +system.physmem.perBankRdBursts::8 18026 # Per bank write bursts +system.physmem.perBankRdBursts::9 18055 # Per bank write bursts +system.physmem.perBankRdBursts::10 18102 # Per bank write bursts +system.physmem.perBankRdBursts::11 18206 # Per bank write bursts +system.physmem.perBankRdBursts::12 18220 # Per bank write bursts +system.physmem.perBankRdBursts::13 18274 # Per bank write bursts +system.physmem.perBankRdBursts::14 18073 # Per bank write bursts +system.physmem.perBankRdBursts::15 18262 # Per bank write bursts system.physmem.perBankWrBursts::0 4171 # Per bank write bursts -system.physmem.perBankWrBursts::1 4099 # Per bank write bursts -system.physmem.perBankWrBursts::2 4135 # Per bank write bursts +system.physmem.perBankWrBursts::1 4098 # Per bank write bursts +system.physmem.perBankWrBursts::2 4134 # Per bank write bursts system.physmem.perBankWrBursts::3 4146 # Per bank write bursts system.physmem.perBankWrBursts::4 4223 # Per bank write bursts -system.physmem.perBankWrBursts::5 4222 # Per bank write bursts +system.physmem.perBankWrBursts::5 4224 # Per bank write bursts system.physmem.perBankWrBursts::6 4173 # Per bank write bursts -system.physmem.perBankWrBursts::7 4094 # Per bank write bursts -system.physmem.perBankWrBursts::8 4096 # Per bank write bursts +system.physmem.perBankWrBursts::7 4092 # Per bank write bursts +system.physmem.perBankWrBursts::8 4093 # Per bank write bursts system.physmem.perBankWrBursts::9 4096 # Per bank write bursts system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::12 4095 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 512588586500 # Total gap between requests +system.physmem.totGap 512876719500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291222 # Read request sizes (log2) +system.physmem.readPktSize::6 291229 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,7 +98,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290535 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290520 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 355 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -145,24 +145,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4016 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4016 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4016 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4016 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4015 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -194,87 +194,86 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 110334 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 207.049577 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 134.865332 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 256.872236 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45104 40.88% 40.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43590 39.51% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9238 8.37% 88.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1655 1.50% 90.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 896 0.81% 91.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 605 0.55% 91.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 780 0.71% 92.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 416 0.38% 92.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8050 7.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 110334 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4016 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.533367 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.247557 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 506.662918 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4014 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 110420 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 206.874986 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 134.678155 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 257.334201 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 45202 40.94% 40.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43704 39.58% 80.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9014 8.16% 88.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2046 1.85% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 604 0.55% 91.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 569 0.52% 91.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 621 0.56% 92.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 527 0.48% 92.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8133 7.37% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 110420 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4015 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.540971 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.171361 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 506.693530 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4013 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4016 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4016 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.453187 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.432732 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.838251 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3107 77.37% 77.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 907 22.58% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4016 # Writes before turning the bus around for reads -system.physmem.totQLat 2758807250 # Total ticks spent queuing -system.physmem.totMemAccLat 8213182250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1454500000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9483.70 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4015 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4015 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.455293 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.434809 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.838731 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3101 77.24% 77.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 914 22.76% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4015 # Writes before turning the bus around for reads +system.physmem.totQLat 2756382250 # Total ticks spent queuing +system.physmem.totMemAccLat 8210476000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1454425000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9475.85 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28233.70 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 36.32 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 8.25 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 36.36 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28225.85 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 36.30 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 8.24 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 36.34 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 8.25 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.35 # Data bus utilization in percentage system.physmem.busUtilRead 0.28 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.93 # Average write queue length when enqueuing -system.physmem.readRowHits 195021 # Number of row buffer hits during reads -system.physmem.writeRowHits 51610 # Number of row buffer hits during writes -system.physmem.readRowHitRate 67.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.08 # Row buffer hit rate for writes -system.physmem.avgGap 1434536.51 # Average gap between requests -system.physmem.pageHitRate 69.08 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 417312000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 227700000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1136202600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 215544240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 33479521920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 103911193800 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 216400632000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 355788106560 # Total energy per rank (pJ) -system.physmem_0.averagePower 694.106023 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 359300376000 # Time in different power states -system.physmem_0.memoryStateTime::REF 17116320000 # Time in different power states +system.physmem.avgWrQLen 27.56 # Average write queue length when enqueuing +system.physmem.readRowHits 194946 # Number of row buffer hits during reads +system.physmem.writeRowHits 51576 # Number of row buffer hits during writes +system.physmem.readRowHitRate 67.02 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.03 # Row buffer hit rate for writes +system.physmem.avgGap 1435314.77 # Average gap between requests +system.physmem.pageHitRate 69.06 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 418362840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 228273375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1136124600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 215531280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 33498338640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 103989168945 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 216505087500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 355990887180 # Total energy per rank (pJ) +system.physmem_0.averagePower 694.111511 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 359471319000 # Time in different power states +system.physmem_0.memoryStateTime::REF 17125940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 136167987750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 136275516000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 416737440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 227386500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1132435200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212628240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 33479521920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 103626578835 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 216650294250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 355745582385 # Total energy per rank (pJ) -system.physmem_1.averagePower 694.023062 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 359717078250 # Time in different power states -system.physmem_1.memoryStateTime::REF 17116320000 # Time in different power states +system.physmem_1.actEnergy 416336760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 227167875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1132396200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212589360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 33498338640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 103752790515 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 216712437000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 355952056350 # Total energy per rank (pJ) +system.physmem_1.averagePower 694.035798 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 359820444250 # Time in different power states +system.physmem_1.memoryStateTime::REF 17125940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 135751825750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 135926935750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 147261658 # Number of BP lookups system.cpu.branchPred.condPredicted 98231058 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1384734 # Number of conditional branches incorrect @@ -289,7 +288,7 @@ system.cpu.branchPred.indirectHits 15988941 # Nu system.cpu.branchPred.indirectMisses 6214 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 1280093 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -319,7 +318,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -349,7 +348,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -379,7 +378,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -410,16 +409,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 512588680500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1025177361 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1025753629 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655085 # Number of instructions committed system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed system.cpu.discardedOps 8621768 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.600202 # CPI: cycles per instruction -system.cpu.ipc 0.624921 # IPC: instructions per cycle +system.cpu.cpi 1.601101 # CPI: cycles per instruction +system.cpu.ipc 0.624570 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 385757467 48.91% 48.91% # Class of committed instruction system.cpu.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction @@ -455,28 +454,28 @@ system.cpu.op_class_0::MemWrite 128980497 16.35% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 788730744 # Class of committed instruction -system.cpu.tickCycles 955908039 # Number of cycles that the object actually ticked -system.cpu.idleCycles 69269322 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 955906199 # Number of cycles that the object actually ticked +system.cpu.idleCycles 69847430 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 778100 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.241926 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4092.223033 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378449407 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782196 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.829382 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 798177500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.241926 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999083 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999083 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 804340500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.223033 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999078 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999078 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 968 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1420 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1421 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1501 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 759383100 # Number of tag accesses system.cpu.dcache.tags.data_accesses 759383100 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 249620680 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 249620680 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits @@ -501,14 +500,14 @@ system.cpu.dcache.demand_misses::cpu.data 850904 # n system.cpu.dcache.demand_misses::total 850904 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 851045 # number of overall misses system.cpu.dcache.overall_misses::total 851045 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24628452500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24628452500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10137526000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10137526000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34765978500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34765978500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34765978500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34765978500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24857030500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24857030500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10252359000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10252359000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35109389500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35109389500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35109389500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35109389500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 250333872 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250333872 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) @@ -533,22 +532,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002243 system.cpu.dcache.demand_miss_rate::total 0.002243 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002244 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002244 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34532.709986 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34532.709986 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73613.962472 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73613.962472 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40857.697813 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40857.697813 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40850.928564 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40850.928564 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34853.209935 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34853.209935 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74447.825898 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74447.825898 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41261.281531 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41261.281531 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41254.445417 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41254.445417 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88716 # number of writebacks -system.cpu.dcache.writebacks::total 88716 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88688 # number of writebacks +system.cpu.dcache.writebacks::total 88688 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 457 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 457 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits @@ -567,16 +566,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782057 system.cpu.dcache.demand_mshr_misses::total 782057 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782196 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782196 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23907337500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23907337500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5084282000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5084282000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28991619500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28991619500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28993407500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28993407500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24135855500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24135855500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5141186000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5141186000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1790000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1790000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29277041500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29277041500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29278831500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29278831500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -587,70 +586,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33543.094558 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33543.094558 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73342.979141 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73342.979141 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37070.980120 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 37070.980120 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37066.678301 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 37066.678301 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33863.715827 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33863.715827 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74163.844090 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74163.844090 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12877.697842 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12877.697842 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37435.943288 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 37435.943288 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37431.579169 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37431.579169 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 24885 # number of replacements -system.cpu.icache.tags.tagsinuse 1711.979735 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 257789647 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1711.965016 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 257789646 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 26636 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 9678.241741 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 9678.241703 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1711.979735 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.835928 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.835928 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1711.965016 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.835920 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.835920 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1596 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 515659204 # Number of tag accesses -system.cpu.icache.tags.data_accesses 515659204 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 257789647 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 257789647 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 257789647 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 257789647 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 257789647 # number of overall hits -system.cpu.icache.overall_hits::total 257789647 # number of overall hits +system.cpu.icache.tags.tag_accesses 515659202 # Number of tag accesses +system.cpu.icache.tags.data_accesses 515659202 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 257789646 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 257789646 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 257789646 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 257789646 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 257789646 # number of overall hits +system.cpu.icache.overall_hits::total 257789646 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 26637 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 26637 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 26637 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 26637 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 26637 # number of overall misses system.cpu.icache.overall_misses::total 26637 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 515552500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 515552500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 515552500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 515552500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 515552500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 515552500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 257816284 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 257816284 # 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number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 257816283 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 257816283 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 257816283 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 257816283 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 257816283 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000103 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000103 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000103 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000103 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000103 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000103 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19354.750910 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19354.750910 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19354.750910 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19354.750910 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19354.750910 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19354.750910 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19472.500657 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19472.500657 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19472.500657 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19472.500657 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19472.500657 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19472.500657 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -665,90 +664,90 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 26637 system.cpu.icache.demand_mshr_misses::total 26637 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 26637 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 26637 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 488916500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 488916500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 488916500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 488916500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 488916500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 488916500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 492053000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 492053000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 492053000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 492053000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 492053000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 492053000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000103 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000103 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000103 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18354.788452 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18354.788452 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18354.788452 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18354.788452 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18354.788452 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18354.788452 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 258816 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32567.443571 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1247529 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 291562 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.278778 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2619.708679 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.014636 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29858.720256 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.079947 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002717 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.911216 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.993880 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32746 # Occupied blocks per task id +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18472.538199 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18472.538199 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18472.538199 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18472.538199 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18472.538199 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18472.538199 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 258837 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32655.350813 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1316948 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 291605 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.516205 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 3732066000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 41.642986 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 88.982590 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 32524.725237 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.001271 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002716 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.992576 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996562 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2978 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29128 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999329 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 13229556 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 13229556 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 88716 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88716 # number of WritebackDirty hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2976 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29149 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 13160277 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 13160277 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 88688 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 88688 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 23552 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 23552 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24067 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 24067 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490282 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 490282 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490275 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 490275 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 24067 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 493513 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 517580 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 493506 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 517573 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 24067 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 493513 # number of overall hits -system.cpu.l2cache.overall_hits::total 517580 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 493506 # number of overall hits +system.cpu.l2cache.overall_hits::total 517573 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2570 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 2570 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222592 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222592 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222599 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 222599 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 2570 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 288683 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 291253 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 288690 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 291260 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2570 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 288683 # number of overall misses -system.cpu.l2cache.overall_misses::total 291253 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4946370000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4946370000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 194980000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 194980000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17689881000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 17689881000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 194980000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22636251000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22831231000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 194980000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22636251000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22831231000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88716 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88716 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 288690 # number of overall misses +system.cpu.l2cache.overall_misses::total 291260 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5003275000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5003275000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 198116500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 198116500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17918475000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 17918475000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 198116500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22921750000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23119866500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 198116500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22921750000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23119866500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 88688 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 88688 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 23552 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 23552 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) @@ -767,26 +766,26 @@ system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.096482 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.096482 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312246 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312246 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312256 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312256 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096482 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.369067 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.360090 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.369076 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.360099 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096482 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.369067 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.360090 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74841.809021 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74841.809021 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75867.704280 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75867.704280 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79472.222721 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79472.222721 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75867.704280 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78412.137189 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78389.685256 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75867.704280 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78412.137189 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78389.685256 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.369076 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.360099 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75702.818841 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75702.818841 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77088.132296 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77088.132296 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80496.655421 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80496.655421 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77088.132296 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79399.182514 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79378.790428 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77088.132296 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79399.182514 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79378.790428 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -809,61 +808,61 @@ system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2566 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2566 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222566 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222566 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222573 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222573 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2566 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 288657 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291223 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 288664 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291230 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2566 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 288657 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291223 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4285460000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4285460000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 169076000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 169076000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15462440500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15462440500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169076000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19747900500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19916976500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169076000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19747900500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19916976500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 288664 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 291230 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4342365000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4342365000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 172194500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 172194500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15690918500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15690918500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 172194500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20033283500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20205478000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 172194500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20033283500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20205478000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096332 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312209 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312209 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312219 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312219 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369034 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.360053 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.360062 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369034 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.360053 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64841.809021 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64841.809021 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65890.880748 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65890.880748 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69473.506735 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69473.506735 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65890.880748 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68413.031730 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68390.808762 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65890.880748 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68413.031730 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68390.808762 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.360062 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65702.818841 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65702.818841 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67106.196415 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67106.196415 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70497.852390 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70497.852390 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67106.196415 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69400.006582 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69379.796037 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67106.196415 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69400.006582 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69379.796037 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1611818 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 803044 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2036 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2021 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 739510 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 154814 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 154786 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 24885 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 882102 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 882151 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 26637 # Transaction distribution @@ -872,53 +871,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342492 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2420650 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3297344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55738368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 59035712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 258816 # Total snoops (count) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55736576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 59033920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 258837 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 4230272 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1067649 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004997 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.070711 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1067670 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.005005 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.070770 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1062329 99.50% 99.50% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5305 0.50% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1062341 99.50% 99.50% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5314 0.50% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1067649 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 919510000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1067670 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 919482000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 39955996 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1173306974 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 225131 # Transaction distribution +system.membus.snoop_filter.tot_requests 548029 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 256840 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 225138 # Transaction distribution system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution -system.membus.trans_dist::CleanEvict 190690 # Transaction distribution +system.membus.trans_dist::CleanEvict 190702 # Transaction distribution system.membus.trans_dist::ReadExReq 66091 # Transaction distribution system.membus.trans_dist::ReadExResp 66091 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225131 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839232 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 839232 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22868480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22868480 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225138 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839258 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 839258 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22868928 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22868928 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 548010 # Request fanout histogram +system.membus.snoop_fanout::samples 291229 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 548010 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 291229 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 548010 # Request fanout histogram -system.membus.reqLayer0.occupancy 917220500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 291229 # Request fanout histogram +system.membus.reqLayer0.occupancy 917201000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1554785500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1554703000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index c91bb3ccb..2975218ad 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.326731 # Number of seconds simulated -sim_ticks 326731324000 # Number of ticks simulated -final_tick 326731324000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.327896 # Number of seconds simulated +sim_ticks 327895638000 # Number of ticks simulated +final_tick 327895638000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165193 # Simulator instruction rate (inst/s) -host_op_rate 203374 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 84248396 # Simulator tick rate (ticks/s) -host_mem_usage 272920 # Number of bytes of host memory used -host_seconds 3878.19 # Real time elapsed on the host +host_inst_rate 125299 # Simulator instruction rate (inst/s) +host_op_rate 154259 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64130088 # Simulator tick rate (ticks/s) +host_mem_usage 277300 # Number of bytes of host memory used +host_seconds 5112.98 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 227072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 47957824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12822400 # Number of bytes read from this memory -system.physmem.bytes_read::total 61007296 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 227072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 227072 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4245376 # Number of bytes written to this memory -system.physmem.bytes_written::total 4245376 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3548 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 749341 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 200350 # Number of read requests responded to by this memory -system.physmem.num_reads::total 953239 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66334 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66334 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 694981 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 146780613 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 39244477 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 186720071 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 694981 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 694981 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 12993477 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 12993477 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 12993477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 694981 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 146780613 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 39244477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 199713548 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 953240 # Number of read requests accepted -system.physmem.writeReqs 66334 # Number of write requests accepted -system.physmem.readBursts 953240 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66334 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 60987072 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20288 # Total number of bytes read from write queue -system.physmem.bytesWritten 4240192 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61007360 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4245376 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 317 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 64 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 266368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 48003200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12980224 # Number of bytes read from this memory +system.physmem.bytes_read::total 61249792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 266368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 266368 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4244096 # Number of bytes written to this memory +system.physmem.bytes_written::total 4244096 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4162 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 750050 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 202816 # Number of read requests responded to by this memory +system.physmem.num_reads::total 957028 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66314 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66314 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 812356 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 146397800 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 39586449 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 186796605 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 812356 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 812356 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 12943435 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12943435 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 12943435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 812356 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 146397800 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 39586449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 199740040 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 957029 # Number of read requests accepted +system.physmem.writeReqs 66314 # Number of write requests accepted +system.physmem.readBursts 957029 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66314 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 61231232 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18624 # Total number of bytes read from write queue +system.physmem.bytesWritten 4237440 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 61249856 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4244096 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 291 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 72 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19685 # Per bank write bursts -system.physmem.perBankRdBursts::1 19287 # Per bank write bursts -system.physmem.perBankRdBursts::2 657567 # Per bank write bursts -system.physmem.perBankRdBursts::3 20052 # Per bank write bursts -system.physmem.perBankRdBursts::4 19480 # Per bank write bursts -system.physmem.perBankRdBursts::5 20770 # Per bank write bursts -system.physmem.perBankRdBursts::6 19386 # Per bank write bursts -system.physmem.perBankRdBursts::7 19760 # Per bank write bursts -system.physmem.perBankRdBursts::8 19321 # Per bank write bursts -system.physmem.perBankRdBursts::9 19768 # Per bank write bursts -system.physmem.perBankRdBursts::10 19303 # Per bank write bursts -system.physmem.perBankRdBursts::11 19444 # Per bank write bursts -system.physmem.perBankRdBursts::12 19433 # Per bank write bursts -system.physmem.perBankRdBursts::13 20871 # Per bank write bursts -system.physmem.perBankRdBursts::14 19269 # Per bank write bursts -system.physmem.perBankRdBursts::15 19527 # Per bank write bursts -system.physmem.perBankWrBursts::0 4288 # Per bank write bursts -system.physmem.perBankWrBursts::1 4110 # Per bank write bursts -system.physmem.perBankWrBursts::2 4140 # Per bank write bursts -system.physmem.perBankWrBursts::3 4154 # Per bank write bursts -system.physmem.perBankWrBursts::4 4242 # Per bank write bursts -system.physmem.perBankWrBursts::5 4232 # Per bank write bursts +system.physmem.perBankRdBursts::0 19913 # Per bank write bursts +system.physmem.perBankRdBursts::1 19609 # Per bank write bursts +system.physmem.perBankRdBursts::2 657177 # Per bank write bursts +system.physmem.perBankRdBursts::3 20974 # Per bank write bursts +system.physmem.perBankRdBursts::4 19738 # Per bank write bursts +system.physmem.perBankRdBursts::5 20841 # Per bank write bursts +system.physmem.perBankRdBursts::6 19544 # Per bank write bursts +system.physmem.perBankRdBursts::7 20056 # Per bank write bursts +system.physmem.perBankRdBursts::8 19527 # Per bank write bursts +system.physmem.perBankRdBursts::9 20071 # Per bank write bursts +system.physmem.perBankRdBursts::10 19467 # Per bank write bursts +system.physmem.perBankRdBursts::11 19786 # Per bank write bursts +system.physmem.perBankRdBursts::12 19618 # Per bank write bursts +system.physmem.perBankRdBursts::13 21115 # Per bank write bursts +system.physmem.perBankRdBursts::14 19501 # Per bank write bursts +system.physmem.perBankRdBursts::15 19801 # Per bank write bursts +system.physmem.perBankWrBursts::0 4241 # Per bank write bursts +system.physmem.perBankWrBursts::1 4104 # Per bank write bursts +system.physmem.perBankWrBursts::2 4141 # Per bank write bursts +system.physmem.perBankWrBursts::3 4151 # Per bank write bursts +system.physmem.perBankWrBursts::4 4245 # Per bank write bursts +system.physmem.perBankWrBursts::5 4233 # Per bank write bursts system.physmem.perBankWrBursts::6 4174 # Per bank write bursts system.physmem.perBankWrBursts::7 4096 # Per bank write bursts -system.physmem.perBankWrBursts::8 4095 # Per bank write bursts +system.physmem.perBankWrBursts::8 4096 # Per bank write bursts system.physmem.perBankWrBursts::9 4095 # Per bank write bursts -system.physmem.perBankWrBursts::10 4095 # Per bank write bursts +system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4095 # Per bank write bursts +system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4146 # Per bank write bursts +system.physmem.perBankWrBursts::15 4151 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 326731313500 # Total gap between requests +system.physmem.totGap 327895627500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 953240 # Read request sizes (log2) +system.physmem.readPktSize::6 957029 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66334 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 759877 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14314 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6736 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6450 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7728 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8758 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 9260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 8005 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3769 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2023 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1473 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 882 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66314 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 765529 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 120932 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6427 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7705 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 9890 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 6812 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2470 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1057 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 621 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -149,48 +149,48 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see @@ -198,120 +198,126 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 187141 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.533437 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 199.264052 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 368.938471 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 57976 30.98% 30.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 60329 32.24% 63.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15964 8.53% 71.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2811 1.50% 73.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2834 1.51% 74.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2850 1.52% 76.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2680 1.43% 77.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 20043 10.71% 88.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21654 11.57% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 187141 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4039 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 232.424858 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 40.579593 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3031.486386 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 4013 99.36% 99.36% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 12 0.30% 99.65% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-12287 1 0.02% 99.68% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-16383 4 0.10% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16384-20479 4 0.10% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-28671 1 0.02% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::53248-57343 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::106496-110591 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::118784-122879 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4039 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4039 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.403318 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.369585 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.145225 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3419 84.65% 84.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 15 0.37% 85.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 455 11.27% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 68 1.68% 97.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 26 0.64% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 15 0.37% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 15 0.37% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 7 0.17% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 9 0.22% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 4 0.10% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 3 0.07% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4039 # Writes before turning the bus around for reads -system.physmem.totQLat 12733277648 # Total ticks spent queuing -system.physmem.totMemAccLat 30600583898 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4764615000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13362.34 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 194181 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 337.148207 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 191.280987 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 364.158297 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 64676 33.31% 33.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 60636 31.23% 64.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15729 8.10% 72.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3217 1.66% 74.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3574 1.84% 76.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2317 1.19% 77.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2364 1.22% 78.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 21831 11.24% 89.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19837 10.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 194181 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3990 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 177.226065 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.842577 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1813.556545 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 3969 99.47% 99.47% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 9 0.23% 99.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-12287 4 0.10% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-16383 2 0.05% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-20479 1 0.03% 99.87% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-28671 1 0.03% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::28672-32767 2 0.05% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::36864-40959 1 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::86016-90111 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3990 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3990 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.593985 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.513577 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.886226 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3332 83.51% 83.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 5 0.13% 83.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 452 11.33% 94.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 50 1.25% 96.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 19 0.48% 96.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 17 0.43% 97.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 10 0.25% 97.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 19 0.48% 97.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 12 0.30% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 15 0.38% 98.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 16 0.40% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 15 0.38% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 9 0.23% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 5 0.13% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.10% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 3 0.08% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.03% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.03% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 3 0.08% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3990 # Writes before turning the bus around for reads +system.physmem.totQLat 12587538724 # Total ticks spent queuing +system.physmem.totMemAccLat 30526376224 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4783690000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13156.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32112.34 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 186.66 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 12.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 186.72 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 12.99 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31906.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 186.74 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 12.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 186.80 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 12.94 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.56 # Data bus utilization in percentage system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.20 # Average write queue length when enqueuing -system.physmem.readRowHits 805882 # Number of row buffer hits during reads -system.physmem.writeRowHits 26140 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.57 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.44 # Row buffer hit rate for writes -system.physmem.avgGap 320458.66 # Average gap between requests -system.physmem.pageHitRate 81.64 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 905544360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 494096625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6208534800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216665280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 21340194720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 220053154905 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 3007065000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 252225255690 # Total energy per rank (pJ) -system.physmem_0.averagePower 771.975754 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3732596290 # Time in different power states -system.physmem_0.memoryStateTime::REF 10910120000 # Time in different power states +system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing +system.physmem.readRowHits 805843 # Number of row buffer hits during reads +system.physmem.writeRowHits 22921 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.23 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 34.60 # Row buffer hit rate for writes +system.physmem.avgGap 320416.15 # Average gap between requests +system.physmem.pageHitRate 81.01 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 934317720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 509796375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6223237800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216334800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 21416478720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 220944760020 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2925699000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 253170624435 # Total energy per rank (pJ) +system.physmem_0.averagePower 772.109253 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3595093339 # Time in different power states +system.physmem_0.memoryStateTime::REF 10949120000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 312084210210 # Time in different power states +system.physmem_0.memoryStateTime::ACT 313351421161 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 509143320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 277806375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1223765400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212654160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 21340194720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 86358123315 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 120283389750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 230205077040 # Total energy per rank (pJ) -system.physmem_1.averagePower 704.579541 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 199538723813 # Time in different power states -system.physmem_1.memoryStateTime::REF 10910120000 # Time in different power states +system.physmem_1.actEnergy 533690640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 291200250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1239209400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212706000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 21416478720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 88116969465 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 119441319000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 231251573475 # Total energy per rank (pJ) +system.physmem_1.averagePower 705.261391 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 198129163855 # Time in different power states +system.physmem_1.memoryStateTime::REF 10949120000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 116279470187 # Time in different power states +system.physmem_1.memoryStateTime::ACT 118816573145 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 174663372 # Number of BP lookups -system.cpu.branchPred.condPredicted 119116658 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4015834 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 96720842 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67756635 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 174659739 # Number of BP lookups +system.cpu.branchPred.condPredicted 119113225 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4015668 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 96720974 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67755362 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.053810 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18785000 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 70.052398 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18785155 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1299597 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 16716087 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 16701520 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 14567 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 1279491 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 16716286 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 16701799 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 14487 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 1279501 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -341,7 +347,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -371,7 +377,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -401,7 +407,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -432,85 +438,85 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 326731324000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 653462649 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 655791277 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 34330546 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 824287133 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174663372 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 103243155 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 614749504 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8068361 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2074 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 34353189 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 824276690 # Number of instructions fetch has processed +system.cpu.fetch.Branches 174659739 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 103242316 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 616975428 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8068049 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3172 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 247743048 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 12728 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 653119493 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.556506 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.252668 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3170 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 247740649 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 12515 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 655368010 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.551156 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.253828 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 191049151 29.25% 29.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 148339787 22.71% 51.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72947000 11.17% 63.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 240783555 36.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 193301276 29.50% 29.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 148337850 22.63% 52.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72946568 11.13% 63.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 240782316 36.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 653119493 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.267289 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.261414 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 75090408 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 234264663 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 277765642 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 61977614 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4021166 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 20809487 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13114 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 924578192 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 11804661 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4021166 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 118033326 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 133536652 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 207511 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 294559211 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 102761627 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 906540244 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6891569 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 27986936 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2218724 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 49336465 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 494906 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 980929615 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4317999600 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1001832293 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34457071 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 655368010 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.266334 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.256919 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 75112130 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 236493276 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 277761287 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 61980307 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4021010 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 20809608 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13112 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 924575224 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 11804312 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4021010 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 118055519 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 135785787 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 212608 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 294557237 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 102735849 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 906541412 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6891100 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 27959034 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2218150 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 49337765 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 468731 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 980926815 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4318009248 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1001835221 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34457086 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 106151385 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6850 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6837 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 138811891 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 271881167 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 160584857 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 6164108 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 12154940 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 899826382 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12579 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 860025252 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 9216952 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 111114003 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 244402361 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 425 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 653119493 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.316796 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.093773 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 106148585 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6844 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6835 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 138814111 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 271882035 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 160585921 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 6159068 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 12159693 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 899827224 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12580 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 860029296 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 9216848 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 111114846 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 244387313 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 426 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 655368010 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.312285 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.094624 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 190460700 29.16% 29.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 182404327 27.93% 57.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 175564310 26.88% 83.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 92270630 14.13% 98.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12417215 1.90% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 192710599 29.40% 29.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 182406257 27.83% 57.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 175554116 26.79% 84.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 92275656 14.08% 98.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12419071 1.89% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 2311 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -518,9 +524,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 653119493 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 655368010 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 66606660 24.62% 24.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 66605310 24.62% 24.62% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 18142 0.01% 24.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 24.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.63% # attempts to use FU when none available @@ -549,13 +555,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.87% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 134118538 49.58% 74.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 69109914 25.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 134121363 49.58% 74.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 69112589 25.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413086253 48.03% 48.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5187655 0.60% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413090005 48.03% 48.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5187656 0.60% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued @@ -577,88 +583,88 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 3187674 0.37% 49.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 2550149 0.30% 49.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550150 0.30% 49.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478193 1.33% 50.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478194 1.33% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 266665790 31.01% 81.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 157232010 18.28% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 266665504 31.01% 81.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 157232585 18.28% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 860025252 # Type of FU issued -system.cpu.iq.rate 1.316105 # Inst issue rate -system.cpu.iq.fu_busy_cnt 270490143 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.314514 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2595335329 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 980330228 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 820077465 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 57541763 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 30641547 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 24878664 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1098495276 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 32020119 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 13987051 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 860029296 # Type of FU issued +system.cpu.iq.rate 1.311438 # Inst issue rate +system.cpu.iq.fu_busy_cnt 270494293 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.314518 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2597595667 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 980331886 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 820082893 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 57542076 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 30641581 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 24878673 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1098503163 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 32020426 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 13986768 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 19640229 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 19641097 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 121 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18814 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 31604361 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18820 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 31605425 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1918936 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 18556 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 17201 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4021166 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10589336 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 14351 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 899849213 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 4021010 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10590461 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6281 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 899849934 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 271881167 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 160584857 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6839 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 943 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11501 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18814 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3295227 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3290376 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6585603 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 850170088 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 263374256 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9855164 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 271882035 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 160585921 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6840 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 959 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3423 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18820 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3295129 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3290187 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6585316 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 850173752 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 263373804 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9855544 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10252 # number of nop insts executed -system.cpu.iew.exec_refs 416063199 # number of memory reference insts executed -system.cpu.iew.exec_branches 143379422 # Number of branches executed -system.cpu.iew.exec_stores 152688943 # Number of stores executed -system.cpu.iew.exec_rate 1.301023 # Inst execution rate -system.cpu.iew.wb_sent 846292107 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 844956129 # cumulative count of insts written-back -system.cpu.iew.wb_producers 487338276 # num instructions producing a value -system.cpu.iew.wb_consumers 808096579 # num instructions consuming a value -system.cpu.iew.wb_rate 1.293044 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.603069 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 103168329 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 10130 # number of nop insts executed +system.cpu.iew.exec_refs 416063188 # number of memory reference insts executed +system.cpu.iew.exec_branches 143381327 # Number of branches executed +system.cpu.iew.exec_stores 152689384 # Number of stores executed +system.cpu.iew.exec_rate 1.296409 # Inst execution rate +system.cpu.iew.wb_sent 846297655 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 844961566 # cumulative count of insts written-back +system.cpu.iew.wb_producers 487343298 # num instructions producing a value +system.cpu.iew.wb_consumers 808106626 # num instructions consuming a value +system.cpu.iew.wb_rate 1.288461 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.603068 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 103169122 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4002820 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 638538795 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.235211 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.072799 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 4002654 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 640787345 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.230876 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.070419 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 348204518 54.53% 54.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 137237104 21.49% 76.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 51340026 8.04% 84.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 28219441 4.42% 88.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 14379877 2.25% 90.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14774087 2.31% 93.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7871873 1.23% 94.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6561542 1.03% 95.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29950327 4.69% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 350447626 54.69% 54.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 137241088 21.42% 76.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51341072 8.01% 84.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 28220230 4.40% 88.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 14380949 2.24% 90.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14774505 2.31% 93.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7871971 1.23% 94.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6561231 1.02% 95.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29948673 4.67% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 638538795 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 640787345 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -704,82 +710,82 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 29950327 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1500478116 # The number of ROB reads -system.cpu.rob.rob_writes 1798380886 # The number of ROB writes -system.cpu.timesIdled 9234 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 343156 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 29948673 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1502729113 # The number of ROB reads +system.cpu.rob.rob_writes 1798382436 # The number of ROB writes +system.cpu.timesIdled 10485 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 423267 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.020001 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.020001 # CPI: Total CPI of All Threads -system.cpu.ipc 0.980392 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.980392 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 868460109 # number of integer regfile reads -system.cpu.int_regfile_writes 500697086 # number of integer regfile writes -system.cpu.fp_regfile_reads 30616061 # number of floating regfile reads -system.cpu.fp_regfile_writes 22959483 # number of floating regfile writes -system.cpu.cc_regfile_reads 3322370942 # number of cc regfile reads -system.cpu.cc_regfile_writes 369203387 # number of cc regfile writes -system.cpu.misc_regfile_reads 606830951 # number of misc regfile reads +system.cpu.cpi 1.023635 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.023635 # CPI: Total CPI of All Threads +system.cpu.ipc 0.976910 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.976910 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 868461212 # number of integer regfile reads +system.cpu.int_regfile_writes 500699124 # number of integer regfile writes +system.cpu.fp_regfile_reads 30616064 # number of floating regfile reads +system.cpu.fp_regfile_writes 22959493 # number of floating regfile writes +system.cpu.cc_regfile_reads 3322386264 # number of cc regfile reads +system.cpu.cc_regfile_writes 369207629 # number of cc regfile writes +system.cpu.misc_regfile_reads 606832888 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2756452 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.912722 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 371048240 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756964 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 134.585813 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 268220000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.912722 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999830 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999830 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2756458 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.912011 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 371050492 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756970 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 134.586336 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 274880000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.912011 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999828 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999828 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 249 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 167 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 751744798 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 751744798 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 243125245 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 243125245 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127906950 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127906950 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 751746846 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 751746846 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 243126867 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 243126867 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127907624 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127907624 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5738 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5738 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 371032195 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 371032195 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 371035352 # number of overall hits -system.cpu.dcache.overall_hits::total 371035352 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2401911 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2401911 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1044527 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1044527 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 371034491 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 371034491 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 371037648 # number of overall hits +system.cpu.dcache.overall_hits::total 371037648 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2401310 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2401310 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1043853 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1043853 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3446438 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3446438 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3447085 # number of overall misses -system.cpu.dcache.overall_misses::total 3447085 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 68215511500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 68215511500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10001211350 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10001211350 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 165500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 165500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 78216722850 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 78216722850 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 78216722850 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 78216722850 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 245527156 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 245527156 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3445163 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3445163 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3445810 # number of overall misses +system.cpu.dcache.overall_misses::total 3445810 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 69278020000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 69278020000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9882341350 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9882341350 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 168500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 168500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 79160361350 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 79160361350 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 79160361350 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 79160361350 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 245528177 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 245528177 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses) @@ -788,70 +794,70 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 system.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 374478633 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 374478633 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 374482437 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 374482437 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009783 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009783 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008100 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.008100 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 374479654 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 374479654 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 374483458 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 374483458 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009780 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009780 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008095 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008095 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009203 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009203 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009205 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009205 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28400.515881 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28400.515881 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9574.871066 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9574.871066 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 55166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 55166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22694.945579 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22694.945579 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22690.685855 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22690.685855 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.009200 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009200 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009202 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009202 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28850.094324 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28850.094324 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9467.177227 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9467.177227 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 56166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 56166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22977.247042 # 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Cycle average of tags in use +system.cpu.icache.tags.total_refs 245757404 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1980032 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 124.117895 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 264413500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.874726 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997802 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997802 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 497466609 # Number of tag accesses -system.cpu.icache.tags.data_accesses 497466609 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 245759426 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 245759426 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 245759426 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 245759426 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 245759426 # number of overall hits -system.cpu.icache.overall_hits::total 245759426 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8157.462943 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8157.462943 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8157.462943 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 75964 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 122 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2856 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 25.917582 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 15 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1979880 # number of writebacks -system.cpu.icache.writebacks::total 1979880 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3014 # 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Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15777 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 61 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 259 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 92 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 412 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1577 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3842 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 9849 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.025513 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962952 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 48582269000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 294714000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 48287555000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 16536801285 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 65119070285 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001919 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001919 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.001792 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367345 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367345 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.271799 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.158926 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.271799 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001889 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001889 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002102 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002102 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367703 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367703 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002102 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272056 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.159217 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002102 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272056 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.201236 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 83155.021064 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14081.081081 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14081.081081 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 99238.250181 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 99238.250181 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67632.995210 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67632.995210 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62911.137390 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62911.137390 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63000.125516 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67237.708965 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 9474058 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736544 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643707 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 759527 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116739 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 642788 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 4016692 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 802648 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4000018 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 986541 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 243725 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 185 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 185 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980577 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036117 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5940848 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270750 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 14211598 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253457344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352858624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 606315968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1296784 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4257152 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 6034326 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.339099 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.661177 # Request fanout histogram +system.cpu.l2cache.overall_mshr_miss_rate::total 0.202053 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 81496.600949 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 81496.600949 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15114.942529 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15114.942529 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 97808.002937 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 97808.002937 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70793.658419 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70793.658419 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64318.301482 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64318.301482 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70793.658419 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64379.114726 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64414.520832 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70793.658419 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64379.114726 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 81496.600949 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68035.976715 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 9473332 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736180 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 642769 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 98 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 97 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 4016330 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 801859 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4000435 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 230920 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 258553 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 174 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 174 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980208 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036124 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5939763 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270746 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 14210509 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253411520 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352859392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 606270912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 555960 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4255168 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5293139 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.121491 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.326697 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 4630880 76.74% 76.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 760658 12.61% 89.35% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 642788 10.65% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 4650072 87.85% 87.85% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 643066 12.15% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6034326 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 9473361000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5293139 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 9472646000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2970865494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2970310996 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4135548979 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4135552978 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 951856 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66334 # Transaction distribution -system.membus.trans_dist::CleanEvict 227102 # Transaction distribution -system.membus.trans_dist::UpgradeReq 185 # Transaction distribution -system.membus.trans_dist::ReadExReq 1383 # Transaction distribution -system.membus.trans_dist::ReadExResp 1383 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 951857 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2200100 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2200100 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65252672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 65252672 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 1254437 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 940010 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 955666 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66314 # Transaction distribution +system.membus.trans_dist::CleanEvict 230920 # Transaction distribution +system.membus.trans_dist::UpgradeReq 174 # Transaction distribution +system.membus.trans_dist::ReadExReq 1362 # Transaction distribution +system.membus.trans_dist::ReadExResp 1362 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 955667 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2211465 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2211465 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65493888 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 65493888 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1246861 # Request fanout histogram +system.membus.snoop_fanout::samples 957203 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1246861 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 957203 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1246861 # Request fanout histogram -system.membus.reqLayer0.occupancy 1754485252 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 957203 # Request fanout histogram +system.membus.reqLayer0.occupancy 1755655982 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 5014122383 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5035261795 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 889d833d4..e76db2752 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.395727 # Nu sim_ticks 395726778500 # Number of ticks simulated final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 860032 # Simulator instruction rate (inst/s) -host_op_rate 1058813 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 531234389 # Simulator tick rate (ticks/s) -host_mem_usage 264584 # Number of bytes of host memory used -host_seconds 744.92 # Real time elapsed on the host +host_inst_rate 969638 # Simulator instruction rate (inst/s) +host_op_rate 1193752 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 598936996 # Simulator tick rate (ticks/s) +host_mem_usage 268708 # Number of bytes of host memory used +host_seconds 660.72 # Real time elapsed on the host sim_insts 640654411 # Number of instructions simulated sim_ops 788730070 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,6 +220,12 @@ system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730744 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 893703778 # Transaction distribution system.membus.trans_dist::ReadResp 893709517 # Transaction distribution @@ -239,14 +245,14 @@ system.membus.pkt_size::total 4241547525 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram -system.membus.snoop_fanout::mean 0.629116 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 379292454 37.09% 37.09% # Request fanout histogram -system.membus.snoop_fanout::1 643377899 62.91% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1022670353 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 1022670353 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 3a062984a..c71a30606 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.045756 # Number of seconds simulated -sim_ticks 1045756396500 # Number of ticks simulated -final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.046047 # Number of seconds simulated +sim_ticks 1046047111500 # Number of ticks simulated +final_tick 1046047111500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 546786 # Simulator instruction rate (inst/s) -host_op_rate 671760 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 894330624 # Simulator tick rate (ticks/s) -host_mem_usage 273552 # Number of bytes of host memory used -host_seconds 1169.32 # Real time elapsed on the host +host_inst_rate 666714 # Simulator instruction rate (inst/s) +host_op_rate 819099 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1090788712 # Simulator tick rate (ticks/s) +host_mem_usage 278188 # Number of bytes of host memory used +host_seconds 958.98 # Real time elapsed on the host sim_insts 639366787 # Number of instructions simulated sim_ops 785501035 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18470976 # Number of bytes read from this memory -system.physmem.bytes_read::total 18583552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18471424 # Number of bytes read from this memory +system.physmem.bytes_read::total 18584000 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 112576 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 112576 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 1759 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288609 # Number of read requests responded to by this memory -system.physmem.num_reads::total 290368 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288616 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290375 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 107650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17662790 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17770441 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 107650 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 107650 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4045179 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4045179 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4045179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 107650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17662790 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21815620 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 107620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17658310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17765930 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 107620 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107620 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4044055 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4044055 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4044055 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 107620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17658310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21809985 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -69,7 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -99,7 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -129,7 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -160,8 +160,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1045756396500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2091512793 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1046047111500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2092094223 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 639366787 # Number of instructions committed @@ -182,7 +182,7 @@ system.cpu.num_mem_refs 381221435 # nu system.cpu.num_load_insts 252240938 # Number of load instructions system.cpu.num_store_insts 128980497 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 2091512792.998000 # Number of busy cycles +system.cpu.num_busy_cycles 2092094222.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 137364860 # Number of branches fetched @@ -221,16 +221,16 @@ system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730744 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 778046 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.549761 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4093.536872 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1041808500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.549761 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999402 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999402 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 1048273500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.536872 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999399 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999399 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id @@ -240,7 +240,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits @@ -265,14 +265,14 @@ system.cpu.dcache.demand_misses::cpu.data 782004 # n system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses system.cpu.dcache.overall_misses::total 782143 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 20169396000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 20169396000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4139811500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4139811500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24309207500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24309207500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24309207500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24309207500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 20392265000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 20392265000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4205904500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4205904500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24598169500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24598169500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24598169500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24598169500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) @@ -297,22 +297,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28300.734831 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28300.734831 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59717.719949 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59717.719949 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31085.784088 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31085.784088 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31080.259620 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31080.259620 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28613.453986 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28613.453986 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60671.126466 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60671.126466 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31455.298822 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31455.298822 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31449.708685 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31449.708685 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88995 # number of writebacks -system.cpu.dcache.writebacks::total 88995 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88967 # number of writebacks +system.cpu.dcache.writebacks::total 88967 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits @@ -329,16 +329,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782003 system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19456669000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 19456669000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4070488500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4070488500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1766000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1766000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23527157500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23527157500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23528923500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23528923500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19679537000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 19679537000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4136581500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4136581500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1768000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1768000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23816118500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23816118500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23817886500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23817886500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -349,26 +349,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27300.708593 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27300.708593 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58717.719949 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58717.719949 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12705.035971 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12705.035971 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30085.763737 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27613.426783 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27613.426783 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59671.126466 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59671.126466 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12719.424460 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12719.424460 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30455.277665 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30455.277665 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30452.125701 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30452.125701 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 8769 # number of replacements -system.cpu.icache.tags.tagsinuse 1391.385132 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1391.373825 # Cycle average of tags in use system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1391.385132 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.679387 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.679387 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1391.373825 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.679382 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.679382 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id @@ -376,7 +376,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1286766008 # Number of tag accesses system.cpu.icache.tags.data_accesses 1286766008 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 643367692 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 643367692 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 643367692 # number of demand (read+write) hits @@ -389,12 +389,12 @@ system.cpu.icache.demand_misses::cpu.inst 10208 # n system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses system.cpu.icache.overall_misses::total 10208 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 219076500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 219076500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 219076500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 219076500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 219076500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 219076500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 220829500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 220829500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 220829500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 220829500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 220829500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 220829500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses @@ -407,12 +407,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21461.255878 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21461.255878 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21461.255878 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21461.255878 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21632.983934 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21632.983934 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21632.983934 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21632.983934 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21632.983934 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21632.983934 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -427,90 +427,90 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10208 system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 208868500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 208868500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 208868500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 208868500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 208868500 # 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number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11014816500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87169500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14286473000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14373642500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87169500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14286473000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14373642500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 288616 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 290375 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3337749500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3337749500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 88922500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 88922500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11237690000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11237690000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 88922500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14575439500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14664362000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 88922500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14575439500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14664362000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.172316 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312163 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312163 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312173 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312173 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.366464 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369007 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.366473 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.366464 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.801900 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.801900 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49556.281978 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49556.281978 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49501.233619 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49501.233619 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369007 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.366473 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.801900 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.801900 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50552.870949 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50552.870949 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50501.251556 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50501.251556 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50552.870949 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.148585 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.461903 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50552.870949 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.148585 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.461903 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1590 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1583 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155093 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155065 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 8769 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 880725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 880772 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution @@ -624,53 +624,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342330 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2371515 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1214528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56967296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 257772 # Total snoops (count) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55750976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56965504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 257791 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 4230272 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1050122 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002597 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.051024 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1050141 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002606 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.051116 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1047402 99.74% 99.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2713 0.26% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1047411 99.74% 99.74% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2723 0.26% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1050122 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 887346500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1050141 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 887318500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 224275 # Transaction distribution +system.membus.snoop_filter.tot_requests 546577 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 256223 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 224282 # Transaction distribution system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution -system.membus.trans_dist::CleanEvict 190094 # Transaction distribution +system.membus.trans_dist::CleanEvict 190103 # Transaction distribution system.membus.trans_dist::ReadExReq 66093 # Transaction distribution system.membus.trans_dist::ReadExResp 66093 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 224275 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836928 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 836928 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22813824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22813824 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 224282 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836951 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 836951 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22814272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22814272 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 546561 # Request fanout histogram +system.membus.snoop_fanout::samples 290376 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 546561 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 290376 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 546561 # Request fanout histogram -system.membus.reqLayer0.occupancy 811325000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 290376 # Request fanout histogram +system.membus.reqLayer0.occupancy 811341000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1451840000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1451875000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 6234d30e2..58628a22b 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.060001 # Number of seconds simulated -sim_ticks 60000593000 # Number of ticks simulated -final_tick 60000593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.060094 # Number of seconds simulated +sim_ticks 60093931000 # Number of ticks simulated +final_tick 60093931000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 262235 # Simulator instruction rate (inst/s) -host_op_rate 262235 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 177912819 # Simulator tick rate (ticks/s) -host_mem_usage 257844 # Number of bytes of host memory used -host_seconds 337.25 # Real time elapsed on the host +host_inst_rate 276952 # Simulator instruction rate (inst/s) +host_op_rate 276952 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 188189933 # Simulator tick rate (ticks/s) +host_mem_usage 264524 # Number of bytes of host memory used +host_seconds 319.33 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 433344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10150272 # Number of bytes read from this memory -system.physmem.bytes_read::total 10583616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 433344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 433344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7325952 # Number of bytes written to this memory -system.physmem.bytes_written::total 7325952 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6771 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158598 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165369 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114468 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114468 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7222329 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 169169528 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 176391857 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7222329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7222329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 122097993 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 122097993 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 122097993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7222329 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 169169528 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 298489850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165369 # Number of read requests accepted -system.physmem.writeReqs 114468 # Number of write requests accepted -system.physmem.readBursts 165369 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114468 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10583232 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 7324288 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10583616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7325952 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 438272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10168832 # Number of bytes read from this memory +system.physmem.bytes_read::total 10607104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 438272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 438272 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7376000 # Number of bytes written to this memory +system.physmem.bytes_written::total 7376000 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158888 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165736 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115250 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115250 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7293116 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 169215623 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 176508739 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7293116 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7293116 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 122741180 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 122741180 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 122741180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7293116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 169215623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 299249919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165736 # Number of read requests accepted +system.physmem.writeReqs 115250 # Number of write requests accepted +system.physmem.readBursts 165736 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115250 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10606464 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 640 # Total number of bytes read from write queue +system.physmem.bytesWritten 7374720 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10607104 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7376000 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 10 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10322 # Per bank write bursts -system.physmem.perBankRdBursts::1 10363 # Per bank write bursts -system.physmem.perBankRdBursts::2 10206 # Per bank write bursts -system.physmem.perBankRdBursts::3 10055 # Per bank write bursts -system.physmem.perBankRdBursts::4 10347 # Per bank write bursts -system.physmem.perBankRdBursts::5 10343 # Per bank write bursts -system.physmem.perBankRdBursts::6 9774 # Per bank write bursts -system.physmem.perBankRdBursts::7 10209 # Per bank write bursts -system.physmem.perBankRdBursts::8 10543 # Per bank write bursts -system.physmem.perBankRdBursts::9 10609 # Per bank write bursts -system.physmem.perBankRdBursts::10 10499 # Per bank write bursts -system.physmem.perBankRdBursts::11 10227 # Per bank write bursts -system.physmem.perBankRdBursts::12 10274 # Per bank write bursts -system.physmem.perBankRdBursts::13 10565 # Per bank write bursts -system.physmem.perBankRdBursts::14 10463 # Per bank write bursts -system.physmem.perBankRdBursts::15 10564 # Per bank write bursts -system.physmem.perBankWrBursts::0 7163 # Per bank write bursts -system.physmem.perBankWrBursts::1 7274 # Per bank write bursts -system.physmem.perBankWrBursts::2 7296 # Per bank write bursts -system.physmem.perBankWrBursts::3 7001 # Per bank write bursts -system.physmem.perBankWrBursts::4 7127 # Per bank write bursts -system.physmem.perBankWrBursts::5 7187 # Per bank write bursts -system.physmem.perBankWrBursts::6 6833 # Per bank write bursts -system.physmem.perBankWrBursts::7 7100 # Per bank write bursts -system.physmem.perBankWrBursts::8 7227 # Per bank write bursts -system.physmem.perBankWrBursts::9 7003 # Per bank write bursts -system.physmem.perBankWrBursts::10 7117 # Per bank write bursts -system.physmem.perBankWrBursts::11 7031 # Per bank write bursts -system.physmem.perBankWrBursts::12 6992 # Per bank write bursts -system.physmem.perBankWrBursts::13 7301 # Per bank write bursts -system.physmem.perBankWrBursts::14 7308 # Per bank write bursts -system.physmem.perBankWrBursts::15 7482 # Per bank write bursts +system.physmem.perBankRdBursts::0 10345 # Per bank write bursts +system.physmem.perBankRdBursts::1 10388 # Per bank write bursts +system.physmem.perBankRdBursts::2 10224 # Per bank write bursts +system.physmem.perBankRdBursts::3 10067 # Per bank write bursts +system.physmem.perBankRdBursts::4 10353 # Per bank write bursts +system.physmem.perBankRdBursts::5 10360 # Per bank write bursts +system.physmem.perBankRdBursts::6 9794 # Per bank write bursts +system.physmem.perBankRdBursts::7 10229 # Per bank write bursts +system.physmem.perBankRdBursts::8 10568 # Per bank write bursts +system.physmem.perBankRdBursts::9 10626 # Per bank write bursts +system.physmem.perBankRdBursts::10 10567 # Per bank write bursts +system.physmem.perBankRdBursts::11 10241 # Per bank write bursts +system.physmem.perBankRdBursts::12 10307 # Per bank write bursts +system.physmem.perBankRdBursts::13 10590 # Per bank write bursts +system.physmem.perBankRdBursts::14 10494 # Per bank write bursts +system.physmem.perBankRdBursts::15 10573 # Per bank write bursts +system.physmem.perBankWrBursts::0 7166 # Per bank write bursts +system.physmem.perBankWrBursts::1 7280 # Per bank write bursts +system.physmem.perBankWrBursts::2 7303 # Per bank write bursts +system.physmem.perBankWrBursts::3 7011 # Per bank write bursts +system.physmem.perBankWrBursts::4 7144 # Per bank write bursts +system.physmem.perBankWrBursts::5 7304 # Per bank write bursts +system.physmem.perBankWrBursts::6 6890 # Per bank write bursts +system.physmem.perBankWrBursts::7 7170 # Per bank write bursts +system.physmem.perBankWrBursts::8 7244 # Per bank write bursts +system.physmem.perBankWrBursts::9 7072 # Per bank write bursts +system.physmem.perBankWrBursts::10 7215 # Per bank write bursts +system.physmem.perBankWrBursts::11 7126 # Per bank write bursts +system.physmem.perBankWrBursts::12 7072 # Per bank write bursts +system.physmem.perBankWrBursts::13 7397 # Per bank write bursts +system.physmem.perBankWrBursts::14 7353 # Per bank write bursts +system.physmem.perBankWrBursts::15 7483 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 60000569500 # Total gap between requests +system.physmem.totGap 60093907500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165369 # Read request sizes (log2) +system.physmem.readPktSize::6 165736 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114468 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 164021 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115250 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 164444 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1265 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -145,27 +145,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7195 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 7151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -194,126 +194,124 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54736 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 327.137094 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 194.166991 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.705237 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19617 35.84% 35.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11794 21.55% 57.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5683 10.38% 67.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3657 6.68% 74.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2805 5.12% 79.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2027 3.70% 83.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1612 2.95% 86.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1505 2.75% 88.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6036 11.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54736 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7044 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.474162 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 336.252876 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7042 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 47112 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 381.637629 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 228.425229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 356.616158 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14360 30.48% 30.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9586 20.35% 50.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5012 10.64% 61.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3327 7.06% 68.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2470 5.24% 73.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1960 4.16% 77.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1618 3.43% 81.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1472 3.12% 84.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7307 15.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 47112 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7135 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.226489 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 17.911576 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 310.890099 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7133 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7044 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7044 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.246735 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.230854 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.753728 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6287 89.25% 89.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 12 0.17% 89.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 574 8.15% 97.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 138 1.96% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 18 0.26% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 7 0.10% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 3 0.04% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 3 0.04% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7044 # Writes before turning the bus around for reads -system.physmem.totQLat 1985984500 # Total ticks spent queuing -system.physmem.totMemAccLat 5086540750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 826815000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12009.85 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7135 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7135 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.149965 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.141117 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.557028 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6628 92.89% 92.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 11 0.15% 93.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 441 6.18% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 47 0.66% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 7 0.10% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7135 # Writes before turning the bus around for reads +system.physmem.totQLat 1892978500 # Total ticks spent queuing +system.physmem.totMemAccLat 5000341000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 828630000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11422.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30759.85 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 176.39 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 122.07 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 176.39 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 122.10 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30172.34 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 176.50 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 122.72 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 176.51 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 122.74 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.33 # Data bus utilization in percentage +system.physmem.busUtil 2.34 # Data bus utilization in percentage system.physmem.busUtilRead 1.38 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.95 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.96 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.00 # Average write queue length when enqueuing -system.physmem.readRowHits 143816 # Number of row buffer hits during reads -system.physmem.writeRowHits 81240 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.97 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 70.97 # Row buffer hit rate for writes -system.physmem.avgGap 214412.57 # Average gap between requests -system.physmem.pageHitRate 80.43 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 198964080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 108561750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 636386400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 369061920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3918454800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 12421358775 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 25100061000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 42752848725 # Total energy per rank (pJ) -system.physmem_0.averagePower 712.626862 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 41606215000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2003300000 # Time in different power states +system.physmem.avgWrQLen 23.81 # Average write queue length when enqueuing +system.physmem.readRowHits 144145 # Number of row buffer hits during reads +system.physmem.writeRowHits 89685 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.98 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.82 # Row buffer hit rate for writes +system.physmem.avgGap 213867.98 # Average gap between requests +system.physmem.pageHitRate 83.22 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 171128160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 93373500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 637486200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 370921680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3924557520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 12045269070 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 25486025250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 42728761380 # Total energy per rank (pJ) +system.physmem_0.averagePower 711.117850 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 42256937250 # Time in different power states +system.physmem_0.memoryStateTime::REF 2006420000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16383815000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15823407750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 214545240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 117063375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 652945800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 372211200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3918454800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13100937570 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24503939250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 42880097235 # Total energy per rank (pJ) -system.physmem_1.averagePower 714.747907 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 40611255500 # Time in different power states -system.physmem_1.memoryStateTime::REF 2003300000 # Time in different power states +system.physmem_1.actEnergy 184781520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 100823250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 654677400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 375431760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3924557520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 12738285900 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24878115750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 42856673100 # Total energy per rank (pJ) +system.physmem_1.averagePower 713.246634 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 41240527500 # Time in different power states +system.physmem_1.memoryStateTime::REF 2006420000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 17379160000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 16840206000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 14695118 # Number of BP lookups -system.cpu.branchPred.condPredicted 9500860 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 385258 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10182600 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6367092 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 14696108 # Number of BP lookups +system.cpu.branchPred.condPredicted 9501028 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 386035 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10214286 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6368013 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.529138 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1712185 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 84621 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 37568 # Number of indirect predictor lookups. +system.cpu.branchPred.BTBHitPct 62.344181 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1712199 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 84611 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 37560 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 31792 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5776 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 5768 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 7597 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20578668 # DTB read hits -system.cpu.dtb.read_misses 95435 # DTB read misses +system.cpu.dtb.read_hits 20579333 # DTB read hits +system.cpu.dtb.read_misses 95423 # DTB read misses system.cpu.dtb.read_acv 10 # DTB read access violations -system.cpu.dtb.read_accesses 20674103 # DTB read accesses -system.cpu.dtb.write_hits 14665915 # DTB write hits -system.cpu.dtb.write_misses 8842 # DTB write misses +system.cpu.dtb.read_accesses 20674756 # DTB read accesses +system.cpu.dtb.write_hits 14666035 # DTB write hits +system.cpu.dtb.write_misses 8840 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14674757 # DTB write accesses -system.cpu.dtb.data_hits 35244583 # DTB hits -system.cpu.dtb.data_misses 104277 # DTB misses +system.cpu.dtb.write_accesses 14674875 # DTB write accesses +system.cpu.dtb.data_hits 35245368 # DTB hits +system.cpu.dtb.data_misses 104263 # DTB misses system.cpu.dtb.data_acv 10 # DTB access violations -system.cpu.dtb.data_accesses 35348860 # DTB accesses -system.cpu.itb.fetch_hits 25646396 # ITB hits -system.cpu.itb.fetch_misses 5177 # ITB misses +system.cpu.dtb.data_accesses 35349631 # DTB accesses +system.cpu.itb.fetch_hits 25649355 # ITB hits +system.cpu.itb.fetch_misses 5175 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25651573 # ITB accesses +system.cpu.itb.fetch_accesses 25654530 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -327,16 +325,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 120001186 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 120187862 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1084586 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1085816 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.356895 # CPI: cycles per instruction -system.cpu.ipc 0.736977 # IPC: instructions per cycle +system.cpu.cpi 1.359006 # CPI: cycles per instruction +system.cpu.ipc 0.735832 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 8748916 9.89% 9.89% # Class of committed instruction system.cpu.op_class_0::IntAlu 44394799 50.20% 60.09% # Class of committed instruction system.cpu.op_class_0::IntMult 41101 0.05% 60.14% # Class of committed instruction @@ -372,58 +370,58 @@ system.cpu.op_class_0::MemWrite 14620629 16.53% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 88438073 # Class of committed instruction -system.cpu.tickCycles 91986001 # Number of cycles that the object actually ticked -system.cpu.idleCycles 28015185 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 200807 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.707874 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34647558 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204903 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 169.092488 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 690770500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.707874 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993825 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993825 # Average percentage of cache occupancy +system.cpu.tickCycles 91997493 # Number of cycles that the object actually ticked +system.cpu.idleCycles 28190369 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 200806 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.595144 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34648172 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204902 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 169.096309 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 696470500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.595144 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993798 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993798 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 661 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3387 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 646 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3399 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70183301 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70183301 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20314289 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20314289 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14333269 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333269 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34647558 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34647558 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34647558 # number of overall hits -system.cpu.dcache.overall_hits::total 34647558 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 61533 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 61533 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 280108 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280108 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 341641 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 341641 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 341641 # number of overall misses -system.cpu.dcache.overall_misses::total 341641 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2738549500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2738549500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21709876500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21709876500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24448426000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24448426000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24448426000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24448426000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20375822 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20375822 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70184522 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70184522 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 20314904 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20314904 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14333268 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333268 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34648172 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34648172 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34648172 # number of overall hits +system.cpu.dcache.overall_hits::total 34648172 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 61529 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 61529 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 280109 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280109 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 341638 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 341638 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 341638 # number of overall misses +system.cpu.dcache.overall_misses::total 341638 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2787384000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2787384000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21745232000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21745232000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24532616000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24532616000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24532616000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24532616000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20376433 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20376433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34989199 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34989199 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34989199 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34989199 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 34989810 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34989810 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34989810 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34989810 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003020 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019168 # miss rate for WriteReq accesses @@ -432,46 +430,46 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.009764 system.cpu.dcache.demand_miss_rate::total 0.009764 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009764 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009764 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44505.379227 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 44505.379227 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77505.378283 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77505.378283 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71561.744638 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71561.744638 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71561.744638 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71561.744638 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45301.955176 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 45301.955176 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77631.322092 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77631.322092 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71808.803470 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71808.803470 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71808.803470 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71808.803470 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 168446 # number of writebacks -system.cpu.dcache.writebacks::total 168446 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 197 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 197 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136541 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136541 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 136738 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 136738 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 136738 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 136738 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61336 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61336 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 168116 # number of writebacks +system.cpu.dcache.writebacks::total 168116 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 194 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 194 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136542 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 136542 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 136736 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 136736 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 136736 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 136736 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61335 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61335 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143567 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 143567 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204903 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204903 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204903 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204903 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2673829500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2673829500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10980283500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10980283500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13654113000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13654113000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13654113000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13654113000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 204902 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204902 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204902 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204902 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2722762000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2722762000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10994246500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10994246500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13717008500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13717008500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13717008500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13717008500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses @@ -480,332 +478,338 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43593.150841 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43593.150841 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76481.945712 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76481.945712 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66636.959927 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66636.959927 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66636.959927 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66636.959927 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 153927 # number of replacements -system.cpu.icache.tags.tagsinuse 1931.746995 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25490420 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 155975 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 163.426318 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 42594058500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1931.746995 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.943236 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.943236 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44391.652401 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44391.652401 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76579.203438 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76579.203438 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66944.239197 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66944.239197 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66944.239197 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66944.239197 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 153916 # number of replacements +system.cpu.icache.tags.tagsinuse 1931.382130 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25493390 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 155964 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 163.456887 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 42683279500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1931.382130 # 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number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25646396 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25646396 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006082 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.006082 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.006082 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.006082 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.006082 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.006082 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15996.393676 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15996.393676 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15996.393676 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15996.393676 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15996.393676 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15996.393676 # average overall miss latency +system.cpu.icache.tags.tag_accesses 51454674 # Number of tag accesses +system.cpu.icache.tags.data_accesses 51454674 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 25493390 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25493390 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25493390 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25493390 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25493390 # number of overall hits +system.cpu.icache.overall_hits::total 25493390 # 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number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25649355 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25649355 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25649355 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25649355 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25649355 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25649355 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006081 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.006081 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.006081 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.006081 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.006081 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.006081 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16150.553009 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16150.553009 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16150.553009 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16150.553009 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16150.553009 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16150.553009 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 153927 # number of writebacks -system.cpu.icache.writebacks::total 153927 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 155976 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 155976 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 155976 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 155976 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 155976 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 155976 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2339078500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2339078500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2339078500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2339078500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2339078500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2339078500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006082 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006082 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006082 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14996.400087 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14996.400087 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14996.400087 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14996.400087 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14996.400087 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14996.400087 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 133391 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30427.789253 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 406173 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 165503 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.454173 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26336.336681 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2098.353555 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1993.099017 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.803721 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064037 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.060825 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.928582 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32112 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1064 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11613 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19147 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 124 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.979980 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 6033974 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 6033974 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 168446 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 168446 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 153927 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 153927 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12684 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12684 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 149204 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 149204 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33621 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 33621 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 149204 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 46305 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 195509 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 149204 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 46305 # number of overall hits -system.cpu.l2cache.overall_hits::total 195509 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 130883 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130883 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6772 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 6772 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27715 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 27715 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 6772 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158598 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 165370 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 6772 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158598 # number of overall misses -system.cpu.l2cache.overall_misses::total 165370 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10631688000 # 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number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 155965 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 155965 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2362957000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2362957000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2362957000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2362957000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2362957000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2362957000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006081 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006081 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006081 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006081 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006081 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006081 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15150.559420 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15150.559420 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15150.559420 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15150.559420 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15150.559420 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15150.559420 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 135276 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31728.322423 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 547427 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 168044 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.257641 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 13928082000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 716.089195 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1994.899360 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29017.333867 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.021853 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71021.699825 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 715613 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 354734 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911825 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911825 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043914 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043914 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.456183 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.456183 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043914 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775434 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.459274 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043914 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775434 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.459274 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71323.628044 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71323.628044 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72223.244269 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72223.244269 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71496.408149 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71496.408149 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72223.244269 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71354.054428 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71389.973271 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72223.244269 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71354.054428 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71389.973271 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 715589 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 354722 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4027 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4027 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4259 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4259 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 217311 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 282914 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 153927 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 51284 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 217299 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 283367 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 153916 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 52715 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143567 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 155976 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 61336 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 465878 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610613 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1076491 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19833728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23894336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 43728064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 133391 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7325952 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 494270 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.008147 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.089894 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 155965 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 61335 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 465845 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610610 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1076455 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19832320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23873152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 43705472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 135276 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 7376064 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 496143 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.008584 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.092253 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 490243 99.19% 99.19% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4027 0.81% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 491884 99.14% 99.14% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4259 0.86% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 494270 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 680179500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 496143 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 679826500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 233962999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 233946499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 307359989 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 307357491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 60000593000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 34486 # Transaction distribution -system.membus.trans_dist::WritebackDirty 114468 # Transaction distribution -system.membus.trans_dist::CleanEvict 15010 # Transaction distribution -system.membus.trans_dist::ReadExReq 130883 # Transaction distribution -system.membus.trans_dist::ReadExResp 130883 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34486 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 460216 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 460216 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17909568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17909568 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 296869 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 131133 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 34828 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115250 # Transaction distribution +system.membus.trans_dist::CleanEvict 15883 # Transaction distribution +system.membus.trans_dist::ReadExReq 130908 # Transaction distribution +system.membus.trans_dist::ReadExResp 130908 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34828 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462605 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 462605 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17983104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17983104 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 294847 # Request fanout histogram +system.membus.snoop_fanout::samples 165736 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 294847 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 165736 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 294847 # Request fanout histogram -system.membus.reqLayer0.occupancy 819183500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 165736 # Request fanout histogram +system.membus.reqLayer0.occupancy 829286500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 873079500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 875094750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 4fef80875..4f7e5b26f 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022275 # Number of seconds simulated -sim_ticks 22275010500 # Number of ticks simulated -final_tick 22275010500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022294 # Number of seconds simulated +sim_ticks 22293541500 # Number of ticks simulated +final_tick 22293541500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 202670 # Simulator instruction rate (inst/s) -host_op_rate 202670 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56720302 # Simulator tick rate (ticks/s) -host_mem_usage 259380 # Number of bytes of host memory used -host_seconds 392.72 # Real time elapsed on the host +host_inst_rate 223643 # Simulator instruction rate (inst/s) +host_op_rate 223643 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62642230 # Simulator tick rate (ticks/s) +host_mem_usage 265292 # Number of bytes of host memory used +host_seconds 355.89 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 409984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10153216 # Number of bytes read from this memory -system.physmem.bytes_read::total 10563200 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 409984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 409984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7322816 # Number of bytes written to this memory -system.physmem.bytes_written::total 7322816 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158644 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165050 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114419 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114419 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 18405558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 455811951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 474217509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 18405558 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 18405558 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 328745793 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 328745793 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 328745793 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 18405558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 455811951 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 802963303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165050 # Number of read requests accepted -system.physmem.writeReqs 114419 # Number of write requests accepted -system.physmem.readBursts 165050 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114419 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10562816 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 7320960 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10563200 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7322816 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 413888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10171008 # Number of bytes read from this memory +system.physmem.bytes_read::total 10584896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 413888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 413888 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7372800 # Number of bytes written to this memory +system.physmem.bytes_written::total 7372800 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6467 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158922 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165389 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115200 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115200 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 18565377 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 456231147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 474796523 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 18565377 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 18565377 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 330714615 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 330714615 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 330714615 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 18565377 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 456231147 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 805511139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165389 # Number of read requests accepted +system.physmem.writeReqs 115200 # Number of write requests accepted +system.physmem.readBursts 165389 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115200 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10584320 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue +system.physmem.bytesWritten 7371392 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10584896 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7372800 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10290 # Per bank write bursts -system.physmem.perBankRdBursts::1 10331 # Per bank write bursts -system.physmem.perBankRdBursts::2 10206 # Per bank write bursts -system.physmem.perBankRdBursts::3 10021 # Per bank write bursts -system.physmem.perBankRdBursts::4 10343 # Per bank write bursts -system.physmem.perBankRdBursts::5 10313 # Per bank write bursts -system.physmem.perBankRdBursts::6 9783 # Per bank write bursts -system.physmem.perBankRdBursts::7 10190 # Per bank write bursts -system.physmem.perBankRdBursts::8 10528 # Per bank write bursts -system.physmem.perBankRdBursts::9 10599 # Per bank write bursts -system.physmem.perBankRdBursts::10 10456 # Per bank write bursts -system.physmem.perBankRdBursts::11 10208 # Per bank write bursts -system.physmem.perBankRdBursts::12 10247 # Per bank write bursts -system.physmem.perBankRdBursts::13 10535 # Per bank write bursts -system.physmem.perBankRdBursts::14 10446 # Per bank write bursts -system.physmem.perBankRdBursts::15 10548 # Per bank write bursts -system.physmem.perBankWrBursts::0 7163 # Per bank write bursts -system.physmem.perBankWrBursts::1 7268 # Per bank write bursts -system.physmem.perBankWrBursts::2 7294 # Per bank write bursts -system.physmem.perBankWrBursts::3 7001 # Per bank write bursts -system.physmem.perBankWrBursts::4 7127 # Per bank write bursts -system.physmem.perBankWrBursts::5 7177 # Per bank write bursts -system.physmem.perBankWrBursts::6 6836 # Per bank write bursts -system.physmem.perBankWrBursts::7 7101 # Per bank write bursts -system.physmem.perBankWrBursts::8 7221 # Per bank write bursts -system.physmem.perBankWrBursts::9 7003 # Per bank write bursts -system.physmem.perBankWrBursts::10 7101 # Per bank write bursts -system.physmem.perBankWrBursts::11 7022 # Per bank write bursts -system.physmem.perBankWrBursts::12 6991 # Per bank write bursts -system.physmem.perBankWrBursts::13 7296 # Per bank write bursts -system.physmem.perBankWrBursts::14 7307 # Per bank write bursts -system.physmem.perBankWrBursts::15 7482 # Per bank write bursts +system.physmem.perBankRdBursts::0 10310 # Per bank write bursts +system.physmem.perBankRdBursts::1 10350 # Per bank write bursts +system.physmem.perBankRdBursts::2 10221 # Per bank write bursts +system.physmem.perBankRdBursts::3 10037 # Per bank write bursts +system.physmem.perBankRdBursts::4 10349 # Per bank write bursts +system.physmem.perBankRdBursts::5 10325 # Per bank write bursts +system.physmem.perBankRdBursts::6 9802 # Per bank write bursts +system.physmem.perBankRdBursts::7 10210 # Per bank write bursts +system.physmem.perBankRdBursts::8 10556 # Per bank write bursts +system.physmem.perBankRdBursts::9 10619 # Per bank write bursts +system.physmem.perBankRdBursts::10 10516 # Per bank write bursts +system.physmem.perBankRdBursts::11 10224 # Per bank write bursts +system.physmem.perBankRdBursts::12 10277 # Per bank write bursts +system.physmem.perBankRdBursts::13 10556 # Per bank write bursts +system.physmem.perBankRdBursts::14 10475 # Per bank write bursts +system.physmem.perBankRdBursts::15 10553 # Per bank write bursts +system.physmem.perBankWrBursts::0 7167 # Per bank write bursts +system.physmem.perBankWrBursts::1 7278 # Per bank write bursts +system.physmem.perBankWrBursts::2 7300 # Per bank write bursts +system.physmem.perBankWrBursts::3 7008 # Per bank write bursts +system.physmem.perBankWrBursts::4 7143 # Per bank write bursts +system.physmem.perBankWrBursts::5 7301 # Per bank write bursts +system.physmem.perBankWrBursts::6 6892 # Per bank write bursts +system.physmem.perBankWrBursts::7 7161 # Per bank write bursts +system.physmem.perBankWrBursts::8 7241 # Per bank write bursts +system.physmem.perBankWrBursts::9 7068 # Per bank write bursts +system.physmem.perBankWrBursts::10 7202 # Per bank write bursts +system.physmem.perBankWrBursts::11 7125 # Per bank write bursts +system.physmem.perBankWrBursts::12 7069 # Per bank write bursts +system.physmem.perBankWrBursts::13 7390 # Per bank write bursts +system.physmem.perBankWrBursts::14 7350 # Per bank write bursts +system.physmem.perBankWrBursts::15 7483 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22274979500 # Total gap between requests +system.physmem.totGap 22293510500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165050 # Read request sizes (log2) +system.physmem.readPktSize::6 165389 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114419 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 51518 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 43059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32071 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115200 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 51841 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 42842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 37971 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 32721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -145,33 +145,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -194,127 +194,125 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 52304 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 341.896604 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 200.837447 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.790414 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18483 35.34% 35.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10568 20.20% 55.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5879 11.24% 66.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2936 5.61% 72.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2943 5.63% 78.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1490 2.85% 80.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2026 3.87% 84.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 952 1.82% 86.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7027 13.43% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 52304 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6990 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.609728 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 338.236069 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 6988 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6990 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6990 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.364807 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.334911 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.053834 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6086 87.07% 87.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 35 0.50% 87.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 455 6.51% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 219 3.13% 97.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 100 1.43% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 53 0.76% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 22 0.31% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 11 0.16% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 7 0.10% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6990 # Writes before turning the bus around for reads -system.physmem.totQLat 5740232250 # Total ticks spent queuing -system.physmem.totMemAccLat 8834807250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 825220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34780.01 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 44806 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 400.727760 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 239.628821 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 367.162466 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13215 29.49% 29.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8315 18.56% 48.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5340 11.92% 59.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2750 6.14% 66.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2605 5.81% 71.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1593 3.56% 75.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1654 3.69% 79.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1106 2.47% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8228 18.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 44806 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7098 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.298957 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 17.933264 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 317.077516 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7097 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7098 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7098 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.226824 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.209944 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.780993 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6477 91.25% 91.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 22 0.31% 91.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 336 4.73% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 168 2.37% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 66 0.93% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 27 0.38% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7098 # Writes before turning the bus around for reads +system.physmem.totQLat 5599085250 # Total ticks spent queuing +system.physmem.totMemAccLat 8699960250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 826900000 # Total ticks spent in databus transfers +system.physmem.avgQLat 33855.88 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53530.01 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 474.20 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 328.66 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 474.22 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 328.75 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 52605.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 474.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 330.65 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 474.80 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 330.71 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.27 # Data bus utilization in percentage -system.physmem.busUtilRead 3.70 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.57 # Data bus utilization in percentage for writes +system.physmem.busUtil 6.29 # Data bus utilization in percentage +system.physmem.busUtilRead 3.71 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.58 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.93 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.33 # Average write queue length when enqueuing -system.physmem.readRowHits 145488 # Number of row buffer hits during reads -system.physmem.writeRowHits 81629 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.15 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.34 # Row buffer hit rate for writes -system.physmem.avgGap 79704.65 # Average gap between requests -system.physmem.pageHitRate 81.27 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 190428840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 103904625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 635177400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 368951760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1454481600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6564184695 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 7603330500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 16920459420 # Total energy per rank (pJ) -system.physmem_0.averagePower 759.821975 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 12566232250 # Time in different power states -system.physmem_0.memoryStateTime::REF 743600000 # Time in different power states +system.physmem.avgWrQLen 24.72 # Average write queue length when enqueuing +system.physmem.readRowHits 145830 # Number of row buffer hits during reads +system.physmem.writeRowHits 89913 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.05 # Row buffer hit rate for writes +system.physmem.avgGap 79452.55 # Average gap between requests +system.physmem.pageHitRate 84.02 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 163424520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 89170125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 636441000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 370882800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1456007280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6110627715 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 8015176500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 16841729940 # Total energy per rank (pJ) +system.physmem_0.averagePower 755.495604 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 13256940500 # Time in different power states +system.physmem_0.memoryStateTime::REF 744380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8959159250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8290987000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 204618960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 111647250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 651565200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 371861280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1454481600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6822625545 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 7376602500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 16993402335 # Total energy per rank (pJ) -system.physmem_1.averagePower 763.098971 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 12188749750 # Time in different power states -system.physmem_1.memoryStateTime::REF 743600000 # Time in different power states +system.physmem_1.actEnergy 175218120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 95605125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 653343600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 375366960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1456007280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6480752940 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 7690505250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 16926799275 # Total energy per rank (pJ) +system.physmem_1.averagePower 759.311692 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 12714890500 # Time in different power states +system.physmem_1.memoryStateTime::REF 744380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9336732250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8833037000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 16474744 # Number of BP lookups -system.cpu.branchPred.condPredicted 10670267 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 324432 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8918177 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7235165 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 16464676 # Number of BP lookups +system.cpu.branchPred.condPredicted 10658312 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 322373 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8884191 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7232535 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.128296 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1973322 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3328 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 39379 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 31470 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 7909 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 2657 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 81.409044 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1975403 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3321 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 39323 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 31540 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 7783 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 2655 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22508484 # DTB read hits -system.cpu.dtb.read_misses 226837 # DTB read misses +system.cpu.dtb.read_hits 22505585 # DTB read hits +system.cpu.dtb.read_misses 226699 # DTB read misses system.cpu.dtb.read_acv 16 # DTB read access violations -system.cpu.dtb.read_accesses 22735321 # DTB read accesses -system.cpu.dtb.write_hits 15806842 # DTB write hits -system.cpu.dtb.write_misses 44564 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 15851406 # DTB write accesses -system.cpu.dtb.data_hits 38315326 # DTB hits -system.cpu.dtb.data_misses 271401 # DTB misses -system.cpu.dtb.data_acv 20 # DTB access violations -system.cpu.dtb.data_accesses 38586727 # DTB accesses -system.cpu.itb.fetch_hits 13727245 # ITB hits -system.cpu.itb.fetch_misses 29559 # ITB misses +system.cpu.dtb.read_accesses 22732284 # DTB read accesses +system.cpu.dtb.write_hits 15808846 # DTB write hits +system.cpu.dtb.write_misses 44546 # DTB write misses +system.cpu.dtb.write_acv 6 # DTB write access violations +system.cpu.dtb.write_accesses 15853392 # DTB write accesses +system.cpu.dtb.data_hits 38314431 # DTB hits +system.cpu.dtb.data_misses 271245 # DTB misses +system.cpu.dtb.data_acv 22 # DTB access violations +system.cpu.dtb.data_accesses 38585676 # DTB accesses +system.cpu.itb.fetch_hits 13724143 # ITB hits +system.cpu.itb.fetch_misses 29345 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13756804 # ITB accesses +system.cpu.itb.fetch_accesses 13753488 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -328,142 +326,142 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 44550025 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 44587088 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15536362 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105039044 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16474744 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9239957 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 27563903 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 886514 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 244 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 4722 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 331564 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 78 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13727245 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 187963 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 15537600 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105003279 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16464676 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9239478 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 27573681 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 883330 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 247 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 4700 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 330450 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 85 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13724143 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 187041 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 43880130 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.393772 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.128235 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 43888428 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.392505 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.127693 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24375049 55.55% 55.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1515026 3.45% 59.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1375639 3.13% 62.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1503768 3.43% 65.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4189647 9.55% 75.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1825739 4.16% 79.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 668569 1.52% 80.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1050805 2.39% 83.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7375888 16.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24387762 55.57% 55.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1515251 3.45% 59.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1377134 3.14% 62.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1500310 3.42% 65.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4190997 9.55% 75.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1825571 4.16% 79.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 669926 1.53% 80.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1050385 2.39% 83.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7371092 16.80% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43880130 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.369803 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.357777 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14899233 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9760394 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18283223 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 591754 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 345526 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3700749 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 99293 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103056970 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 314917 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 345526 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15243567 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4452634 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 97322 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18515033 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5226048 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102057831 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7235 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 94720 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 348136 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4717245 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 61355857 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123078605 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122759511 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 319093 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43888428 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.369270 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.355015 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14897050 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9776190 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18280655 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 589828 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 344705 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3701787 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 98635 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103032848 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 312916 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 344705 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15240775 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4552016 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 97125 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18511621 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5142186 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102032260 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5895 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 92509 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 354670 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4626637 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 61342957 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123044735 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 122725402 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 319332 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8808976 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5695 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5747 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2360993 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23135657 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16359365 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1252776 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 502701 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90727911 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5569 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88607473 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 70141 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11141723 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4452155 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 986 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43880130 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.019307 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.245631 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 8796076 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5684 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5736 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2358572 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23134576 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16358313 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1246652 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 504576 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90719727 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5556 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88603709 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 68043 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11133526 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4439018 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 973 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43888428 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.018840 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.245634 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17424086 39.71% 39.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 5721163 13.04% 52.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5107482 11.64% 64.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4378378 9.98% 74.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4320360 9.85% 84.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2636536 6.01% 90.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1944467 4.43% 94.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1375974 3.14% 97.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 971684 2.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17434377 39.72% 39.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 5720394 13.03% 52.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5103914 11.63% 64.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4383916 9.99% 74.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4317842 9.84% 84.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2637316 6.01% 90.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1940633 4.42% 94.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1378295 3.14% 97.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 971741 2.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43880130 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43888428 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 243434 9.65% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1167545 46.27% 55.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1112329 44.08% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 241284 9.57% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1166228 46.24% 55.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1114848 44.20% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49382948 55.73% 55.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43980 0.05% 55.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49379489 55.73% 55.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 44005 0.05% 55.78% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121151 0.14% 55.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121171 0.14% 55.92% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 92 0.00% 55.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 120663 0.14% 56.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 120707 0.14% 56.05% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 62 0.00% 56.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 39093 0.04% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 39092 0.04% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.10% # Type of FU issued @@ -485,82 +483,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.10% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22902831 25.85% 81.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15996653 18.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22899221 25.84% 81.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15999870 18.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88607473 # Type of FU issued -system.cpu.iq.rate 1.988943 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2523308 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028477 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 223077288 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101475255 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86832445 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 611237 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 420100 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 299852 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90825011 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 305770 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1671661 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88603709 # Type of FU issued +system.cpu.iq.rate 1.987206 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2522360 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028468 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 223074890 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101458980 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86835527 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 611359 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 420488 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 299878 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90820238 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 305831 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1672227 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2859019 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5476 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20375 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1745988 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2857938 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5878 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20874 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1744936 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3024 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 205293 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3021 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 200758 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 345526 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1271875 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2754338 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100226384 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 125320 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23135657 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16359365 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5569 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3722 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2752972 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20375 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 115768 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 151556 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 267324 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87911556 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22736014 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 695917 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 344705 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1315985 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2729229 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100214269 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 118431 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23134576 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16358313 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5556 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3898 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2727794 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20874 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 113179 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 152389 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 265568 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87909421 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22732927 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 694288 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9492904 # number of nop insts executed -system.cpu.iew.exec_refs 38587764 # number of memory reference insts executed -system.cpu.iew.exec_branches 15119893 # Number of branches executed -system.cpu.iew.exec_stores 15851750 # Number of stores executed -system.cpu.iew.exec_rate 1.973322 # Inst execution rate -system.cpu.iew.wb_sent 87534383 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87132297 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33840523 # num instructions producing a value -system.cpu.iew.wb_consumers 44256350 # num instructions consuming a value -system.cpu.iew.wb_rate 1.955830 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.764648 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 8655398 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 9488986 # number of nop insts executed +system.cpu.iew.exec_refs 38586655 # number of memory reference insts executed +system.cpu.iew.exec_branches 15119960 # Number of branches executed +system.cpu.iew.exec_stores 15853728 # Number of stores executed +system.cpu.iew.exec_rate 1.971634 # Inst execution rate +system.cpu.iew.wb_sent 87537444 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87135405 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33842966 # num instructions producing a value +system.cpu.iew.wb_consumers 44247648 # num instructions consuming a value +system.cpu.iew.wb_rate 1.954274 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.764853 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 8653815 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 226701 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42610108 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.073233 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.886041 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 225413 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42617548 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.072871 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.885939 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 21149437 49.63% 49.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 6275459 14.73% 64.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2900348 6.81% 71.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1740796 4.09% 75.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1682035 3.95% 79.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1127009 2.64% 81.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1202859 2.82% 84.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 795530 1.87% 86.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5736635 13.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21149374 49.63% 49.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 6281932 14.74% 64.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2908445 6.82% 71.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1738602 4.08% 75.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1681485 3.95% 79.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1121192 2.63% 81.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1200701 2.82% 84.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 796598 1.87% 86.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5739219 13.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42610108 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42617548 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -606,465 +604,471 @@ system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5736635 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 132552201 # The number of ROB reads -system.cpu.rob.rob_writes 195265380 # The number of ROB writes -system.cpu.timesIdled 45343 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 669895 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 5739219 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 132555474 # The number of ROB reads +system.cpu.rob.rob_writes 195263120 # The number of ROB writes +system.cpu.timesIdled 45271 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 698660 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.559732 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.559732 # CPI: Total CPI of All Threads -system.cpu.ipc 1.786570 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.786570 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116366061 # number of integer regfile reads -system.cpu.int_regfile_writes 57668563 # number of integer regfile writes -system.cpu.fp_regfile_reads 255567 # number of floating regfile reads -system.cpu.fp_regfile_writes 240367 # number of floating regfile writes -system.cpu.misc_regfile_reads 38271 # number of misc regfile reads +system.cpu.cpi 0.560197 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.560197 # CPI: Total CPI of All Threads +system.cpu.ipc 1.785085 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.785085 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116363135 # number of integer regfile reads +system.cpu.int_regfile_writes 57669565 # number of integer regfile writes +system.cpu.fp_regfile_reads 255561 # number of floating regfile reads +system.cpu.fp_regfile_writes 240404 # number of floating regfile writes +system.cpu.misc_regfile_reads 38263 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 201418 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.642288 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 33984828 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205514 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.365026 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 229821500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.642288 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993809 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993809 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 201400 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.443451 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 33984025 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205496 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.375603 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 232048500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.443451 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993761 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993761 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2776 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1244 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2679 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1341 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70818146 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70818146 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20423642 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20423642 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13561123 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13561123 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 63 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 63 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 33984765 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33984765 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33984765 # number of overall hits -system.cpu.dcache.overall_hits::total 33984765 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 269234 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 269234 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1052254 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1052254 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1321488 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1321488 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1321488 # number of overall misses -system.cpu.dcache.overall_misses::total 1321488 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 17321162000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 17321162000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 89091667377 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 89091667377 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 106412829377 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 106412829377 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 106412829377 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 106412829377 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20692876 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20692876 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70817108 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70817108 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 20422994 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20422994 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13560978 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13560978 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 53 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 53 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 33983972 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33983972 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33983972 # number of overall hits +system.cpu.dcache.overall_hits::total 33983972 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 269382 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 269382 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1052399 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1052399 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1321781 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1321781 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1321781 # number of overall misses +system.cpu.dcache.overall_misses::total 1321781 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18043068500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18043068500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 88421559159 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 88421559159 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106464627659 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106464627659 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106464627659 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106464627659 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20692376 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20692376 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 63 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 63 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35306253 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35306253 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35306253 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35306253 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.013011 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.013011 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.072006 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.072006 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037429 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037429 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037429 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037429 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64334.972552 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 64334.972552 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84667.454224 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 84667.454224 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80525.006188 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80525.006188 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80525.006188 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80525.006188 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6873080 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 275 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 89218 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 53 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 53 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35305753 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35305753 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35305753 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35305753 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.013018 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.013018 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.072016 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.072016 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037438 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037438 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037438 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037438 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66979.488236 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66979.488236 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84019.045209 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 84019.045209 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80546.344409 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80546.344409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80546.344409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80546.344409 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6874865 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 279 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 86609 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.036921 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 137.500000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 168806 # number of writebacks -system.cpu.dcache.writebacks::total 168806 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207108 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 207108 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 908866 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 908866 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1115974 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1115974 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1115974 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1115974 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62126 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62126 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143388 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143388 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205514 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205514 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205514 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205514 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3205966000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3205966000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14246299714 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14246299714 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17452265714 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17452265714 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17452265714 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17452265714 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003002 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003002 # mshr miss rate for ReadReq accesses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 79.378182 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 139.500000 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 168502 # number of writebacks +system.cpu.dcache.writebacks::total 168502 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207279 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 207279 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 909006 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 909006 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1116285 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1116285 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1116285 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1116285 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62103 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62103 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143393 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143393 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205496 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205496 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205496 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205496 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3336459000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3336459000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14128429272 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14128429272 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17464888272 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17464888272 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17464888272 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17464888272 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003001 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003001 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009812 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009812 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005821 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005821 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005821 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005821 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51604.255867 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51604.255867 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99354.895207 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99354.895207 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84920.081912 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84920.081912 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84920.081912 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84920.081912 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 90292 # number of replacements -system.cpu.icache.tags.tagsinuse 1916.963164 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13622372 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 92340 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 147.524063 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 18757985500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1916.963164 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.936017 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.936017 # Average percentage of cache occupancy +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005820 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005820 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005820 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005820 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53724.602676 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53724.602676 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98529.421046 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98529.421046 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84988.945147 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84988.945147 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84988.945147 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84988.945147 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 90436 # number of replacements +system.cpu.icache.tags.tagsinuse 1916.490065 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13619166 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 92484 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 147.259699 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 18779712500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1916.490065 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.935786 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.935786 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1468 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 384 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1460 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 389 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27546828 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27546828 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 13622372 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13622372 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13622372 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13622372 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13622372 # number of overall hits -system.cpu.icache.overall_hits::total 13622372 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 104872 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 104872 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 104872 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 104872 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 104872 # number of overall misses -system.cpu.icache.overall_misses::total 104872 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1921920999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1921920999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1921920999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1921920999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1921920999 # 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Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 168502 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 168502 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 90436 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 90436 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12584 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12584 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 86017 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 86017 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33990 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 33990 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 86017 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 46574 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 132591 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 86017 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 46574 # number of overall hits +system.cpu.l2cache.overall_hits::total 132591 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 130811 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 130811 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6468 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 6468 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 28111 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 28111 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 6468 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 158922 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 165390 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 6468 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 158922 # number of overall misses +system.cpu.l2cache.overall_misses::total 165390 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13777150000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 13777150000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 548837500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 548837500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2881866500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2881866500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 548837500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 16659016500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17207854000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 548837500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 16659016500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17207854000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 168502 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 168502 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 90436 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 90436 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143395 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143395 # 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miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.912242 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.069936 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.069936 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.452666 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.452666 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.069936 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.773358 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.555035 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.069936 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.773358 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.555035 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105321.035693 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105321.035693 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84854.282622 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84854.282622 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102517.395326 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 102517.395326 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84854.282622 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 104825.112319 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 104044.101820 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84854.282622 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 104825.112319 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 104044.101820 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 114419 # number of writebacks -system.cpu.l2cache.writebacks::total 114419 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 111 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 111 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130780 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130780 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6407 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6407 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27864 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27864 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 6407 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158644 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165051 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 6407 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158644 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 165051 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12586888000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12586888000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 460830500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 460830500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2469459000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2469459000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 460830500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15056347000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15517177500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 460830500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15056347000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15517177500 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 115201 # number of writebacks +system.cpu.l2cache.writebacks::total 115201 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 112 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 112 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130811 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130811 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6468 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6468 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 28111 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 28111 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 6468 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158922 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 165390 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 6468 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158922 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 165390 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12469040000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12469040000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 484167500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 484167500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2600756500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2600756500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 484167500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15069796500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15553964000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 484167500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15069796500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15553964000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912052 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912052 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.069384 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.069384 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.448530 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.448530 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069384 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771938 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.554132 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069384 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771938 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.554132 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96244.746903 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96244.746903 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71926.096457 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71926.096457 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88625.430663 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88625.430663 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71926.096457 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94906.501349 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94014.440991 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71926.096457 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94906.501349 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94014.440991 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 589565 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 291710 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912242 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912242 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.069936 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.069936 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452666 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452666 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069936 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773358 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.555035 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069936 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773358 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.555035 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95321.035693 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95321.035693 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74855.828695 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74855.828695 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92517.395326 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92517.395326 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74855.828695 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94825.112319 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94044.162283 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74855.828695 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94825.112319 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94044.162283 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 589817 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 291836 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4045 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4045 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4239 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4239 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 154463 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 283225 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 90292 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 51275 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143391 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143391 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 92341 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 62123 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 274973 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612446 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 887419 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11688448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23956480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 35644928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 133082 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7322816 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 430937 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009387 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.096428 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 154585 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 283703 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 90436 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 52571 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143395 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143395 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 92485 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 62101 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 275405 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612392 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 887797 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11706880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23935872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 35642752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 134874 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 7372864 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 432855 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009793 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.098475 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 426892 99.06% 99.06% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4045 0.94% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 428616 99.02% 99.02% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4239 0.98% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 430937 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 553880500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 432855 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 553846500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 138521976 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 138734483 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 308281978 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 308248491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 34270 # Transaction distribution -system.membus.trans_dist::WritebackDirty 114419 # Transaction distribution -system.membus.trans_dist::CleanEvict 14728 # Transaction distribution -system.membus.trans_dist::ReadExReq 130780 # Transaction distribution -system.membus.trans_dist::ReadExResp 130780 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34270 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 459247 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 459247 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17886016 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17886016 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 296135 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 130746 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 34578 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115200 # Transaction distribution +system.membus.trans_dist::CleanEvict 15546 # Transaction distribution +system.membus.trans_dist::ReadExReq 130811 # Transaction distribution +system.membus.trans_dist::ReadExResp 130811 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34578 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 461524 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 461524 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17957696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17957696 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 294197 # Request fanout histogram +system.membus.snoop_fanout::samples 165389 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 294197 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 165389 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 294197 # Request fanout histogram -system.membus.reqLayer0.occupancy 776999500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 165389 # Request fanout histogram +system.membus.reqLayer0.occupancy 780841500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 852713250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 854544750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index 50bae5738..7abf225fd 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058768 # Number of seconds simulated -sim_ticks 58768125500 # Number of ticks simulated -final_tick 58768125500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058750 # Number of seconds simulated +sim_ticks 58750410500 # Number of ticks simulated +final_tick 58750410500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 140139 # Simulator instruction rate (inst/s) -host_op_rate 179217 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 116134728 # Simulator tick rate (ticks/s) -host_mem_usage 275656 # Number of bytes of host memory used -host_seconds 506.03 # Real time elapsed on the host +host_inst_rate 179920 # Simulator instruction rate (inst/s) +host_op_rate 230092 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 149057017 # Simulator tick rate (ticks/s) +host_mem_usage 281832 # Number of bytes of host memory used +host_seconds 394.15 # Real time elapsed on the host sim_insts 70915150 # Number of instructions simulated sim_ops 90690106 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 285632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7924672 # Number of bytes read from this memory -system.physmem.bytes_read::total 8210304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 285632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 285632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5517568 # Number of bytes written to this memory -system.physmem.bytes_written::total 5517568 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4463 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123823 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128286 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 86212 # Number of write requests responded to by this memory -system.physmem.num_writes::total 86212 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 4860322 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 134846431 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 139706753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4860322 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4860322 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 93887085 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 93887085 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 93887085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4860322 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 134846431 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 233593838 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128286 # Number of read requests accepted -system.physmem.writeReqs 86212 # Number of write requests accepted -system.physmem.readBursts 128286 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 86212 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8209920 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 5515840 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8210304 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5517568 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 286336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7938624 # Number of bytes read from this memory +system.physmem.bytes_read::total 8224960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 286336 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 286336 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5539328 # Number of bytes written to this memory +system.physmem.bytes_written::total 5539328 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4474 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124041 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128515 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 86552 # Number of write requests responded to by this memory +system.physmem.num_writes::total 86552 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 4873770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 135124571 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 139998341 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4873770 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4873770 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 94285775 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 94285775 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 94285775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4873770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 135124571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 234284116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128515 # Number of read requests accepted +system.physmem.writeReqs 86552 # Number of write requests accepted +system.physmem.readBursts 128515 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 86552 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8224512 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue +system.physmem.bytesWritten 5537600 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8224960 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5539328 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8065 # Per bank write bursts -system.physmem.perBankRdBursts::1 8314 # Per bank write bursts -system.physmem.perBankRdBursts::2 8239 # Per bank write bursts -system.physmem.perBankRdBursts::3 8142 # Per bank write bursts -system.physmem.perBankRdBursts::4 8284 # Per bank write bursts -system.physmem.perBankRdBursts::5 8404 # Per bank write bursts -system.physmem.perBankRdBursts::6 8054 # Per bank write bursts -system.physmem.perBankRdBursts::7 7915 # Per bank write bursts -system.physmem.perBankRdBursts::8 8035 # Per bank write bursts -system.physmem.perBankRdBursts::9 7585 # Per bank write bursts -system.physmem.perBankRdBursts::10 7763 # Per bank write bursts -system.physmem.perBankRdBursts::11 7814 # Per bank write bursts -system.physmem.perBankRdBursts::12 7871 # Per bank write bursts -system.physmem.perBankRdBursts::13 7866 # Per bank write bursts -system.physmem.perBankRdBursts::14 7967 # Per bank write bursts -system.physmem.perBankRdBursts::15 7962 # Per bank write bursts -system.physmem.perBankWrBursts::0 5395 # Per bank write bursts -system.physmem.perBankWrBursts::1 5541 # Per bank write bursts -system.physmem.perBankWrBursts::2 5468 # Per bank write bursts -system.physmem.perBankWrBursts::3 5336 # Per bank write bursts -system.physmem.perBankWrBursts::4 5363 # Per bank write bursts -system.physmem.perBankWrBursts::5 5561 # Per bank write bursts -system.physmem.perBankWrBursts::6 5259 # Per bank write bursts -system.physmem.perBankWrBursts::7 5180 # Per bank write bursts -system.physmem.perBankWrBursts::8 5154 # Per bank write bursts -system.physmem.perBankWrBursts::9 5103 # Per bank write bursts -system.physmem.perBankWrBursts::10 5293 # Per bank write bursts -system.physmem.perBankWrBursts::11 5270 # Per bank write bursts -system.physmem.perBankWrBursts::12 5531 # Per bank write bursts +system.physmem.perBankRdBursts::0 8086 # Per bank write bursts +system.physmem.perBankRdBursts::1 8335 # Per bank write bursts +system.physmem.perBankRdBursts::2 8257 # Per bank write bursts +system.physmem.perBankRdBursts::3 8155 # Per bank write bursts +system.physmem.perBankRdBursts::4 8301 # Per bank write bursts +system.physmem.perBankRdBursts::5 8413 # Per bank write bursts +system.physmem.perBankRdBursts::6 8070 # Per bank write bursts +system.physmem.perBankRdBursts::7 7917 # Per bank write bursts +system.physmem.perBankRdBursts::8 8053 # Per bank write bursts +system.physmem.perBankRdBursts::9 7612 # Per bank write bursts +system.physmem.perBankRdBursts::10 7771 # Per bank write bursts +system.physmem.perBankRdBursts::11 7825 # Per bank write bursts +system.physmem.perBankRdBursts::12 7888 # Per bank write bursts +system.physmem.perBankRdBursts::13 7870 # Per bank write bursts +system.physmem.perBankRdBursts::14 7981 # Per bank write bursts +system.physmem.perBankRdBursts::15 7974 # Per bank write bursts +system.physmem.perBankWrBursts::0 5399 # Per bank write bursts +system.physmem.perBankWrBursts::1 5549 # Per bank write bursts +system.physmem.perBankWrBursts::2 5476 # Per bank write bursts +system.physmem.perBankWrBursts::3 5348 # Per bank write bursts +system.physmem.perBankWrBursts::4 5387 # Per bank write bursts +system.physmem.perBankWrBursts::5 5588 # Per bank write bursts +system.physmem.perBankWrBursts::6 5325 # Per bank write bursts +system.physmem.perBankWrBursts::7 5260 # Per bank write bursts +system.physmem.perBankWrBursts::8 5187 # Per bank write bursts +system.physmem.perBankWrBursts::9 5136 # Per bank write bursts +system.physmem.perBankWrBursts::10 5306 # Per bank write bursts +system.physmem.perBankWrBursts::11 5279 # Per bank write bursts +system.physmem.perBankWrBursts::12 5541 # Per bank write bursts system.physmem.perBankWrBursts::13 5597 # Per bank write bursts -system.physmem.perBankWrBursts::14 5703 # Per bank write bursts -system.physmem.perBankWrBursts::15 5431 # Per bank write bursts +system.physmem.perBankWrBursts::14 5706 # Per bank write bursts +system.physmem.perBankWrBursts::15 5441 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58768094000 # Total gap between requests +system.physmem.totGap 58750379000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128286 # Read request sizes (log2) +system.physmem.readPktSize::6 128515 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 86212 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 116156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12104 # What read queue length does an incoming req see +system.physmem.writePktSize::6 86552 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 116239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12249 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,27 +145,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -194,106 +194,104 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38803 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 353.665026 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 214.783131 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.990632 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12260 31.60% 31.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8290 21.36% 52.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4146 10.68% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2807 7.23% 70.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2540 6.55% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1701 4.38% 81.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1262 3.25% 85.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1176 3.03% 88.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4621 11.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38803 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5298 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.212911 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 352.385643 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5295 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 32968 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 417.384130 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 256.722785 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 362.908382 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8749 26.54% 26.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6430 19.50% 46.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3309 10.04% 56.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2430 7.37% 63.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2267 6.88% 70.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1599 4.85% 75.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1281 3.89% 79.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1267 3.84% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5636 17.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 32968 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5346 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.036289 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 17.665302 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 347.416280 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5344 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5298 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5297 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.269398 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.253066 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.759205 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4663 88.03% 88.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 7 0.13% 88.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 496 9.36% 97.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 106 2.00% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 16 0.30% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 8 0.15% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5297 # Writes before turning the bus around for reads -system.physmem.totQLat 1679255750 # Total ticks spent queuing -system.physmem.totMemAccLat 4084505750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 641400000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13090.55 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5346 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5346 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.184998 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.174634 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.600598 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4870 91.10% 91.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 4 0.07% 91.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 438 8.19% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 27 0.51% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 7 0.13% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5346 # Writes before turning the bus around for reads +system.physmem.totQLat 1552277750 # Total ticks spent queuing +system.physmem.totMemAccLat 3961802750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 642540000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12079.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31840.55 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 139.70 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 93.86 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 139.71 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 93.89 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30829.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 139.99 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 94.26 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 140.00 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 94.29 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.82 # Data bus utilization in percentage +system.physmem.busUtil 1.83 # Data bus utilization in percentage system.physmem.busUtilRead 1.09 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.33 # Average write queue length when enqueuing -system.physmem.readRowHits 111800 # Number of row buffer hits during reads -system.physmem.writeRowHits 63851 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.15 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.06 # Row buffer hit rate for writes -system.physmem.avgGap 273979.68 # Average gap between requests -system.physmem.pageHitRate 81.89 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 153014400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 83490000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 509886000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 279190800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3838102320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11659704255 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 25030042500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41553430275 # Total energy per rank (pJ) -system.physmem_0.averagePower 707.134890 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 41510709500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1962220000 # Time in different power states +system.physmem.avgWrQLen 23.56 # Average write queue length when enqueuing +system.physmem.readRowHits 112029 # Number of row buffer hits during reads +system.physmem.writeRowHits 70027 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.91 # Row buffer hit rate for writes +system.physmem.avgGap 273172.45 # Average gap between requests +system.physmem.pageHitRate 84.65 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 130599000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 71259375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 511009200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 280655280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3837085200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11237331690 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 25391203500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41459143245 # Total energy per rank (pJ) +system.physmem_0.averagePower 705.717335 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 42124223000 # Time in different power states +system.physmem_0.memoryStateTime::REF 1961700000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15290173000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14661610750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 140215320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76506375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 490152000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 279145440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3838102320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11133864720 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 25491305250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41449291425 # Total energy per rank (pJ) -system.physmem_1.averagePower 705.362708 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 42280803500 # Time in different power states -system.physmem_1.memoryStateTime::REF 1962220000 # Time in different power states +system.physmem_1.actEnergy 118555920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 64688250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 491072400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 279819360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3837085200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10919729115 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 25669800000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41380750245 # Total energy per rank (pJ) +system.physmem_1.averagePower 704.382975 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 42589738750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1961700000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14520166000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14196261750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 14827521 # Number of BP lookups -system.cpu.branchPred.condPredicted 9922528 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 342114 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9663077 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6571727 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 14827613 # Number of BP lookups +system.cpu.branchPred.condPredicted 9922572 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 342024 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9662819 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6571830 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 68.008637 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1719937 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 68.011519 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1720035 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 176106 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 158425 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 17681 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 24889 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 175655 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 158613 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 17042 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 24764 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -323,7 +321,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -353,7 +351,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -383,7 +381,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -414,16 +412,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 117536251 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 117500821 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915150 # Number of instructions committed system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1179302 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1179078 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.657421 # CPI: cycles per instruction -system.cpu.ipc 0.603347 # IPC: instructions per cycle +system.cpu.cpi 1.656921 # CPI: cycles per instruction +system.cpu.ipc 0.603529 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction @@ -459,474 +457,480 @@ system.cpu.op_class_0::MemWrite 20555739 22.67% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 90690106 # Class of committed instruction -system.cpu.tickCycles 97988256 # Number of cycles that the object actually ticked -system.cpu.idleCycles 19547995 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 156444 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.129500 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42637241 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160540 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.586402 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 821026500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.129500 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993196 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993196 # Average percentage of cache occupancy +system.cpu.tickCycles 97998947 # Number of cycles that the object actually ticked +system.cpu.idleCycles 19501874 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 156451 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.791520 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42637484 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160547 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.576336 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 830343500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.791520 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993113 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993113 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1100 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2952 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1054 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2998 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86035236 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86035236 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 22879875 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22879875 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19642158 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19642158 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83370 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83370 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 86035297 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86035297 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 22880319 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22880319 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19642152 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642152 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83175 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83175 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42522033 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42522033 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42605403 # number of overall hits -system.cpu.dcache.overall_hits::total 42605403 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 47768 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 47768 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 207743 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207743 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 44596 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 44596 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 255511 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 255511 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 300107 # number of overall misses -system.cpu.dcache.overall_misses::total 300107 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1443300500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1443300500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16810663000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16810663000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18253963500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18253963500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18253963500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18253963500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22927643 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22927643 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42522471 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42522471 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42605646 # number of overall hits +system.cpu.dcache.overall_hits::total 42605646 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 47369 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 47369 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207749 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207749 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 44773 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 44773 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 255118 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 255118 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 299891 # number of overall misses +system.cpu.dcache.overall_misses::total 299891 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1548941500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1548941500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16628210000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16628210000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18177151500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18177151500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18177151500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18177151500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22927688 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22927688 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 127966 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 127966 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 127948 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 127948 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42777544 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42777544 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42905510 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42905510 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002083 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002083 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 42777589 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42777589 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42905537 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42905537 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002066 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002066 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010466 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.010466 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348499 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.348499 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.005973 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005973 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006995 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006995 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30214.798610 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30214.798610 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80920.478668 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80920.478668 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71441.008411 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71441.008411 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60824.850803 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60824.850803 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.349931 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.349931 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005964 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005964 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006990 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006990 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32699.476451 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32699.476451 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80039.903923 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80039.903923 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71249.976481 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71249.976481 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60612.527552 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60612.527552 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 128383 # number of writebacks -system.cpu.dcache.writebacks::total 128383 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 18246 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 18246 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100706 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 100706 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 118952 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 118952 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 118952 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 118952 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29522 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29522 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 128145 # number of writebacks +system.cpu.dcache.writebacks::total 128145 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 17840 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 17840 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100712 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100712 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 118552 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 118552 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 118552 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 118552 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29529 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29529 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107037 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 107037 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23981 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 23981 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136559 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136559 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 160540 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160540 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 576668000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 576668000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8488003000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8488003000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1709526500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1709526500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9064671000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9064671000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10774197500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10774197500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 136566 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136566 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 160547 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160547 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 586674000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 586674000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8401236500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8401236500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788829000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788829000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8987910500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8987910500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10776739500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10776739500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187401 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187401 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187428 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187428 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19533.500440 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19533.500440 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79299.709446 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79299.709446 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71286.706142 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71286.706142 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66379.154798 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66379.154798 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67112.230597 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67112.230597 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 43538 # number of replacements -system.cpu.icache.tags.tagsinuse 1854.967198 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25047260 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 45580 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 549.523036 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19867.723255 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19867.723255 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78489.087885 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78489.087885 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74593.594929 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74593.594929 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65813.676171 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65813.676171 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67125.137810 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67125.137810 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # 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Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 45 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 907 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1012 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 913 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1006 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50231262 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50231262 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 25047260 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25047260 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25047260 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25047260 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25047260 # number of overall hits -system.cpu.icache.overall_hits::total 25047260 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 45581 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 45581 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 45581 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 45581 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 45581 # 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number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25092841 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25092841 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001816 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001816 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001816 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001816 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001816 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001816 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19884.831399 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19884.831399 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19884.831399 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19884.831399 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19884.831399 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19884.831399 # average overall miss latency +system.cpu.icache.tags.tag_accesses 50231999 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50231999 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 25047618 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25047618 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25047618 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25047618 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25047618 # number of overall hits +system.cpu.icache.overall_hits::total 25047618 # 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number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25093206 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25093206 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25093206 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25093206 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25093206 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25093206 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001817 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001817 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001817 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001817 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001817 # 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average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 43538 # number of writebacks -system.cpu.icache.writebacks::total 43538 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45581 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 45581 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 45581 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 45581 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 45581 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 45581 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 860790500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 860790500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 860790500 # 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average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18884.853338 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18884.853338 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18884.853338 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18884.853338 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18884.853338 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 96393 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29915.680999 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 163475 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 127546 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.281694 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26835.960013 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1436.225853 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1643.495133 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.818969 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043830 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.050155 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.912954 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31153 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1859 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12744 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15761 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 596 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.950714 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3420655 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3420655 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 128383 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 128383 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 39935 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 39935 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4757 # 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mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001817 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19146.398175 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19146.398175 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19146.398175 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19146.398175 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19146.398175 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19146.398175 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 97176 # 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average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76442.904888 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69747.647849 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71888.595011 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71814.096518 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69747.647849 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71888.595011 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71814.096518 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 406103 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 200020 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955903 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955903 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098162 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.405980 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405980 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.623456 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.623456 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70055.831387 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70055.831387 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72211.396648 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72211.396648 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79916.014546 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79916.014546 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72211.396648 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71782.700881 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71797.628311 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72211.396648 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71782.700881 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71797.628311 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 406131 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 200034 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7844 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3360 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3331 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 99083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 214595 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 43538 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 38242 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_snoops 3482 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3452 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 99097 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 214697 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 43545 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 38930 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107037 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107037 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 45581 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 53503 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134699 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477524 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 612223 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5703552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18491072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 24194624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 96393 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5517568 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 302514 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.037258 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.189899 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 45588 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 53510 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134720 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477545 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 612265 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5704448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18476288 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 24180736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 97176 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5539328 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 303311 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.037565 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.190662 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 291272 96.28% 96.28% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 11213 3.71% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 29 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 291947 96.25% 96.25% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11334 3.74% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 302514 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 374972500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 303311 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 374755500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 68384970 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 68396468 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 240842435 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 240852935 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 26006 # Transaction distribution -system.membus.trans_dist::WritebackDirty 86212 # Transaction distribution -system.membus.trans_dist::CleanEvict 6916 # Transaction distribution -system.membus.trans_dist::ReadExReq 102280 # Transaction distribution -system.membus.trans_dist::ReadExResp 102280 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 26006 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 349700 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 349700 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13727872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13727872 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 222304 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 93865 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 26198 # Transaction distribution +system.membus.trans_dist::WritebackDirty 86552 # Transaction distribution +system.membus.trans_dist::CleanEvict 7237 # Transaction distribution +system.membus.trans_dist::ReadExReq 102317 # Transaction distribution +system.membus.trans_dist::ReadExResp 102317 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 26198 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 350819 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 350819 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13764288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13764288 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 221414 # Request fanout histogram +system.membus.snoop_fanout::samples 128515 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 221414 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 128515 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 221414 # Request fanout histogram -system.membus.reqLayer0.occupancy 586752500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 128515 # Request fanout histogram +system.membus.reqLayer0.occupancy 587526000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 676437000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 677474000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 854b1472f..7d5e42cd5 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033525 # Number of seconds simulated -sim_ticks 33524756000 # Number of ticks simulated -final_tick 33524756000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.037283 # Number of seconds simulated +sim_ticks 37283333000 # Number of ticks simulated +final_tick 37283333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128434 # Simulator instruction rate (inst/s) -host_op_rate 164252 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60722809 # Simulator tick rate (ticks/s) -host_mem_usage 277836 # Number of bytes of host memory used -host_seconds 552.10 # Real time elapsed on the host +host_inst_rate 125888 # Simulator instruction rate (inst/s) +host_op_rate 160996 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66191855 # Simulator tick rate (ticks/s) +host_mem_usage 284264 # Number of bytes of host memory used +host_seconds 563.26 # Real time elapsed on the host sim_insts 70907652 # Number of instructions simulated sim_ops 90682607 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 697984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2927552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6172096 # Number of bytes read from this memory -system.physmem.bytes_read::total 9797632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 697984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 697984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6216960 # Number of bytes written to this memory -system.physmem.bytes_written::total 6216960 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10906 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 45743 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96439 # Number of read requests responded to by this memory -system.physmem.num_reads::total 153088 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97140 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97140 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 20819958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 87325080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 184105620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 292250658 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 20819958 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 20819958 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 185443855 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 185443855 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 185443855 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 20819958 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 87325080 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 184105620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 477694513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 153089 # Number of read requests accepted -system.physmem.writeReqs 97140 # Number of write requests accepted -system.physmem.readBursts 153089 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97140 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9788224 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue -system.physmem.bytesWritten 6215872 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9797696 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6216960 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 2379328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5690752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6174592 # Number of bytes read from this memory +system.physmem.bytes_read::total 14244672 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2379328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2379328 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6224768 # Number of bytes written to this memory +system.physmem.bytes_written::total 6224768 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 37177 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 88918 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96478 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222573 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97262 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97262 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 63817470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 152635281 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 165612661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 382065412 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 63817470 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 63817470 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 166958464 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 166958464 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 166958464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 63817470 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 152635281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 165612661 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 549023876 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222574 # Number of read requests accepted +system.physmem.writeReqs 97262 # Number of write requests accepted +system.physmem.readBursts 222574 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97262 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 14235136 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue +system.physmem.bytesWritten 6223360 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 14244736 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6224768 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9103 # Per bank write bursts -system.physmem.perBankRdBursts::1 9407 # Per bank write bursts -system.physmem.perBankRdBursts::2 9452 # Per bank write bursts -system.physmem.perBankRdBursts::3 11458 # Per bank write bursts -system.physmem.perBankRdBursts::4 10748 # Per bank write bursts -system.physmem.perBankRdBursts::5 11390 # Per bank write bursts -system.physmem.perBankRdBursts::6 10031 # Per bank write bursts -system.physmem.perBankRdBursts::7 8920 # Per bank write bursts -system.physmem.perBankRdBursts::8 9321 # Per bank write bursts -system.physmem.perBankRdBursts::9 9437 # Per bank write bursts -system.physmem.perBankRdBursts::10 9070 # Per bank write bursts -system.physmem.perBankRdBursts::11 9080 # Per bank write bursts -system.physmem.perBankRdBursts::12 8731 # Per bank write bursts -system.physmem.perBankRdBursts::13 8724 # Per bank write bursts -system.physmem.perBankRdBursts::14 9025 # Per bank write bursts -system.physmem.perBankRdBursts::15 9044 # Per bank write bursts -system.physmem.perBankWrBursts::0 5968 # Per bank write bursts -system.physmem.perBankWrBursts::1 6230 # Per bank write bursts -system.physmem.perBankWrBursts::2 6083 # Per bank write bursts -system.physmem.perBankWrBursts::3 6155 # Per bank write bursts -system.physmem.perBankWrBursts::4 6058 # Per bank write bursts -system.physmem.perBankWrBursts::5 6286 # Per bank write bursts -system.physmem.perBankWrBursts::6 6021 # Per bank write bursts -system.physmem.perBankWrBursts::7 5958 # Per bank write bursts -system.physmem.perBankWrBursts::8 5969 # Per bank write bursts -system.physmem.perBankWrBursts::9 6064 # Per bank write bursts -system.physmem.perBankWrBursts::10 6185 # Per bank write bursts -system.physmem.perBankWrBursts::11 5907 # Per bank write bursts -system.physmem.perBankWrBursts::12 6058 # Per bank write bursts -system.physmem.perBankWrBursts::13 6089 # Per bank write bursts -system.physmem.perBankWrBursts::14 6121 # Per bank write bursts -system.physmem.perBankWrBursts::15 5971 # Per bank write bursts +system.physmem.perBankRdBursts::0 9684 # Per bank write bursts +system.physmem.perBankRdBursts::1 9951 # Per bank write bursts +system.physmem.perBankRdBursts::2 12571 # Per bank write bursts +system.physmem.perBankRdBursts::3 25345 # Per bank write bursts +system.physmem.perBankRdBursts::4 17391 # Per bank write bursts +system.physmem.perBankRdBursts::5 22070 # Per bank write bursts +system.physmem.perBankRdBursts::6 11722 # Per bank write bursts +system.physmem.perBankRdBursts::7 14054 # Per bank write bursts +system.physmem.perBankRdBursts::8 11726 # Per bank write bursts +system.physmem.perBankRdBursts::9 15447 # Per bank write bursts +system.physmem.perBankRdBursts::10 11755 # Per bank write bursts +system.physmem.perBankRdBursts::11 11322 # Per bank write bursts +system.physmem.perBankRdBursts::12 9441 # Per bank write bursts +system.physmem.perBankRdBursts::13 9563 # Per bank write bursts +system.physmem.perBankRdBursts::14 9879 # Per bank write bursts +system.physmem.perBankRdBursts::15 20503 # Per bank write bursts +system.physmem.perBankWrBursts::0 5981 # Per bank write bursts +system.physmem.perBankWrBursts::1 6205 # Per bank write bursts +system.physmem.perBankWrBursts::2 6090 # Per bank write bursts +system.physmem.perBankWrBursts::3 6159 # Per bank write bursts +system.physmem.perBankWrBursts::4 6110 # Per bank write bursts +system.physmem.perBankWrBursts::5 6252 # Per bank write bursts +system.physmem.perBankWrBursts::6 5998 # Per bank write bursts +system.physmem.perBankWrBursts::7 5984 # Per bank write bursts +system.physmem.perBankWrBursts::8 5961 # Per bank write bursts +system.physmem.perBankWrBursts::9 6093 # Per bank write bursts +system.physmem.perBankWrBursts::10 6222 # Per bank write bursts +system.physmem.perBankWrBursts::11 5895 # Per bank write bursts +system.physmem.perBankWrBursts::12 6037 # Per bank write bursts +system.physmem.perBankWrBursts::13 6052 # Per bank write bursts +system.physmem.perBankWrBursts::14 6175 # Per bank write bursts +system.physmem.perBankWrBursts::15 6026 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 33524744500 # Total gap between requests +system.physmem.totGap 37283321500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 153089 # Read request sizes (log2) +system.physmem.readPktSize::6 222574 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97140 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 50282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13705 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4726 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3666 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 71 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97262 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 113358 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61350 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14014 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5990 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5097 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 77 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see @@ -149,36 +149,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6528 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -198,107 +198,109 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 96335 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 166.118316 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 104.810468 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 234.858667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 60546 62.85% 62.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22368 23.22% 86.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3987 4.14% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1542 1.60% 91.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 931 0.97% 92.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 863 0.90% 93.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 636 0.66% 94.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 773 0.80% 95.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4689 4.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 96335 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5845 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.165269 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 198.412430 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5844 99.98% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5845 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5845 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.616424 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.570046 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.313075 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4545 77.76% 77.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 48 0.82% 78.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 753 12.88% 91.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 215 3.68% 95.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 127 2.17% 97.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 88 1.51% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 42 0.72% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 17 0.29% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 5 0.09% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 5 0.09% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5845 # Writes before turning the bus around for reads -system.physmem.totQLat 6714977565 # Total ticks spent queuing -system.physmem.totMemAccLat 9582621315 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 764705000 # Total ticks spent in databus transfers -system.physmem.avgQLat 43905.67 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 132565 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 154.319345 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.621145 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 210.186270 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 82651 62.35% 62.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 32256 24.33% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6354 4.79% 91.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2721 2.05% 93.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1163 0.88% 94.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1002 0.76% 95.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 846 0.64% 95.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 812 0.61% 96.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4760 3.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 132565 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5874 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 37.864488 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 211.288279 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5866 99.86% 99.86% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 7 0.12% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-15871 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5874 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5874 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.554307 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.512747 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.243213 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4672 79.54% 79.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 38 0.65% 80.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 729 12.41% 92.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 209 3.56% 96.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 107 1.82% 97.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 58 0.99% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 31 0.53% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 16 0.27% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 11 0.19% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5874 # Writes before turning the bus around for reads +system.physmem.totQLat 7261518854 # Total ticks spent queuing +system.physmem.totMemAccLat 11431968854 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1112120000 # Total ticks spent in databus transfers +system.physmem.avgQLat 32647.19 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 62655.67 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 291.97 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 185.41 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 292.25 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 185.44 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 51397.19 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 166.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 382.07 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 166.96 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.73 # Data bus utilization in percentage -system.physmem.busUtilRead 2.28 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.45 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.43 # Average read queue length when enqueuing +system.physmem.busUtil 4.29 # Data bus utilization in percentage +system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.30 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.45 # Average write queue length when enqueuing -system.physmem.readRowHits 120882 # Number of row buffer hits during reads -system.physmem.writeRowHits 32837 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 33.80 # Row buffer hit rate for writes -system.physmem.avgGap 133976.26 # Average gap between requests -system.physmem.pageHitRate 61.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 378438480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 206489250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 627572400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 315854640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2189350800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 15155251200 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 6817959750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25690916520 # Total energy per rank (pJ) -system.physmem_0.averagePower 766.433942 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11238384768 # Time in different power states -system.physmem_0.memoryStateTime::REF 1119300000 # Time in different power states +system.physmem.readRowHits 157163 # Number of row buffer hits during reads +system.physmem.writeRowHits 29925 # Number of row buffer hits during writes +system.physmem.readRowHitRate 70.66 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 30.77 # Row buffer hit rate for writes +system.physmem.avgGap 116570.12 # Average gap between requests +system.physmem.pageHitRate 58.52 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 537077520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 293048250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 957496800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 315958320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2434985280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 23206024395 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2012333250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 29756923815 # Total energy per rank (pJ) +system.physmem_0.averagePower 798.183082 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3201879547 # Time in different power states +system.physmem_0.memoryStateTime::REF 1244880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 21162395232 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32834079203 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 349513920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 190707000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 564751200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 313295040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2189350800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13737724470 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 8061404250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 25406746680 # Total energy per rank (pJ) -system.physmem_1.averagePower 757.956338 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 13314860915 # Time in different power states -system.physmem_1.memoryStateTime::REF 1119300000 # Time in different power states +system.physmem_1.actEnergy 464871960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 253650375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 777051600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 313949520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2434985280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 21592790730 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3427453500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 29264752965 # Total energy per rank (pJ) +system.physmem_1.averagePower 784.981262 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 5568954615 # Time in different power states +system.physmem_1.memoryStateTime::REF 1244880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 19085999585 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30467009135 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 17055826 # Number of BP lookups -system.cpu.branchPred.condPredicted 11447804 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 598855 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9258903 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7371283 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 17068882 # Number of BP lookups +system.cpu.branchPred.condPredicted 11456187 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 597693 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9279962 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7373647 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 79.612920 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1853216 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101575 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 232758 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 195217 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 37541 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 22230 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 79.457728 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1854916 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101589 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 233217 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 195584 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 37633 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 22185 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -328,7 +330,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -358,7 +360,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -388,7 +390,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -419,130 +421,130 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 67049513 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 74566667 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5112037 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87027076 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17055826 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9419716 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 60300614 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1224115 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 37 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 12656 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22418203 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 68072 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 66043378 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.665685 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.303820 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5541341 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87099155 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17068882 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9424147 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 65038748 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1222021 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 11659 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 48 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 30739 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22432357 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 69340 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 71233545 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.545306 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.327706 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20904696 31.65% 31.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8151419 12.34% 44.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9105743 13.79% 57.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27881520 42.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 26059108 36.58% 36.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8166381 11.46% 48.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9112889 12.79% 60.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27895167 39.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 66043378 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.254377 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.297952 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8568047 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 20331818 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31035970 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5662045 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 445498 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3138719 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 168392 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 100377883 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2807284 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 445498 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13201972 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6021135 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 843957 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 31848304 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13682512 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 98401933 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 864722 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3910657 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 69359 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4461482 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5194138 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103316551 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 453880702 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 114363596 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 706 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 71233545 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.228908 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.168071 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8928507 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 25221623 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 30949867 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5689167 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 444381 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3134053 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 168503 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 100299686 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2798262 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 444381 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13572247 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10675080 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 842433 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 31772787 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13926617 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 98328841 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 859440 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 4124148 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 69439 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4596367 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5265270 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103255092 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 453545884 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 114277398 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 716 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629369 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9687182 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18952 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18977 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12759909 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24172969 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21779154 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1438398 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2287665 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97467378 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34812 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94518121 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 609879 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6819583 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 18148637 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1026 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 66043378 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.431152 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.152558 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9625723 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18974 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 19002 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12839389 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24155878 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21759886 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1433320 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2321800 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97398916 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34841 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94478155 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 593843 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6751150 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 17960313 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1055 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 71233545 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.326316 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.168839 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17971444 27.21% 27.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17366377 26.30% 53.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17018277 25.77% 79.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11635318 17.62% 96.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2050574 3.10% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1388 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23112455 32.45% 32.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17441476 24.48% 56.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17040128 23.92% 80.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11602976 16.29% 97.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2035055 2.86% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1455 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 66043378 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 71233545 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6745698 22.64% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 37 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11091756 37.22% 59.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 11960162 40.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6731709 22.63% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 38 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11081856 37.26% 59.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 11930481 40.11% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49324075 52.18% 52.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 86626 0.09% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49303920 52.19% 52.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 86563 0.09% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.28% # Type of FU issued @@ -563,89 +565,89 @@ system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.28% # Ty system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 12 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 12 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 19 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23968009 25.36% 77.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21139361 22.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23954982 25.36% 77.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21132627 22.37% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94518121 # Type of FU issued -system.cpu.iq.rate 1.409676 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29797653 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.315259 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 285486823 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 104332871 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93229184 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 329 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 574 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 84 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124315586 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 188 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1381077 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 94478155 # Type of FU issued +system.cpu.iq.rate 1.267029 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29744084 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.314825 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 290527434 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 104196109 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93201296 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 348 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 616 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 96 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 124222040 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 199 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1368179 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1306707 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2085 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11900 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1223416 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1289616 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2048 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11973 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1204148 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 147221 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 186554 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 144864 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 185613 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 445498 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 578203 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 566637 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97517928 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 444381 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 624509 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1115710 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97447803 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24172969 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21779154 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18892 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1555 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 562180 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11900 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 250835 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 223196 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 474031 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93719339 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23701905 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 798782 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24155878 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21759886 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18921 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1617 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1111435 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11973 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 249911 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 221890 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 471801 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93685311 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23691817 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 792844 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 15738 # number of nop insts executed -system.cpu.iew.exec_refs 44631646 # number of memory reference insts executed -system.cpu.iew.exec_branches 14212084 # Number of branches executed -system.cpu.iew.exec_stores 20929741 # Number of stores executed -system.cpu.iew.exec_rate 1.397763 # Inst execution rate -system.cpu.iew.wb_sent 93338125 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93229268 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44994314 # num instructions producing a value -system.cpu.iew.wb_consumers 76693481 # num instructions consuming a value -system.cpu.iew.wb_rate 1.390454 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.586677 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 5957514 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 14046 # number of nop insts executed +system.cpu.iew.exec_refs 44616394 # number of memory reference insts executed +system.cpu.iew.exec_branches 14207133 # Number of branches executed +system.cpu.iew.exec_stores 20924577 # Number of stores executed +system.cpu.iew.exec_rate 1.256397 # Inst execution rate +system.cpu.iew.wb_sent 93308677 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93201392 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44951021 # num instructions producing a value +system.cpu.iew.wb_consumers 76633881 # num instructions consuming a value +system.cpu.iew.wb_rate 1.249907 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.586569 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 5894305 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 432296 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 65078464 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.393520 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.163869 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 431064 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 70277782 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.290424 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.118209 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 31565690 48.50% 48.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16713735 25.68% 74.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4316875 6.63% 80.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4188712 6.44% 87.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1942227 2.98% 90.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1235606 1.90% 92.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 754913 1.16% 93.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 587526 0.90% 94.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3773180 5.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 36842990 52.42% 52.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16674938 23.73% 76.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4291723 6.11% 82.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4149088 5.90% 88.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1947878 2.77% 90.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1240751 1.77% 92.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 737656 1.05% 93.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 580756 0.83% 94.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3812002 5.42% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 65078464 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 70277782 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913204 # Number of instructions committed system.cpu.commit.committedOps 90688159 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -691,546 +693,552 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688159 # Class of committed instruction -system.cpu.commit.bw_lim_events 3773180 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 157925658 # The number of ROB reads -system.cpu.rob.rob_writes 194257744 # The number of ROB writes -system.cpu.timesIdled 27177 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1006135 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3812002 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 163022945 # The number of ROB reads +system.cpu.rob.rob_writes 194122181 # The number of ROB writes +system.cpu.timesIdled 54257 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3333122 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907652 # Number of Instructions Simulated system.cpu.committedOps 90682607 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.945589 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.945589 # CPI: Total CPI of All Threads -system.cpu.ipc 1.057542 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.057542 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 102008139 # number of integer regfile reads -system.cpu.int_regfile_writes 56630693 # number of integer regfile writes -system.cpu.fp_regfile_reads 48 # number of floating regfile reads -system.cpu.fp_regfile_writes 42 # number of floating regfile writes -system.cpu.cc_regfile_reads 345209533 # number of cc regfile reads -system.cpu.cc_regfile_writes 38766867 # number of cc regfile writes -system.cpu.misc_regfile_reads 44112663 # number of misc regfile reads +system.cpu.cpi 1.051603 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.051603 # CPI: Total CPI of All Threads +system.cpu.ipc 0.950930 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.950930 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 101976703 # number of integer regfile reads +system.cpu.int_regfile_writes 56611271 # number of integer regfile writes +system.cpu.fp_regfile_reads 60 # number of floating regfile reads +system.cpu.fp_regfile_writes 48 # number of floating regfile writes +system.cpu.cc_regfile_reads 345090037 # number of cc regfile reads +system.cpu.cc_regfile_writes 38758670 # number of cc regfile writes +system.cpu.misc_regfile_reads 44101489 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 486293 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.756058 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40330532 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 486805 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 82.847407 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 150823500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.756058 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997570 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997570 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 484862 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.874566 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40338135 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485374 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.107325 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 151605500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.874566 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997802 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997802 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84456645 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84456645 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21406566 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21406566 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18832689 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18832689 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 59994 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 59994 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15306 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15306 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84467396 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84467396 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 21414103 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21414103 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18832546 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18832546 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60212 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60212 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15310 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15310 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40239255 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40239255 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40299249 # number of overall hits -system.cpu.dcache.overall_hits::total 40299249 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 567937 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 567937 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1017212 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1017212 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68679 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68679 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 618 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 618 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1585149 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1585149 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1653828 # number of overall misses -system.cpu.dcache.overall_misses::total 1653828 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9485185000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9485185000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14264451930 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14264451930 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5633500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5633500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23749636930 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23749636930 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23749636930 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23749636930 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21974503 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21974503 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40246649 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40246649 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40306861 # number of overall hits +system.cpu.dcache.overall_hits::total 40306861 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 566310 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 566310 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1017355 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1017355 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68643 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68643 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 613 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 613 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1583665 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1583665 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1652308 # number of overall misses +system.cpu.dcache.overall_misses::total 1652308 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13581553500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13581553500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13903205430 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13903205430 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5738500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5738500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27484758930 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27484758930 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27484758930 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27484758930 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21980413 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21980413 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128673 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128673 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15924 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15924 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128855 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128855 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15923 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15923 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41824404 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41824404 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41953077 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41953077 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025845 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025845 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051245 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051245 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.533748 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.533748 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038809 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038809 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037900 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037900 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039421 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039421 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16701.121779 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16701.121779 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14023.086564 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14023.086564 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9115.695793 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9115.695793 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14982.589605 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14982.589605 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14360.403216 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14360.403216 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2907482 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 131418 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.123925 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 486293 # number of writebacks -system.cpu.dcache.writebacks::total 486293 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 267392 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 267392 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 868636 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 868636 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 618 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 618 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1136028 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1136028 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1136028 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1136028 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 300545 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 300545 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148576 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148576 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37700 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37700 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 449121 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 449121 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 486821 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 486821 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3693304500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3693304500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2308719470 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2308719470 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1888982500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1888982500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6002023970 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6002023970 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7891006470 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7891006470 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013677 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013677 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007485 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007485 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292991 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292991 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010738 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.010738 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011604 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.011604 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12288.690546 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12288.690546 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15538.979849 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15538.979849 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50105.636605 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50105.636605 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13363.935265 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13363.935265 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16209.256523 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16209.256523 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 325000 # number of replacements -system.cpu.icache.tags.tagsinuse 510.229072 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22083387 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 325512 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.842006 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 1115028500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.229072 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996541 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996541 # Average percentage of cache occupancy +system.cpu.dcache.demand_accesses::cpu.data 41830314 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41830314 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41959169 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41959169 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025764 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025764 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051252 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051252 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532715 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.532715 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038498 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038498 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037859 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037859 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039379 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039379 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23982.542247 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23982.542247 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13666.031454 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 13666.031454 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9361.337684 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9361.337684 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17355.159664 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17355.159664 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16634.161990 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16634.161990 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2820837 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 130956 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 21.540342 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 484862 # number of writebacks +system.cpu.dcache.writebacks::total 484862 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 267183 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 267183 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 868792 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 868792 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 613 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 613 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1135975 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1135975 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1135975 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1135975 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299127 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299127 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148563 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148563 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37696 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 37696 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 447690 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 447690 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 485386 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 485386 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6671017500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6671017500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2276896471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2276896471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1910092000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1910092000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8947913971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8947913971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10858005971 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10858005971 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013609 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013609 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007484 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007484 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292546 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292546 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010703 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.010703 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011568 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.011568 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22301.622722 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22301.622722 # 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Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 8 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45161716 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45161716 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 22083387 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22083387 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22083387 # 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number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16495 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 45190725 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45190725 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 22094458 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22094458 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22094458 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22094458 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22094458 # number of overall hits +system.cpu.icache.overall_hits::total 22094458 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 337685 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 337685 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 337685 # 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number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22432143 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22432143 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22432143 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015054 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015054 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015054 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015054 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015054 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015054 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16485.450589 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16485.450589 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16485.450589 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16485.450589 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16485.450589 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16485.450589 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 546680 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 53 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 25668 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 16.015580 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 24.500000 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 325000 # 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number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 325529 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3259633220 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 3259633220 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3259633220 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 3259633220 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3259633220 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 3259633220 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014521 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014521 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014521 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014521 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014521 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014521 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10013.342037 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10013.342037 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 822902 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 826054 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 2760 # number of redundant prefetches already in prefetch queue +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.298114 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 26.500000 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 325915 # number of writebacks +system.cpu.icache.writebacks::total 325915 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 11245 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 11245 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 11245 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 11245 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 11245 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 11245 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 326440 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 326440 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 326440 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 326440 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 326440 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 326440 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5156036946 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 5156036946 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5156036946 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 5156036946 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5156036946 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 5156036946 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014552 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014552 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014552 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014552 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014552 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014552 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15794.746189 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15794.746189 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15794.746189 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15794.746189 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15794.746189 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15794.746189 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 822007 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 825699 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 3235 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 78906 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 128177 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15989.063291 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1184574 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 144531 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 8.195986 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 78661 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 125486 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15697.579441 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 682126 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 141813 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.810039 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15883.544788 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 105.518503 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.969455 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006440 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.975895 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 30 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 16324 # 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number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 185500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 185500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 680267500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 680267500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2701591500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2701591500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5893524000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5893524000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2701591500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6573791500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9275383000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2701591500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6573791500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 9954483724 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19229866724 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056099 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056099 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.033507 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.033507 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.110605 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.110605 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.033507 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.093966 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.069739 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.033507 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.093966 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056514 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056514 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.113894 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.113894 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.239093 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239093 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113894 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.183195 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.155329 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113894 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183195 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.208431 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91646.708819 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14531.250000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14531.250000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79433.009476 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79433.009476 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70741.587971 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70741.587971 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75872.186280 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75872.186280 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70741.587971 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76521.172638 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75408.411297 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70741.587971 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76521.172638 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86213.546642 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1623643 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 811337 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80260 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 67456 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56671 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 663721 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 357454 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 550979 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 79349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 142185 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148612 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148612 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 325529 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 338193 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 976039 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1459935 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2435974 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41632640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62278272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 103910912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 318692 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6218112 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1131024 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.140178 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.373630 # Request fanout histogram +system.cpu.l2cache.overall_mshr_miss_rate::total 0.297300 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 86371.461875 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 86371.461875 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15458.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15458.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81003.512741 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81003.512741 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72666.402173 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72666.402173 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73193.293592 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73193.293592 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72666.402173 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73930.941991 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73558.106522 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72666.402173 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73930.941991 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 86371.461875 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79676.925949 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1622603 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 810817 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79904 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 18775 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18774 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 663212 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 351973 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 556066 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 28224 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 144126 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 148601 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148601 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 326440 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336773 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 978779 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455634 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2434413 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41749696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62095104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 103844800 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 269627 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6225728 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1081438 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.091286 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.288019 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 983264 86.94% 86.94% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 136975 12.11% 99.05% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 10785 0.95% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 982719 90.87% 90.87% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 98718 9.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1131024 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1623114500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 4.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 488687208 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 730433064 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 144751 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97140 # Transaction distribution -system.membus.trans_dist::CleanEvict 28117 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16 # Transaction distribution -system.membus.trans_dist::ReadExReq 8337 # Transaction distribution -system.membus.trans_dist::ReadExResp 8337 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 144752 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 431450 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 431450 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16014592 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 16014592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoop_fanout::total 1081438 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1622078500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 489794228 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 728148836 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 348072 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 205263 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 214175 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97262 # Transaction distribution +system.membus.trans_dist::CleanEvict 28224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 12 # Transaction distribution +system.membus.trans_dist::ReadExReq 8398 # Transaction distribution +system.membus.trans_dist::ReadExResp 8398 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 214176 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570645 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 570645 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20469440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20469440 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 278362 # Request fanout histogram +system.membus.snoop_fanout::samples 222586 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 278362 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 222586 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 278362 # Request fanout histogram -system.membus.reqLayer0.occupancy 747889943 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 222586 # Request fanout histogram +system.membus.reqLayer0.occupancy 837454269 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 799798093 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 1175863136 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 096e1a113..d8a41d287 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.219571 # Number of seconds simulated -sim_ticks 1219570622500 # Number of ticks simulated -final_tick 1219570622500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.222275 # Number of seconds simulated +sim_ticks 1222274983500 # Number of ticks simulated +final_tick 1222274983500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 313924 # Simulator instruction rate (inst/s) -host_op_rate 313924 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 209623743 # Simulator tick rate (ticks/s) -host_mem_usage 249764 # Number of bytes of host memory used -host_seconds 5817.90 # Real time elapsed on the host +host_inst_rate 407632 # Simulator instruction rate (inst/s) +host_op_rate 407632 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 272801132 # Simulator tick rate (ticks/s) +host_mem_usage 256700 # Number of bytes of host memory used +host_seconds 4480.46 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1219570622500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124970496 # Number of bytes read from this memory -system.physmem.bytes_read::total 125032128 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65417280 # Number of bytes written to this memory -system.physmem.bytes_written::total 65417280 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1952664 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1953627 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1022145 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1022145 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 50536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 102470897 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 102521433 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 50536 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 50536 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 53639600 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 53639600 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 53639600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 50536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 102470897 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 156161033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1953627 # Number of read requests accepted -system.physmem.writeReqs 1022145 # Number of write requests accepted -system.physmem.readBursts 1953627 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1022145 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 124950016 # Total number of bytes read from DRAM +system.physmem.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 61440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 126177664 # Number of bytes read from this memory +system.physmem.bytes_read::total 126239104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61440 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 66092544 # Number of bytes written to this memory +system.physmem.bytes_written::total 66092544 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 960 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1971526 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1972486 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1032696 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1032696 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 50267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 103231814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 103282081 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 50267 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 50267 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 54073384 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 54073384 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 54073384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 50267 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 103231814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 157355465 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1972486 # Number of read requests accepted +system.physmem.writeReqs 1032696 # Number of write requests accepted +system.physmem.readBursts 1972486 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1032696 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 126156992 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 82112 # Total number of bytes read from write queue -system.physmem.bytesWritten 65416064 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125032128 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65417280 # Total written bytes from the system interface side +system.physmem.bytesWritten 66090816 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 126239104 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 66092544 # Total written bytes from the system interface side system.physmem.servicedByWrQ 1283 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118315 # Per bank write bursts -system.physmem.perBankRdBursts::1 113533 # Per bank write bursts -system.physmem.perBankRdBursts::2 115749 # Per bank write bursts -system.physmem.perBankRdBursts::3 117256 # Per bank write bursts -system.physmem.perBankRdBursts::4 117296 # Per bank write bursts -system.physmem.perBankRdBursts::5 117124 # Per bank write bursts -system.physmem.perBankRdBursts::6 119398 # Per bank write bursts -system.physmem.perBankRdBursts::7 124125 # Per bank write bursts -system.physmem.perBankRdBursts::8 126652 # Per bank write bursts -system.physmem.perBankRdBursts::9 129582 # Per bank write bursts -system.physmem.perBankRdBursts::10 128170 # Per bank write bursts -system.physmem.perBankRdBursts::11 129930 # Per bank write bursts -system.physmem.perBankRdBursts::12 125581 # Per bank write bursts -system.physmem.perBankRdBursts::13 124839 # Per bank write bursts -system.physmem.perBankRdBursts::14 122149 # Per bank write bursts -system.physmem.perBankRdBursts::15 122645 # Per bank write bursts -system.physmem.perBankWrBursts::0 61422 # Per bank write bursts -system.physmem.perBankWrBursts::1 61664 # Per bank write bursts -system.physmem.perBankWrBursts::2 60725 # Per bank write bursts -system.physmem.perBankWrBursts::3 61395 # Per bank write bursts -system.physmem.perBankWrBursts::4 61816 # Per bank write bursts -system.physmem.perBankWrBursts::5 63307 # Per bank write bursts -system.physmem.perBankWrBursts::6 64357 # Per bank write bursts -system.physmem.perBankWrBursts::7 65854 # Per bank write bursts -system.physmem.perBankWrBursts::8 65580 # Per bank write bursts -system.physmem.perBankWrBursts::9 66032 # Per bank write bursts -system.physmem.perBankWrBursts::10 65645 # Per bank write bursts -system.physmem.perBankWrBursts::11 65946 # Per bank write bursts -system.physmem.perBankWrBursts::12 64510 # Per bank write bursts -system.physmem.perBankWrBursts::13 64527 # Per bank write bursts -system.physmem.perBankWrBursts::14 64900 # Per bank write bursts -system.physmem.perBankWrBursts::15 64446 # Per bank write bursts +system.physmem.perBankRdBursts::0 119355 # Per bank write bursts +system.physmem.perBankRdBursts::1 114736 # Per bank write bursts +system.physmem.perBankRdBursts::2 116711 # Per bank write bursts +system.physmem.perBankRdBursts::3 118315 # Per bank write bursts +system.physmem.perBankRdBursts::4 118360 # Per bank write bursts +system.physmem.perBankRdBursts::5 118227 # Per bank write bursts +system.physmem.perBankRdBursts::6 120694 # Per bank write bursts +system.physmem.perBankRdBursts::7 125539 # Per bank write bursts +system.physmem.perBankRdBursts::8 127875 # Per bank write bursts +system.physmem.perBankRdBursts::9 130856 # Per bank write bursts +system.physmem.perBankRdBursts::10 129453 # Per bank write bursts +system.physmem.perBankRdBursts::11 131175 # Per bank write bursts +system.physmem.perBankRdBursts::12 126741 # Per bank write bursts +system.physmem.perBankRdBursts::13 125953 # Per bank write bursts +system.physmem.perBankRdBursts::14 123325 # Per bank write bursts +system.physmem.perBankRdBursts::15 123888 # Per bank write bursts +system.physmem.perBankWrBursts::0 62004 # Per bank write bursts +system.physmem.perBankWrBursts::1 62322 # Per bank write bursts +system.physmem.perBankWrBursts::2 61319 # Per bank write bursts +system.physmem.perBankWrBursts::3 62011 # Per bank write bursts +system.physmem.perBankWrBursts::4 62436 # Per bank write bursts +system.physmem.perBankWrBursts::5 63988 # Per bank write bursts +system.physmem.perBankWrBursts::6 65064 # Per bank write bursts +system.physmem.perBankWrBursts::7 66489 # Per bank write bursts +system.physmem.perBankWrBursts::8 66234 # Per bank write bursts +system.physmem.perBankWrBursts::9 66705 # Per bank write bursts +system.physmem.perBankWrBursts::10 66339 # Per bank write bursts +system.physmem.perBankWrBursts::11 66709 # Per bank write bursts +system.physmem.perBankWrBursts::12 65174 # Per bank write bursts +system.physmem.perBankWrBursts::13 65212 # Per bank write bursts +system.physmem.perBankWrBursts::14 65629 # Per bank write bursts +system.physmem.perBankWrBursts::15 65034 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1219570506500 # Total gap between requests +system.physmem.totGap 1222274866500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1953627 # Read request sizes (log2) +system.physmem.readPktSize::6 1972486 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1022145 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1833407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 118928 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1032696 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1847755 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 123438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -145,27 +145,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 30664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 32017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 59725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 60150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 60164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 60165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 60205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 60270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 60241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 60697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 61009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 60531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 61008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 30048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 31196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 61015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 61067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 61245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 60829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 60715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -194,139 +194,137 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1832533 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.880589 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.106196 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 130.417770 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1454670 79.38% 79.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 261169 14.25% 93.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 48917 2.67% 96.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20611 1.12% 97.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13239 0.72% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7059 0.39% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5499 0.30% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4584 0.25% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16785 0.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1832533 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59623 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.744209 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 148.154914 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 59464 99.73% 99.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 114 0.19% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 10 0.02% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 6 0.01% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 6 0.01% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-3071 5 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3583 3 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1846311 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 104.123632 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.172382 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 131.523418 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1463397 79.26% 79.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 266113 14.41% 93.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 48771 2.64% 96.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20101 1.09% 97.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12770 0.69% 98.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7489 0.41% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5280 0.29% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4734 0.26% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 17656 0.96% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1846311 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60557 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.510131 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 23.099317 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 136.122575 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 60389 99.72% 99.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 130 0.21% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 8 0.01% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 5 0.01% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 4 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-3071 4 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3583 1 0.00% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3584-4095 4 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-5119 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4608-5119 4 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-9727 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10752-11263 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-9727 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-12799 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12800-13311 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59623 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59623 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.143149 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.107238 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.113236 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27459 46.05% 46.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1251 2.10% 48.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 26456 44.37% 92.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3936 6.60% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 436 0.73% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 70 0.12% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 12 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 3 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59623 # Writes before turning the bus around for reads -system.physmem.totQLat 36415699500 # Total ticks spent queuing -system.physmem.totMemAccLat 73022149500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9761720000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18652.30 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 60557 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60557 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.052843 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.021089 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.041900 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 29161 48.15% 48.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1164 1.92% 50.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 28160 46.50% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2021 3.34% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 45 0.07% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 6 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60557 # Writes before turning the bus around for reads +system.physmem.totQLat 36942736250 # Total ticks spent queuing +system.physmem.totMemAccLat 73902792500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9856015000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18741.21 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37402.30 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 102.45 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 53.64 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 102.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 53.64 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37491.21 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 103.21 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 54.07 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 103.28 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 54.07 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.22 # Data bus utilization in percentage -system.physmem.busUtilRead 0.80 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.23 # Data bus utilization in percentage +system.physmem.busUtilRead 0.81 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.66 # Average write queue length when enqueuing -system.physmem.readRowHits 723035 # Number of row buffer hits during reads -system.physmem.writeRowHits 418897 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.03 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.98 # Row buffer hit rate for writes -system.physmem.avgGap 409833.32 # Average gap between requests -system.physmem.pageHitRate 38.39 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6719093640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3666172125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7353785400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3243499200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 79656261360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 415707006375 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 367085761500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 883431579600 # Total energy per rank (pJ) -system.physmem_0.averagePower 724.380520 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 607907659750 # Time in different power states -system.physmem_0.memoryStateTime::REF 40724060000 # Time in different power states +system.physmem.avgWrQLen 25.40 # Average write queue length when enqueuing +system.physmem.readRowHits 727606 # Number of row buffer hits during reads +system.physmem.writeRowHits 429946 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.91 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.63 # Row buffer hit rate for writes +system.physmem.avgGap 406722.41 # Average gap between requests +system.physmem.pageHitRate 38.53 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6766986240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3692304000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7425061800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3276501840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 79832731680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 416045775330 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 368409693000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 885449053890 # Total energy per rank (pJ) +system.physmem_0.averagePower 724.429872 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 610096075500 # Time in different power states +system.physmem_0.memoryStateTime::REF 40814280000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 570937965250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 571360638500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7134833160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3893014125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7874240400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3379877280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 79656261360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 426752022060 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 357397152750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 886087401135 # Total energy per rank (pJ) -system.physmem_1.averagePower 726.558192 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 591710247250 # Time in different power states -system.physmem_1.memoryStateTime::REF 40724060000 # Time in different power states +system.physmem_1.actEnergy 7191102240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3923716500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7949838000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3415193280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 79832731680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 427319070030 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 358520838000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 888152489730 # Total energy per rank (pJ) +system.physmem_1.averagePower 726.641687 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 593574305750 # Time in different power states +system.physmem_1.memoryStateTime::REF 40814280000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 587134092250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 587881640500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1219570622500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 246937199 # Number of BP lookups -system.cpu.branchPred.condPredicted 186891611 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15587043 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 168278704 # Number of BTB lookups -system.cpu.branchPred.BTBHits 165579614 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 246953326 # Number of BP lookups +system.cpu.branchPred.condPredicted 186908369 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15587365 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 168276583 # Number of BTB lookups +system.cpu.branchPred.BTBHits 165592346 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.396060 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18556464 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 106119 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 314 # Number of indirect predictor lookups. +system.cpu.branchPred.BTBHitPct 98.404866 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18556185 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 105918 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 315 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 63 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 251 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 252 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 101 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 453406129 # DTB read hits -system.cpu.dtb.read_misses 5001511 # DTB read misses +system.cpu.dtb.read_hits 453405484 # DTB read hits +system.cpu.dtb.read_misses 5001335 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 458407640 # DTB read accesses -system.cpu.dtb.write_hits 161376524 # DTB write hits -system.cpu.dtb.write_misses 1709205 # DTB write misses +system.cpu.dtb.read_accesses 458406819 # DTB read accesses +system.cpu.dtb.write_hits 161377349 # DTB write hits +system.cpu.dtb.write_misses 1709149 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 163085729 # DTB write accesses -system.cpu.dtb.data_hits 614782653 # DTB hits -system.cpu.dtb.data_misses 6710716 # DTB misses +system.cpu.dtb.write_accesses 163086498 # DTB write accesses +system.cpu.dtb.data_hits 614782833 # DTB hits +system.cpu.dtb.data_misses 6710484 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 621493369 # DTB accesses -system.cpu.itb.fetch_hits 600073027 # ITB hits +system.cpu.dtb.data_accesses 621493317 # DTB accesses +system.cpu.itb.fetch_hits 600105517 # ITB hits system.cpu.itb.fetch_misses 19 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 600073046 # ITB accesses +system.cpu.itb.fetch_accesses 600105536 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -340,16 +338,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1219570622500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2439141245 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1222274983500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2444549967 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1826378509 # Number of instructions committed system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.discardedOps 55113124 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 55126564 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.335507 # CPI: cycles per instruction -system.cpu.ipc 0.748779 # IPC: instructions per cycle +system.cpu.cpi 1.338468 # CPI: cycles per instruction +system.cpu.ipc 0.747123 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 83736345 4.58% 4.58% # Class of committed instruction system.cpu.op_class_0::IntAlu 1129914150 61.87% 66.45% # Class of committed instruction system.cpu.op_class_0::IntMult 75 0.00% 66.45% # Class of committed instruction @@ -385,59 +383,59 @@ system.cpu.op_class_0::MemWrite 162429806 8.89% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 1826378509 # Class of committed instruction -system.cpu.tickCycles 2082121954 # Number of cycles that the object actually ticked -system.cpu.idleCycles 357019291 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1219570622500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9121976 # number of replacements -system.cpu.dcache.tags.tagsinuse 4080.816467 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 602780801 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9126072 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 66.050410 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 16880243500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4080.816467 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.996293 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996293 # Average percentage of cache occupancy +system.cpu.tickCycles 2082292947 # Number of cycles that the object actually ticked +system.cpu.idleCycles 362257020 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 9121995 # number of replacements +system.cpu.dcache.tags.tagsinuse 4080.838657 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 602779955 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9126091 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 66.050180 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 16887433500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4080.838657 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996299 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996299 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1561 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2409 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 70 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1547 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2420 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 71 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1233657814 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1233657814 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1219570622500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 444298266 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 444298266 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 158482535 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158482535 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 602780801 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 602780801 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 602780801 # number of overall hits -system.cpu.dcache.overall_hits::total 602780801 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7239103 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7239103 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2245967 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2245967 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9485070 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9485070 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9485070 # number of overall misses -system.cpu.dcache.overall_misses::total 9485070 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 184068939500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 184068939500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 108510867000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 108510867000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 292579806500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 292579806500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 292579806500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 292579806500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 451537369 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 451537369 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1233656307 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1233656307 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 444297476 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 444297476 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158482479 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158482479 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 602779955 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 602779955 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 602779955 # number of overall hits +system.cpu.dcache.overall_hits::total 602779955 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7239130 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7239130 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2246023 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2246023 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9485153 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9485153 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9485153 # number of overall misses +system.cpu.dcache.overall_misses::total 9485153 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 185791393500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 185791393500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 110650401500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 110650401500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 296441795000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 296441795000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 296441795000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 296441795000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 451536606 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 451536606 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 612265871 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 612265871 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 612265871 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 612265871 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 612265108 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 612265108 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 612265108 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 612265108 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016032 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016032 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013974 # miss rate for WriteReq accesses @@ -446,46 +444,46 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015492 system.cpu.dcache.demand_miss_rate::total 0.015492 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015492 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015492 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25427.036955 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25427.036955 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48313.651536 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48313.651536 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30846.351846 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30846.351846 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30846.351846 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30846.351846 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25664.878722 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25664.878722 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49265.034908 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 49265.034908 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31253.243358 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31253.243358 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31253.243358 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31253.243358 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3686661 # number of writebacks -system.cpu.dcache.writebacks::total 3686661 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 370 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 370 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 358628 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 358628 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 358998 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 358998 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 358998 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 358998 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238733 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238733 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887339 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887339 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9126072 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126072 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9126072 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126072 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 176823131500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 176823131500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83341929000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83341929000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260165060500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 260165060500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260165060500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 260165060500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3671998 # number of writebacks +system.cpu.dcache.writebacks::total 3671998 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 362 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 362 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 358700 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 358700 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 359062 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 359062 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 359062 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 359062 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238768 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7238768 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887323 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1887323 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9126091 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9126091 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9126091 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9126091 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 178546113500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 178546113500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85195528000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85195528000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 263741641500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 263741641500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 263741641500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 263741641500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016031 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016031 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011742 # mshr miss rate for WriteReq accesses @@ -494,67 +492,67 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014905 system.cpu.dcache.demand_mshr_miss_rate::total 0.014905 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014905 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014905 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24427.359249 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24427.359249 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44158.430997 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44158.430997 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28507.890416 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28507.890416 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28507.890416 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28507.890416 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1219570622500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24665.262583 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24665.262583 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45140.936660 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45140.936660 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28899.738289 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28899.738289 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28899.738289 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28899.738289 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 752.953880 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 600072064 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 963 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 623127.792316 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 752.723923 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 600104557 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 960 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 625108.913542 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 752.953880 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.367653 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.367653 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 960 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 878 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.468750 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1200147017 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1200147017 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1219570622500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 600072064 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 600072064 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 600072064 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 600072064 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 600072064 # number of overall hits -system.cpu.icache.overall_hits::total 600072064 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 963 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 963 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 963 # 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number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 600073027 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 600073027 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 600073027 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 752.723923 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.367541 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.367541 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 957 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 876 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.467285 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1200211994 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1200211994 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 600104557 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 600104557 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 600104557 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 600104557 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 600104557 # number of overall hits +system.cpu.icache.overall_hits::total 600104557 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 960 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 960 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 960 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 960 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 960 # number of overall misses +system.cpu.icache.overall_misses::total 960 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 77923500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 77923500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 77923500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 77923500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 77923500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 77923500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 600105517 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 600105517 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 600105517 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 600105517 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 600105517 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 600105517 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 79261.163032 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 79261.163032 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 79261.163032 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 79261.163032 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78667.708333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88684.566676 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 88679.691516 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1022145 # number of writebacks -system.cpu.l2cache.writebacks::total 1022145 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1032696 # number of writebacks +system.cpu.l2cache.writebacks::total 1032696 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 242 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 780512 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 780512 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 963 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 963 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1172152 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1172152 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1952664 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1953627 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1952664 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1953627 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61012806000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61012806000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 64288500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 64288500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90528433000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90528433000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64288500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151541239000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 151605527500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64288500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151541239000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 151605527500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 792050 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 792050 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 960 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 960 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1179476 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1179476 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 960 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1971526 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1972486 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 960 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1971526 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1972486 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62873970500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62873970500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65921000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65921000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 92254698500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 92254698500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65921000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 155128669000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 155194590000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65921000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 155128669000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 155194590000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413552 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413552 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.419668 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.419668 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161928 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161928 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162939 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162939 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213965 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214048 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216032 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216114 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213965 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214048 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78170.234410 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78170.234410 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66758.566978 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66758.566978 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77232.673749 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77232.673749 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66758.566978 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77607.432205 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77602.084482 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66758.566978 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77607.432205 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77602.084482 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18249014 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121979 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216032 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.216114 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79381.314942 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79381.314942 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68667.708333 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68667.708333 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78216.681391 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78216.681391 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68667.708333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78684.566676 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78679.691516 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68667.708333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78684.566676 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78679.691516 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18249049 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121998 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1272 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1272 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1439 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1439 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1219570622500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7239696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4708806 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 7239728 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4704694 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6334072 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887339 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887339 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 963 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238733 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1929 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374120 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27376049 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820014912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 820076736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1920902 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 65417280 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11047937 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000115 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.010729 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::CleanEvict 6357340 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1887323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1887323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 960 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238768 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1923 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374177 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27376100 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819077696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 819139328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1940039 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 66092544 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11067090 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000130 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.011402 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11046665 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1272 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11065651 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1439 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11047937 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12811171000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1444500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11067090 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12796525500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1440000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13689108000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13689136500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 1219570622500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1173115 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1022145 # Transaction distribution -system.membus.trans_dist::CleanEvict 897727 # Transaction distribution -system.membus.trans_dist::ReadExReq 780512 # Transaction distribution -system.membus.trans_dist::ReadExResp 780512 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1173115 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5827126 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5827126 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190449408 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190449408 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 3911328 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1938842 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 1222274983500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1180436 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1032696 # Transaction distribution +system.membus.trans_dist::CleanEvict 906146 # Transaction distribution +system.membus.trans_dist::ReadExReq 792050 # Transaction distribution +system.membus.trans_dist::ReadExResp 792050 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1180436 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5883814 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5883814 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192331648 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 192331648 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3873499 # Request fanout histogram +system.membus.snoop_fanout::samples 1972486 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3873499 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1972486 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3873499 # Request fanout histogram -system.membus.reqLayer0.occupancy 8456520500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1972486 # Request fanout histogram +system.membus.reqLayer0.occupancy 8508050000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 10686565250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 10787775250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index cd08b0f17..7435ab9ce 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,110 +1,110 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.669588 # Number of seconds simulated -sim_ticks 669587683000 # Number of ticks simulated -final_tick 669587683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.629948 # Number of seconds simulated +sim_ticks 629947889500 # Number of ticks simulated +final_tick 629947889500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 209688 # Simulator instruction rate (inst/s) -host_op_rate 209688 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 80876198 # Simulator tick rate (ticks/s) -host_mem_usage 251300 # Number of bytes of host memory used -host_seconds 8279.17 # Real time elapsed on the host -sim_insts 1736043781 # Number of instructions simulated -sim_ops 1736043781 # Number of ops (including micro ops) simulated +host_inst_rate 297749 # Simulator instruction rate (inst/s) +host_op_rate 297749 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 111692471 # Simulator tick rate (ticks/s) +host_mem_usage 257464 # Number of bytes of host memory used +host_seconds 5640.02 # Real time elapsed on the host +sim_insts 1679312925 # Number of instructions simulated +sim_ops 1679312925 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 60736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125489536 # Number of bytes read from this memory -system.physmem.bytes_read::total 125550272 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 60736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 60736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65555456 # Number of bytes written to this memory -system.physmem.bytes_written::total 65555456 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 949 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1960774 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1961723 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1024304 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1024304 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 90707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 187413149 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 187503855 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 90707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 90707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 97904214 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 97904214 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 97904214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 90707 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 187413149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 285408070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1961723 # Number of read requests accepted -system.physmem.writeReqs 1024304 # Number of write requests accepted -system.physmem.readBursts 1961723 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1024304 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125465280 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 84992 # Total number of bytes read from write queue -system.physmem.bytesWritten 65553920 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125550272 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65555456 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1328 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 56512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 116052224 # Number of bytes read from this memory +system.physmem.bytes_read::total 116108736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 56512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 56512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65771840 # Number of bytes written to this memory +system.physmem.bytes_written::total 65771840 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 883 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1813316 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1814199 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1027685 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1027685 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 89709 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 184225118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 184314827 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 89709 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 89709 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 104408382 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 104408382 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 104408382 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 89709 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 184225118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 288723209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1814199 # Number of read requests accepted +system.physmem.writeReqs 1027685 # Number of write requests accepted +system.physmem.readBursts 1814199 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1027685 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 116025984 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 82752 # Total number of bytes read from write queue +system.physmem.bytesWritten 65770240 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 116108736 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65771840 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1293 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118674 # Per bank write bursts -system.physmem.perBankRdBursts::1 113905 # Per bank write bursts -system.physmem.perBankRdBursts::2 116110 # Per bank write bursts -system.physmem.perBankRdBursts::3 117640 # Per bank write bursts -system.physmem.perBankRdBursts::4 117758 # Per bank write bursts -system.physmem.perBankRdBursts::5 117504 # Per bank write bursts -system.physmem.perBankRdBursts::6 119855 # Per bank write bursts -system.physmem.perBankRdBursts::7 124644 # Per bank write bursts -system.physmem.perBankRdBursts::8 127350 # Per bank write bursts -system.physmem.perBankRdBursts::9 130115 # Per bank write bursts -system.physmem.perBankRdBursts::10 128783 # Per bank write bursts -system.physmem.perBankRdBursts::11 130505 # Per bank write bursts -system.physmem.perBankRdBursts::12 126282 # Per bank write bursts -system.physmem.perBankRdBursts::13 125429 # Per bank write bursts -system.physmem.perBankRdBursts::14 122618 # Per bank write bursts -system.physmem.perBankRdBursts::15 123223 # Per bank write bursts -system.physmem.perBankWrBursts::0 61508 # Per bank write bursts -system.physmem.perBankWrBursts::1 61766 # Per bank write bursts -system.physmem.perBankWrBursts::2 60822 # Per bank write bursts -system.physmem.perBankWrBursts::3 61512 # Per bank write bursts -system.physmem.perBankWrBursts::4 61965 # Per bank write bursts -system.physmem.perBankWrBursts::5 63432 # Per bank write bursts -system.physmem.perBankWrBursts::6 64483 # Per bank write bursts -system.physmem.perBankWrBursts::7 65996 # Per bank write bursts -system.physmem.perBankWrBursts::8 65772 # Per bank write bursts -system.physmem.perBankWrBursts::9 66160 # Per bank write bursts -system.physmem.perBankWrBursts::10 65806 # Per bank write bursts -system.physmem.perBankWrBursts::11 66084 # Per bank write bursts -system.physmem.perBankWrBursts::12 64700 # Per bank write bursts -system.physmem.perBankWrBursts::13 64663 # Per bank write bursts -system.physmem.perBankWrBursts::14 65022 # Per bank write bursts -system.physmem.perBankWrBursts::15 64589 # Per bank write bursts +system.physmem.perBankRdBursts::0 109825 # Per bank write bursts +system.physmem.perBankRdBursts::1 106113 # Per bank write bursts +system.physmem.perBankRdBursts::2 107421 # Per bank write bursts +system.physmem.perBankRdBursts::3 108541 # Per bank write bursts +system.physmem.perBankRdBursts::4 108748 # Per bank write bursts +system.physmem.perBankRdBursts::5 108721 # Per bank write bursts +system.physmem.perBankRdBursts::6 111475 # Per bank write bursts +system.physmem.perBankRdBursts::7 116266 # Per bank write bursts +system.physmem.perBankRdBursts::8 117532 # Per bank write bursts +system.physmem.perBankRdBursts::9 120021 # Per bank write bursts +system.physmem.perBankRdBursts::10 119000 # Per bank write bursts +system.physmem.perBankRdBursts::11 120366 # Per bank write bursts +system.physmem.perBankRdBursts::12 116224 # Per bank write bursts +system.physmem.perBankRdBursts::13 115367 # Per bank write bursts +system.physmem.perBankRdBursts::14 113352 # Per bank write bursts +system.physmem.perBankRdBursts::15 113934 # Per bank write bursts +system.physmem.perBankWrBursts::0 61679 # Per bank write bursts +system.physmem.perBankWrBursts::1 62003 # Per bank write bursts +system.physmem.perBankWrBursts::2 61008 # Per bank write bursts +system.physmem.perBankWrBursts::3 61698 # Per bank write bursts +system.physmem.perBankWrBursts::4 62148 # Per bank write bursts +system.physmem.perBankWrBursts::5 63666 # Per bank write bursts +system.physmem.perBankWrBursts::6 64723 # Per bank write bursts +system.physmem.perBankWrBursts::7 66137 # Per bank write bursts +system.physmem.perBankWrBursts::8 65915 # Per bank write bursts +system.physmem.perBankWrBursts::9 66335 # Per bank write bursts +system.physmem.perBankWrBursts::10 66021 # Per bank write bursts +system.physmem.perBankWrBursts::11 66389 # Per bank write bursts +system.physmem.perBankWrBursts::12 64907 # Per bank write bursts +system.physmem.perBankWrBursts::13 64927 # Per bank write bursts +system.physmem.perBankWrBursts::14 65328 # Per bank write bursts +system.physmem.perBankWrBursts::15 64776 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 669587587500 # Total gap between requests +system.physmem.totGap 629947397500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1961723 # Read request sizes (log2) +system.physmem.readPktSize::6 1814199 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1024304 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1618543 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 241060 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 69851 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 30927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1027685 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1469096 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 241446 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 70874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 31473 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -145,29 +145,29 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 26257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 27847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 63644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 65120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 25872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 27378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 51064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 57932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 60149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 63157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 65572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see @@ -194,156 +194,139 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1769781 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.933083 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.950192 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 137.486388 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1375005 77.69% 77.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 271238 15.33% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 53445 3.02% 96.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21262 1.20% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12891 0.73% 97.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6578 0.37% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4909 0.28% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3869 0.22% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20584 1.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1769781 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60104 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.614784 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 150.080179 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 59932 99.71% 99.71% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 127 0.21% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 10 0.02% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 7 0.01% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 8 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1631200 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 111.449220 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 84.546651 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 143.577205 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1240852 76.07% 76.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 269138 16.50% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 51923 3.18% 95.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20333 1.25% 97.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12353 0.76% 97.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6354 0.39% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4947 0.30% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3735 0.23% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21565 1.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1631200 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60546 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.938741 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 22.568202 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 131.498063 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 60449 99.84% 99.84% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 61 0.10% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 7 0.01% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 6 0.01% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 2 0.00% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2560-3071 4 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-3583 3 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-4095 1 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-4095 2 0.00% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-5119 3 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4608-5119 4 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-9727 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-9727 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60104 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60104 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.041794 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.999820 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.231211 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 31815 52.93% 52.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1444 2.40% 55.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 21085 35.08% 90.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4727 7.86% 98.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 762 1.27% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 188 0.31% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 35 0.06% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 13 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 6 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 5 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60104 # Writes before turning the bus around for reads -system.physmem.totQLat 40549512750 # Total ticks spent queuing -system.physmem.totMemAccLat 77306919000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9801975000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20684.36 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::12288-12799 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12800-13311 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 60546 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60546 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.973210 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.937472 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.113084 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 32669 53.96% 53.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1474 2.43% 56.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 22634 37.38% 93.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3027 5.00% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 624 1.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 106 0.18% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 9 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60546 # Writes before turning the bus around for reads +system.physmem.totQLat 37088946500 # Total ticks spent queuing +system.physmem.totMemAccLat 71080934000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9064530000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20458.28 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39434.36 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 187.38 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 97.90 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 187.50 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 97.90 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39208.28 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 184.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 104.41 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 184.31 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 104.41 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.23 # Data bus utilization in percentage -system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes +system.physmem.busUtil 2.25 # Data bus utilization in percentage +system.physmem.busUtilRead 1.44 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.82 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.98 # Average write queue length when enqueuing -system.physmem.readRowHits 792652 # Number of row buffer hits during reads -system.physmem.writeRowHits 422237 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.43 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.22 # Row buffer hit rate for writes -system.physmem.avgGap 224240.30 # Average gap between requests -system.physmem.pageHitRate 40.70 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6484506840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3538173375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7379478600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3249616320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 43734125760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 304395031755 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 134738783250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 503519715900 # Total energy per rank (pJ) -system.physmem_0.averagePower 751.985934 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 222173701250 # Time in different power states -system.physmem_0.memoryStateTime::REF 22358960000 # Time in different power states +system.physmem.avgWrQLen 24.61 # Average write queue length when enqueuing +system.physmem.readRowHits 781743 # Number of row buffer hits during reads +system.physmem.writeRowHits 427619 # Number of row buffer hits during writes +system.physmem.readRowHitRate 43.12 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.61 # Row buffer hit rate for writes +system.physmem.avgGap 221665.42 # Average gap between requests +system.physmem.pageHitRate 42.57 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5990438160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3268592250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6841434600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3259841760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 41145046800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 279886127580 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 132453942750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 472845423900 # Total energy per rank (pJ) +system.physmem_0.averagePower 750.611658 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 218497726500 # Time in different power states +system.physmem_0.memoryStateTime::REF 21035300000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 425054234250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 390413882500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6895022400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3762165000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7911430800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3387718080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 43734125760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 311120339490 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 128839390500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 505650192030 # Total energy per rank (pJ) -system.physmem_1.averagePower 755.167712 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 212315780250 # Time in different power states -system.physmem_1.memoryStateTime::REF 22358960000 # Time in different power states +system.physmem_1.actEnergy 6341433840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3460107750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7299201000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3399395040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 41145046800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 287961158835 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 125370582000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 474976925265 # Total energy per rank (pJ) +system.physmem_1.averagePower 753.995279 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 206677750500 # Time in different power states +system.physmem_1.memoryStateTime::REF 21035300000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 434911888500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 402234088500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 409349783 # Number of BP lookups -system.cpu.branchPred.condPredicted 318159413 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15962959 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 282310323 # Number of BTB lookups -system.cpu.branchPred.BTBHits 278567233 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 393343738 # Number of BP lookups +system.cpu.branchPred.condPredicted 308206683 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15638618 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 270406177 # Number of BTB lookups +system.cpu.branchPred.BTBHits 266678706 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.674122 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 26172089 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 47 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 12632 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 1004 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 11628 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 76 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 98.621529 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 24232356 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 43 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 11458 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 743 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 10715 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 54 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 644930756 # DTB read hits -system.cpu.dtb.read_misses 12159240 # DTB read misses +system.cpu.dtb.read_hits 615604408 # DTB read hits +system.cpu.dtb.read_misses 10829988 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 657089996 # DTB read accesses -system.cpu.dtb.write_hits 218090963 # DTB write hits -system.cpu.dtb.write_misses 7511655 # DTB write misses +system.cpu.dtb.read_accesses 626434396 # DTB read accesses +system.cpu.dtb.write_hits 204678819 # DTB write hits +system.cpu.dtb.write_misses 7425838 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 225602618 # DTB write accesses -system.cpu.dtb.data_hits 863021719 # DTB hits -system.cpu.dtb.data_misses 19670895 # DTB misses +system.cpu.dtb.write_accesses 212104657 # DTB write accesses +system.cpu.dtb.data_hits 820283227 # DTB hits +system.cpu.dtb.data_misses 18255826 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 882692614 # DTB accesses -system.cpu.itb.fetch_hits 420612911 # ITB hits +system.cpu.dtb.data_accesses 838539053 # DTB accesses +system.cpu.itb.fetch_hits 399075166 # ITB hits system.cpu.itb.fetch_misses 37 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 420612948 # ITB accesses +system.cpu.itb.fetch_accesses 399075203 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -356,753 +339,751 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 669587683000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1339175367 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 23 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 629947889500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1259895780 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 431750962 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3410040939 # Number of instructions fetch has processed -system.cpu.fetch.Branches 409349783 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 304740326 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 884658040 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 45380368 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 409587649 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3241372877 # Number of instructions fetch has processed +system.cpu.fetch.Branches 393343738 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 290911805 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 828631431 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 43212526 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1660 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 420612911 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8286314 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1339100880 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.546515 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.150664 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 1670 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 106 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 399075166 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 7874466 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1259827144 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.572871 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.161590 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 714090223 53.33% 53.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 47658538 3.56% 56.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 24213511 1.81% 58.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 45104764 3.37% 62.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 142790793 10.66% 72.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 65948937 4.92% 77.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 43596223 3.26% 80.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 29427236 2.20% 83.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 226270655 16.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 668246093 53.04% 53.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 43806893 3.48% 56.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 23751936 1.89% 58.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 40823777 3.24% 61.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 134784051 10.70% 72.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61318653 4.87% 77.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 43063501 3.42% 80.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28777614 2.28% 82.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 215254626 17.09% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1339100880 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.305673 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.546374 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 353769972 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 403619551 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 524217734 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 34804152 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 22689471 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 62026814 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 760 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3256105292 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2070 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 22689471 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 372006695 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 212568628 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7422 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 537155412 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 194673252 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3173749438 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1811256 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 20472342 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 148588016 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 30888023 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2371822708 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4117670877 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4117534302 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 136574 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 995619745 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 151 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 149 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 99632674 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 717246724 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 272457234 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 90451892 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 58631522 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2884174304 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 130 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2620036143 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1544818 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1148130652 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 502718906 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 101 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1339100880 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.956564 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.148176 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1259827144 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.312203 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.572731 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 336809889 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 370413676 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 497881112 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 33116842 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 21605625 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58265374 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 679 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3099960384 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1859 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 21605625 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 354079753 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 199727925 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 5296 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 510193154 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 174215391 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3021993285 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1813082 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 19910474 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 129183664 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 30561708 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2254247429 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3918399799 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3918272154 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 127644 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1331032194 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 923215197 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 126 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 124 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 94488821 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 681241316 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255797496 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 84438658 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 55736283 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2741763403 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 107 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2499259906 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1517170 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1062450541 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 465504121 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 84 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1259827144 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.983812 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.153359 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 535608565 40.00% 40.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 169639715 12.67% 52.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 157955882 11.80% 64.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 149207498 11.14% 75.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 126008488 9.41% 85.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 84159132 6.28% 91.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 68020206 5.08% 96.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 34099830 2.55% 98.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14401564 1.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 494791866 39.27% 39.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 161324184 12.81% 52.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 149742004 11.89% 63.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 141543893 11.24% 75.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 119990032 9.52% 84.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 80369213 6.38% 91.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 66025796 5.24% 96.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 32462182 2.58% 98.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 13577974 1.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1339100880 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1259827144 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 13158046 35.85% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18960543 51.65% 87.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4589272 12.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 12419183 35.12% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18417667 52.09% 87.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4521757 12.79% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1716921702 65.53% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 112 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 896133 0.03% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 22 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 32 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 26 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 671538399 25.63% 91.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 230679552 8.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1641003125 65.66% 65.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 98 0.00% 65.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 896111 0.04% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 23 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 164 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 32 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 26 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 640377775 25.62% 91.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 216982552 8.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2620036143 # Type of FU issued -system.cpu.iq.rate 1.956455 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36707861 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014010 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6615486651 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4031199558 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2518604332 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1939194 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1248781 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 886609 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2655777108 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 966896 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69396468 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2499259906 # Type of FU issued +system.cpu.iq.rate 1.983704 # Inst issue rate +system.cpu.iq.fu_busy_cnt 35358607 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014148 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6293293204 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3803117225 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2401572542 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1929523 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1233317 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 883284 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2533656719 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 961794 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 60564498 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 272651061 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 372885 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 145563 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 111728732 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 251534222 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 355806 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 138747 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 101659209 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 286 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6308614 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 256 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6319064 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 22689471 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 149827283 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 21278630 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3035173177 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6594541 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 717246724 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 272457234 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 130 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 801857 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 20733670 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 145563 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10633550 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8701156 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19334706 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2574881369 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 657090005 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 45154774 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 21605625 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 137066476 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 20199207 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2888644044 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6351774 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 681241316 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255797496 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 107 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 653480 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 19719948 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 138747 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10434747 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8530204 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18964951 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2455710851 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 626434405 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 43549049 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 150998743 # number of nop insts executed -system.cpu.iew.exec_refs 882692691 # number of memory reference insts executed -system.cpu.iew.exec_branches 315484112 # Number of branches executed -system.cpu.iew.exec_stores 225602686 # Number of stores executed -system.cpu.iew.exec_rate 1.922737 # Inst execution rate -system.cpu.iew.wb_sent 2549313271 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2519490941 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1487485532 # num instructions producing a value -system.cpu.iew.wb_consumers 1918368513 # num instructions consuming a value -system.cpu.iew.wb_rate 1.881375 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.775391 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 998632615 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15962246 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1201120469 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.515069 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.548329 # Number of insts commited each cycle +system.cpu.iew.exec_nop 146880534 # number of nop insts executed +system.cpu.iew.exec_refs 838539129 # number of memory reference insts executed +system.cpu.iew.exec_branches 303173790 # Number of branches executed +system.cpu.iew.exec_stores 212104724 # Number of stores executed +system.cpu.iew.exec_rate 1.949138 # Inst execution rate +system.cpu.iew.wb_sent 2430569294 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2402455826 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1423499549 # num instructions producing a value +system.cpu.iew.wb_consumers 1834375042 # num instructions consuming a value +system.cpu.iew.wb_rate 1.906869 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.776013 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 934600585 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 23 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 15637980 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1130658933 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.557680 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.564025 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 712379439 59.31% 59.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 159650119 13.29% 72.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 79517213 6.62% 79.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 52024602 4.33% 83.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28479101 2.37% 85.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 19489140 1.62% 87.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19970906 1.66% 89.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23045357 1.92% 91.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106564592 8.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 654603026 57.90% 57.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 156815138 13.87% 71.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 77634971 6.87% 78.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 50637990 4.48% 83.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28095009 2.48% 85.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 18859448 1.67% 87.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19659708 1.74% 89.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22259274 1.97% 90.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 102094369 9.03% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1201120469 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1819780126 # Number of instructions committed -system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1130658933 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1761204444 # Number of instructions committed +system.cpu.commit.committedOps 1761204444 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 605324165 # Number of memory references committed -system.cpu.commit.loads 444595663 # Number of loads committed +system.cpu.commit.refs 583845365 # Number of memory references committed +system.cpu.commit.loads 429707085 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 214632552 # Number of branches committed -system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. -system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 83736345 4.60% 4.60% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 1129914149 62.09% 66.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 75 0.00% 66.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.69% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 805244 0.04% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 13 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 100 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 11 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 24 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 444595663 24.43% 91.17% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Class of committed instruction +system.cpu.commit.branches 208988363 # Number of branches committed +system.cpu.commit.fp_insts 805327 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1662744776 # Number of committed integer instructions. +system.cpu.commit.function_calls 16089601 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 81891519 4.65% 4.65% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 1094662288 62.15% 66.80% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 66 0.00% 66.80% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.80% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 805058 0.05% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 13 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 100 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 11 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 24 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.85% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 429707085 24.40% 91.25% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 154138280 8.75% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction -system.cpu.commit.bw_lim_events 106564592 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3827189418 # The number of ROB reads -system.cpu.rob.rob_writes 5774940551 # The number of ROB writes -system.cpu.timesIdled 705 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 74487 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1736043781 # Number of Instructions Simulated -system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.771395 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.771395 # CPI: Total CPI of All Threads -system.cpu.ipc 1.296353 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.296353 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3463571137 # number of integer regfile reads -system.cpu.int_regfile_writes 2019338951 # number of integer regfile writes -system.cpu.fp_regfile_reads 39668 # number of floating regfile reads -system.cpu.fp_regfile_writes 612 # number of floating regfile writes +system.cpu.commit.op_class_0::total 1761204444 # Class of committed instruction +system.cpu.commit.bw_lim_events 102094369 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3648383709 # The number of ROB reads +system.cpu.rob.rob_writes 5520911290 # The number of ROB writes +system.cpu.timesIdled 650 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 68636 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1679312925 # Number of Instructions Simulated +system.cpu.committedOps 1679312925 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.750245 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.750245 # CPI: Total CPI of All Threads +system.cpu.ipc 1.332898 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.332898 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3307128958 # number of integer regfile reads +system.cpu.int_regfile_writes 1925697564 # number of integer regfile writes +system.cpu.fp_regfile_reads 36300 # number of floating regfile reads +system.cpu.fp_regfile_writes 615 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9207202 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.451175 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 712346624 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9211298 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 77.334011 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5127954500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.451175 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997913 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997913 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 8606834 # number of replacements +system.cpu.dcache.tags.tagsinuse 4086.896222 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 685926884 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 8610930 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 79.657701 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5135502500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4086.896222 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997777 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997777 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 699 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2968 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 950 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2966 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 55 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 11 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1470154674 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1470154674 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 556848448 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 556848448 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155498172 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155498172 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1415363302 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1415363302 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 536911304 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 536911304 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 149015576 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 149015576 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 712346620 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 712346620 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 712346620 # number of overall hits -system.cpu.dcache.overall_hits::total 712346620 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12894733 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12894733 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5230330 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5230330 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 685926880 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 685926880 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 685926880 # number of overall hits +system.cpu.dcache.overall_hits::total 685926880 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12326597 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12326597 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5122704 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5122704 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 18125063 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 18125063 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 18125063 # number of overall misses -system.cpu.dcache.overall_misses::total 18125063 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 412093066500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 412093066500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 315139193599 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 315139193599 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 85500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 85500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 727232260099 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 727232260099 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 727232260099 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 727232260099 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 569743181 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 569743181 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17449301 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17449301 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17449301 # number of overall misses +system.cpu.dcache.overall_misses::total 17449301 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 397459380500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 397459380500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 314315569058 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 314315569058 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 73500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 73500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 711774949558 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 711774949558 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 711774949558 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 711774949558 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 549237901 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 549237901 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 154138280 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 154138280 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 730471683 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 730471683 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 730471683 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 730471683 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022633 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022633 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032541 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032541 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 703376181 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 703376181 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 703376181 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 703376181 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022443 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022443 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.033234 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.033234 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024813 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024813 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.024813 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.024813 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31958.247332 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31958.247332 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60252.258194 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60252.258194 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40123.019716 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40123.019716 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40123.019716 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40123.019716 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15672953 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 9573691 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1104455 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 68040 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.190667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 140.706805 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3727750 # number of writebacks -system.cpu.dcache.writebacks::total 3727750 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5562625 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5562625 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3351141 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3351141 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 8913766 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 8913766 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 8913766 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 8913766 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7332108 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7332108 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879189 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1879189 # number of WriteReq MSHR misses +system.cpu.dcache.demand_miss_rate::cpu.data 0.024808 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024808 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.024808 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.024808 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32244.047607 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32244.047607 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61357.355228 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61357.355228 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 73500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 73500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40791.029369 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40791.029369 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40791.029369 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40791.029369 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 16026921 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 9753373 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1104089 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 68174 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.515968 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 143.065876 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 3596228 # number of writebacks +system.cpu.dcache.writebacks::total 3596228 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5571741 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5571741 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3266630 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3266630 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 8838371 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 8838371 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 8838371 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 8838371 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 6754856 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 6754856 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1856074 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1856074 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9211297 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9211297 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9211297 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9211297 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 182971511500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 182971511500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84313777567 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84313777567 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 84500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 84500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 267285289067 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 267285289067 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 267285289067 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 267285289067 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012869 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012869 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011692 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 8610930 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 8610930 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 8610930 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 8610930 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 164940989000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 164940989000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84797281851 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84797281851 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 72500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 72500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 249738270851 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 249738270851 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 249738270851 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 249738270851 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012299 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012299 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.012042 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.012042 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012610 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012610 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012610 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012610 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24954.830384 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24954.830384 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44867.108932 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44867.108932 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 84500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 84500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.117684 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.117684 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.117684 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.117684 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 753.790798 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 420611422 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 949 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 443215.407798 # Average number of references to valid blocks. +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012242 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012242 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012242 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012242 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24418.135487 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24418.135487 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45686.369105 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45686.369105 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 72500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 72500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29002.473699 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29002.473699 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29002.473699 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29002.473699 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 744.964371 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 399073789 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 883 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 451952.195923 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 753.790798 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.368062 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.368062 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 948 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 882 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.462891 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 841226771 # Number of tag accesses -system.cpu.icache.tags.data_accesses 841226771 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 420611422 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 420611422 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 420611422 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 420611422 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 420611422 # number of overall hits -system.cpu.icache.overall_hits::total 420611422 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1489 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1489 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1489 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1489 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1489 # number of overall misses -system.cpu.icache.overall_misses::total 1489 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 114620499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 114620499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 114620499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 114620499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 114620499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 114620499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 420612911 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 420612911 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 420612911 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 420612911 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 420612911 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 420612911 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # 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number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 399073789 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 399073789 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 399073789 # number of overall hits +system.cpu.icache.overall_hits::total 399073789 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1377 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1377 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1377 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1377 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1377 # number of overall misses +system.cpu.icache.overall_misses::total 1377 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 106712499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 106712499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 106712499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 106712499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 106712499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 106712499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 399075166 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 399075166 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 399075166 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 399075166 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 399075166 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 399075166 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77496.368192 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77496.368192 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77496.368192 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77496.368192 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77496.368192 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77496.368192 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 390 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 68.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 130 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1 # number of writebacks -system.cpu.icache.writebacks::total 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 540 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 540 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 540 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 540 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 540 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 540 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 949 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 949 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 949 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 949 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 949 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 949 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 79774499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 79774499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 79774499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 79774499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 79774499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 79774499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 494 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 494 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 494 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 494 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 494 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 494 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 883 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 883 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 883 # 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mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84061.642782 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84061.642782 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84061.642782 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 84061.642782 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84061.642782 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 84061.642782 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1929018 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31408.626842 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 14580161 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1958805 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.443396 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 28140218000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14352.619403 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.692409 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 17030.315030 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.438007 # 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Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3727750 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3727750 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1106786 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1106786 # number of ReadExReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6143738 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6143738 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.data 7250524 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7250524 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7250524 # 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number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7332093 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7332093 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 949 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9211298 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9212247 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 949 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9211298 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9212247 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411035 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.411035 # miss rate for ReadExReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 85009.625142 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4200 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 22514 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5526 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 139563701 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 139563701 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 3596228 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3596228 # number of WritebackDirty hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1089344 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1089344 # number of ReadExReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5708271 # 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average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 89669.259116 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82552.687039 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89672.703483 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 89669.259116 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.210583 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.210664 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91318.006638 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91318.006638 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83501.698754 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83501.698754 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89770.039969 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89770.039969 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83501.698754 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90424.584297 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 90421.214817 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83501.698754 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90424.584297 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 90421.214817 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1024304 # number of writebacks -system.cpu.l2cache.writebacks::total 1024304 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 240 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 240 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 772419 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 772419 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 949 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 949 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1188355 # 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number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 164 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 164 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 766745 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 766745 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 883 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 883 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1046571 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1046571 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 883 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1813316 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1814199 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 145835185500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 145900087500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64902000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 145835185500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 145900087500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411035 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411035 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413097 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413097 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162076 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162076 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.154936 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.154936 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.212866 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.212947 # 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average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79631.695495 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72552.687039 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79672.703483 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79669.259116 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72552.687039 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79672.703483 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79669.259116 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18419450 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9207203 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.210583 # 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average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80421.214817 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73501.698754 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80424.584297 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80421.214817 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 17218648 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 8606834 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1275 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1275 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1383 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1383 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7333042 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4752054 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6384166 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1879205 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1879205 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 949 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7332093 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1899 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27629798 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27631697 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 60800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 828099072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 828159872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1929018 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 65555456 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11141265 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000114 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.010697 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 6755724 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4623913 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 5764670 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1856089 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1856089 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 883 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6754842 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1766 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 25828695 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 25830461 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 781258112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 781314624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1781749 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 65771840 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 10393563 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000133 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.011535 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11139990 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1275 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 10392180 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1383 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11141265 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12937476000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 10393563 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12205552000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1423999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1324500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13816947000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 12916395000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1189304 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1024304 # Transaction distribution -system.membus.trans_dist::CleanEvict 903679 # Transaction distribution -system.membus.trans_dist::ReadExReq 772419 # Transaction distribution -system.membus.trans_dist::ReadExResp 772419 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1189304 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5851429 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5851429 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191105728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 191105728 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 3594729 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1780530 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 629947889500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1047454 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1027685 # Transaction distribution +system.membus.trans_dist::CleanEvict 752845 # Transaction distribution +system.membus.trans_dist::ReadExReq 766745 # Transaction distribution +system.membus.trans_dist::ReadExResp 766745 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1047454 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5408928 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5408928 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 181880576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 181880576 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3889706 # Request fanout histogram +system.membus.snoop_fanout::samples 1814199 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3889706 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1814199 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3889706 # Request fanout histogram -system.membus.reqLayer0.occupancy 8475680000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1814199 # Request fanout histogram +system.membus.reqLayer0.occupancy 8122837000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 10684396000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 9853981000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index 9e88e1d85..5f8a25a7f 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.913189 # Nu sim_ticks 913189263000 # Number of ticks simulated final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2010513 # Simulator instruction rate (inst/s) -host_op_rate 2010513 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1008901575 # Simulator tick rate (ticks/s) -host_mem_usage 239516 # Number of bytes of host memory used -host_seconds 905.13 # Real time elapsed on the host +host_inst_rate 1729437 # Simulator instruction rate (inst/s) +host_op_rate 1729437 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 867853739 # Simulator tick rate (ticks/s) +host_mem_usage 243124 # Number of bytes of host memory used +host_seconds 1052.24 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -130,6 +130,12 @@ system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1826378509 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 2270974172 # Transaction distribution system.membus.trans_dist::ReadResp 2270974172 # Transaction distribution @@ -144,14 +150,14 @@ system.membus.pkt_size::total 10108087278 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 2431702674 # Request fanout histogram -system.membus.snoop_fanout::mean 0.751070 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.432393 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 605324165 24.89% 24.89% # Request fanout histogram -system.membus.snoop_fanout::1 1826378509 75.11% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2431702674 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 2431702674 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 6bd6eda32..622e92943 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.636720 # Number of seconds simulated -sim_ticks 2636719559500 # Number of ticks simulated -final_tick 2636719559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.639614 # Number of seconds simulated +sim_ticks 2639613874500 # Number of ticks simulated +final_tick 2639613874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1223384 # Simulator instruction rate (inst/s) -host_op_rate 1223384 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1772587765 # Simulator tick rate (ticks/s) -host_mem_usage 249508 # Number of bytes of host memory used -host_seconds 1487.50 # Real time elapsed on the host +host_inst_rate 1111155 # Simulator instruction rate (inst/s) +host_op_rate 1111155 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1611744129 # Simulator tick rate (ticks/s) +host_mem_usage 254908 # Number of bytes of host memory used +host_seconds 1637.74 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124892160 # Number of bytes read from this memory -system.physmem.bytes_read::total 124943488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 126106432 # Number of bytes read from this memory +system.physmem.bytes_read::total 126157760 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 51328 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 51328 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65405568 # Number of bytes written to this memory -system.physmem.bytes_written::total 65405568 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 66087296 # Number of bytes written to this memory +system.physmem.bytes_written::total 66087296 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 802 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1951440 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1952242 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1021962 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1021962 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19467 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47366494 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47385960 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19467 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19467 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 24805660 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 24805660 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 24805660 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19467 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47366494 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 72191620 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states +system.physmem.num_reads::cpu.data 1970413 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1971215 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1032614 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1032614 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19445 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47774575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47794021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19445 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19445 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 25036729 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 25036729 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 25036729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19445 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47774575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 72830749 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -72,8 +72,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 2636719559500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5273439119 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 2639613874500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 5279227749 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1819780127 # Number of instructions committed @@ -92,7 +92,7 @@ system.cpu.num_mem_refs 611922547 # nu system.cpu.num_load_insts 449492741 # Number of load instructions system.cpu.num_store_insts 162429806 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5273439119 # Number of busy cycles +system.cpu.num_busy_cycles 5279227749 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 214632552 # Number of branches fetched @@ -131,26 +131,26 @@ system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1826378509 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9107638 # number of replacements -system.cpu.dcache.tags.tagsinuse 4079.293901 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4079.303630 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 41036287500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4079.293901 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995921 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995921 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 41048093500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4079.303630 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995924 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995924 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1197 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2638 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1191 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2646 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 206 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits @@ -167,14 +167,14 @@ system.cpu.dcache.demand_misses::cpu.data 9111734 # n system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses system.cpu.dcache.overall_misses::total 9111734 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 151181633000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 151181633000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 62898029000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 62898029000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 214079662000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 214079662000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 214079662000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 214079662000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 152711735000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 152711735000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 64261460000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 64261460000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 216973195000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 216973195000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 216973195000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 216973195000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -191,22 +191,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20932.285660 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20932.285660 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33291.358266 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33291.358266 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23494.942017 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23494.942017 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23494.942017 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23494.942017 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21144.140311 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21144.140311 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34013.009972 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34013.009972 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23812.503196 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23812.503196 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23812.503196 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23812.503196 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3679426 # number of writebacks -system.cpu.dcache.writebacks::total 3679426 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3664823 # number of writebacks +system.cpu.dcache.writebacks::total 3664823 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses @@ -215,14 +215,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 143959219000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 143959219000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61008709000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 61008709000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204967928000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 204967928000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204967928000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 204967928000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145489321000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 145489321000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62372140000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 62372140000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207861461000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 207861461000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207861461000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 207861461000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses @@ -231,24 +231,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19932.285660 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19932.285660 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32291.358266 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32291.358266 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20144.140311 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20144.140311 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33013.009972 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33013.009972 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22812.503196 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22812.503196 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22812.503196 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22812.503196 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 612.605858 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 612.633318 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 612.605858 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.299124 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.299124 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 612.633318 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.299137 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.299137 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id @@ -256,7 +256,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 730 system.cpu.icache.tags.occ_task_id_percent::1024 0.391113 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 3652757822 # Number of tag accesses system.cpu.icache.tags.data_accesses 3652757822 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits @@ -269,12 +269,12 @@ system.cpu.icache.demand_misses::cpu.inst 802 # n system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 49759500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 49759500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 49759500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 49759500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 49759500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 49759500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 50541500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 50541500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 50541500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 50541500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 50541500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 50541500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses @@ -287,12 +287,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62044.264339 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62044.264339 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62044.264339 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62044.264339 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62044.264339 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62044.264339 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63019.326683 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63019.326683 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63019.326683 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63019.326683 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63019.326683 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63019.326683 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -307,86 +307,86 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802 system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 48957500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 48957500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 48957500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 48957500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 48957500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 48957500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49739500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 49739500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49739500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 49739500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49739500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 49739500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61044.264339 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61044.264339 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61044.264339 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61044.264339 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1919525 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30540.825713 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 14380256 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1949317 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.377074 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 218471945000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15091.675189 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 38.824340 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15410.326183 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.460561 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001185 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.470286 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.932032 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29792 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1058 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1255 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27302 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909180 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 149600037 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 149600037 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3679426 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3679426 # number of WritebackDirty hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62019.326683 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62019.326683 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62019.326683 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62019.326683 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62019.326683 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62019.326683 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 1938767 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31260.683710 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 16248398 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1971535 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 8.241496 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 217871689000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 8.109026 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 38.419408 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31214.155276 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000247 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001172 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.952580 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.954000 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 664 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2920 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1281 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27794 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 147732935 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 147732935 # 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miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161865 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161865 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162883 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162883 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.214168 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214237 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.216250 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.216319 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.374326 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216250 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.216319 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50509.975062 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50509.975062 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.002550 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.002550 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50509.975062 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.001523 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.005580 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50509.975062 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.001523 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.005580 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 18220175 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9107639 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1122 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1122 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1292 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1292 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4701388 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4697437 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6325775 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6348968 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution @@ -504,53 +504,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27331106 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 27332711 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818634240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 818685632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1919525 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 65405568 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11032061 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000102 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.010084 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 817699648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 817751040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1938767 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 66087296 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11051303 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000117 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.010812 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11030939 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1122 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11050011 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1292 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11032061 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12789514500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11051303 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12774911500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1169857 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1021962 # Transaction distribution -system.membus.trans_dist::CleanEvict 896683 # Transaction distribution -system.membus.trans_dist::ReadExReq 782385 # Transaction distribution -system.membus.trans_dist::ReadExResp 782385 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1169857 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5823129 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5823129 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190349056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190349056 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 3908932 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1937717 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1177209 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1032614 # Transaction distribution +system.membus.trans_dist::CleanEvict 905103 # Transaction distribution +system.membus.trans_dist::ReadExReq 794006 # Transaction distribution +system.membus.trans_dist::ReadExResp 794006 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1177209 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5880147 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5880147 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192245056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 192245056 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3870887 # Request fanout histogram +system.membus.snoop_fanout::samples 1971215 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3870887 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1971215 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3870887 # Request fanout histogram -system.membus.reqLayer0.occupancy 7958742500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1971215 # Request fanout histogram +system.membus.reqLayer0.occupancy 8039396000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 9761210000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 9856075000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index a63511156..ddbab1eb8 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.128034 # Number of seconds simulated -sim_ticks 1128033563500 # Number of ticks simulated -final_tick 1128033563500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.130744 # Number of seconds simulated +sim_ticks 1130744162500 # Number of ticks simulated +final_tick 1130744162500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 296898 # Simulator instruction rate (inst/s) -host_op_rate 319862 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 216832014 # Simulator tick rate (ticks/s) -host_mem_usage 266856 # Number of bytes of host memory used -host_seconds 5202.34 # Real time elapsed on the host +host_inst_rate 210155 # Simulator instruction rate (inst/s) +host_op_rate 226410 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 153850224 # Simulator tick rate (ticks/s) +host_mem_usage 274312 # Number of bytes of host memory used +host_seconds 7349.64 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 130888128 # Number of bytes read from this memory -system.physmem.bytes_read::total 130938240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67194432 # Number of bytes written to this memory -system.physmem.bytes_written::total 67194432 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2045127 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2045910 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1049913 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1049913 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 44424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 116032122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 116076546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 44424 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 44424 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 59567759 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 59567759 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 59567759 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 44424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 116032122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 175644306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2045910 # Number of read requests accepted -system.physmem.writeReqs 1049913 # Number of write requests accepted -system.physmem.readBursts 2045910 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1049913 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 130851840 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 86400 # Total number of bytes read from write queue -system.physmem.bytesWritten 67192960 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 130938240 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 67194432 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1350 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 50240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 132094976 # Number of bytes read from this memory +system.physmem.bytes_read::total 132145216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50240 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67850112 # Number of bytes written to this memory +system.physmem.bytes_written::total 67850112 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 785 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2063984 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2064769 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1060158 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1060158 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 44431 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 116821276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 116865707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 44431 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 44431 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 60004831 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 60004831 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 60004831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 44431 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 116821276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 176870538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2064769 # Number of read requests accepted +system.physmem.writeReqs 1060158 # Number of write requests accepted +system.physmem.readBursts 2064769 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1060158 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 132060352 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 84864 # Total number of bytes read from write queue +system.physmem.bytesWritten 67848640 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132145216 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 67850112 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1326 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 127234 # Per bank write bursts -system.physmem.perBankRdBursts::1 124635 # Per bank write bursts -system.physmem.perBankRdBursts::2 121565 # Per bank write bursts -system.physmem.perBankRdBursts::3 123578 # Per bank write bursts -system.physmem.perBankRdBursts::4 122544 # Per bank write bursts -system.physmem.perBankRdBursts::5 122632 # Per bank write bursts -system.physmem.perBankRdBursts::6 123221 # Per bank write bursts -system.physmem.perBankRdBursts::7 123735 # Per bank write bursts -system.physmem.perBankRdBursts::8 131340 # Per bank write bursts -system.physmem.perBankRdBursts::9 133478 # Per bank write bursts -system.physmem.perBankRdBursts::10 132036 # Per bank write bursts -system.physmem.perBankRdBursts::11 133242 # Per bank write bursts -system.physmem.perBankRdBursts::12 133211 # Per bank write bursts -system.physmem.perBankRdBursts::13 133326 # Per bank write bursts -system.physmem.perBankRdBursts::14 129274 # Per bank write bursts -system.physmem.perBankRdBursts::15 129509 # Per bank write bursts -system.physmem.perBankWrBursts::0 66120 # Per bank write bursts -system.physmem.perBankWrBursts::1 64398 # Per bank write bursts -system.physmem.perBankWrBursts::2 62563 # Per bank write bursts -system.physmem.perBankWrBursts::3 62980 # Per bank write bursts -system.physmem.perBankWrBursts::4 62981 # Per bank write bursts -system.physmem.perBankWrBursts::5 63086 # Per bank write bursts -system.physmem.perBankWrBursts::6 64437 # Per bank write bursts -system.physmem.perBankWrBursts::7 65431 # Per bank write bursts -system.physmem.perBankWrBursts::8 67296 # Per bank write bursts -system.physmem.perBankWrBursts::9 67792 # Per bank write bursts -system.physmem.perBankWrBursts::10 67535 # Per bank write bursts -system.physmem.perBankWrBursts::11 67858 # Per bank write bursts -system.physmem.perBankWrBursts::12 67312 # Per bank write bursts -system.physmem.perBankWrBursts::13 67784 # Per bank write bursts -system.physmem.perBankWrBursts::14 66474 # Per bank write bursts -system.physmem.perBankWrBursts::15 65843 # Per bank write bursts +system.physmem.perBankRdBursts::0 128520 # Per bank write bursts +system.physmem.perBankRdBursts::1 125806 # Per bank write bursts +system.physmem.perBankRdBursts::2 122672 # Per bank write bursts +system.physmem.perBankRdBursts::3 124571 # Per bank write bursts +system.physmem.perBankRdBursts::4 123572 # Per bank write bursts +system.physmem.perBankRdBursts::5 123679 # Per bank write bursts +system.physmem.perBankRdBursts::6 124365 # Per bank write bursts +system.physmem.perBankRdBursts::7 124958 # Per bank write bursts +system.physmem.perBankRdBursts::8 132489 # Per bank write bursts +system.physmem.perBankRdBursts::9 134780 # Per bank write bursts +system.physmem.perBankRdBursts::10 133233 # Per bank write bursts +system.physmem.perBankRdBursts::11 134506 # Per bank write bursts +system.physmem.perBankRdBursts::12 134518 # Per bank write bursts +system.physmem.perBankRdBursts::13 134594 # Per bank write bursts +system.physmem.perBankRdBursts::14 130540 # Per bank write bursts +system.physmem.perBankRdBursts::15 130640 # Per bank write bursts +system.physmem.perBankWrBursts::0 66781 # Per bank write bursts +system.physmem.perBankWrBursts::1 64941 # Per bank write bursts +system.physmem.perBankWrBursts::2 63173 # Per bank write bursts +system.physmem.perBankWrBursts::3 63584 # Per bank write bursts +system.physmem.perBankWrBursts::4 63558 # Per bank write bursts +system.physmem.perBankWrBursts::5 63644 # Per bank write bursts +system.physmem.perBankWrBursts::6 65047 # Per bank write bursts +system.physmem.perBankWrBursts::7 66055 # Per bank write bursts +system.physmem.perBankWrBursts::8 67972 # Per bank write bursts +system.physmem.perBankWrBursts::9 68438 # Per bank write bursts +system.physmem.perBankWrBursts::10 68161 # Per bank write bursts +system.physmem.perBankWrBursts::11 68586 # Per bank write bursts +system.physmem.perBankWrBursts::12 68040 # Per bank write bursts +system.physmem.perBankWrBursts::13 68530 # Per bank write bursts +system.physmem.perBankWrBursts::14 67159 # Per bank write bursts +system.physmem.perBankWrBursts::15 66466 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1128033469500 # Total gap between requests +system.physmem.totGap 1130744067500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2045910 # Read request sizes (log2) +system.physmem.readPktSize::6 2064769 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1049913 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1917702 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 126844 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1060158 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1931837 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 131592 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,27 +145,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 32849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 34013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 61217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 61114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 32506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 62386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 62542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 62618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 62533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 62474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 62468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 62484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 62514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 62444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 62124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 61991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -194,113 +194,111 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1910047 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.685692 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.827100 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.490486 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1485463 77.77% 77.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 305174 15.98% 93.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52509 2.75% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20929 1.10% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13256 0.69% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7619 0.40% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5519 0.29% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5102 0.27% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 14476 0.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1910047 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61113 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.412400 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 159.518866 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 61065 99.92% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 24 0.04% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1925169 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.839212 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.850367 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 126.421931 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1496084 77.71% 77.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 309482 16.08% 93.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52255 2.71% 96.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20716 1.08% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12793 0.66% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7748 0.40% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5753 0.30% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5054 0.26% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15284 0.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1925169 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61990 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.244314 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 23.928422 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 148.698604 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 61952 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 16 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 5 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61113 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61113 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.179487 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.144319 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.100540 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 26981 44.15% 44.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1028 1.68% 45.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 28814 47.15% 92.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3825 6.26% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 400 0.65% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 47 0.08% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 11 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 6 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61113 # Writes before turning the bus around for reads -system.physmem.totQLat 38097515250 # Total ticks spent queuing -system.physmem.totMemAccLat 76433015250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10222800000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18633.60 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::17408-18431 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 61990 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61990 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.101710 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.070337 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.034747 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 28322 45.69% 45.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1015 1.64% 47.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 30732 49.58% 96.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1873 3.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 43 0.07% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 61990 # Writes before turning the bus around for reads +system.physmem.totQLat 38536102500 # Total ticks spent queuing +system.physmem.totMemAccLat 77225658750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10317215000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18675.63 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37383.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 116.00 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 59.57 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 116.08 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 59.57 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37425.63 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 116.79 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 60.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 116.87 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 60.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.37 # Data bus utilization in percentage +system.physmem.busUtil 1.38 # Data bus utilization in percentage system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing -system.physmem.readRowHits 772369 # Number of row buffer hits during reads -system.physmem.writeRowHits 412032 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.78 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.24 # Row buffer hit rate for writes -system.physmem.avgGap 364372.73 # Average gap between requests -system.physmem.pageHitRate 38.27 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7040703600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3841653750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7715315400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3317734080 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 73677630000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 423036881190 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 305734953750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 824364871770 # Total energy per rank (pJ) -system.physmem_0.averagePower 730.798394 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 505893058250 # Time in different power states -system.physmem_0.memoryStateTime::REF 37667500000 # Time in different power states +system.physmem.avgWrQLen 25.42 # Average write queue length when enqueuing +system.physmem.readRowHits 775929 # Number of row buffer hits during reads +system.physmem.writeRowHits 422476 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.85 # Row buffer hit rate for writes +system.physmem.avgGap 361846.55 # Average gap between requests +system.physmem.pageHitRate 38.37 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7091695800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3869476875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7785421800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3348753840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 73854608880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 423921506085 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 306584736000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 826456199280 # Total energy per rank (pJ) +system.physmem_0.averagePower 730.896688 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 507283799000 # Time in different power states +system.physmem_0.memoryStateTime::REF 37757980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 584472684250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 585701078500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7399251720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4037290125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 8232221400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3485553120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 73677630000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 432494110575 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 297439138500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 826765195440 # Total energy per rank (pJ) -system.physmem_1.averagePower 732.926278 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 492041493250 # Time in different power states -system.physmem_1.memoryStateTime::REF 37667500000 # Time in different power states +system.physmem_1.actEnergy 7462581840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4071845250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 8309316600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3520920960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 73854608880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 432965070225 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 298651785000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 828836128755 # Total energy per rank (pJ) +system.physmem_1.averagePower 733.001436 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 494051909000 # Time in different power states +system.physmem_1.memoryStateTime::REF 37757980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 598324400250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 598934101500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 240019627 # Number of BP lookups -system.cpu.branchPred.condPredicted 186610234 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 240019432 # Number of BP lookups +system.cpu.branchPred.condPredicted 186610009 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 14528957 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 131647639 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122324320 # Number of BTB hits +system.cpu.branchPred.BTBLookups 131647101 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122324380 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.917975 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15657430 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 92.918400 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15657431 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 534 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 535 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 232 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 302 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 303 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 162 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +328,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +358,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -390,7 +388,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -421,16 +419,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1128033563500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2256067127 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2261488325 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 41363716 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 41363718 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.460651 # CPI: cycles per instruction -system.cpu.ipc 0.684626 # IPC: instructions per cycle +system.cpu.cpi 1.464161 # CPI: cycles per instruction +system.cpu.ipc 0.682985 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction @@ -466,61 +464,61 @@ system.cpu.op_class_0::MemWrite 174847046 10.51% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 1664032481 # Class of committed instruction -system.cpu.tickCycles 1844612574 # Number of cycles that the object actually ticked -system.cpu.idleCycles 411454553 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9220101 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.702912 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624495427 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9224197 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.701874 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 9818932500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.702912 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997486 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997486 # Average percentage of cache occupancy +system.cpu.tickCycles 1844743027 # Number of cycles that the object actually ticked +system.cpu.idleCycles 416745298 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 9220102 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.712457 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624495296 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9224198 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.701853 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 9823555500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.712457 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997488 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997488 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 241 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1240 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 62 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1231 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1277391791 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1277391791 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 454164210 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 454164210 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170331094 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170331094 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1277391740 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1277391740 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 454164183 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 454164183 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170330990 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170330990 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624495304 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624495304 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624495305 # number of overall hits -system.cpu.dcache.overall_hits::total 624495305 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7333415 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7333415 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2254953 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2254953 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 624495173 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624495173 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624495174 # number of overall hits +system.cpu.dcache.overall_hits::total 624495174 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7333416 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7333416 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2255057 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2255057 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9588368 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9588368 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9588370 # number of overall misses -system.cpu.dcache.overall_misses::total 9588370 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 190988166000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 190988166000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 108977258000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 108977258000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 299965424000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 299965424000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 299965424000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 299965424000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461497625 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461497625 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9588473 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9588473 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9588475 # number of overall misses +system.cpu.dcache.overall_misses::total 9588475 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 192638967000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 192638967000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 111261397000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 111261397000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 303900364000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 303900364000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 303900364000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 303900364000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461497599 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461497599 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -529,10 +527,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 634083672 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 634083672 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 634083675 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 634083675 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 634083646 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 634083646 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 634083649 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 634083649 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015890 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015890 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses @@ -543,50 +541,50 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015122 system.cpu.dcache.demand_miss_rate::total 0.015122 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015122 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015122 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26043.550788 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26043.550788 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48327.950960 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48327.950960 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31284.304482 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31284.304482 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31284.297957 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31284.297957 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26268.653926 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26268.653926 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49338.618492 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 49338.618492 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31694.344240 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31694.344240 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31694.337629 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31694.337629 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3684499 # number of writebacks -system.cpu.dcache.writebacks::total 3684499 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3670051 # number of writebacks +system.cpu.dcache.writebacks::total 3670051 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364123 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 364123 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 364172 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 364172 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 364172 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 364172 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333366 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7333366 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364227 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 364227 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 364276 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 364276 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 364276 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 364276 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333367 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7333367 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890830 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1890830 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9224196 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9224196 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9224197 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9224197 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183652478000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 183652478000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84692070000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84692070000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 74000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 74000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268344548000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 268344548000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268344622000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 268344622000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9224197 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9224197 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9224198 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9224198 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 185303496000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 185303496000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86626211500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 86626211500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 75000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 75000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 271929707500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 271929707500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 271929782500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 271929782500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses @@ -597,338 +595,344 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014547 system.cpu.dcache.demand_mshr_miss_rate::total 0.014547 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25043.408170 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25043.408170 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44790.948948 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44790.948948 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29091.375335 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29091.375335 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29091.380204 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29091.380204 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 30 # number of replacements -system.cpu.icache.tags.tagsinuse 660.287317 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 466254411 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 819 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 569297.205128 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25268.542540 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25268.542540 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45813.855027 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45813.855027 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 75000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 75000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29480.041189 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29480.041189 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29480.046124 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29480.046124 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 33 # number of replacements +system.cpu.icache.tags.tagsinuse 660.343836 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 466264831 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 822 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 567232.154501 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 660.287317 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.322406 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.322406 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 660.343836 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.322434 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.322434 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 752 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 751 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.385254 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 932511279 # Number of tag accesses -system.cpu.icache.tags.data_accesses 932511279 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 466254411 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 466254411 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 466254411 # 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number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 61690000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 61690000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 466255230 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 466255230 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 466255230 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 466255230 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 466255230 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 466255230 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 932532128 # Number of tag accesses +system.cpu.icache.tags.data_accesses 932532128 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 466264831 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 466264831 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 466264831 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 466264831 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 466264831 # number of overall hits +system.cpu.icache.overall_hits::total 466264831 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 822 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 822 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 822 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 822 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 822 # number of overall misses +system.cpu.icache.overall_misses::total 822 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62977000 # 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number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75323.565324 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75323.565324 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75323.565324 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75323.565324 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75323.565324 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75323.565324 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76614.355231 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76614.355231 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76614.355231 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76614.355231 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76614.355231 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76614.355231 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 30 # number of writebacks -system.cpu.icache.writebacks::total 30 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 819 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 819 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 819 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 819 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 819 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 819 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 60871000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 60871000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 60871000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 60871000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60871000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 60871000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 33 # number of writebacks +system.cpu.icache.writebacks::total 33 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 822 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 822 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 822 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 822 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 822 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 822 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62155000 # 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mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74323.565324 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74323.565324 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74323.565324 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74323.565324 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74323.565324 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74323.565324 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 2013239 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31266.385554 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 14508014 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2043015 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.101276 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 59831992000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14855.828649 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.313947 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16384.242958 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.453364 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000803 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.500007 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.954174 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1246 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12853 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15553 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 151482269 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 151482269 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3684499 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3684499 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 30 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 30 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1089818 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1089818 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 36 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6089246 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6089246 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 36 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7179064 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7179100 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 36 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7179064 # number of overall hits -system.cpu.l2cache.overall_hits::total 7179100 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 801012 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75614.355231 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 2032337 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31884.361365 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 16378235 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2065105 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.930945 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 54418076000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 10.408988 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.813492 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31848.138885 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000318 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000788 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.971928 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.973033 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 912 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2876 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7195 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21737 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 149613593 # 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mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423630 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.956044 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.169651 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.169651 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.221713 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.221778 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221713 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.221778 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77875.455049 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77875.455049 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65647.509579 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65647.509579 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77380.803222 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77380.803222 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65647.509579 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77574.542803 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77569.978152 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65647.509579 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77574.542803 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77569.978152 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18445147 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220143 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429612 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.429612 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954988 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.170680 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.170680 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223758 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.223823 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223758 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.223823 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79177.093746 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79177.093746 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67071.337580 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67071.337580 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78236.520701 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78236.520701 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67071.337580 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78606.702862 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78602.317257 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67071.337580 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78606.702862 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78602.317257 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18445155 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220147 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1285 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1279 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1445 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1439 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7334186 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4734412 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 30 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6498928 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 7334190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4730209 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6522230 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1890830 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1890830 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 819 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333367 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1668 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668495 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27670163 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826156544 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 826210880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2013239 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 67194432 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11238255 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000258 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.016087 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 822 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333368 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1677 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668498 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27670175 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825231936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 825286656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2032337 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 67850112 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11257357 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000272 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.016509 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11235364 99.97% 99.97% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2885 0.03% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11254306 99.97% 99.97% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3045 0.03% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11238255 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12907102500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11257357 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12892661500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1228500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1233000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13836298494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13836299994 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1244898 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1049913 # Transaction distribution -system.membus.trans_dist::CleanEvict 962255 # Transaction distribution -system.membus.trans_dist::ReadExReq 801012 # Transaction distribution -system.membus.trans_dist::ReadExResp 801012 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1244898 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6103988 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6103988 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198132672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 198132672 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 4095876 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2031264 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1252445 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1060158 # Transaction distribution +system.membus.trans_dist::CleanEvict 970949 # Transaction distribution +system.membus.trans_dist::ReadExReq 812324 # Transaction distribution +system.membus.trans_dist::ReadExResp 812324 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1252445 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6160645 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6160645 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 199995328 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 199995328 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 4058078 # Request fanout histogram +system.membus.snoop_fanout::samples 2064769 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4058078 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2064769 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4058078 # Request fanout histogram -system.membus.reqLayer0.occupancy 8755432500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2064769 # Request fanout histogram +system.membus.reqLayer0.occupancy 8803577000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 11187827500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11289358000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 3edaccc65..4f03996ba 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.767804 # Number of seconds simulated -sim_ticks 767803843500 # Number of ticks simulated -final_tick 767803843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.770752 # Number of seconds simulated +sim_ticks 770752376500 # Number of ticks simulated +final_tick 770752376500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 212750 # Simulator instruction rate (inst/s) -host_op_rate 229206 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 105758139 # Simulator tick rate (ticks/s) -host_mem_usage 308972 # Number of bytes of host memory used -host_seconds 7260.00 # Real time elapsed on the host +host_inst_rate 147248 # Simulator instruction rate (inst/s) +host_op_rate 158637 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73478006 # Simulator tick rate (ticks/s) +host_mem_usage 329736 # Number of bytes of host memory used +host_seconds 10489.57 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 235320384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63711040 # Number of bytes read from this memory -system.physmem.bytes_read::total 299096640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104697344 # Number of bytes written to this memory -system.physmem.bytes_written::total 104697344 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1019 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3676881 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 995485 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4673385 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1635896 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1635896 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 84938 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 306485030 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 82978277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 389548245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 84938 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 84938 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 136359495 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 136359495 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 136359495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 84938 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 306485030 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 82978277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 525907740 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4673385 # Number of read requests accepted -system.physmem.writeReqs 1635896 # Number of write requests accepted -system.physmem.readBursts 4673385 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1635896 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 298598336 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 498304 # Total number of bytes read from write queue -system.physmem.bytesWritten 104693696 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 299096640 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104697344 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7786 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 65664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 236002624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63781504 # Number of bytes read from this memory +system.physmem.bytes_read::total 299849792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65664 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104607936 # Number of bytes written to this memory +system.physmem.bytes_written::total 104607936 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1026 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3687541 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 996586 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4685153 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1634499 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1634499 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 85195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 306197725 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 82752264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 389035183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 85195 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 85195 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 135721847 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 135721847 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 135721847 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 85195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 306197725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 82752264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 524757030 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4685154 # Number of read requests accepted +system.physmem.writeReqs 1634499 # Number of write requests accepted +system.physmem.readBursts 4685154 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1634499 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 299347712 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 502144 # Total number of bytes read from write queue +system.physmem.bytesWritten 104604544 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 299849856 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104607936 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7846 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 26 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 301126 # Per bank write bursts -system.physmem.perBankRdBursts::1 298685 # Per bank write bursts -system.physmem.perBankRdBursts::2 284250 # Per bank write bursts -system.physmem.perBankRdBursts::3 287696 # Per bank write bursts -system.physmem.perBankRdBursts::4 287908 # Per bank write bursts -system.physmem.perBankRdBursts::5 285921 # Per bank write bursts -system.physmem.perBankRdBursts::6 280645 # Per bank write bursts -system.physmem.perBankRdBursts::7 277366 # Per bank write bursts -system.physmem.perBankRdBursts::8 293768 # Per bank write bursts -system.physmem.perBankRdBursts::9 299240 # Per bank write bursts -system.physmem.perBankRdBursts::10 292091 # Per bank write bursts -system.physmem.perBankRdBursts::11 297828 # Per bank write bursts -system.physmem.perBankRdBursts::12 299005 # Per bank write bursts -system.physmem.perBankRdBursts::13 298032 # Per bank write bursts -system.physmem.perBankRdBursts::14 293386 # Per bank write bursts -system.physmem.perBankRdBursts::15 288652 # Per bank write bursts -system.physmem.perBankWrBursts::0 103980 # Per bank write bursts -system.physmem.perBankWrBursts::1 101811 # Per bank write bursts -system.physmem.perBankWrBursts::2 99205 # Per bank write bursts -system.physmem.perBankWrBursts::3 99712 # Per bank write bursts -system.physmem.perBankWrBursts::4 99000 # Per bank write bursts -system.physmem.perBankWrBursts::5 99026 # Per bank write bursts -system.physmem.perBankWrBursts::6 102693 # Per bank write bursts -system.physmem.perBankWrBursts::7 104157 # Per bank write bursts -system.physmem.perBankWrBursts::8 105172 # Per bank write bursts -system.physmem.perBankWrBursts::9 104159 # Per bank write bursts -system.physmem.perBankWrBursts::10 102137 # Per bank write bursts -system.physmem.perBankWrBursts::11 102620 # Per bank write bursts -system.physmem.perBankWrBursts::12 102863 # Per bank write bursts -system.physmem.perBankWrBursts::13 102594 # Per bank write bursts -system.physmem.perBankWrBursts::14 104213 # Per bank write bursts -system.physmem.perBankWrBursts::15 102497 # Per bank write bursts +system.physmem.perBankRdBursts::0 301314 # Per bank write bursts +system.physmem.perBankRdBursts::1 301808 # Per bank write bursts +system.physmem.perBankRdBursts::2 285079 # Per bank write bursts +system.physmem.perBankRdBursts::3 287721 # Per bank write bursts +system.physmem.perBankRdBursts::4 288732 # Per bank write bursts +system.physmem.perBankRdBursts::5 286480 # Per bank write bursts +system.physmem.perBankRdBursts::6 281880 # Per bank write bursts +system.physmem.perBankRdBursts::7 278193 # Per bank write bursts +system.physmem.perBankRdBursts::8 293719 # Per bank write bursts +system.physmem.perBankRdBursts::9 299847 # Per bank write bursts +system.physmem.perBankRdBursts::10 291529 # Per bank write bursts +system.physmem.perBankRdBursts::11 297903 # Per bank write bursts +system.physmem.perBankRdBursts::12 299405 # Per bank write bursts +system.physmem.perBankRdBursts::13 299387 # Per bank write bursts +system.physmem.perBankRdBursts::14 294305 # Per bank write bursts +system.physmem.perBankRdBursts::15 290006 # Per bank write bursts +system.physmem.perBankWrBursts::0 103629 # Per bank write bursts +system.physmem.perBankWrBursts::1 101748 # Per bank write bursts +system.physmem.perBankWrBursts::2 99222 # Per bank write bursts +system.physmem.perBankWrBursts::3 99944 # Per bank write bursts +system.physmem.perBankWrBursts::4 98990 # Per bank write bursts +system.physmem.perBankWrBursts::5 98822 # Per bank write bursts +system.physmem.perBankWrBursts::6 102440 # Per bank write bursts +system.physmem.perBankWrBursts::7 104048 # Per bank write bursts +system.physmem.perBankWrBursts::8 105134 # Per bank write bursts +system.physmem.perBankWrBursts::9 103994 # Per bank write bursts +system.physmem.perBankWrBursts::10 101818 # Per bank write bursts +system.physmem.perBankWrBursts::11 102570 # Per bank write bursts +system.physmem.perBankWrBursts::12 102850 # Per bank write bursts +system.physmem.perBankWrBursts::13 102376 # Per bank write bursts +system.physmem.perBankWrBursts::14 104237 # Per bank write bursts +system.physmem.perBankWrBursts::15 102624 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 767803802500 # Total gap between requests +system.physmem.totGap 770752366000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4673385 # Read request sizes (log2) +system.physmem.readPktSize::6 4685154 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1635896 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2761676 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1029435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 325938 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 231496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 148985 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 81565 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 37573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 23615 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 17937 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1691 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 802 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1634499 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2776424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1031022 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 327510 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 229431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 146630 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 80164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 37430 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 17710 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 771 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -149,36 +149,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 25842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 28487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 73202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 85102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 100017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 106315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 107141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 108142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 109489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 111392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 111204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 103853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 101152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 100444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 25690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 28168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 56471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 73716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 85142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 100116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 107040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 108147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 109209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 110723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 110766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 103820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 100949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 100270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -198,123 +198,130 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4243508 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 95.037234 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.939445 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 102.771916 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3380789 79.67% 79.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 664864 15.67% 95.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 95298 2.25% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35170 0.83% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22966 0.54% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12163 0.29% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7344 0.17% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5345 0.13% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19569 0.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4243508 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 97753 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.727814 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 100.001834 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 95363 97.56% 97.56% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 1154 1.18% 98.74% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 681 0.70% 99.43% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-1023 412 0.42% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1279 112 0.11% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1535 14 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1791 8 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1792-2047 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-2815 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3328-3583 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3840-4095 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-4351 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 97753 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 97753 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.734412 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.690766 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.259650 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 68350 69.92% 69.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1981 2.03% 71.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18352 18.77% 90.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 5702 5.83% 96.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 2016 2.06% 98.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 741 0.76% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 311 0.32% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 155 0.16% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 75 0.08% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 43 0.04% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 16 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 8 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 97753 # Writes before turning the bus around for reads -system.physmem.totQLat 128478496877 # Total ticks spent queuing -system.physmem.totMemAccLat 215958478127 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23327995000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27537.41 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 4255173 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 94.931559 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.862227 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 102.833954 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3394354 79.77% 79.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 663703 15.60% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 94226 2.21% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35436 0.83% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22765 0.53% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12171 0.29% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7342 0.17% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5345 0.13% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19831 0.47% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4255173 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 97794 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.827914 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 99.473591 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-127 93707 95.82% 95.82% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-255 1671 1.71% 97.53% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-383 768 0.79% 98.31% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::384-511 406 0.42% 98.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-639 365 0.37% 99.10% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::640-767 337 0.34% 99.45% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-895 234 0.24% 99.69% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::896-1023 165 0.17% 99.86% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1151 89 0.09% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1152-1279 24 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1407 12 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1408-1535 4 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1664-1791 3 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2175 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2176-2303 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2304-2431 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2688-2815 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2944-3071 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3456-3583 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-3711 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3968-4095 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 97794 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 97794 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.713152 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.671812 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.223073 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 68724 70.27% 70.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1896 1.94% 72.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18671 19.09% 91.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 5634 5.76% 97.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1729 1.77% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 613 0.63% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 266 0.27% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 147 0.15% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 67 0.07% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 30 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 9 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 6 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 97794 # Writes before turning the bus around for reads +system.physmem.totQLat 128325813562 # Total ticks spent queuing +system.physmem.totMemAccLat 216025338562 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23386540000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27435.83 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46287.41 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 388.90 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 136.35 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 389.55 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 136.36 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46185.83 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 388.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 135.72 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 389.04 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 135.72 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.10 # Data bus utilization in percentage -system.physmem.busUtilRead 3.04 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.07 # Data bus utilization in percentage for writes +system.physmem.busUtil 4.09 # Data bus utilization in percentage +system.physmem.busUtilRead 3.03 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing -system.physmem.readRowHits 1710736 # Number of row buffer hits during reads -system.physmem.writeRowHits 347188 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.86 # Average write queue length when enqueuing +system.physmem.readRowHits 1715091 # Number of row buffer hits during reads +system.physmem.writeRowHits 341475 # Number of row buffer hits during writes system.physmem.readRowHitRate 36.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 21.22 # Row buffer hit rate for writes -system.physmem.avgGap 121694.34 # Average gap between requests -system.physmem.pageHitRate 32.66 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 15941658600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8698325625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 17967846000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5246104320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 50149101600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 414557114310 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 97034832000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 609594982455 # Total energy per rank (pJ) -system.physmem_0.averagePower 793.947771 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 158900831773 # Time in different power states -system.physmem_0.memoryStateTime::REF 25638600000 # Time in different power states +system.physmem.writeRowHitRate 20.89 # Row buffer hit rate for writes +system.physmem.avgGap 121961.18 # Average gap between requests +system.physmem.pageHitRate 32.58 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 15989112720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8724218250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 18025846800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5241069360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 50341337280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 417928675995 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 95843265750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 612093526155 # Total energy per rank (pJ) +system.physmem_0.averagePower 794.157652 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 156909498029 # Time in different power states +system.physmem_0.memoryStateTime::REF 25736880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 583262954477 # Time in different power states +system.physmem_0.memoryStateTime::ACT 588099785971 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 16139254320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8806140750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18423607800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5354132400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 50149101600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 410075734410 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 100965867000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 609913838280 # Total energy per rank (pJ) -system.physmem_1.averagePower 794.363055 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 165472936005 # Time in different power states -system.physmem_1.memoryStateTime::REF 25638600000 # Time in different power states +system.physmem_1.actEnergy 16179556680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8828131125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18455494200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5349602880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 50341337280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 412908393870 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 100247038500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 612309554535 # Total energy per rank (pJ) +system.physmem_1.averagePower 794.437909 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 164276600328 # Time in different power states +system.physmem_1.memoryStateTime::REF 25736880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 576690946995 # Time in different power states +system.physmem_1.memoryStateTime::ACT 580733308672 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 286292198 # Number of BP lookups -system.cpu.branchPred.condPredicted 223415085 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14631198 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 158639381 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150355883 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 286275195 # Number of BP lookups +system.cpu.branchPred.condPredicted 223398341 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14628424 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 157667483 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150349199 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.778410 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16642674 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 61 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3027 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 1888 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1139 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 95.358406 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16643020 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 63 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3069 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 1906 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1163 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 137 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -344,7 +351,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -374,7 +381,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -404,7 +411,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -435,95 +442,95 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1535607688 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1541504754 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13928755 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067573004 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286292198 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 167000445 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1506957925 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29287239 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 992 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656968436 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 958 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1535531474 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.442524 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.228151 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13925502 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067484101 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286275195 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166994125 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1512857238 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29281631 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 279 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 1018 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656940019 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 946 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1541424852 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.436951 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.229037 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 453078112 29.51% 29.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465445913 30.31% 59.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101427094 6.61% 66.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515580355 33.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 459011037 29.78% 29.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465435057 30.20% 59.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101419068 6.58% 66.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515559690 33.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1535531474 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.186436 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.346420 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74706893 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 538056624 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849925630 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58199384 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14642943 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42203258 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 730 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037275151 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52500118 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14642943 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139803593 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 457092273 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13624 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837854747 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 86124294 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976468269 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26746953 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45300136 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 126625 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1588286 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 25069373 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985943496 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9128568020 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432995559 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 145 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1541424852 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.185712 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.341212 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74709451 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 544021839 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849845592 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58207832 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14640138 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42201657 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 726 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037180089 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52484609 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14640138 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139806563 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 462600801 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15884 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837785307 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 86576159 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976384850 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26739549 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45323653 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 126929 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1602638 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 25499860 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985860548 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9128169124 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432875929 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 133 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 311044551 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 174 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 310961603 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 175 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 175 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111502635 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542585286 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199312070 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26927303 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29234152 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1948047142 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 111534180 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542566077 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199303375 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26892889 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29237160 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1947969517 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 231 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857492479 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13497229 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 284014957 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 647584065 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 1857492369 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13496690 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 283937332 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 647289356 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1535531474 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.209674 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.150607 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1541424852 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.205049 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.150817 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 582548107 37.94% 37.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 326134076 21.24% 59.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378190631 24.63% 83.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219663672 14.31% 98.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28988815 1.89% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6173 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 588435916 38.17% 38.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 326131475 21.16% 59.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378210554 24.54% 83.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219654013 14.25% 98.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28986723 1.88% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6171 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1535531474 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1541424852 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166038532 40.99% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1976 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166021321 40.99% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1993 0.00% 40.99% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available @@ -551,13 +558,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191466165 47.27% 88.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47567904 11.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191489776 47.28% 88.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47539480 11.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138257084 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 800920 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138243662 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 800931 0.04% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -579,88 +586,88 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 31 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532121986 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186312436 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532135699 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186312026 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857492479 # Type of FU issued -system.cpu.iq.rate 1.209614 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405074577 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218076 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5669087998 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2232075127 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805719723 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 240 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 252 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 72 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262566922 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 134 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17809734 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857492369 # Type of FU issued +system.cpu.iq.rate 1.204986 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405052570 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218064 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5674958613 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2231919871 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805704142 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 237 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 230 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 70 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262544806 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17811536 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84278952 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66732 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13280 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24465025 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84259743 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66618 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13244 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24456330 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4505677 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4870984 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4512030 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4891489 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14642943 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25375759 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1295309 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1948047519 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14640138 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25364964 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1346928 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1947969899 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542585286 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199312070 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 542566077 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199303375 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 169 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159534 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1134383 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13280 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7701154 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8705181 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16406335 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827826675 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516940315 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29665804 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 159350 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1186169 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13244 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7699482 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8703162 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16402644 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827831567 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516957415 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29660802 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 146 # number of nop insts executed -system.cpu.iew.exec_refs 698692225 # number of memory reference insts executed -system.cpu.iew.exec_branches 229542687 # Number of branches executed -system.cpu.iew.exec_stores 181751910 # Number of stores executed -system.cpu.iew.exec_rate 1.190295 # Inst execution rate -system.cpu.iew.wb_sent 1808754463 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805719795 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169207800 # num instructions producing a value -system.cpu.iew.wb_consumers 1689618799 # num instructions consuming a value -system.cpu.iew.wb_rate 1.175899 # insts written-back per cycle +system.cpu.iew.exec_nop 151 # number of nop insts executed +system.cpu.iew.exec_refs 698708795 # number of memory reference insts executed +system.cpu.iew.exec_branches 229542425 # Number of branches executed +system.cpu.iew.exec_stores 181751380 # Number of stores executed +system.cpu.iew.exec_rate 1.185745 # Inst execution rate +system.cpu.iew.wb_sent 1808736265 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805704212 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169174812 # num instructions producing a value +system.cpu.iew.wb_consumers 1689572222 # num instructions consuming a value +system.cpu.iew.wb_rate 1.171391 # insts written-back per cycle system.cpu.iew.wb_fanout 0.691995 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 258113026 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 258041892 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14630522 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1496036001 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.112294 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.028030 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14627747 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1501940299 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.107922 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.025263 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 915722932 61.21% 61.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250663462 16.76% 77.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110062832 7.36% 85.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55282207 3.70% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29306686 1.96% 90.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34079757 2.28% 93.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24721963 1.65% 94.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18129916 1.21% 96.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58066246 3.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 921653315 61.36% 61.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250636600 16.69% 78.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110060462 7.33% 85.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55269176 3.68% 89.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29319156 1.95% 91.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34080655 2.27% 93.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24723288 1.65% 94.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18133421 1.21% 96.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58064226 3.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1496036001 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1501940299 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563042 # Number of instructions committed system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -706,78 +713,78 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58066246 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3360114616 # The number of ROB reads -system.cpu.rob.rob_writes 3883791528 # The number of ROB writes -system.cpu.timesIdled 840 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 76214 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 58064226 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3365949800 # The number of ROB reads +system.cpu.rob.rob_writes 3883638365 # The number of ROB writes +system.cpu.timesIdled 837 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 79902 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563024 # Number of Instructions Simulated system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.994202 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.994202 # CPI: Total CPI of All Threads -system.cpu.ipc 1.005832 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.005832 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175815840 # number of integer regfile reads -system.cpu.int_regfile_writes 1261595611 # number of integer regfile writes +system.cpu.cpi 0.998020 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.998020 # CPI: Total CPI of All Threads +system.cpu.ipc 1.001984 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.001984 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175818987 # number of integer regfile reads +system.cpu.int_regfile_writes 1261576435 # number of integer regfile writes system.cpu.fp_regfile_reads 42 # number of floating regfile reads -system.cpu.fp_regfile_writes 54 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965778765 # number of cc regfile reads -system.cpu.cc_regfile_writes 551854660 # number of cc regfile writes -system.cpu.misc_regfile_reads 675853618 # number of misc regfile reads +system.cpu.fp_regfile_writes 52 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965775009 # number of cc regfile reads +system.cpu.cc_regfile_writes 551856674 # number of cc regfile writes +system.cpu.misc_regfile_reads 675846934 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 17003710 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.964650 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638076364 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17004222 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.524584 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 78426500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.964650 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 17003150 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.964340 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638065664 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17003662 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.525191 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 79206500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.964340 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999930 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999930 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 406 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335728390 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335728390 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 469357603 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469357603 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168718615 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168718615 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335709608 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335709608 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 469347574 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469347574 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168717937 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168717937 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638076218 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638076218 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638076218 # number of overall hits -system.cpu.dcache.overall_hits::total 638076218 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17418310 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17418310 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3867432 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3867432 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638065511 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638065511 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638065511 # number of overall hits +system.cpu.dcache.overall_hits::total 638065511 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17419228 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17419228 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3868110 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3868110 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21285742 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21285742 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21285744 # number of overall misses -system.cpu.dcache.overall_misses::total 21285744 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 411945425500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 411945425500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 148954509432 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 148954509432 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 196500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 196500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 560899934932 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 560899934932 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 560899934932 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 560899934932 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486775913 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486775913 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 21287338 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21287338 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21287340 # number of overall misses +system.cpu.dcache.overall_misses::total 21287340 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 416423435500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 416423435500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 150253086257 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 150253086257 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 199500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 199500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 566676521757 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 566676521757 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 566676521757 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 566676521757 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486766802 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486766802 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -786,470 +793,470 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659361960 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659361960 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659361962 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659361962 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035783 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022409 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.022409 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659352849 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659352849 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659352851 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659352851 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035786 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035786 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022413 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022413 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032282 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032282 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032282 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032282 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23650.137442 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23650.137442 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38515.094624 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38515.094624 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49125 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26350.969345 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26350.969345 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26350.966869 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26350.966869 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 20530392 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3397643 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 943594 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67194 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.757654 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50.564678 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 17003710 # number of writebacks -system.cpu.dcache.writebacks::total 17003710 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151672 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3151672 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1129843 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1129843 # number of WriteReq MSHR hits +system.cpu.dcache.demand_miss_rate::cpu.data 0.032285 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032285 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032285 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032285 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23905.963887 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23905.963887 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38844.057242 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38844.057242 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49875 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49875 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26620.356277 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26620.356277 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26620.353776 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26620.353776 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20685246 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3452781 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 946049 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67233 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.864878 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 51.355450 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 17003150 # number of writebacks +system.cpu.dcache.writebacks::total 17003150 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3153076 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3153076 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1130592 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1130592 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4281515 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4281515 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4281515 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4281515 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266638 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14266638 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737589 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737589 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4283668 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4283668 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4283668 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4283668 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266152 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14266152 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737518 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737518 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17004227 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17004227 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17004228 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17004228 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331755520500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 331755520500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115729212265 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 115729212265 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447484732765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 447484732765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447484800765 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 447484800765 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 17003670 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17003670 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17003671 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17003671 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335207977500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 335207977500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116679674033 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 116679674033 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451887651533 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 451887651533 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451887720533 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 451887720533 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23253.938349 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23253.938349 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42274.136938 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42274.136938 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 589 # number of replacements -system.cpu.icache.tags.tagsinuse 444.836642 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656966815 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1075 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 611131.920930 # Average number of references to valid blocks. +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025788 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025788 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025788 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025788 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23496.733913 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23496.733913 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42622.431718 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42622.431718 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26575.889295 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26575.889295 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26575.891790 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26575.891790 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 588 # number of replacements +system.cpu.icache.tags.tagsinuse 444.874436 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656938405 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1074 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 611674.492551 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 444.836642 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.868822 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.868822 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 444.874436 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.868895 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.868895 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 486 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 443 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313937945 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313937945 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 656966815 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656966815 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656966815 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656966815 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656966815 # number of overall hits -system.cpu.icache.overall_hits::total 656966815 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1620 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1620 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1620 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1620 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1620 # number of overall misses -system.cpu.icache.overall_misses::total 1620 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 98788987 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 98788987 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 98788987 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 98788987 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 98788987 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 453 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2943 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4353 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5523 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1825 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.050598 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.921448 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 552242422 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 552242422 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 4833112 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 23 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 463 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4068 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7095 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2886 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1253 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.008728 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962219 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 561777243 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 561777243 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 4835234 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 312336320998 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 312404671498 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 68350500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 312336320998 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 73218164638 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 385622836136 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356743 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356743 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947026 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189181 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189181 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216158 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216204 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216158 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356810 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356810 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954461 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954461 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189922 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189922 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954461 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216791 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216837 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954461 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216791 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.283548 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63250.407244 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14166.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14166.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95076.186400 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95076.186400 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64852.796860 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64852.796860 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79693.954803 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79693.954803 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83775.868400 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78900.981823 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 34009604 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004315 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2918086 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2899299 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18787 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 14267664 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 6469008 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 12171187 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 5770180 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1436414 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 6 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 6 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737633 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737633 # Transaction distribution +system.cpu.l2cache.overall_mshr_miss_rate::total 0.287303 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61104.298554 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 61104.298554 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15277.777778 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15277.777778 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96035.613700 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96035.613700 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66553.554041 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66553.554041 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80654.828088 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80654.828088 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66553.554041 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84730.465021 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84725.402270 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66553.554041 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84730.465021 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61104.298554 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78931.951042 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 34008488 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17003756 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21185 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 201663 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 201662 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 14267181 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 6469733 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 12168504 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 3012569 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1490485 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 11 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 9 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 9 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737555 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737555 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 1076 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266589 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2740 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51012175 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 51014915 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106496 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176508224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2176614720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 8842499 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 104697920 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 25847794 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.114446 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.320627 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266107 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2738 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51010503 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 51013241 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176436672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2176543040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 6137564 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 104608640 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 23142303 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009630 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.097659 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 22908415 88.63% 88.63% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2920592 11.30% 99.93% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 18787 0.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 22919446 99.04% 99.04% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 222856 0.96% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 25847794 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 34009101529 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 23142303 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 34007983525 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 13538 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 16538 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1613498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1611000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25506339992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 25505500994 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 3696594 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1635896 # Transaction distribution -system.membus.trans_dist::CleanEvict 3001813 # Transaction distribution -system.membus.trans_dist::UpgradeReq 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 976790 # Transaction distribution -system.membus.trans_dist::ReadExResp 976790 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3696595 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13984484 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13984484 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403793920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 403793920 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 9332231 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 4668264 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 3708204 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1634499 # Transaction distribution +system.membus.trans_dist::CleanEvict 3012569 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9 # Transaction distribution +system.membus.trans_dist::ReadExReq 976948 # Transaction distribution +system.membus.trans_dist::ReadExResp 976948 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3708206 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14017383 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14017383 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404457664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 404457664 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 9311100 # Request fanout histogram +system.membus.snoop_fanout::samples 4685163 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 9311100 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4685163 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 9311100 # Request fanout histogram -system.membus.reqLayer0.occupancy 17657610874 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4685163 # Request fanout histogram +system.membus.reqLayer0.occupancy 17662405597 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 25413256779 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 25476549560 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index a861bb889..ddb5178a1 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.832017 # Nu sim_ticks 832017490500 # Number of ticks simulated final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1008264 # Simulator instruction rate (inst/s) -host_op_rate 1086251 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 543126570 # Simulator tick rate (ticks/s) -host_mem_usage 256604 # Number of bytes of host memory used -host_seconds 1531.90 # Real time elapsed on the host +host_inst_rate 1176831 # Simulator instruction rate (inst/s) +host_op_rate 1267857 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 633929666 # Simulator tick rate (ticks/s) +host_mem_usage 260476 # Number of bytes of host memory used +host_seconds 1312.48 # Real time elapsed on the host sim_insts 1544563042 # Number of instructions simulated sim_ops 1664032434 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,6 +220,12 @@ system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032481 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 1999474725 # Transaction distribution system.membus.trans_dist::ReadResp 1999474786 # Transaction distribution @@ -239,14 +245,14 @@ system.membus.pkt_size::total 8383808423 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 2172060895 # Request fanout histogram -system.membus.snoop_fanout::mean 0.711106 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 627495305 28.89% 28.89% # Request fanout histogram -system.membus.snoop_fanout::1 1544565590 71.11% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2172060895 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 2172060895 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index e3d403cda..02e32a48c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.377030 # Number of seconds simulated -sim_ticks 2377029670500 # Number of ticks simulated -final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.379922 # Number of seconds simulated +sim_ticks 2379921906500 # Number of ticks simulated +final_tick 2379921906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 744525 # Simulator instruction rate (inst/s) -host_op_rate 802329 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1150119113 # Simulator tick rate (ticks/s) -host_mem_usage 266344 # Number of bytes of host memory used -host_seconds 2066.77 # Real time elapsed on the host +host_inst_rate 802178 # Simulator instruction rate (inst/s) +host_op_rate 864460 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1240688848 # Simulator tick rate (ticks/s) +host_mem_usage 272000 # Number of bytes of host memory used +host_seconds 1918.23 # Real time elapsed on the host sim_insts 1538759602 # Number of instructions simulated sim_ops 1658228915 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124870272 # Number of bytes read from this memory -system.physmem.bytes_read::total 124909696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 126077056 # Number of bytes read from this memory +system.physmem.bytes_read::total 126116480 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65352128 # Number of bytes written to this memory -system.physmem.bytes_written::total 65352128 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 66029376 # Number of bytes written to this memory +system.physmem.bytes_written::total 66029376 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1951098 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1951714 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1021127 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1021127 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 16585 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 52532063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52548648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 16585 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 16585 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 27493190 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 27493190 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 27493190 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16585 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 52532063 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 80041838 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.physmem.num_reads::cpu.data 1969954 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1970570 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1031709 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1031709 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 16565 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 52975291 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52991856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 16565 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 16565 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 27744346 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 27744346 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 27744346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 16565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 52975291 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 80736202 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -69,7 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -99,7 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -129,7 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -160,8 +160,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 2377029670500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 4754059341 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 2379921906500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 4759843813 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1538759602 # Number of instructions committed @@ -182,7 +182,7 @@ system.cpu.num_mem_refs 633153380 # nu system.cpu.num_load_insts 458306334 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 4754059340.998000 # Number of busy cycles +system.cpu.num_busy_cycles 4759843812.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 213462427 # Number of branches fetched @@ -221,26 +221,26 @@ system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032481 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9111140 # number of replacements -system.cpu.dcache.tags.tagsinuse 4083.741120 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4083.747199 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25224281500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4083.741120 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997007 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997007 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 25232837500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.747199 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997009 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997009 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1156 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1149 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2648 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits @@ -263,14 +263,14 @@ system.cpu.dcache.demand_misses::cpu.data 9115235 # n system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 151235084500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 151235084500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 62883763000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 62883763000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 214118847500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 214118847500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 214118847500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 214118847500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 152766688500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 152766688500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 64243803000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 64243803000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 217010491500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 217010491500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 217010491500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 217010491500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) @@ -295,22 +295,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20929.045752 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20929.045752 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33286.820150 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33286.820150 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23490.216928 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23490.216928 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23490.214351 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23490.214351 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21141.000605 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21141.000605 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34006.742189 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34006.742189 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23807.448903 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23807.448903 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23807.446291 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23807.446291 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3681379 # number of writebacks -system.cpu.dcache.writebacks::total 3681379 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3667054 # number of writebacks +system.cpu.dcache.writebacks::total 3667054 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses @@ -321,16 +321,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 144008998500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 144008998500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 60994614000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 60994614000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 205003612500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 205003612500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 205003673500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 205003673500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145540602500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 145540602500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62354654000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 62354654000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207895256500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 207895256500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207895318500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 207895318500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses @@ -341,26 +341,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19929.045752 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19929.045752 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32286.820150 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32286.820150 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22490.216928 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20141.000605 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20141.000605 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33006.742189 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33006.742189 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22807.448903 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22807.448903 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22807.453203 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22807.453203 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 7 # number of replacements -system.cpu.icache.tags.tagsinuse 515.144337 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 515.169434 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 515.144337 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.251535 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.251535 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 515.169434 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.251548 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.251548 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id @@ -368,7 +368,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 606 system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 3089131820 # Number of tag accesses system.cpu.icache.tags.data_accesses 3089131820 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1544564953 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1544564953 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1544564953 # number of demand (read+write) hits @@ -381,12 +381,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses system.cpu.icache.overall_misses::total 638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 38540000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 38540000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 38540000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 38540000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 38540000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 38540000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 39132000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 39132000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 39132000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 39132000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 39132000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 39132000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1544565591 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1544565591 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1544565591 # number of demand (read+write) accesses @@ -399,12 +399,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60407.523511 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 60407.523511 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 60407.523511 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 60407.523511 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61335.423197 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61335.423197 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61335.423197 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61335.423197 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61335.423197 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61335.423197 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -419,90 +419,90 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 638 system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37902000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 37902000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37902000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 37902000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37902000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 37902000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 38494000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 38494000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38494000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 38494000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38494000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 38494000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59407.523511 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59407.523511 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1919027 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31012.105366 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 14386231 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1948795 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.382116 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 150459065000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15503.034415 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.646166 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15485.424786 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.473115 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000722 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.472578 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.946414 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1085 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1728 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26842 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 149644904 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 149644904 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3681379 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3681379 # number of WritebackDirty hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60335.423197 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60335.423197 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60335.423197 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60335.423197 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60335.423197 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60335.423197 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 1938113 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31679.342131 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 16254769 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1970881 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 8.247463 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 138952277000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 10.111234 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.251326 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31645.979571 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000309 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000710 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.965759 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.966777 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 744 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2874 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1739 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27370 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 147777841 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 147777841 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 3667054 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3667054 # 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number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 36689000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 116106326500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 116143015500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 3681379 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 3681379 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 1969954 # number of overall misses +system.cpu.l2cache.overall_misses::total 1970570 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48018674000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 48018674000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 37281000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 37281000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71177285500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 71177285500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 37281000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 119195959500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 119233240500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 37281000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 119195959500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 119233240500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 3667054 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 3667054 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 7 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 7 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses) @@ -517,101 +517,101 @@ system.cpu.l2cache.demand_accesses::total 9115874 # n system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414014 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.414014 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.420134 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.420134 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.965517 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161770 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161770 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162779 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162779 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.214048 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214101 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.216117 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.216169 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.214048 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.214101 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.332424 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.332424 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59560.064935 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59560.064935 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59513.461065 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59513.461065 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59560.064935 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59508.214574 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59560.064935 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59508.214574 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.216117 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.216169 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.083155 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.083155 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60521.103896 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60521.103896 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60511.627126 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60511.627126 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60521.103896 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60506.976051 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60506.980468 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60521.103896 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60506.976051 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60506.980468 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1021127 # number of writebacks -system.cpu.l2cache.writebacks::total 1021127 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 219 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 219 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782134 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 782134 # number of ReadExReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 1031709 # number of writebacks +system.cpu.l2cache.writebacks::total 1031709 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 220 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 220 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 793696 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 793696 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 616 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 616 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168964 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168964 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1176258 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1176258 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1951098 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1951714 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1969954 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1970570 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1951098 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1951714 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38715893000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38715893000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 30529000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 30529000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57879453500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57879453500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30529000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96595346500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 96625875500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30529000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96595346500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 96625875500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1969954 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1970570 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 40081714000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 40081714000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 31121000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 31121000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59414705500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59414705500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31121000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99496419500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 99527540500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31121000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99496419500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 99527540500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414014 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414014 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420134 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420134 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965517 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161770 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161770 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162779 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162779 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214101 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216117 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216169 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214101 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.332424 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.332424 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49560.064935 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49560.064935 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49513.461065 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49513.461065 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216117 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.216169 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.083155 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.083155 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50521.103896 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50521.103896 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50511.627126 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50511.627126 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50521.103896 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50506.976051 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50506.980468 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50521.103896 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50506.976051 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50506.980468 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1220 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1220 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4698763 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6327661 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6350490 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 638 # Transaction distribution @@ -620,53 +620,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27341612 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 27342895 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818983360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 819024640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1919027 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 65352128 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11034901 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000201 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.014186 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818066560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 818107840 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1938113 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 66029376 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11053987 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000215 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.014666 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11032680 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2221 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11051609 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2378 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11034901 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12794896500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11053987 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12780571500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1169580 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1021127 # Transaction distribution -system.membus.trans_dist::CleanEvict 897056 # Transaction distribution -system.membus.trans_dist::ReadExReq 782134 # Transaction distribution -system.membus.trans_dist::ReadExResp 782134 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1169580 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5821611 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5821611 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190261824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190261824 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 3907683 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1937205 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1176874 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1031709 # Transaction distribution +system.membus.trans_dist::CleanEvict 905404 # Transaction distribution +system.membus.trans_dist::ReadExReq 793696 # Transaction distribution +system.membus.trans_dist::ReadExResp 793696 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1176874 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5878253 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5878253 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192145856 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 192145856 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3869897 # Request fanout histogram +system.membus.snoop_fanout::samples 1970570 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3869897 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1970570 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3869897 # Request fanout histogram -system.membus.reqLayer0.occupancy 7968854000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1970570 # Request fanout histogram +system.membus.reqLayer0.occupancy 8048170000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 9758570000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 9852850000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 907fd74ca..e4956c5fa 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.846007 # Nu sim_ticks 2846007227500 # Number of ticks simulated final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 953043 # Simulator instruction rate (inst/s) -host_op_rate 1484927 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 901693633 # Simulator tick rate (ticks/s) -host_mem_usage 259304 # Number of bytes of host memory used -host_seconds 3156.29 # Real time elapsed on the host +host_inst_rate 913315 # Simulator instruction rate (inst/s) +host_op_rate 1423027 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 864105629 # Simulator tick rate (ticks/s) +host_mem_usage 264708 # Number of bytes of host memory used +host_seconds 3293.59 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -104,6 +104,12 @@ system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 4686862596 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution @@ -122,14 +128,14 @@ system.membus.pkt_size::total 38674388193 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 5690945966 # Request fanout histogram -system.membus.snoop_fanout::mean 0.705196 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.455955 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1677713084 29.48% 29.48% # Request fanout histogram -system.membus.snoop_fanout::1 4013232882 70.52% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5690945966 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5690945966 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 33a716627..3b577baaf 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,51 +1,51 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.895948 # Number of seconds simulated -sim_ticks 5895947852500 # Number of ticks simulated -final_tick 5895947852500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.898831 # Number of seconds simulated +sim_ticks 5898831348500 # Number of ticks simulated +final_tick 5898831348500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 735742 # Simulator instruction rate (inst/s) -host_op_rate 1146353 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1442081312 # Simulator tick rate (ticks/s) -host_mem_usage 269296 # Number of bytes of host memory used -host_seconds 4088.50 # Real time elapsed on the host +host_inst_rate 637466 # Simulator instruction rate (inst/s) +host_op_rate 993229 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1250066735 # Simulator tick rate (ticks/s) +host_mem_usage 275724 # Number of bytes of host memory used +host_seconds 4718.81 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124876480 # Number of bytes read from this memory -system.physmem.bytes_read::total 124919680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 126068992 # Number of bytes read from this memory +system.physmem.bytes_read::total 126112192 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65426496 # Number of bytes written to this memory -system.physmem.bytes_written::total 65426496 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 66108032 # Number of bytes written to this memory +system.physmem.bytes_written::total 66108032 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1951195 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1951870 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1022289 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1022289 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7327 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 21180052 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 21187379 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7327 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7327 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11096858 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11096858 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11096858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 21180052 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 32284237 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states +system.physmem.num_reads::cpu.data 1969828 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1970503 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1032938 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1032938 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7323 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 21371859 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 21379183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7323 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7323 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 11206971 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11206971 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11206971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7323 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 21371859 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 32586154 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 5895947852500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 11791895705 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 5898831348500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 11797662697 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 3008081022 # Number of instructions committed @@ -66,7 +66,7 @@ system.cpu.num_mem_refs 1677713084 # nu system.cpu.num_load_insts 1239184746 # Number of load instructions system.cpu.num_store_insts 438528338 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 11791895704.997999 # Number of busy cycles +system.cpu.num_busy_cycles 11797662696.997999 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 248500691 # Number of branches fetched @@ -105,26 +105,26 @@ system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 4686862596 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9108581 # number of replacements -system.cpu.dcache.tags.tagsinuse 4084.587762 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4084.589706 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 58914110500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587762 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 58922805500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4084.589706 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 901 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2764 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 898 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2768 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits @@ -141,14 +141,14 @@ system.cpu.dcache.demand_misses::cpu.data 9112677 # n system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses system.cpu.dcache.overall_misses::total 9112677 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 151166404000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 151166404000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 62906975000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 62906975000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 214073379000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 214073379000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 214073379000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 214073379000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 152690255000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 152690255000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 64265951000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 64265951000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 216956206000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 216956206000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 216956206000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 216956206000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses) @@ -165,22 +165,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20928.913656 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20928.913656 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33287.160677 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33287.160677 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23491.821229 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23491.821229 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23491.821229 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23491.821229 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21139.890071 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21139.890071 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34006.261420 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34006.261420 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23808.174700 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23808.174700 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23808.174700 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23808.174700 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3682716 # number of writebacks -system.cpu.dcache.writebacks::total 3682716 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3669049 # number of writebacks +system.cpu.dcache.writebacks::total 3669049 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses @@ -189,14 +189,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 143943554000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 143943554000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61017148000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 61017148000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204960702000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 204960702000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204960702000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 204960702000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145467405000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 145467405000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62376124000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 62376124000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207843529000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 207843529000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207843529000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 207843529000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses @@ -205,31 +205,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19928.913656 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19928.913656 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32287.160677 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32287.160677 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20139.890071 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20139.890071 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33006.261420 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33006.261420 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22808.174700 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22808.174700 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22808.174700 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22808.174700 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 10 # number of replacements -system.cpu.icache.tags.tagsinuse 555.751337 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 555.760511 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5945529.195556 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 555.751337 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.271363 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.271363 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 555.760511 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.271367 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.271367 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 665 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.324707 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 8026466439 # Number of tag accesses system.cpu.icache.tags.data_accesses 8026466439 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 4013232207 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4013232207 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4013232207 # number of demand (read+write) hits @@ -242,12 +242,12 @@ system.cpu.icache.demand_misses::cpu.inst 675 # n system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses system.cpu.icache.overall_misses::total 675 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 41859500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 41859500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 41859500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 41859500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 41859500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 41859500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 42528500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 42528500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 42528500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 42528500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 42528500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 42528500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4013232882 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4013232882 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4013232882 # number of demand (read+write) accesses @@ -260,12 +260,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62014.074074 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62014.074074 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62014.074074 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62014.074074 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62014.074074 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62014.074074 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63005.185185 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63005.185185 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63005.185185 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63005.185185 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63005.185185 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63005.185185 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -280,86 +280,86 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 675 system.cpu.icache.demand_mshr_misses::total 675 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 41853500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41853500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 41853500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61014.074074 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61014.074074 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1919169 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31137.283983 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 14382005 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1948952 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.379353 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 341160385000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15261.679989 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.568616 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15850.035379 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.465750 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000780 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.483705 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.950234 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29783 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 995 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 740 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27925 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908905 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 149614323 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 149614323 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3682716 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3682716 # number of WritebackDirty hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62005.185185 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62005.185185 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62005.185185 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62005.185185 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62005.185185 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62005.185185 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 1938075 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31745.660470 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 16250887 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1970843 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 8.245653 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 320350195000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 11.856683 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.308015 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31708.495772 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000362 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000772 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.967666 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.968801 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 435 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3097 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 786 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 28399 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 147746387 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 147746387 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 3669049 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3669049 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 10 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1107394 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1107394 # 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number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 69541354000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 40170500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 116096124500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 116136295000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 40170500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 116096124500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 116136295000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 3682716 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 3682716 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 1969828 # number of overall misses +system.cpu.l2cache.overall_misses::total 1970503 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48034822000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 48034822000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 40839500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 40839500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71139776000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 71139776000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 40839500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 119174598000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 119215437500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 40839500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 119174598000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 119215437500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 3669049 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 3669049 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 10 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 10 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses) @@ -374,101 +374,101 @@ system.cpu.l2cache.demand_accesses::total 9113352 # n system.cpu.l2cache.overall_accesses::cpu.inst 675 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414024 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.414024 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.420125 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.420125 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161815 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161815 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162798 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162798 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.214119 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214177 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.216163 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.216222 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.214119 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.214177 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.008946 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.008946 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.851852 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.851852 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.012834 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.012834 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.851852 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.011275 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59500.015370 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.851852 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.011275 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59500.015370 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.216163 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.216222 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.962963 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.962963 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.003402 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.003402 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.962963 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.002031 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60500.003045 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.962963 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.002031 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60500.003045 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1022289 # number of writebacks -system.cpu.l2cache.writebacks::total 1022289 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 212 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 212 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782433 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 782433 # number of ReadExReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 1032938 # number of writebacks +system.cpu.l2cache.writebacks::total 1032938 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 213 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 213 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 793964 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 793964 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 675 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 675 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168762 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168762 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1175864 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1175864 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1951195 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1951870 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1969828 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1970503 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1951195 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1951870 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38730440500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38730440500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 33420500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 33420500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57853734000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57853734000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33420500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96584174500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 96617595000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33420500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96584174500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 96617595000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1969828 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1970503 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 40095182000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 40095182000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 34089500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 34089500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59381136000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59381136000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34089500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99476318000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 99510407500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34089500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99476318000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 99510407500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414024 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414024 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420125 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420125 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161815 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161815 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162798 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162798 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214177 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216163 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216222 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214177 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.008946 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.008946 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.851852 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.851852 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.012834 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.012834 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216163 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.216222 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.962963 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.962963 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.003402 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.003402 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.962963 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.002031 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.003045 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.962963 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.002031 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.003045 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 18221943 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9108591 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1002 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1002 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1186 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1186 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4705005 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4701987 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6322745 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6344669 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 675 # Transaction distribution @@ -477,55 +477,61 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27333935 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 27335295 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818905152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 818948992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1919169 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 65426496 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11032521 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000091 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.009530 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818030464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 818074304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1938075 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 66108032 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11051427 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000107 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.010359 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11031519 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1002 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11050241 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1186 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11032521 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12793697500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11051427 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12780030500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1169437 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1022289 # Transaction distribution -system.membus.trans_dist::CleanEvict 896090 # Transaction distribution -system.membus.trans_dist::ReadExReq 782433 # Transaction distribution -system.membus.trans_dist::ReadExResp 782433 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1169437 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5822119 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5822119 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5822119 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190346176 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190346176 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190346176 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 3907605 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1937102 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1176539 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1032938 # Transaction distribution +system.membus.trans_dist::CleanEvict 904164 # Transaction distribution +system.membus.trans_dist::ReadExReq 793964 # Transaction distribution +system.membus.trans_dist::ReadExResp 793964 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1176539 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5878108 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5878108 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5878108 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192220224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 192220224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 192220224 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3870249 # Request fanout histogram +system.membus.snoop_fanout::samples 1970503 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3870249 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1970503 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3870249 # Request fanout histogram -system.membus.reqLayer0.occupancy 7959407000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1970503 # Request fanout histogram +system.membus.reqLayer0.occupancy 8039359500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 9759350000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 9852515000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 78502d1ca..d3e370d8a 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.053345 # Number of seconds simulated -sim_ticks 53344764500 # Number of ticks simulated -final_tick 53344764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.053349 # Number of seconds simulated +sim_ticks 53349450500 # Number of ticks simulated +final_tick 53349450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 260335 # Simulator instruction rate (inst/s) -host_op_rate 260335 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 151110624 # Simulator tick rate (ticks/s) -host_mem_usage 253412 # Number of bytes of host memory used -host_seconds 353.02 # Real time elapsed on the host +host_inst_rate 273465 # Simulator instruction rate (inst/s) +host_op_rate 273465 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 158745564 # Simulator tick rate (ticks/s) +host_mem_usage 258296 # Number of bytes of host memory used +host_seconds 336.07 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 202880 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 137728 # Number of bytes read from this memory system.physmem.bytes_read::total 340608 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 202880 # Nu system.physmem.num_reads::cpu.inst 3170 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2152 # Number of read requests responded to by this memory system.physmem.num_reads::total 5322 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3803185 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2581847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6385031 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3803185 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3803185 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3803185 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2581847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6385031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3802851 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2581620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6384471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3802851 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3802851 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3802851 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2581620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6384471 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5322 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 5322 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 53344677500 # Total gap between requests +system.physmem.totGap 53349362500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -92,8 +92,8 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 4932 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -187,29 +187,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 989 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 343.749242 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 211.692592 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.528362 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 314 31.75% 31.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 216 21.84% 53.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 88 8.90% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 117 11.83% 74.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 52 5.26% 79.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 40 4.04% 83.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 29 2.93% 86.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 21 2.12% 88.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 112 11.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 989 # Bytes accessed per row activation -system.physmem.totQLat 40222250 # Total ticks spent queuing -system.physmem.totMemAccLat 140009750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 982 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 345.743381 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 213.338865 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.606559 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 303 30.86% 30.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 220 22.40% 53.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 94 9.57% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 105 10.69% 73.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 62 6.31% 79.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 36 3.67% 83.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 29 2.95% 86.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 22 2.24% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 111 11.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 982 # Bytes accessed per row activation +system.physmem.totQLat 40016750 # Total ticks spent queuing +system.physmem.totMemAccLat 139804250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26610000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7557.73 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7519.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26307.73 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.39 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26269.12 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.38 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.39 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.38 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage @@ -217,49 +217,49 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4331 # Number of row buffer hits during reads +system.physmem.readRowHits 4333 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.38 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.42 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10023426.81 # Average gap between requests -system.physmem.pageHitRate 81.38 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3538080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1930500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 20022600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 10024307.12 # Average gap between requests +system.physmem.pageHitRate 81.42 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3462480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1889250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19843200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3484144560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1791514845 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 30434811000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 35735961585 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.917071 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 50627942250 # Time in different power states +system.physmem_0.actBackEnergy 1795262310 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 30431523750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 35736125550 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.920144 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 50622338000 # Time in different power states system.physmem_0.memoryStateTime::REF 1781260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 934855250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 940274500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3938760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2149125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 21411000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3923640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2140875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 21247200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3484144560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1835182260 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 30396506250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 35743331955 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.055238 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 50563679500 # Time in different power states +system.physmem_1.actBackEnergy 1822659075 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 30407483250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 35741598600 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.022916 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 50582866250 # Time in different power states system.physmem_1.memoryStateTime::REF 1781260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 998933000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 980601250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 11450644 # Number of BP lookups -system.cpu.branchPred.condPredicted 8210940 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 11450641 # Number of BP lookups +system.cpu.branchPred.condPredicted 8210938 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 765018 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6085193 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5320740 # Number of BTB hits +system.cpu.branchPred.BTBLookups 6085190 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5320739 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.437490 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1176675 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 87.437516 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1176674 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 26315 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 24242 # Number of indirect target hits. @@ -270,22 +270,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20415220 # DTB read hits +system.cpu.dtb.read_hits 20415218 # DTB read hits system.cpu.dtb.read_misses 43383 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20458603 # DTB read accesses +system.cpu.dtb.read_accesses 20458601 # DTB read accesses system.cpu.dtb.write_hits 6579912 # DTB write hits system.cpu.dtb.write_misses 276 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 6580188 # DTB write accesses -system.cpu.dtb.data_hits 26995132 # DTB hits +system.cpu.dtb.data_hits 26995130 # DTB hits system.cpu.dtb.data_misses 43659 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 27038791 # DTB accesses -system.cpu.itb.fetch_hits 22968620 # ITB hits +system.cpu.dtb.data_accesses 27038789 # DTB accesses +system.cpu.itb.fetch_hits 22968614 # ITB hits system.cpu.itb.fetch_misses 90 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 22968710 # ITB accesses +system.cpu.itb.fetch_accesses 22968704 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,16 +299,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 53344764500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 106689529 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 106698901 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903089 # Number of instructions committed system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2191325 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2191321 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.160892 # CPI: cycles per instruction -system.cpu.ipc 0.861407 # IPC: instructions per cycle +system.cpu.cpi 1.160994 # CPI: cycles per instruction +system.cpu.ipc 0.861331 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction system.cpu.op_class_0::IntAlu 51001454 55.49% 63.90% # Class of committed instruction system.cpu.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction @@ -344,16 +344,16 @@ system.cpu.op_class_0::MemWrite 6501126 7.07% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 91903089 # Class of committed instruction -system.cpu.tickCycles 103791732 # Number of cycles that the object actually ticked -system.cpu.idleCycles 2897797 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 103791781 # Number of cycles that the object actually ticked +system.cpu.idleCycles 2907120 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1447.584436 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26572205 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1447.584590 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26572201 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2231 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11910.445988 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11910.444195 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1447.584436 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1447.584590 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.353414 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.353414 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2074 # Occupied blocks per task id @@ -363,41 +363,41 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 228 system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.506348 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 53153443 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 53153443 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20074007 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20074007 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6498198 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6498198 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26572205 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26572205 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26572205 # number of overall hits -system.cpu.dcache.overall_hits::total 26572205 # number of overall hits +system.cpu.dcache.tags.tag_accesses 53153439 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 53153439 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 20074005 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20074005 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6498196 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6498196 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26572201 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26572201 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26572201 # number of overall hits +system.cpu.dcache.overall_hits::total 26572201 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 496 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 496 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2905 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2905 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3401 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3401 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3401 # number of overall misses -system.cpu.dcache.overall_misses::total 3401 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 37448500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37448500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 219755500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 219755500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 257204000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 257204000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 257204000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 257204000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20074503 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20074503 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 2907 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2907 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3403 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3403 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3403 # number of overall misses +system.cpu.dcache.overall_misses::total 3403 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 37687000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37687000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 223750000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 223750000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 261437000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 261437000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 261437000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 261437000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20074501 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20074501 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26575606 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26575606 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26575606 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26575606 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 26575604 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26575604 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26575604 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26575604 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000447 # miss rate for WriteReq accesses @@ -406,14 +406,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000128 system.cpu.dcache.demand_miss_rate::total 0.000128 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000128 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75501.008065 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75501.008065 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75647.332186 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75647.332186 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75625.992355 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75625.992355 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75625.992355 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75625.992355 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75981.854839 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75981.854839 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76969.384245 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76969.384245 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76825.448134 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76825.448134 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76825.448134 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76825.448134 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -424,12 +424,12 @@ system.cpu.dcache.writebacks::writebacks 107 # nu system.cpu.dcache.writebacks::total 107 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1162 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1162 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1170 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1170 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1170 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1170 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1164 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1164 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1172 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1172 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1172 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1172 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 488 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 488 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1743 # number of WriteReq MSHR misses @@ -438,14 +438,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2231 system.cpu.dcache.demand_mshr_misses::total 2231 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2231 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2231 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36544000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36544000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 137282000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 137282000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 173826000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 173826000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 173826000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 173826000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36777500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36777500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 140150000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 140150000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 176927500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 176927500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 176927500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 176927500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses @@ -454,24 +454,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74885.245902 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74885.245902 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78761.904762 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78761.904762 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77913.939937 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77913.939937 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77913.939937 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77913.939937 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75363.729508 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75363.729508 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80407.343660 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80407.343660 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79304.123711 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 79304.123711 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79304.123711 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 79304.123711 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 13865 # number of replacements -system.cpu.icache.tags.tagsinuse 1642.714068 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22952789 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1642.701416 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22952783 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15830 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1449.955085 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1449.954706 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1642.714068 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.802106 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.802106 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1642.701416 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.802100 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.802100 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id @@ -479,45 +479,45 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 670 system.cpu.icache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 947 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45953070 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45953070 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 22952789 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22952789 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22952789 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22952789 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22952789 # number of overall hits -system.cpu.icache.overall_hits::total 22952789 # number of overall hits +system.cpu.icache.tags.tag_accesses 45953058 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45953058 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 22952783 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22952783 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22952783 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22952783 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22952783 # number of overall hits +system.cpu.icache.overall_hits::total 22952783 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15831 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15831 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15831 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15831 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15831 # number of overall misses system.cpu.icache.overall_misses::total 15831 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 409090000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 409090000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 409090000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 409090000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 409090000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 409090000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22968620 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22968620 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22968620 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22968620 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22968620 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22968620 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 411111000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 411111000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 411111000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 411111000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 411111000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 411111000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22968614 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22968614 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22968614 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22968614 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22968614 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22968614 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000689 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000689 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000689 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25841.071316 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25841.071316 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25841.071316 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25841.071316 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25841.071316 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25841.071316 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25968.732234 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25968.732234 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25968.732234 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25968.732234 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25968.732234 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25968.732234 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -532,48 +532,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15831 system.cpu.icache.demand_mshr_misses::total 15831 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15831 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15831 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 393260000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 393260000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 393260000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 393260000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 393260000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 393260000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 395281000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 395281000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 395281000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 395281000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 395281000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 395281000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000689 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000689 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000689 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24841.134483 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24841.134483 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24841.134483 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24841.134483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24841.134483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24841.134483 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24968.795401 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24968.795401 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24968.795401 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24968.795401 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24968.795401 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24968.795401 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2482.282304 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 26642 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3671 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.257423 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3575.444447 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 26761 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5322 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 5.028373 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.761061 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2102.458659 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 362.062585 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000542 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2102.450993 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1472.993454 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064162 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011049 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.075753 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3671 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 771 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 183 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2509 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.112030 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 262078 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 262078 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_percent::cpu.data 0.044952 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.109114 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5322 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 920 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 569 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3605 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.162415 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 261986 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 261986 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 13865 # number of WritebackClean hits @@ -602,18 +600,18 @@ system.cpu.l2cache.demand_misses::total 5322 # nu system.cpu.l2cache.overall_misses::cpu.inst 3170 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2152 # number of overall misses system.cpu.l2cache.overall_misses::total 5322 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 134394000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 134394000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 236583500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 236583500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35249500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 35249500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 236583500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 169643500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 406227000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 236583500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 169643500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 406227000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 137262000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 137262000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 238604500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 238604500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35483000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 35483000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 238604500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 172745000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 411349500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 238604500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 172745000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 411349500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 13865 # number of WritebackClean accesses(hits+misses) @@ -642,18 +640,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.294668 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200253 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964590 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.294668 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78272.568433 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78272.568433 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74632.018927 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74632.018927 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81033.333333 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81033.333333 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74632.018927 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78830.622677 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76329.763247 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74632.018927 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78830.622677 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76329.763247 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79942.923704 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79942.923704 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75269.558360 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75269.558360 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81570.114943 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81570.114943 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75269.558360 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80271.840149 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77292.277339 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75269.558360 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80271.840149 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77292.277339 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -672,18 +670,18 @@ system.cpu.l2cache.demand_mshr_misses::total 5322 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3170 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2152 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5322 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 117224000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 117224000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 204883500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 204883500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30899500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30899500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 204883500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 148123500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 353007000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 204883500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 148123500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 353007000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 120092000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 120092000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 206904500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 206904500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31133000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31133000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 206904500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151225000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 358129500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 206904500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151225000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 358129500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985083 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985083 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for ReadCleanReq accesses @@ -696,25 +694,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.294668 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964590 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.294668 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68272.568433 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68272.568433 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64632.018927 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64632.018927 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71033.333333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71033.333333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64632.018927 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68830.622677 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66329.763247 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64632.018927 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68830.622677 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66329.763247 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69942.923704 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69942.923704 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65269.558360 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65269.558360 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71570.114943 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71570.114943 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65269.558360 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70271.840149 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67292.277339 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65269.558360 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70271.840149 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67292.277339 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 32083 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 14022 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 16318 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 13865 # Transaction distribution @@ -748,7 +746,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 23745000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3346500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 53344764500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 5322 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 53349450500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3605 # Transaction distribution system.membus.trans_dist::ReadExReq 1717 # Transaction distribution system.membus.trans_dist::ReadExResp 1717 # Transaction distribution @@ -769,9 +773,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5322 # Request fanout histogram -system.membus.reqLayer0.occupancy 6419500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6421000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 28179750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 28180500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 002e3eec9..720778178 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.021909 # Number of seconds simulated -sim_ticks 21909208500 # Number of ticks simulated -final_tick 21909208500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.021906 # Number of seconds simulated +sim_ticks 21906070500 # Number of ticks simulated +final_tick 21906070500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 183723 # Simulator instruction rate (inst/s) -host_op_rate 183723 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47816944 # Simulator tick rate (ticks/s) -host_mem_usage 254944 # Number of bytes of host memory used -host_seconds 458.19 # Real time elapsed on the host +host_inst_rate 201237 # Simulator instruction rate (inst/s) +host_op_rate 201237 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52367931 # Simulator tick rate (ticks/s) +host_mem_usage 260088 # Number of bytes of host memory used +host_seconds 418.31 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory system.physmem.bytes_read::total 334528 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 195968 # Nu system.physmem.num_reads::cpu.inst 3062 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory system.physmem.num_reads::total 5227 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8944550 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6324281 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15268831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8944550 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8944550 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8944550 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6324281 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15268831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 8945831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6325187 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15271018 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8945831 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8945831 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8945831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6325187 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15271018 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5227 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 5227 # Number of DRAM read bursts, including those serviced by the write queue @@ -43,7 +43,7 @@ system.physmem.servicedByWrQ 0 # Nu system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 470 # Per bank write bursts -system.physmem.perBankRdBursts::1 291 # Per bank write bursts +system.physmem.perBankRdBursts::1 292 # Per bank write bursts system.physmem.perBankRdBursts::2 302 # Per bank write bursts system.physmem.perBankRdBursts::3 523 # Per bank write bursts system.physmem.perBankRdBursts::4 220 # Per bank write bursts @@ -55,7 +55,7 @@ system.physmem.perBankRdBursts::9 278 # Pe system.physmem.perBankRdBursts::10 249 # Per bank write bursts system.physmem.perBankRdBursts::11 251 # Per bank write bursts system.physmem.perBankRdBursts::12 395 # Per bank write bursts -system.physmem.perBankRdBursts::13 339 # Per bank write bursts +system.physmem.perBankRdBursts::13 338 # Per bank write bursts system.physmem.perBankRdBursts::14 492 # Per bank write bursts system.physmem.perBankRdBursts::15 449 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21909113500 # Total gap between requests +system.physmem.totGap 21905974500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,11 +91,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3269 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 507 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 857 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 387.435239 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 233.348968 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 357.138574 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 246 28.70% 28.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 186 21.70% 50.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 85 9.92% 60.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 65 7.58% 67.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 37 4.32% 72.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 35 4.08% 76.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 34 3.97% 80.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 49 5.72% 86.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 120 14.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 857 # Bytes accessed per row activation -system.physmem.totQLat 42496500 # Total ticks spent queuing -system.physmem.totMemAccLat 140502750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 862 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 385.707657 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 229.399691 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 360.883028 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 260 30.16% 30.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 179 20.77% 50.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 93 10.79% 61.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 57 6.61% 68.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 30 3.48% 71.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 37 4.29% 76.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 31 3.60% 79.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 50 5.80% 85.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 125 14.50% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 862 # Bytes accessed per row activation +system.physmem.totQLat 40339750 # Total ticks spent queuing +system.physmem.totMemAccLat 138346000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26135000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8130.19 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7717.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26880.19 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26467.57 # Average memory access latency per DRAM burst system.physmem.avgRdBW 15.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.27 # Average system read bandwidth in MiByte/s @@ -217,75 +217,75 @@ system.physmem.busUtilRead 0.12 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4359 # Number of row buffer hits during reads +system.physmem.readRowHits 4357 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.39 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.36 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4191527.36 # Average gap between requests -system.physmem.pageHitRate 83.39 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3076920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1678875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19468800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 4190926.82 # Average gap between requests +system.physmem.pageHitRate 83.36 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3129840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1707750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19570200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1430579280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 930163050 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 12325856250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14710823175 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.635656 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 20502630500 # Time in different power states +system.physmem_0.actBackEnergy 905463810 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 12347522250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14707973130 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.505534 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 20538678250 # Time in different power states system.physmem_0.memoryStateTime::REF 731380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 668984500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 632936750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3341520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1823250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20771400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3333960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1819125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20779200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1430579280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 904676355 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12348213000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14709404805 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.570899 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 20540502500 # Time in different power states +system.physmem_1.actBackEnergy 902236185 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12350353500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14709101250 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.557040 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 20543762750 # Time in different power states system.physmem_1.memoryStateTime::REF 731380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 632027000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 628284250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 16102191 # Number of BP lookups -system.cpu.branchPred.condPredicted 11688099 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 930994 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8963309 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7508263 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 16102243 # Number of BP lookups +system.cpu.branchPred.condPredicted 11688063 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 931000 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8962915 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7507921 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.766642 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1594548 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 465 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 29370 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 25724 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 3646 # Number of indirect misses. +system.cpu.branchPred.BTBHitPct 83.766509 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1594308 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 466 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 29379 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 25730 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 3649 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 560 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 24064579 # DTB read hits -system.cpu.dtb.read_misses 206327 # DTB read misses -system.cpu.dtb.read_acv 4 # DTB read access violations -system.cpu.dtb.read_accesses 24270906 # DTB read accesses -system.cpu.dtb.write_hits 7168860 # DTB write hits -system.cpu.dtb.write_misses 1193 # DTB write misses +system.cpu.dtb.read_hits 24059471 # DTB read hits +system.cpu.dtb.read_misses 206747 # DTB read misses +system.cpu.dtb.read_acv 6 # DTB read access violations +system.cpu.dtb.read_accesses 24266218 # DTB read accesses +system.cpu.dtb.write_hits 7167964 # DTB write hits +system.cpu.dtb.write_misses 1190 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 7170053 # DTB write accesses -system.cpu.dtb.data_hits 31233439 # DTB hits -system.cpu.dtb.data_misses 207520 # DTB misses -system.cpu.dtb.data_acv 4 # DTB access violations -system.cpu.dtb.data_accesses 31440959 # DTB accesses -system.cpu.itb.fetch_hits 15932703 # ITB hits +system.cpu.dtb.write_accesses 7169154 # DTB write accesses +system.cpu.dtb.data_hits 31227435 # DTB hits +system.cpu.dtb.data_misses 207937 # DTB misses +system.cpu.dtb.data_acv 6 # DTB access violations +system.cpu.dtb.data_accesses 31435372 # DTB accesses +system.cpu.itb.fetch_hits 15930202 # ITB hits system.cpu.itb.fetch_misses 79 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 15932782 # ITB accesses +system.cpu.itb.fetch_accesses 15930281 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,140 +299,140 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 21909208500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 43818418 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 21906070500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 43812142 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 16643559 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 137979359 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16102191 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9128535 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 25956071 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1939868 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 165 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2614 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 15932703 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 367699 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 43572351 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.166672 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.433625 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 16640800 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 137955116 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16102243 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9127959 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 25951378 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1939862 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2284 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 15930202 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 367997 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 43564561 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.166682 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.433652 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19392056 44.51% 44.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2618542 6.01% 50.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1330036 3.05% 53.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1934112 4.44% 58.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3001913 6.89% 64.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1292242 2.97% 67.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1355704 3.11% 70.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 886645 2.03% 73.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11761101 26.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19388904 44.51% 44.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2617971 6.01% 50.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1329653 3.05% 53.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1933242 4.44% 58.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3001866 6.89% 64.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1292154 2.97% 67.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1355153 3.11% 70.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 885983 2.03% 73.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11759635 26.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43572351 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.367475 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.148890 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12867028 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8206518 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19434084 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2106116 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 958605 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2654233 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11853 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 132149690 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 49712 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 958605 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13986113 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4641138 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10397 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20305818 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3670280 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 128777120 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 70822 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2026790 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1359443 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 54939 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 94599417 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 167333836 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 159779688 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7554147 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43564561 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367529 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.148787 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12866207 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8201064 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19435677 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2103016 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 958597 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2653560 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11864 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 132121785 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 49799 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 958597 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13983011 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4637206 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10599 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20305280 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3669868 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 128752916 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 70736 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2012785 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1367413 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 56554 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 94580122 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 167299448 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 159747069 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7552378 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 26172056 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 950 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 946 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8271760 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26904379 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8704430 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3459754 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1614105 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111855372 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1919 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 99762873 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 119457 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27677581 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 21095041 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1530 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43572351 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.289591 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.099378 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 26152761 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 954 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 949 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8254781 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26901517 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8704631 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3463893 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1634991 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111837286 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1924 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 99746434 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 118591 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27659500 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 21091403 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1535 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43564561 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.289623 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.099110 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11226739 25.77% 25.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7658694 17.58% 43.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7470474 17.14% 60.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5702469 13.09% 73.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4463101 10.24% 83.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2983064 6.85% 90.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2041659 4.69% 95.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1171062 2.69% 98.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 855089 1.96% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11223672 25.76% 25.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7655343 17.57% 43.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7467756 17.14% 60.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5704970 13.10% 73.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4467403 10.25% 83.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2981246 6.84% 90.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2039535 4.68% 95.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1169471 2.68% 98.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 855165 1.96% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43572351 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43564561 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 483998 20.16% 20.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 481664 20.16% 20.16% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 20.16% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 20.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 538 0.02% 20.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 522 0.02% 20.18% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 34928 1.45% 21.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 12187 0.51% 22.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1012495 42.17% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 694978 28.95% 93.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 161680 6.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 34768 1.46% 21.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 12121 0.51% 22.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1011551 42.34% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 688710 28.83% 93.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 159620 6.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60663003 60.81% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 489936 0.49% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60652801 60.81% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 489881 0.49% 61.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2847512 2.85% 64.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115351 0.12% 64.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2443315 2.45% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 314199 0.31% 67.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 765838 0.77% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2847832 2.86% 64.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115342 0.12% 64.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2442782 2.45% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 314177 0.31% 67.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 766025 0.77% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.80% # Type of FU issued @@ -454,82 +454,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.80% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.80% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24854808 24.91% 92.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7268585 7.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24850091 24.91% 92.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7267177 7.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 99762873 # Type of FU issued -system.cpu.iq.rate 2.276734 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2400804 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024065 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 229929463 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 129921880 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 89757813 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15688895 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9653551 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7189472 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 93781732 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8381938 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1923340 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 99746434 # Type of FU issued +system.cpu.iq.rate 2.276685 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2388956 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023950 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 229877287 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 129889935 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 89741335 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15687689 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9649325 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7189295 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 93754597 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8380786 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1921314 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6908181 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11335 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 40937 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2203327 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6905319 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11494 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 40918 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2203528 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 42874 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1494 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 42875 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1512 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 958605 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3611196 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 465334 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 122779718 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 241439 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26904379 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8704430 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1919 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 38387 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 421097 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 40937 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 531949 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 502390 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1034339 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 98437326 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24271451 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1325547 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 958597 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3610605 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 461685 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 122758059 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 241249 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 26901517 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8704631 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1924 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 38682 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 417297 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 40918 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 531922 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 502439 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1034361 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 98421413 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24266766 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1325021 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10922427 # number of nop insts executed -system.cpu.iew.exec_refs 31441543 # number of memory reference insts executed -system.cpu.iew.exec_branches 12471856 # Number of branches executed -system.cpu.iew.exec_stores 7170092 # Number of stores executed -system.cpu.iew.exec_rate 2.246483 # Inst execution rate -system.cpu.iew.wb_sent 97646069 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 96947285 # cumulative count of insts written-back -system.cpu.iew.wb_producers 66976790 # num instructions producing a value -system.cpu.iew.wb_consumers 94960923 # num instructions consuming a value -system.cpu.iew.wb_rate 2.212478 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.705309 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 30878414 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 10918849 # number of nop insts executed +system.cpu.iew.exec_refs 31435958 # number of memory reference insts executed +system.cpu.iew.exec_branches 12470734 # Number of branches executed +system.cpu.iew.exec_stores 7169192 # Number of stores executed +system.cpu.iew.exec_rate 2.246441 # Inst execution rate +system.cpu.iew.wb_sent 97629714 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 96930630 # cumulative count of insts written-back +system.cpu.iew.wb_producers 66965531 # num instructions producing a value +system.cpu.iew.wb_consumers 94946242 # num instructions consuming a value +system.cpu.iew.wb_rate 2.212415 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.705299 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 30856710 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 919665 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39078577 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.351750 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.919984 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 919666 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 39073158 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.352076 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.920100 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14680368 37.57% 37.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8532696 21.83% 59.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3879932 9.93% 69.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1909819 4.89% 74.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1376650 3.52% 77.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1035169 2.65% 80.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 692226 1.77% 82.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 728499 1.86% 84.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6243218 15.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14677251 37.56% 37.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8528323 21.83% 59.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3880033 9.93% 69.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1914323 4.90% 74.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1374739 3.52% 77.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1034073 2.65% 80.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 692942 1.77% 82.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 727068 1.86% 84.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6244406 15.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39078577 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39073158 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -575,118 +575,118 @@ system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction -system.cpu.commit.bw_lim_events 6243218 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 155615788 # The number of ROB reads -system.cpu.rob.rob_writes 250112160 # The number of ROB writes -system.cpu.timesIdled 4756 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 246067 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6244406 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 155587477 # The number of ROB reads +system.cpu.rob.rob_writes 250066312 # The number of ROB writes +system.cpu.timesIdled 4758 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 247581 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.520534 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.520534 # CPI: Total CPI of All Threads -system.cpu.ipc 1.921103 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.921103 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 133011224 # number of integer regfile reads -system.cpu.int_regfile_writes 72905073 # number of integer regfile writes -system.cpu.fp_regfile_reads 6263399 # number of floating regfile reads -system.cpu.fp_regfile_writes 6178143 # number of floating regfile writes -system.cpu.misc_regfile_reads 719113 # number of misc regfile reads +system.cpu.cpi 0.520460 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.520460 # CPI: Total CPI of All Threads +system.cpu.ipc 1.921379 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.921379 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 132984940 # number of integer regfile reads +system.cpu.int_regfile_writes 72890464 # number of integer regfile writes +system.cpu.fp_regfile_reads 6263699 # number of floating regfile reads +system.cpu.fp_regfile_writes 6177982 # number of floating regfile writes +system.cpu.misc_regfile_reads 719169 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 158 # number of replacements -system.cpu.dcache.tags.tagsinuse 1457.375474 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28588753 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1457.358075 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28585648 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2245 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12734.411136 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12733.028062 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1457.375474 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355805 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355805 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1457.358075 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355800 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355800 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2087 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 137 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 536 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 543 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1389 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.509521 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 57198843 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 57198843 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 22095651 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22095651 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492632 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492632 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 470 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 470 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28588283 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28588283 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28588283 # number of overall hits -system.cpu.dcache.overall_hits::total 28588283 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1074 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1074 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8471 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8471 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 57192649 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 57192649 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 22092545 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22092545 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492630 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492630 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 473 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 473 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28585175 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28585175 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28585175 # number of overall hits +system.cpu.dcache.overall_hits::total 28585175 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1080 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1080 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8473 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8473 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9545 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9545 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9545 # number of overall misses -system.cpu.dcache.overall_misses::total 9545 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 71413000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 71413000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 546757246 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 546757246 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 85000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 85000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 618170246 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 618170246 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 618170246 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 618170246 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22096725 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22096725 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9553 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9553 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9553 # number of overall misses +system.cpu.dcache.overall_misses::total 9553 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 72549500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 72549500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 550211742 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 550211742 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 86000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 86000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 622761242 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 622761242 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 622761242 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 622761242 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22093625 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22093625 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 471 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 471 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28597828 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28597828 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28597828 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28597828 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 474 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 474 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28594728 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28594728 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28594728 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28594728 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000049 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000049 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001303 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001303 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002123 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002123 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002110 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002110 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66492.551210 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66492.551210 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64544.592846 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64544.592846 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64763.776427 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64763.776427 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64763.776427 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64763.776427 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32543 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 127 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 392 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67175.462963 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67175.462963 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64937.063850 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64937.063850 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 86000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 86000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65190.122684 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65190.122684 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65190.122684 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65190.122684 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33457 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 131 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 396 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.017857 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 63.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 84.487374 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 65.500000 # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 108 # number of writebacks system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 559 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 559 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6742 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6742 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7301 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7301 # 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number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1729 # number of WriteReq MSHR misses @@ -697,154 +697,152 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2244 system.cpu.dcache.demand_mshr_misses::total 2244 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2244 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2244 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39779500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 39779500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 135885995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 135885995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 84000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 84000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 175665495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 175665495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 175665495 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 175665495 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40822500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 40822500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 136978995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 136978995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 85000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 85000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 177801495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 177801495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 177801495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 177801495 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002123 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002123 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002110 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002110 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77241.747573 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77241.747573 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78592.246964 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78592.246964 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 84000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 84000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78282.306150 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78282.306150 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78282.306150 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78282.306150 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79266.990291 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79266.990291 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79224.404280 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79224.404280 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 85000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 85000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79234.177807 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 79234.177807 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79234.177807 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 79234.177807 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 9515 # number of replacements -system.cpu.icache.tags.tagsinuse 1600.928709 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 15918297 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1600.893985 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 15915792 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11453 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1389.880119 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1389.661399 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1600.928709 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.781703 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.781703 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1600.893985 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.781687 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.781687 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1938 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 752 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 753 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 944 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 943 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.946289 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 31876857 # Number of tag accesses -system.cpu.icache.tags.data_accesses 31876857 # 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miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000905 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31066.625026 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 31066.625026 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 31066.625026 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 31066.625026 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 31066.625026 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 31066.625026 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 446 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 159 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 89.200000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 9515 # number of writebacks system.cpu.icache.writebacks::total 9515 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2951 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2951 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2951 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2951 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2951 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2951 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2955 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2955 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2955 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2955 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2955 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2955 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11454 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 11454 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 11454 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 11454 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11454 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11454 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 336702000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 336702000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 336702000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 336702000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 336702000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 336702000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 337628000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 337628000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 337628000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 337628000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 337628000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 337628000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000719 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000719 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000719 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000719 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000719 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000719 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29396.018858 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29396.018858 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29396.018858 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 29396.018858 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29396.018858 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 29396.018858 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29476.863978 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29476.863978 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29476.863978 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 29476.863978 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29476.863978 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 29476.863978 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2407.364249 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 18027 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3589 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 5.022848 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3490.224517 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 18145 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5227 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.471399 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.652891 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2008.506649 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 381.204708 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000539 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061295 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011633 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.073467 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3589 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 909 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.515587 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1482.708930 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061265 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.045249 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.106513 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5227 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 263 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1371 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109528 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 192294 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 192294 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3517 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.159515 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 192203 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 192203 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 108 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 108 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 9515 # number of WritebackClean hits @@ -873,18 +871,18 @@ system.cpu.l2cache.demand_misses::total 5227 # nu system.cpu.l2cache.overall_misses::cpu.inst 3062 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2165 # number of overall misses system.cpu.l2cache.overall_misses::total 5227 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 132876500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 132876500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 231097000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 231097000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 38506000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 38506000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 231097000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 171382500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 402479500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 231097000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 171382500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 402479500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 133969500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 133969500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 232023500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 232023500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 39550000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 39550000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 232023500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 173519500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 405543000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 232023500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 173519500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 405543000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 108 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 108 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 9515 # number of WritebackClean accesses(hits+misses) @@ -913,18 +911,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.381561 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.267330 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964365 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.381561 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78024.955960 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78024.955960 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75472.566950 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75472.566950 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83346.320346 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83346.320346 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75472.566950 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79160.508083 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77000.095657 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75472.566950 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79160.508083 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77000.095657 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78666.764533 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78666.764533 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75775.146963 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75775.146963 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85606.060606 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85606.060606 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75775.146963 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80147.575058 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77586.187105 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75775.146963 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80147.575058 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77586.187105 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -943,18 +941,18 @@ system.cpu.l2cache.demand_mshr_misses::total 5227 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3062 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5227 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115846500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115846500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 200477000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 200477000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33886000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33886000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 200477000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 149732500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 350209500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 200477000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 149732500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 350209500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 116939500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 116939500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 201403500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 201403500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 34930000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 34930000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 201403500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151869500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 353273000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 201403500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151869500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 353273000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984962 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984962 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.267330 # mshr miss rate for ReadCleanReq accesses @@ -967,25 +965,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.381561 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.267330 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.381561 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68024.955960 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68024.955960 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65472.566950 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65472.566950 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73346.320346 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73346.320346 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65472.566950 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69160.508083 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67000.095657 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65472.566950 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69160.508083 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67000.095657 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68666.764533 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68666.764533 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65775.146963 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65775.146963 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75606.060606 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75606.060606 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65775.146963 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70147.575058 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67586.187105 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65775.146963 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70147.575058 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67586.187105 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 23372 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9673 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 11969 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 108 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 9515 # Transaction distribution @@ -1019,7 +1017,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 17179500 # La system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3367500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 5227 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 21906070500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3524 # Transaction distribution system.membus.trans_dist::ReadExReq 1703 # Transaction distribution system.membus.trans_dist::ReadExResp 1703 # Transaction distribution @@ -1040,9 +1044,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5227 # Request fanout histogram -system.membus.reqLayer0.occupancy 6276500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6278000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 27456000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 27461750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 91b6b6b0a..9382954d5 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.132486 # Number of seconds simulated -sim_ticks 132485848500 # Number of ticks simulated -final_tick 132485848500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.132488 # Number of seconds simulated +sim_ticks 132487590500 # Number of ticks simulated +final_tick 132487590500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 159309 # Simulator instruction rate (inst/s) -host_op_rate 167937 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 122483807 # Simulator tick rate (ticks/s) -host_mem_usage 270152 # Number of bytes of host memory used -host_seconds 1081.66 # Real time elapsed on the host +host_inst_rate 200266 # Simulator instruction rate (inst/s) +host_op_rate 211113 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 153975874 # Simulator tick rate (ticks/s) +host_mem_usage 275560 # Number of bytes of host memory used +host_seconds 860.44 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 138240 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory system.physmem.bytes_read::total 247552 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 138240 # Nu system.physmem.num_reads::cpu.inst 2160 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory system.physmem.num_reads::total 3868 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1043432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 825084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1868517 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1043432 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1043432 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1043432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 825084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1868517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1043418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 825073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1868492 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1043418 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1043418 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1043418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 825073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1868492 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3868 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 3868 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 132485754500 # Total gap between requests +system.physmem.totGap 132487495500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3626 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 233 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 929 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 264.680301 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 173.140302 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 275.634226 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 285 30.68% 30.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 355 38.21% 68.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 86 9.26% 78.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 48 5.17% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 35 3.77% 87.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 24 2.58% 89.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 21 2.26% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 19 2.05% 93.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 56 6.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 929 # Bytes accessed per row activation -system.physmem.totQLat 30291250 # Total ticks spent queuing -system.physmem.totMemAccLat 102816250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 926 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 265.468683 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.726650 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 275.485307 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 276 29.81% 29.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 359 38.77% 68.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 87 9.40% 77.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 56 6.05% 84.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 31 3.35% 87.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 22 2.38% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 18 1.94% 91.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 16 1.73% 93.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 61 6.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 926 # Bytes accessed per row activation +system.physmem.totQLat 28381250 # Total ticks spent queuing +system.physmem.totMemAccLat 100906250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19340000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7831.24 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7337.45 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26581.24 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26087.45 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.87 # Average system read bandwidth in MiByte/s @@ -217,56 +217,56 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2934 # Number of row buffer hits during reads +system.physmem.readRowHits 2936 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.85 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.90 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34251746.25 # Average gap between requests -system.physmem.pageHitRate 75.85 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3182760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1736625 # Energy for precharge commands per rank (pJ) +system.physmem.avgGap 34252196.35 # Average gap between requests +system.physmem.pageHitRate 75.90 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3190320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1740750 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 16161600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 8653148400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3626588520 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 76308756000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 88609573905 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.835850 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 126944435250 # Time in different power states +system.physmem_0.actBackEnergy 3615176835 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 76318766250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 88608184155 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.825360 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 126962854750 # Time in different power states system.physmem_0.memoryStateTime::REF 4423900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1115186250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1098483750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3825360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2087250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13790400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3795120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2070750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13782600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 8653148400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3635416395 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 76301020500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 88609288305 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.833625 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 126931702750 # Time in different power states +system.physmem_1.actBackEnergy 3628387440 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 76307186250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 88608370560 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.826698 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 126942838750 # Time in different power states system.physmem_1.memoryStateTime::REF 4423900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1127787750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1117460750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 49693791 # Number of BP lookups -system.cpu.branchPred.condPredicted 39499604 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 49693795 # Number of BP lookups +system.cpu.branchPred.condPredicted 39499605 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5516746 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24160971 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 24160974 # Number of BTB lookups system.cpu.branchPred.BTBHits 22899506 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.778914 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1894448 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 94.778903 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1894449 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 213843 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 208090 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 5753 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 40382 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,16 +387,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 132485848500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 264971697 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 264975181 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317810 # Number of instructions committed system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11524051 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11524054 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.537692 # CPI: cycles per instruction -system.cpu.ipc 0.650325 # IPC: instructions per cycle +system.cpu.cpi 1.537712 # CPI: cycles per instruction +system.cpu.ipc 0.650317 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction @@ -432,18 +432,18 @@ system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 181650743 # Class of committed instruction -system.cpu.tickCycles 256731546 # Number of cycles that the object actually ticked -system.cpu.idleCycles 8240151 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 256731939 # Number of cycles that the object actually ticked +system.cpu.idleCycles 8243242 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1378.678714 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40755400 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1378.670840 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40755401 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22504.362231 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22504.362783 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1378.678714 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.336591 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336591 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1378.670840 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336590 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336590 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id @@ -451,11 +451,11 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81517417 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81517417 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 28347488 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28347488 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 81517419 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81517419 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 28347489 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28347489 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12362636 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 12362636 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits @@ -464,10 +464,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40710124 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40710124 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40710586 # number of overall hits -system.cpu.dcache.overall_hits::total 40710586 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 40710125 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40710125 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40710587 # number of overall hits +system.cpu.dcache.overall_hits::total 40710587 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 751 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 751 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1651 # number of WriteReq misses @@ -478,16 +478,16 @@ system.cpu.dcache.demand_misses::cpu.data 2402 # n system.cpu.dcache.demand_misses::total 2402 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2403 # number of overall misses system.cpu.dcache.overall_misses::total 2403 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 55315500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 55315500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 127182500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 127182500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 182498000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 182498000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 182498000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 182498000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28348239 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28348239 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 55860000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 55860000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 128578000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 128578000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 184438000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 184438000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 184438000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 184438000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28348240 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28348240 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) @@ -496,10 +496,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40712526 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40712526 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40712989 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40712989 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40712527 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40712527 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40712990 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40712990 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000134 # miss rate for WriteReq accesses @@ -510,14 +510,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000059 system.cpu.dcache.demand_miss_rate::total 0.000059 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000059 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73655.792277 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73655.792277 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77033.615990 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77033.615990 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75977.518734 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75977.518734 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75945.900957 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75945.900957 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74380.825566 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 74380.825566 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77878.861296 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77878.861296 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76785.179017 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76785.179017 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76753.225135 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76753.225135 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -544,16 +544,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1810 system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52182500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 52182500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86133500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 86133500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138316000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 138316000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138386000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 138386000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52704000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 52704000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 87045000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 87045000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 71000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 71000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 139749000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 139749000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 139820000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 139820000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -564,26 +564,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73393.108298 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73393.108298 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78374.431301 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78374.431301 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76417.679558 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76417.679558 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76414.135837 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76414.135837 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74126.582278 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74126.582278 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79203.821656 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79203.821656 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77209.392265 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77209.392265 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77205.963556 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77205.963556 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2864 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.966015 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1424.957423 # Cycle average of tags in use system.cpu.icache.tags.total_refs 70941364 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4663 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 15213.674459 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.966015 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.695784 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.695784 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1424.957423 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.695780 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.695780 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1799 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id @@ -593,7 +593,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 system.cpu.icache.tags.occ_task_id_percent::1024 0.878418 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 141896719 # Number of tag accesses system.cpu.icache.tags.data_accesses 141896719 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 70941364 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 70941364 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 70941364 # number of demand (read+write) hits @@ -606,12 +606,12 @@ system.cpu.icache.demand_misses::cpu.inst 4664 # n system.cpu.icache.demand_misses::total 4664 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4664 # number of overall misses system.cpu.icache.overall_misses::total 4664 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 200959500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 200959500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 200959500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 200959500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 200959500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 200959500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 201505000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 201505000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 201505000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 201505000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 201505000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 201505000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 70946028 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 70946028 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 70946028 # number of demand (read+write) accesses @@ -624,12 +624,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43087.371355 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43087.371355 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43087.371355 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43087.371355 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43087.371355 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43087.371355 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43204.331046 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 43204.331046 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 43204.331046 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 43204.331046 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43204.331046 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 43204.331046 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -644,48 +644,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4664 system.cpu.icache.demand_mshr_misses::total 4664 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4664 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4664 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196296500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 196296500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196296500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 196296500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196296500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 196296500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 196842000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 196842000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 196842000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 196842000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 196842000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 196842000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42087.585763 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42087.585763 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42087.585763 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 42087.585763 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42087.585763 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 42087.585763 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42204.545455 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42204.545455 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42204.545455 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 42204.545455 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42204.545455 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 42204.545455 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2000.553914 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5137 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2785 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.844524 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2835.484229 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5160 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3868 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.334023 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.029612 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.714154 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 489.810148 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046012 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.014948 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.061052 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2785 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 156 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2004 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084991 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 76244 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 76244 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.704814 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.779416 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046011 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.040521 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.086532 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3868 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 533 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 366 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2841 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118042 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 76228 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 76228 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 2534 # number of WritebackClean hits @@ -714,18 +712,18 @@ system.cpu.l2cache.demand_misses::total 3885 # nu system.cpu.l2cache.overall_misses::cpu.inst 2162 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1723 # number of overall misses system.cpu.l2cache.overall_misses::total 3885 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84399500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 84399500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 162646500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 162646500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50260000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 50260000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 162646500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 134659500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 297306000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 162646500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 134659500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 297306000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 85311000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 85311000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 163192000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 163192000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50782500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 50782500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 163192000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 136093500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 299285500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 163192000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 136093500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 299285500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 2534 # number of WritebackClean accesses(hits+misses) @@ -754,18 +752,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.600000 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463551 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951408 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.600000 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77359.761687 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77359.761687 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75229.648474 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75229.648474 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79525.316456 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79525.316456 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75229.648474 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78154.091701 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76526.640927 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75229.648474 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78154.091701 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76526.640927 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78195.233731 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78195.233731 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75481.961147 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75481.961147 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80352.056962 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80352.056962 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75481.961147 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78986.360998 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77036.164736 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75481.961147 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78986.360998 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77036.164736 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -794,18 +792,18 @@ system.cpu.l2cache.demand_mshr_misses::total 3869 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2161 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3869 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73489500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73489500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 140980000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 140980000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43051500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43051500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140980000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116541000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 257521000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140980000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116541000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 257521000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 74401000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 74401000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 141524500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 141524500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43559000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43559000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 141524500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 117960000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 259484500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 141524500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 117960000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 259484500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for ReadCleanReq accesses @@ -818,25 +816,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.597529 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.597529 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67359.761687 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67359.761687 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65238.315595 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65238.315595 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69775.526742 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69775.526742 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65238.315595 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68232.435597 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66560.093047 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65238.315595 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68232.435597 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66560.093047 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68195.233731 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68195.233731 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65490.282277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65490.282277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70598.055105 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70598.055105 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65490.282277 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69063.231850 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67067.588524 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65490.282277 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69063.231850 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67067.588524 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 9381 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 3042 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 336 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 5375 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2864 # Transaction distribution @@ -870,7 +868,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 6994999 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2723985 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 132485848500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 3868 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 132487590500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 2777 # Transaction distribution system.membus.trans_dist::ReadExReq 1091 # Transaction distribution system.membus.trans_dist::ReadExResp 1091 # Transaction distribution @@ -891,9 +895,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3868 # Request fanout histogram -system.membus.reqLayer0.occupancy 4518000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4519500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20557500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20563000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 46c589cfc..834ad990c 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.084938 # Number of seconds simulated -sim_ticks 84937723500 # Number of ticks simulated -final_tick 84937723500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.085052 # Number of seconds simulated +sim_ticks 85051506000 # Number of ticks simulated +final_tick 85051506000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 178410 # Simulator instruction rate (inst/s) -host_op_rate 188074 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 87948168 # Simulator tick rate (ticks/s) -host_mem_usage 268236 # Number of bytes of host memory used -host_seconds 965.77 # Real time elapsed on the host +host_inst_rate 137318 # Simulator instruction rate (inst/s) +host_op_rate 144756 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67782320 # Simulator tick rate (ticks/s) +host_mem_usage 272616 # Number of bytes of host memory used +host_seconds 1254.77 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 587328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 132096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 70976 # Number of bytes read from this memory -system.physmem.bytes_read::total 790400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 587328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 587328 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 9177 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1109 # Number of read requests responded to by this memory -system.physmem.num_reads::total 12350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 6914807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1555210 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 835624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9305641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6914807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6914807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6914807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1555210 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 835624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9305641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 12351 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 651584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 192256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71040 # Number of bytes read from this memory +system.physmem.bytes_read::total 914880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 651584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 651584 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 10181 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3004 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1110 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14295 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 7661052 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2260466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 835259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10756776 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7661052 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7661052 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7661052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2260466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 835259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10756776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 14295 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 12351 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 14295 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 790464 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 914880 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 790464 # Total read bytes from the system interface side +system.physmem.bytesReadSys 914880 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1113 # Per bank write bursts -system.physmem.perBankRdBursts::1 381 # Per bank write bursts -system.physmem.perBankRdBursts::2 5089 # Per bank write bursts -system.physmem.perBankRdBursts::3 423 # Per bank write bursts -system.physmem.perBankRdBursts::4 1959 # Per bank write bursts +system.physmem.perBankRdBursts::0 1374 # Per bank write bursts +system.physmem.perBankRdBursts::1 495 # Per bank write bursts +system.physmem.perBankRdBursts::2 5094 # Per bank write bursts +system.physmem.perBankRdBursts::3 807 # Per bank write bursts +system.physmem.perBankRdBursts::4 2274 # Per bank write bursts system.physmem.perBankRdBursts::5 424 # Per bank write bursts -system.physmem.perBankRdBursts::6 265 # Per bank write bursts -system.physmem.perBankRdBursts::7 373 # Per bank write bursts -system.physmem.perBankRdBursts::8 266 # Per bank write bursts -system.physmem.perBankRdBursts::9 219 # Per bank write bursts -system.physmem.perBankRdBursts::10 295 # Per bank write bursts -system.physmem.perBankRdBursts::11 324 # Per bank write bursts -system.physmem.perBankRdBursts::12 199 # Per bank write bursts -system.physmem.perBankRdBursts::13 249 # Per bank write bursts -system.physmem.perBankRdBursts::14 229 # Per bank write bursts -system.physmem.perBankRdBursts::15 543 # Per bank write bursts +system.physmem.perBankRdBursts::6 384 # Per bank write bursts +system.physmem.perBankRdBursts::7 621 # Per bank write bursts +system.physmem.perBankRdBursts::8 270 # Per bank write bursts +system.physmem.perBankRdBursts::9 230 # Per bank write bursts +system.physmem.perBankRdBursts::10 354 # Per bank write bursts +system.physmem.perBankRdBursts::11 348 # Per bank write bursts +system.physmem.perBankRdBursts::12 319 # Per bank write bursts +system.physmem.perBankRdBursts::13 267 # Per bank write bursts +system.physmem.perBankRdBursts::14 239 # Per bank write bursts +system.physmem.perBankRdBursts::15 795 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 84937714500 # Total gap between requests +system.physmem.totGap 85051447500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 12351 # Read request sizes (log2) +system.physmem.readPktSize::6 14295 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,15 +95,15 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 10935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 975 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 12841 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1014 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 173 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see @@ -191,86 +191,86 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 7250 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 108.738207 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 85.269087 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 131.624325 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 5249 72.40% 72.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 1564 21.57% 93.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 167 2.30% 96.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 93 1.28% 97.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 42 0.58% 98.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 24 0.33% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 18 0.25% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 21 0.29% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 72 0.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 7250 # Bytes accessed per row activation -system.physmem.totQLat 171430514 # Total ticks spent queuing -system.physmem.totMemAccLat 403011764 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 61755000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13879.89 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 8758 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 104.242978 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 83.732821 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 121.093987 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 6415 73.25% 73.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 1879 21.45% 94.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 191 2.18% 96.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 97 1.11% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 0.40% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 31 0.35% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 21 0.24% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 17 0.19% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 72 0.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 8758 # Bytes accessed per row activation +system.physmem.totQLat 205669486 # Total ticks spent queuing +system.physmem.totMemAccLat 473700736 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 71475000 # Total ticks spent in databus transfers +system.physmem.avgQLat 14387.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32629.89 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 9.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 33137.51 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 10.76 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 9.31 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 10.76 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.07 # Data bus utilization in percentage -system.physmem.busUtilRead 0.07 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.08 # Data bus utilization in percentage +system.physmem.busUtilRead 0.08 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5094 # Number of row buffer hits during reads +system.physmem.readRowHits 5530 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.24 # Row buffer hit rate for reads +system.physmem.readRowHitRate 38.68 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 6876990.89 # Average gap between requests -system.physmem.pageHitRate 41.24 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 48452040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 26437125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 78179400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 5949734.00 # Average gap between requests +system.physmem.pageHitRate 38.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 56571480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 30867375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 89442600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5547372480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16645874445 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 36357960750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 58704276240 # Total energy per rank (pJ) -system.physmem_0.averagePower 691.186004 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 60381088491 # Time in different power states -system.physmem_0.memoryStateTime::REF 2836080000 # Time in different power states +system.physmem_0.refreshEnergy 5555000880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 17335593540 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 35823020250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 58890496125 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.426384 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 59484367239 # Time in different power states +system.physmem_0.memoryStateTime::REF 2839980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 21718991509 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22725351261 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6335280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3456750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 17877600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 9616320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 5247000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 21801000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5547372480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3295031490 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 48069226500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 56939300100 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.405119 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 79958437412 # Time in different power states -system.physmem_1.memoryStateTime::REF 2836080000 # Time in different power states +system.physmem_1.refreshEnergy 5555000880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4216606920 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 47330903250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 57139175370 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.834595 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 78723898183 # Time in different power states +system.physmem_1.memoryStateTime::REF 2839980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2138239588 # Time in different power states +system.physmem_1.memoryStateTime::ACT 3485604317 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 85626366 # Number of BP lookups -system.cpu.branchPred.condPredicted 68177013 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5935452 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 39946926 # Number of BTB lookups -system.cpu.branchPred.BTBHits 38187698 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 85633597 # Number of BP lookups +system.cpu.branchPred.condPredicted 68181299 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5935035 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 39958046 # Number of BTB lookups +system.cpu.branchPred.BTBHits 38197568 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.596087 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3683716 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81912 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 681689 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 653746 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 27943 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 40316 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 95.594184 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3683467 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81914 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 681978 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 654112 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 27866 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40296 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -300,7 +300,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +330,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +360,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -391,97 +391,97 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 169875448 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 170103013 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5671940 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 347162762 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85626366 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42525160 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 157499775 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11884731 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5682904 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 347166765 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85633597 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42535147 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 157608501 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11884039 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2048 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 3808 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78326624 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 18246 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169120520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.147875 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.049260 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3989 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78333693 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 18018 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169239484 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.146393 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.050401 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17456404 10.32% 10.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30071791 17.78% 28.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31598997 18.68% 46.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 89993328 53.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17572638 10.38% 10.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30072408 17.77% 28.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31601234 18.67% 46.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 89993204 53.18% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169120520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.504054 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.043631 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17509987 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17244874 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 121866560 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6731455 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5767644 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11064434 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 189777 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 304997911 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27240618 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5767644 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37477523 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8502539 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 578983 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108355768 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8438063 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 277420851 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13180734 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3058487 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 843003 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2280960 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 36243 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 27083 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 481449871 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1187780717 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 296461789 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3004325 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169239484 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.503422 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.040921 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17519961 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17356982 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 121861075 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6734206 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5767260 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11064637 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 189821 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 304987544 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27243895 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5767260 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37487022 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8574296 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 598391 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108353196 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8459319 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 277412346 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13179472 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3059617 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 843440 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2298708 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 38369 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 27077 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 481431446 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1187749796 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 296450503 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3005240 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 188472942 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23603 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23603 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13353784 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 33915046 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14407100 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2540378 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1803003 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 263798584 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45955 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214411803 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5187874 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 82208585 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 216955908 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 739 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169120520 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.267805 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.017994 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 188454517 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23636 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23644 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13356506 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 33916395 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14406588 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2541453 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1809916 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 263792468 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45987 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214404594 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5189732 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 82202501 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 216956580 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 771 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169239484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.266871 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.018138 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52408217 30.99% 30.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 35940187 21.25% 52.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65510990 38.74% 90.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13642635 8.07% 99.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1570936 0.93% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47343 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 212 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52525006 31.04% 31.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 35947009 21.24% 52.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65510390 38.71% 90.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13639375 8.06% 99.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1570056 0.93% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47432 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 216 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169120520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169239484 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35659439 66.16% 66.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 153265 0.28% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35663808 66.17% 66.17% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 153282 0.28% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.45% # attempts to use FU when none available @@ -500,22 +500,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.45% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1066 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1064 0.00% 66.45% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35730 0.07% 66.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 240 0.00% 66.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35736 0.07% 66.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 239 0.00% 66.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.52% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 958 0.00% 66.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34286 0.06% 66.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14056522 26.08% 92.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3955910 7.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34308 0.06% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14056089 26.08% 92.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3953676 7.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 166992897 77.88% 77.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 919175 0.43% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 166984371 77.88% 77.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 919276 0.43% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.31% # Type of FU issued @@ -534,91 +534,91 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.31% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33015 0.02% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33022 0.02% 78.33% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165179 0.08% 78.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245702 0.11% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460499 0.21% 78.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206683 0.10% 78.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165180 0.08% 78.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245718 0.11% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460481 0.21% 78.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206631 0.10% 78.87% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.90% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 31868874 14.86% 93.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13371819 6.24% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 31870339 14.86% 93.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13371616 6.24% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214411803 # Type of FU issued -system.cpu.iq.rate 1.262171 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53897621 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.251374 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 653076785 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344050437 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204251594 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3952836 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2009578 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806333 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266175663 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2133761 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1598827 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214404594 # Type of FU issued +system.cpu.iq.rate 1.260440 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53899365 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.251391 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653186184 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344036614 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204245973 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3951585 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2011286 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806392 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266171590 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2132369 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1599233 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6018902 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7447 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7034 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1762466 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6020251 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7425 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7087 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1761954 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25527 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 769 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25499 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 790 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5767644 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5618767 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 62916 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 263864756 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5767260 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5621824 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 63176 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 263858489 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 33915046 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14407100 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23547 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3855 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 55872 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7034 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3149041 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3246654 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6395695 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207125960 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30633355 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7285843 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 33916395 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14406588 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23579 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3874 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 56135 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7087 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3147809 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3246868 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6394677 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207120469 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30635063 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7284125 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 20217 # number of nop insts executed -system.cpu.iew.exec_refs 43771495 # number of memory reference insts executed -system.cpu.iew.exec_branches 44852998 # Number of branches executed -system.cpu.iew.exec_stores 13138140 # Number of stores executed -system.cpu.iew.exec_rate 1.219281 # Inst execution rate -system.cpu.iew.wb_sent 206368045 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206057927 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129397136 # num instructions producing a value -system.cpu.iew.wb_consumers 221651580 # num instructions consuming a value -system.cpu.iew.wb_rate 1.212994 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.583786 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 68672645 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 20034 # number of nop insts executed +system.cpu.iew.exec_refs 43773548 # number of memory reference insts executed +system.cpu.iew.exec_branches 44851099 # Number of branches executed +system.cpu.iew.exec_stores 13138485 # Number of stores executed +system.cpu.iew.exec_rate 1.217618 # Inst execution rate +system.cpu.iew.wb_sent 206362307 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206052365 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129396792 # num instructions producing a value +system.cpu.iew.wb_consumers 221653711 # num instructions consuming a value +system.cpu.iew.wb_rate 1.211339 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.583779 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 68665439 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5760731 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 157823719 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.150970 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.652577 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5760276 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 157944348 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.150091 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.652266 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73232232 46.40% 46.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41142749 26.07% 72.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22534270 14.28% 86.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9514853 6.03% 92.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3552076 2.25% 95.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2143258 1.36% 96.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1327703 0.84% 97.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1008942 0.64% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3367636 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73354007 46.44% 46.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41142542 26.05% 72.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22532573 14.27% 86.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9515365 6.02% 92.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3551587 2.25% 95.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2142504 1.36% 96.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1329210 0.84% 97.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1010049 0.64% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3366511 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 157823719 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 157944348 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317410 # Number of instructions committed system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -664,83 +664,83 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction -system.cpu.commit.bw_lim_events 3367636 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 404773869 # The number of ROB reads -system.cpu.rob.rob_writes 511956769 # The number of ROB writes -system.cpu.timesIdled 9030 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 754928 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3366511 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 404888417 # The number of ROB reads +system.cpu.rob.rob_writes 511940612 # The number of ROB writes +system.cpu.timesIdled 9843 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 863529 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303022 # Number of Instructions Simulated system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.985911 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.985911 # CPI: Total CPI of All Threads -system.cpu.ipc 1.014290 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.014290 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218725741 # number of integer regfile reads -system.cpu.int_regfile_writes 114168991 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904222 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441435 # number of floating regfile writes -system.cpu.cc_regfile_reads 708194084 # number of cc regfile reads -system.cpu.cc_regfile_writes 229512691 # number of cc regfile writes -system.cpu.misc_regfile_reads 57440842 # number of misc regfile reads +system.cpu.cpi 0.987232 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.987232 # CPI: Total CPI of All Threads +system.cpu.ipc 1.012933 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.012933 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218721236 # number of integer regfile reads +system.cpu.int_regfile_writes 114166498 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904044 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441835 # number of floating regfile writes +system.cpu.cc_regfile_reads 708181937 # number of cc regfile reads +system.cpu.cc_regfile_writes 229500026 # number of cc regfile writes +system.cpu.misc_regfile_reads 57441519 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 72581 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.413915 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41031177 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73093 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 561.355766 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 508221500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.413915 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998855 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998855 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 72593 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.410345 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41032184 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73105 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 561.277396 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 509673500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.410345 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998848 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998848 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 229 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 160 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 230 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82360603 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82360603 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 28644947 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28644947 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341311 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341311 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 82362697 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82362697 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 28645946 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28645946 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341320 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341320 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 364 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 364 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22148 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22148 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22147 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22147 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40986258 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40986258 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40986622 # number of overall hits -system.cpu.dcache.overall_hits::total 40986622 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89227 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89227 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22976 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22976 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 40987266 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40987266 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40987630 # number of overall hits +system.cpu.dcache.overall_hits::total 40987630 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89269 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89269 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22967 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22967 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 259 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 259 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 112203 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 112203 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112319 # number of overall misses -system.cpu.dcache.overall_misses::total 112319 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1066843000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1066843000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 241030499 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 241030499 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2297500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2297500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1307873499 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1307873499 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1307873499 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1307873499 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28734174 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28734174 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_misses::cpu.data 260 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 260 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 112236 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112236 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112352 # number of overall misses +system.cpu.dcache.overall_misses::total 112352 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1192862000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1192862000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 244207999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 244207999 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2309000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2309000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1437069999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1437069999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1437069999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1437069999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28735215 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28735215 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 480 # number of SoftPFReq accesses(hits+misses) @@ -749,70 +749,70 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41098461 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41098461 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41098941 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41098941 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003105 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003105 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 41099502 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41099502 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41099982 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41099982 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003107 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003107 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001858 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001858 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241667 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.241667 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011559 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011559 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002730 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002730 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002733 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002733 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11956.504197 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11956.504197 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10490.533557 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10490.533557 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8870.656371 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8870.656371 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11656.314885 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11656.314885 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11644.276561 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11644.276561 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 10738 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011604 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011604 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002731 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002731 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002734 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002734 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13362.555870 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13362.555870 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10632.995123 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10632.995123 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8880.769231 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8880.769231 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12804.002272 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12804.002272 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12790.782532 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12790.782532 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 168 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10626 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 864 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 83 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 12.428241 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 72581 # number of writebacks -system.cpu.dcache.writebacks::total 72581 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24802 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24802 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14421 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 14421 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 259 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 259 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 39223 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 39223 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 39223 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 39223 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64425 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64425 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8555 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8555 # number of WriteReq MSHR misses +system.cpu.dcache.blocked::no_targets 868 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 12.241935 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 72593 # number of writebacks +system.cpu.dcache.writebacks::total 72593 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24834 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24834 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14410 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14410 # 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number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 739220499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 740182499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 740182499 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 72992 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 72992 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73105 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73105 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 724757000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 724757000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85765499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85765499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 963000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 963000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 810522499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 810522499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 811485499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 811485499 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002242 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002242 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses @@ -821,370 +821,373 @@ system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.235417 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.235417 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001776 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.001776 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001778 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001778 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10149.833139 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10149.833139 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9972.822794 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9972.822794 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8513.274336 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8513.274336 # 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Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.594536 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997255 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997255 # Average percentage of cache occupancy +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001779 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001779 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11247.877706 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11247.877706 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10022.846675 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10022.846675 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8522.123894 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8522.123894 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11104.264837 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11104.264837 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11100.273565 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11100.273565 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 53637 # number of replacements +system.cpu.icache.tags.tagsinuse 510.592571 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78276090 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54149 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1445.568524 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 84288957500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.592571 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997251 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997251 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 278 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 49 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 156707315 # Number of tag accesses -system.cpu.icache.tags.data_accesses 156707315 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 78269055 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78269055 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78269055 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78269055 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78269055 # 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number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1245757924 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1245757924 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1245757924 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1245757924 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78333663 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78333663 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78333663 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78333663 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78333663 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78333663 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000735 # 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average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 73195 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3246 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21637.884494 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21637.884494 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21637.884494 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21637.884494 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21637.884494 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21637.884494 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 76503 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 31 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19208.778853 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19208.778853 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 9269 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 9269 # number of prefetch candidates identified +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20772.141274 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20772.141274 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20772.141274 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20772.141274 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20772.141274 # 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Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 121 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2706 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 24 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 87 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 141 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 856 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 162 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1653 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015503 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 199 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 957 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.007385 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.165161 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4005348 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4005348 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 64707 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 64707 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 51067 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 51067 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8388 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 220162000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 66910636 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1008008136 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027140 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027140 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.169536 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.169536 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.028385 # 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average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34294.294469 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70476.495726 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70476.495726 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69132.327304 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69132.327304 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71733.333333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71733.333333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69132.327304 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71590.843023 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69583.703967 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69132.327304 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.843023 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64237.953732 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 253433 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 126224 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10473 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 11905 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3377 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8528 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 118606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 64698 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 61506 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 11007 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2350 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8622 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8622 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 54136 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 64471 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161894 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218767 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 380661 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6896512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9323136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 16219648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 13357 # Total snoops (count) +system.cpu.l2cache.overall_mshr_miss_rate::total 0.119437 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33222.758689 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33222.758689 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72811.440678 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72811.440678 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70811.855417 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70811.855417 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73330.382948 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73330.382948 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70811.855417 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73289.613848 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71376.374668 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70811.855417 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73289.613848 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33222.758689 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66320.687940 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 253485 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 126250 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10456 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 904 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 903 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 118630 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 64707 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 61523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8624 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8624 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 54150 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64481 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161936 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218803 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 380739 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6898304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9324672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 16222976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2352 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 140586 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.219979 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.541213 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 129607 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.087812 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.283049 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 118188 84.07% 84.07% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 13870 9.87% 93.93% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 8528 6.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 118227 91.22% 91.22% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11379 8.78% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 140586 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 252920500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 129607 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 252972500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 81207989 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 81228989 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 109644490 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 109661492 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 12116 # Transaction distribution -system.membus.trans_dist::ReadExReq 234 # Transaction distribution -system.membus.trans_dist::ReadExResp 234 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 12117 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 24701 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 24701 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 790400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 790400 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 14295 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 10463 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 85051506000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 14059 # Transaction distribution +system.membus.trans_dist::ReadExReq 236 # Transaction distribution +system.membus.trans_dist::ReadExResp 236 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 14059 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28590 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28590 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 914880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 914880 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 12351 # Request fanout histogram +system.membus.snoop_fanout::samples 14295 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 12351 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 14295 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 12351 # Request fanout histogram -system.membus.reqLayer0.occupancy 15618188 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 14295 # Request fanout histogram +system.membus.reqLayer0.occupancy 18052130 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 66520835 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 77159307 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index d24e062d1..c2d15923a 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.103324 # Number of seconds simulated -sim_ticks 103324153500 # Number of ticks simulated -final_tick 103324153500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.103278 # Number of seconds simulated +sim_ticks 103278421500 # Number of ticks simulated +final_tick 103278421500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 51505 # Simulator instruction rate (inst/s) -host_op_rate 86327 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40294413 # Simulator tick rate (ticks/s) -host_mem_usage 304184 # Number of bytes of host memory used -host_seconds 2564.23 # Real time elapsed on the host +host_inst_rate 68420 # Simulator instruction rate (inst/s) +host_op_rate 114678 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53503682 # Simulator tick rate (ticks/s) +host_mem_usage 309068 # Number of bytes of host memory used +host_seconds 1930.31 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 231488 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 232192 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 130496 # Number of bytes read from this memory -system.physmem.bytes_read::total 361984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 231488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 231488 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3617 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 362688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 232192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 232192 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3628 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2039 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5656 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2240405 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1262977 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3503382 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2240405 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2240405 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2240405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1262977 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3503382 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5656 # Number of read requests accepted +system.physmem.num_reads::total 5667 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2248214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1263536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3511750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2248214 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2248214 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2248214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1263536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3511750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5668 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5656 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5668 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 361984 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 362752 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 361984 # Total read bytes from the system interface side +system.physmem.bytesReadSys 362752 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 310 # Per bank write bursts -system.physmem.perBankRdBursts::1 382 # Per bank write bursts -system.physmem.perBankRdBursts::2 476 # Per bank write bursts -system.physmem.perBankRdBursts::3 358 # Per bank write bursts -system.physmem.perBankRdBursts::4 362 # Per bank write bursts -system.physmem.perBankRdBursts::5 335 # Per bank write bursts -system.physmem.perBankRdBursts::6 419 # Per bank write bursts -system.physmem.perBankRdBursts::7 385 # Per bank write bursts +system.physmem.perBankRdBursts::0 314 # Per bank write bursts +system.physmem.perBankRdBursts::1 385 # Per bank write bursts +system.physmem.perBankRdBursts::2 471 # Per bank write bursts +system.physmem.perBankRdBursts::3 359 # Per bank write bursts +system.physmem.perBankRdBursts::4 360 # Per bank write bursts +system.physmem.perBankRdBursts::5 334 # Per bank write bursts +system.physmem.perBankRdBursts::6 420 # Per bank write bursts +system.physmem.perBankRdBursts::7 393 # Per bank write bursts system.physmem.perBankRdBursts::8 389 # Per bank write bursts -system.physmem.perBankRdBursts::9 295 # Per bank write bursts -system.physmem.perBankRdBursts::10 260 # Per bank write bursts -system.physmem.perBankRdBursts::11 270 # Per bank write bursts -system.physmem.perBankRdBursts::12 228 # Per bank write bursts -system.physmem.perBankRdBursts::13 484 # Per bank write bursts -system.physmem.perBankRdBursts::14 420 # Per bank write bursts +system.physmem.perBankRdBursts::9 296 # Per bank write bursts +system.physmem.perBankRdBursts::10 257 # Per bank write bursts +system.physmem.perBankRdBursts::11 272 # Per bank write bursts +system.physmem.perBankRdBursts::12 232 # Per bank write bursts +system.physmem.perBankRdBursts::13 487 # Per bank write bursts +system.physmem.perBankRdBursts::14 416 # Per bank write bursts system.physmem.perBankRdBursts::15 283 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 103323899000 # Total gap between requests +system.physmem.totGap 103278386000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5656 # Read request sizes (log2) +system.physmem.readPktSize::6 5668 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,12 +91,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4508 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 949 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4530 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 947 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -187,321 +187,321 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1264 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 286.278481 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 164.439317 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 318.670037 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 554 43.83% 43.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 264 20.89% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 105 8.31% 73.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 69 5.46% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 45 3.56% 82.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 57 4.51% 86.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 28 2.22% 88.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 17 1.34% 90.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 125 9.89% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1264 # Bytes accessed per row activation -system.physmem.totQLat 43672750 # Total ticks spent queuing -system.physmem.totMemAccLat 149722750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 28280000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7721.49 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1276 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 283.335423 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.570090 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 315.354372 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 562 44.04% 44.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 260 20.38% 64.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 126 9.87% 74.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 65 5.09% 79.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 38 2.98% 82.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 52 4.08% 86.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 32 2.51% 88.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 25 1.96% 90.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 116 9.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1276 # Bytes accessed per row activation +system.physmem.totQLat 44968750 # Total ticks spent queuing +system.physmem.totMemAccLat 151243750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 28340000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7933.79 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26471.49 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.50 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26683.79 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.51 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.50 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4391 # Number of row buffer hits during reads +system.physmem.readRowHits 4387 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.63 # Row buffer hit rate for reads +system.physmem.readRowHitRate 77.40 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 18268016.09 # Average gap between requests -system.physmem.pageHitRate 77.63 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5624640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3069000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 23610600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 18221310.16 # Average gap between requests +system.physmem.pageHitRate 77.40 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5677560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3097875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 23649600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 6748591200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3147948405 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 59232949500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 69161793345 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.369133 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 98535205500 # Time in different power states -system.physmem_0.memoryStateTime::REF 3450200000 # Time in different power states +system.physmem_0.refreshEnergy 6745539840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3123252585 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 59226559500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 69127776960 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.342795 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 98524507750 # Time in different power states +system.physmem_0.memoryStateTime::REF 3448640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1338454000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1303957250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3931200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2145000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20490600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3969000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2165625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20412600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 6748591200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2964574845 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 59393774250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 69133507095 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.095685 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 98803806250 # Time in different power states -system.physmem_1.memoryStateTime::REF 3450200000 # Time in different power states +system.physmem_1.refreshEnergy 6745539840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3000772125 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 59333991750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 69106850940 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.140248 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 98704275500 # Time in different power states +system.physmem_1.memoryStateTime::REF 3448640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1069805000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1124404000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 40908032 # Number of BP lookups -system.cpu.branchPred.condPredicted 40908032 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6741329 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 35316490 # Number of BTB lookups +system.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 40909998 # Number of BP lookups +system.cpu.branchPred.condPredicted 40909998 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6747980 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 35338690 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3206071 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 604531 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 35316490 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 9869044 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 25447446 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 5035252 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 3198330 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 606499 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 35338690 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 9879284 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 25459406 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 5040736 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 206648308 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 206556844 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 46351281 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 420030465 # Number of instructions fetch has processed -system.cpu.fetch.Branches 40908032 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13075115 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 152558958 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14935189 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 126 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 5881 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 68758 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 764 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 179 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 41261989 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1525874 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 8 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 206453541 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.416062 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.660543 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 46378865 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 420308215 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40909998 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13077614 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 152415438 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14966481 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 135 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5953 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 72789 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 564 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 110 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 41283191 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1528436 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 206357094 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.419964 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.660932 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 99211398 48.06% 48.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5135847 2.49% 50.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5374620 2.60% 53.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5328555 2.58% 55.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6013612 2.91% 58.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5856529 2.84% 61.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5733209 2.78% 64.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4747222 2.30% 66.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 69052549 33.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 99044157 48.00% 48.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5139433 2.49% 50.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5380650 2.61% 53.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5336666 2.59% 55.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6016483 2.92% 58.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5851353 2.84% 61.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5736237 2.78% 64.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4733991 2.29% 66.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 69118124 33.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 206453541 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.197960 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.032586 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32305475 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 86547165 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 62440790 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17692517 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 7467594 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 591140753 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 7467594 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42099614 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 46622929 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 29580 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 68917298 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 41316526 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 552365156 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1615 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 36415427 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4818042 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 146051 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 629691896 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1486514399 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 974943820 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 15152274 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 206357094 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.198057 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.034831 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32325248 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 86371056 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 62511253 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17666297 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 7483240 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 591444337 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 7483240 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42110583 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 46566289 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 29410 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 68967744 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 41199828 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 552624215 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1533 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 36277086 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4842177 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 151976 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 630066400 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1487530571 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 975657611 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 15077279 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 370262446 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2381 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2386 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 89347483 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 128815998 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 45923960 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 77358410 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 25275137 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 490566423 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 62065 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 338414549 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1099553 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 269265104 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 527048763 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 60820 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 206453541 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.639180 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.804126 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 370636950 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2363 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2376 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 89140950 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 128894590 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 45939948 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 77227738 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 25186602 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 490698604 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 59973 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 338566221 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1098463 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 269395193 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 527209931 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 58728 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 206357094 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.640681 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.805896 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 73345677 35.53% 35.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 46646037 22.59% 58.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32854801 15.91% 74.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20905072 10.13% 84.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 15063521 7.30% 91.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8409386 4.07% 95.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5213188 2.53% 98.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2363320 1.14% 99.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1652539 0.80% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 73312584 35.53% 35.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46573584 22.57% 58.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32816576 15.90% 74.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20907210 10.13% 84.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15065478 7.30% 91.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8412685 4.08% 95.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5234413 2.54% 98.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2370472 1.15% 99.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1664092 0.81% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 206453541 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 206357094 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 758238 19.31% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2733075 69.60% 88.91% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 435620 11.09% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 762770 19.47% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2718793 69.40% 88.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 436106 11.13% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1211810 0.36% 0.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 216608884 64.01% 64.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 799973 0.24% 64.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7048329 2.08% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1813849 0.54% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 84312637 24.91% 92.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 26619067 7.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1211777 0.36% 0.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 216613901 63.98% 64.34% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 799985 0.24% 64.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7047582 2.08% 66.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1810682 0.53% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 84424015 24.94% 92.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 26658279 7.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 338414549 # Type of FU issued -system.cpu.iq.rate 1.637635 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3926933 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011604 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 880106724 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 745207821 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 316030450 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 8202401 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 15512263 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3567674 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 337013730 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 4115942 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18154732 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 338566221 # Type of FU issued +system.cpu.iq.rate 1.639095 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3917669 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011571 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 880328489 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 745561228 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 316131833 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 8177179 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 15427221 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3556889 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 337169115 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 4102998 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18179072 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 72166411 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 54986 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 863760 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 25408243 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 72245003 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 55572 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 872144 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 25424231 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 50543 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 50651 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 53 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 7467594 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35770303 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 592137 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 490628488 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1259959 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 128815998 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 45923960 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22654 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 545800 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 38626 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 863760 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1294864 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6880130 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8174994 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 326485130 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 80685795 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 11929419 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 7483240 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35798970 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 583606 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 490758577 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1261619 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 128894590 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 45939948 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 21909 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 539997 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 37637 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 872144 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1294345 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6884684 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8179029 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 326602378 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 80777118 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11963843 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 106318426 # number of memory reference insts executed -system.cpu.iew.exec_branches 18939296 # Number of branches executed -system.cpu.iew.exec_stores 25632631 # Number of stores executed -system.cpu.iew.exec_rate 1.579907 # Inst execution rate -system.cpu.iew.wb_sent 322610085 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 319598124 # cumulative count of insts written-back -system.cpu.iew.wb_producers 256503247 # num instructions producing a value -system.cpu.iew.wb_consumers 435667509 # num instructions consuming a value -system.cpu.iew.wb_rate 1.546580 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.588759 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 269290512 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 106442155 # number of memory reference insts executed +system.cpu.iew.exec_branches 18940356 # Number of branches executed +system.cpu.iew.exec_stores 25665037 # Number of stores executed +system.cpu.iew.exec_rate 1.581174 # Inst execution rate +system.cpu.iew.wb_sent 322715986 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 319688722 # cumulative count of insts written-back +system.cpu.iew.wb_producers 256576217 # num instructions producing a value +system.cpu.iew.wb_consumers 435723594 # num instructions consuming a value +system.cpu.iew.wb_rate 1.547703 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.588851 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 269420821 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6746174 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 163890954 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.350675 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.933271 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6753005 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 163742250 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.351901 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.936120 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 67206524 41.01% 41.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 54940140 33.52% 74.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13261155 8.09% 82.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 10687834 6.52% 89.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5446779 3.32% 92.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3132108 1.91% 94.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1092307 0.67% 95.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1156922 0.71% 95.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6967185 4.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 67180478 41.03% 41.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 54846489 33.50% 74.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13227508 8.08% 82.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 10675855 6.52% 89.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5434961 3.32% 92.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3126709 1.91% 94.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1096647 0.67% 95.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1147781 0.70% 95.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7005822 4.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 163890954 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 163742250 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -547,478 +547,469 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 6967185 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 647577665 # The number of ROB reads -system.cpu.rob.rob_writes 1024269930 # The number of ROB writes -system.cpu.timesIdled 2819 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 194767 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 7005822 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 647520633 # The number of ROB reads +system.cpu.rob.rob_writes 1024585644 # The number of ROB writes +system.cpu.timesIdled 2803 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 199750 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.564674 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.564674 # CPI: Total CPI of All Threads -system.cpu.ipc 0.639111 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.639111 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 524516370 # number of integer regfile reads -system.cpu.int_regfile_writes 289029189 # number of integer regfile writes -system.cpu.fp_regfile_reads 4536413 # number of floating regfile reads -system.cpu.fp_regfile_writes 3331836 # number of floating regfile writes -system.cpu.cc_regfile_reads 107017358 # number of cc regfile reads -system.cpu.cc_regfile_writes 65774990 # number of cc regfile writes -system.cpu.misc_regfile_reads 176892429 # number of misc regfile reads +system.cpu.cpi 1.563981 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.563981 # CPI: Total CPI of All Threads +system.cpu.ipc 0.639394 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.639394 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 524858514 # number of integer regfile reads +system.cpu.int_regfile_writes 289109549 # number of integer regfile writes +system.cpu.fp_regfile_reads 4527972 # number of floating regfile reads +system.cpu.fp_regfile_writes 3322072 # number of floating regfile writes +system.cpu.cc_regfile_reads 107078976 # number of cc regfile reads +system.cpu.cc_regfile_writes 65816113 # number of cc regfile writes +system.cpu.misc_regfile_reads 177007720 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 72 # number of replacements -system.cpu.dcache.tags.tagsinuse 1525.498489 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 82766316 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2113 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 39170.050166 # Average number of references to valid blocks. +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 77 # number of replacements +system.cpu.dcache.tags.tagsinuse 1524.395872 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 82831685 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2117 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 39126.917808 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1525.498489 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.372436 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.372436 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2041 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 101 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 409 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.498291 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 165539971 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 165539971 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 62251936 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 62251936 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513707 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513707 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 82765643 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 82765643 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 82765643 # number of overall hits -system.cpu.dcache.overall_hits::total 82765643 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1262 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1262 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2024 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2024 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3286 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3286 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3286 # number of overall misses -system.cpu.dcache.overall_misses::total 3286 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 84231000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 84231000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 131983500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 131983500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 216214500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 216214500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 216214500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 216214500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 62253198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 62253198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 1524.395872 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.372167 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.372167 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2040 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 411 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1479 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 165670739 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 165670739 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 62317357 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 62317357 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513773 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513773 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 82831130 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 82831130 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 82831130 # number of overall hits +system.cpu.dcache.overall_hits::total 82831130 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1223 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1223 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1958 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1958 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3181 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3181 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3181 # number of overall misses +system.cpu.dcache.overall_misses::total 3181 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 77985000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 77985000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 124974000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 124974000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 202959000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 202959000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 202959000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 202959000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 62318580 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 62318580 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 82768929 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 82768929 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 82768929 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 82768929 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 82834311 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 82834311 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 82834311 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 82834311 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000099 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000099 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66744.057052 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66744.057052 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65209.239130 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65209.239130 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65798.691418 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65798.691418 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65798.691418 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65798.691418 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 369 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 73 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000095 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000095 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000038 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000038 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000038 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000038 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63765.331153 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63765.331153 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63827.374872 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63827.374872 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63803.520905 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63803.520905 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63803.520905 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63803.520905 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 403 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.125000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 36.500000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 18 # number of writebacks -system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 661 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 661 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 7 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 7 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 668 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 668 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 668 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 668 # number of overall MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.777778 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 16 # number of writebacks +system.cpu.dcache.writebacks::total 16 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 622 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 622 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 8 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 8 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 630 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 601 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 601 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2017 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2017 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2618 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2618 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2618 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2618 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47710000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 47710000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 129636500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 129636500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 177346500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 177346500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 177346500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 177346500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1950 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1950 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2551 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2551 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2551 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2551 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47286500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 47286500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 122663000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 122663000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 169949500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 169949500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 169949500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 169949500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000098 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000098 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79384.359401 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79384.359401 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64271.938523 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64271.938523 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 6515 # number of replacements -system.cpu.icache.tags.tagsinuse 1663.291735 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 41248897 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8499 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4853.382398 # Average number of references to valid blocks. +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000095 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000095 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000031 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000031 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000031 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78679.700499 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78679.700499 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62904.102564 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62904.102564 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66620.736966 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66620.736966 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66620.736966 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66620.736966 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 6489 # number of replacements +system.cpu.icache.tags.tagsinuse 1681.757073 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 41270224 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8478 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4867.919792 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1663.291735 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.812154 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.812154 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1984 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 845 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 155 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 736 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.968750 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 82532972 # Number of tag accesses -system.cpu.icache.tags.data_accesses 82532972 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 41248897 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 41248897 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 41248897 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 41248897 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 41248897 # number of overall hits -system.cpu.icache.overall_hits::total 41248897 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13089 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13089 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13089 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13089 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13089 # number of overall misses -system.cpu.icache.overall_misses::total 13089 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 485791000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 485791000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 485791000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 485791000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 485791000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 485791000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 41261986 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41261986 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 41261986 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41261986 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 41261986 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41261986 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000317 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000317 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000317 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000317 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000317 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000317 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37114.447246 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 37114.447246 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 37114.447246 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 37114.447246 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 37114.447246 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 37114.447246 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2090 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 305 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 30 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 69.666667 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 305 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 6515 # number of writebacks -system.cpu.icache.writebacks::total 6515 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4088 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4088 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4088 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4088 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4088 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4088 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9001 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 9001 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 9001 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 9001 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 9001 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 9001 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 340708000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 340708000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 340708000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 340708000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 340708000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 340708000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000218 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000218 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000218 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37852.238640 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37852.238640 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.occ_blocks::cpu.inst 1681.757073 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.821170 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.821170 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1989 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 832 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 747 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.971191 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 82575282 # Number of tag accesses +system.cpu.icache.tags.data_accesses 82575282 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 41270227 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 41270227 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 41270227 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 41270227 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 41270227 # number of overall hits +system.cpu.icache.overall_hits::total 41270227 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12961 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12961 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12961 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12961 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12961 # number of overall misses +system.cpu.icache.overall_misses::total 12961 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 483569000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 483569000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 483569000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 483569000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 483569000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 483569000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 41283188 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41283188 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 41283188 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 41283188 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 41283188 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 41283188 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000314 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000314 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000314 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000314 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000314 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000314 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37309.544017 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 37309.544017 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 37309.544017 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37309.544017 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 37309.544017 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37309.544017 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1349 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 53.960000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 6489 # number of writebacks +system.cpu.icache.writebacks::total 6489 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4054 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4054 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4054 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4054 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4054 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4054 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8907 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 8907 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 8907 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 8907 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 8907 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 8907 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 345609000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 345609000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 345609000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 345609000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 345609000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 345609000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000216 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000216 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000216 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000216 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000216 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000216 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38801.953520 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38801.953520 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38801.953520 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 38801.953520 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38801.953520 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 38801.953520 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2796.844278 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 11471 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4155 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.760770 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3906.658043 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 11874 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5667 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.095289 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 4.971138 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2402.103394 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 389.769746 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073306 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011895 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.085353 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4155 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 992 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2824 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.126801 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 146881 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 146881 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 18 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 18 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 6469 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66037.600221 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66037.600221 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76377.819549 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76377.819549 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66037.600221 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67493.379107 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66562.411598 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66037.600221 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67493.379107 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66562.411598 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18206 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 7138 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 549 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1512 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1512 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3628 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3628 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 528 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 528 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3628 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2040 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5668 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3628 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2040 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5668 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 99707000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 99707000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 244218500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 244218500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 40155000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 40155000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 244218500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 139862000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 384080500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 244218500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 139862000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 384080500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995392 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995392 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.428133 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.428133 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.881469 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.881469 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.428133 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963173 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.535121 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.428133 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963173 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.535121 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65943.783069 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65943.783069 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67314.911797 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67314.911797 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76051.136364 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76051.136364 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67314.911797 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68559.803922 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67762.967537 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67314.911797 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68559.803922 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67762.967537 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18024 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 7043 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 478 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 9600 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 18 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6515 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 54 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 505 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 505 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1513 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1513 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 9001 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 600 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24009 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5308 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 29317 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 960512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 136384 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1096896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 507 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 32448 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11619 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.094328 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.292297 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 9504 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6489 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 61 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 433 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 433 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 8907 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 599 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23869 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5178 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 29047 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 957568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 136512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1094080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 433 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 27712 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11458 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.082912 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.275760 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 10523 90.57% 90.57% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1096 9.43% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 10508 91.71% 91.71% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 950 8.29% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11619 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15636499 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11458 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15517998 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 13500000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 13359000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3422499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3392501 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4149 # Transaction distribution -system.membus.trans_dist::UpgradeReq 500 # Transaction distribution -system.membus.trans_dist::ReadExReq 1507 # Transaction distribution -system.membus.trans_dist::ReadExResp 1507 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4149 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11812 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11812 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11812 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 361984 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 361984 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 361984 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 5668 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 103278421500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 4155 # Transaction distribution +system.membus.trans_dist::ReadExReq 1512 # Transaction distribution +system.membus.trans_dist::ReadExResp 1512 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4156 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11335 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11335 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11335 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 362688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 362688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 362688 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 6156 # Request fanout histogram +system.membus.snoop_fanout::samples 5668 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6156 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5668 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6156 # Request fanout histogram -system.membus.reqLayer0.occupancy 7649501 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5668 # Request fanout histogram +system.membus.reqLayer0.occupancy 7074000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 30011250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 30060000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |